A DOUBLE ZVS-PWM ACTIVE-CLAMPING FORWARD CONVERTER
RenC Tonico BascopC
Ivo Barbi
and
FEDERAL UNIVERSITY OF SANTA CATARINA
Department of Electrical Engineering
Power Electronic Institute
P. 0. Box. 51 19
88.040-970 - Floriandpolis - SC - Brazil
Tel.: (55)48-331.9204 - Fax: (55) 48-234.5422
E-mail: ivo@inep.ufsc.br; rene@inep.ufsc.br
Abstract - This paper presents a new isolated dc-dc
converter, named Double ZVS-PWM Active-Clamping
Forward Converter, which operates without switching losses
from no-load up to hll-load. The proposed converter is based
on two active-clamping forward converters, coupled with a
single high frequency transformer. This converter is suitable
for high input voltage and high power applications. Operation
principle, theoretical analysis, design example and
experimental results, taken from a 3kW laboratory prototype,
are presented.
hand, they are capable of automatically balance the voltage of
the input capacitors associated in series and connected to a dc
bus voltage. If one of the voltages is higher, the respective
capacitor will transfer energy to the other through the
transformer during the on time.
In this paper we propose the converter shown in Fig. 1.
The converter is composed of two active-clamping ZVSPWM forward converters coupled by single transformer. The
proposed converter was derived from the topologies proposed
in references [5, 61.This converter is described and analyzed
in the following sections.
I. INTRODUCTION
Nowadays, the most used power converter topology in
high power dc-dc power supplies applications is the fullbridge zero-voltage-switching pulse-width-modulation (FBZVS-PWM) converter. It is considered one of the best
alternative for high power applications and its control strategy
is well known. This converter possesses the most desirable
characteristic of both, the hard switching PWM and the soft
switching resonant converters, avoiding their major
drawbacks, such as commutation losses in the first mode and
variable switching frequency and high conduction losses in
the second mode[ 11.
However, the conventional FB-ZVS-PWM converter is
not suitable for high input voltage applications because the
total input voltage is applied across its blocking switches.
Among the alternatives to overcome this drawbacks are
the series connection of switches and multilevel topologies. In
the series connection of the switches, the static and dynamic
sharing of the voltage across the switches is difficult to obtain
and requires specific techniques. Multilevel topologies seems
to be a more effective solution because they can solve the
problem of static and dynamic sharing of the voltage and
minimize the electromagnetic interference, since the dv/dt is
reduced [2].
Another alternative to solve the problems of the series
connection of the switches is the association of two or more
converters in series reducing the voltage stress on each
switching device. This method is appropriate if a perfect
division of the voltage between the converters can be
guaranteed at any time. This condition is attainable by
coupling the converters with a single high-frequency power
transformer as explained in [3, 41. The associated converters
coupled by a single transformer are controlled by the same
control circuit, in this way, the pulse-width-modulator and
drive circuit are identical for all the converters, allowing a
good sharing of the voltage across the switches. On the other
0-7803-5160-6/99/$10.00
0 1999 IEEE.
I
I
Fig. 1. The proposed converter.
11. CIRCUIT DESCRIPTION
AND
PRINCIPLE OF OPERATION
A. Circuit Description
The proposed converter is shown in Fig. 1. It is
composed of the following components: main switches SI and
S2, auxiliary switches S3 and S4, resonant inductances L
1 and
Lr2,high frequency transformer, rectifier diodes D,, and Dn,
output filter Lo and CO,input voltage sources 2Vi, clamping
capacitors Ccl and Cc2,commutation capacitors C,, and CI?,
anti-parallel diodes Dl, DZ,D3 and Dd, and load R,,.
B. Principle of Operation
The following assumptions are made to simplify the
analysis:
0 the circuit operates in steady-state;
a all components are considered ideal;
596
the output inductor filter Lo is large enough to be
considered as a current source with a value equal to the load
current I,;
the voltage over input capacitors are equal (VI=V2=Vi);
the resonant inductors are equal (LrI=LrZ=Lr);
the clamping capacitors are equal (Ccl=Cc2=Cc);
the resonant capacitors are equal (Crl=CrZ=Cr);
0 the transformer leakage inductance is absorbed into Ll
and Lrz;
0 there is no difference among the gate signals applied to
each pair the of switches (SI,S2and S3,S4),they have identical
duty cycles.
Fig. 2 shows the topological stages of the converter for a
half-period and Fig. 3 shows the main theoretical waveforms
for one switching period. The six sequential circuit states are
described below:
First Stage (to, tl): During this stage, the power is
transferred to the load in two ways. Power is transferred from
the input source VI through switch S1 and also, there is a
power transfer to the load when capacitor Cc2 discharges
through switch S4. The switches S2 and S3 are in “off’ state
and the voltage over them is equal to the voltage over the
clamping capacitors C,I and C,Z.
Second Stage (tl, t2): At instant tl, switch SI is tuned-off
with zero voltage. Capacitor Crlbegins to charge linearly with
a constant current. This stage finishes when the voltage over
SI is VI, and over S3is Vc-VI.
Third Stage (tz, t3): At instant t2, the transformer voltage
is zero, in such a way that, the capacitor C,,begins the
resonance with LrI. Also, the output current I, starts the
freewheeling process. When the voltage over Sl reaches V,
this stage finishes.
Fourth Stage (4, t4): At instant t3, diode D3 is direct
biased and starts conducting the current through Lrl, which
decreases linearly. In the same manner, the current through
Lr2 decreases linearly. During this stage the load current
keeps freewheeling through diodes DrI and Dn. Switch S3
must be gated on before diode D3 is reverse biased. This stage
finishes when the switch S4 is turned OK
Fifth Stage (t4, t5): When switch S4 is turned off, the
current through L2is deviated to resonant capacitor Cr2.This
capacitor is discharged in a resonant way. During this stage
the load current keeps freewheeling. This stage finishes when
voltage over capacitor Cr2 is null and the diode D2 starts to
conduct.
Sixth Stage (t5, ts): At the instant t5, diode D2 is direct
biased and begins conducting the Lr2 resonant inductor
current. During this condition, the switch S2 must be gated to
conduct. The current through Lr2 decreases linearly until it
reaches zero. Thereafter, this current changes direction and
flow through switch S2. When the sum of the currents in LrI
and Lr2 is equal to -nI, this stage finishes. During this stage
there is no power transferred to the load; therefore, only a
reduction in the duty cycle occurs.
597
b
LII
-
-
a ) First Stage
,_I
VI
v2
-
b ) Second Stage
L.1
c ) - Third Stage
d
- Fourth Stage
U2
W
y2
la
DI2
1”lrLlrr
ER
-
f ) Sixth Stage
Fig. 2. States of operation of the converter.
n : transformer turns ratio (NJ");
At, : no power transfer time.
The no power transfer time in half period is:
At, =
n.1, .L, 42-0)
(3 1
v,
The reduction of duty cycle in the period T, is given by
(4)
AD=- 2.A1,
Ts
Substituting(3) into (4), we obtain
AD =
2 . f , .L, . n . l , .(2-0)
(5)
v,
Substituting (1) and (3) into (2), the average output
voltage
- is obtained as
2.f, .L, . n . l ,
(6)
v, = n . v i
D
.[-
1
VI
C. Commutation Analysis
This converter presents soft turn-on and turn-off
commutation during its operation.
Turn-on : to analyze this commutation consider the fifth
stage (the main switch S2tums-on).
Equation (7) is obtained for no load (critical) operation
condition of the converter. Therefore,
b
,I
a
U
11
IS
)6
Fig. 3. Main waveforms of the converter.
111. THEORETICAL
ANALYSIS
Qon
A. Clamping Characteristic
The clamping voltage and input voltage ratio (VJVJ can
be obtained determining the average voltage over the main
switch SI and then, applying loop voltage equations. So,
The clamping characteristic is shown in Fig. 12.
B. Output Characteristics
= ~o eton
where:
i:switching ti-equency and resonance ti-equency ratio
9 on : displacement angle of the oscillation fiequency
ton:discharge time of the resonant capacitor,
Displacement angle e on as function of during the turnon is shown in Fig. 4.
The discharge time of the resonant capacitor Cr2is given
by
8,".i
ton = -
r
2.n.f,
In the sixth stage, a reduction in the duty ratio occurs
because S2 is gated on but output freewheeling maintains zero
voltage across +e transformer.
According to the waveforms shown in Fig. 3, and
considering that the commutation time is much smaller than
the switching period, the average output voltage is given by
where:
Vo : output voltage;
D: duty cycle;
Vc : clamping voltage;
Ts : switching period;
eon
'I
Iradl
>:
0
O B
om
"a
0 0
(I,
0,:
at,
01s
Fig. 4. Displacement angle e on as
function of during tum-on.
-
f
598
011
-
0:
Turn off: In this case, it is analyzed the turn-off of the
switch S I which happens in the second and third stages.
During this switching, the resonant capacitor Crl is charged.
The equation (1 1) is also obtained for no load operation
condition of the converter. Therefore,
eoff = @ , * t o f f
(12)
Displacement angle eonas function of T during the turnoff is shown in Fig. 5.
@a
Id1
1) Resonant inductor L,: The resonant inductor is
defined by the specified maximum reduction of duty cycle
and is calculated from (5).
L, =
*AD,,
200 .0.2
= 5.6pH
2 . f. .n .I, .(2 - 0-) = 2.1. lo5 .0.6.50.(2 - 0.8)
2) Clamping capacitor CC:To determine the capacitance
it is consider that the resonance period of the clamping
capacitor and resonance inductor is three times the switching
period Ts. Therefore,
2.x .
= 3 . T,
24
3) Resonant capacitor C,: To determine the capacitance
it is necessary to find the oscillation frequency between L,
and C,. For this purpose, Fig 5 and equation (13)
- are used.
From the curve of Dmi,=0.65, values of Bo@and f are:
,8 = 0.56rad
22
2
,I
1.6
1.4
1.1
I
f = 0.1
0..
From equation (13), the commutation time is:
06
L
.
02
0
o
om
am
am
an
0.12
a14
016
at,
The oscillation frequency is obtained from equation (12).
-0 2
t
Fig. 5. Displacement angle ,
8 as
function of
7 during turn-off.
The charge time of the resonant capacitor Crlis given by
Iv. SIMPLIFIED DESIGN EXAMPLE
A methodology and design procedure is presented in this
section.
5.6
CO =
output power;
input voltage;
output voltage;
output current;
switching frequency.
V0=60V
10=50A
f,=1 OOkHZ
B. Determination of passive components
Assuming ideal switches and diodes .and considering:
maximum duty cycle
Dm, =0.8
maximum duty cycle reduction
AD- =0.2
The transformer turns ratio is calculated from (6)
- (2-D")
.%-
(2-0.8) 60 - o.6
(0.8-0.2)200
The clamping voltage is calculated from (1)
2
.Vi = -.
200=333.34\/
V, =
(2- 0.8)
(2- Dmx)
n-NS
N,
(Dmx-ADw)
V,
1
lo6
= 4.6nF
(2. x a1 IO6)'
4) Output filter: The output filter can be calculated in the
same way as for a conventional hll-bridge converter. This
filter is designed for a maximum current ripple AIh=5A (1 0%
of I,) and a maximum voltage ripple AV,=0.48 (0.8% of Vo).
A. Input Data
P0=3000w
2Vi=400V
1
c, =
A',
=
5
P.X.~,.AV, 2 . x . 1 . 1 0 ~
.0.48
= 17pF
Maximum allowable series resistance of output capacitor
COmust be:
AVO
- 0,48
RSE = -- -= 0,096Q
5
AkO
C. Semiconductors voltage and current stresses
1) Main and auxiliary switches: the maximum voltage
across the blocking switches is:
vs,szs,,
=
2.V
= -=
2.200
(2-D-)
(2-0.8)
333.34u
The rms current through the main switches (SI, Sz) and
auxiliary switches (S3, S4) can be calculated by means of the
normalized current values determined in [7]; for AD,,=0.2
we have:
Isr.sz,
= 0.04
1s3.s4m,
= 0.015
Hence,
599
2) Output rectifier diodes: in the output rectifier, the
diode reverse voltage is:
v,.
2.200
2.200
= 0,6.= 200.0V
(2- 0.8)
=n.
(2 - D,,)
The interaction of the transformer leakage inductance with
the rectifier capacitance during the reverse-recovery
processes causes overshoots of the diode reverse voltage.
The overshoots can be controlled using soft-recovery
rectifiers and a clamping circuit such as that shown in Fig. 6.
The diode's average current is given by
lDrlD,Z,vp
= '0 =
2
In the same way, to determine the external resonant
capacitor the output intrinsic MOSFET's capacitances C,,
are subtracted; C,, are of 870pF and 980pF.
In this section experimental waveforms obtained for an
output power of P0=2780W and P0=90W are presented.
The waveforms obtained for P0=2780W are shown in
Figs. 7 and 8. On the other hand, the waveforms obtained for
P0=90W are shown in Figs. 9 and 10. These results c o n f m
the soft commutation features of the converter.
The output characteristic, the clamping characteristic and
the esciency of the converter are shown in Figs. 11, 12 and
13 respectively. They confirm the theoretically predicted
results.
50
= 25.OA
2
V. EXPERIMENTAL
RESULTS
To verify the practical aspects of the proposed converter,
a prototype was built with the following components:
APT5012LNR - 500V, 42A, 0.1252 MOSFET
Si,S2
JRFP460 - 500V, 20A, 0.27R MOSFET
s3, s 4
HFA5OPA60C - 600V, 50A diode
Drl, Dr2
6pF/400V - polypropylene capacitor
CCI,Cc2
3300pF, 350V - electrolytic capacitor
C1,C2
2.7nF/1.6kV - polypropylene capacitor
Crl, C,,
Ferrite core EE75/50 - IP12;
Trl
NpI=Nm=lO turns, N s ~ = N s ~6=turns
21pH - Ferrite core EE65/26 IP12;
LO
Nh=12 turns
3.9pH Ferrite core EE42/15 IP12;
L,1, Lr2
NLrl=NLR=7
turns.
Cwl, C m 0.1 pF, 630V polypropylene capacitor
Rb1, Rm2 33kW 5W - resistor
DDrl,DDr2 MUR440 - diode
Ref2
20 O m V
200~5
Fig. 7. Voltage and current in switch SI.
(10Ndiv.; 100V/div.; 2uddiv)
-
-
-
Ref2
20 OmV
2 Oops
Fig. 8. Voltage and current in switch S4.
( 1 ONdiv.;100Vldiv.; 2usldiv.)
1VI
Fig. 6. Circuit diagram of the laboratory prototype.
Ref2
For inductor design, the leakage transformer inductance is
subtracted of the resonant inductance calculated. In the
prototype, the leakage inductance is around 1.7pH.
600
i o omv
2 oovs
L,,
,
Fig. 9. Voltage and current in switch SI.
2Ndiv.; lOOV/div.; 2uddiv.)
VI. CONCLUSIONS
An new active-clamping ZVS-PWM dc-dc converter
based in two single forward-converters was proposed in the
paper. Analysis of the clamping characteristic, output
characteristic, commutation characteristic and design
methodology are presented.
Experimental results show that the converter presents the
following features:
0 Soft commutation of switches SI, S1, S3, S4 for any load
current.
The power flow from the input to the output is
controlled with only two switches, SI and Sz. In this way,
conduction losses of the converter are low. Besides, the
current flowing through the auxiliary switches SS and S4 is
very low.
0 Overshoots voltages across the switches caused by the
transformer leakage inductance are reduced by the use of
active clamping circuits.
0 Good sharing of the voltage across the switches is
observed.
Fig. 10. Voltage and current in switch S4.
(2Ndiv.; lOOV/div.;2us/div.)
a4
72
a
40
36
24
2
IZ0 0
20
I0
Fig. 1 1 . Output characteristicof the converter.
p
J. A. SabatB, V. Vlatkovic, R. B. Ridley, F. C. Lee, and
B. H. Cho, “Design Considerations for High-Voltage
High-Power Full-Bridge Zero-Voltage-Switching
PWM Converter”, in IEEE Applied Power Electronics
Conference (APEC) Rec., 1990, pp. 275-284.
E. Deschamps and I. Barbi, ”A New DC-to-DC ZVS
PWM Converter for High Input Voltage Applications”,
in IEEE Power Electronics Specialists’ Conference
(PESC) Rec., 1998, pp. 967-972.
M. Miller, A. Buffh and U. Carlsson, “High Frequency
ZVS for High Power Rectifiers”, in International
Telecommunication Energy Conference (MTELEC)
Proc., 1993, pp. 424-430.
N. Kutkut, G. Luckjitt and D. Divan, “A Dual Bridge
High Current DC-to-DC Converter with Soft Switching
Capability”, in IEEE Industry Applications Society
(IAS) Conf. Rec., 1997, pp. 1398-1405.
[SI B. Carsten, “Design Techniques for Transformers Active
Reset Circuits at High Frequencies and Power Levels”,
in High Frequency Power Conversion (HFPC) conf.
proc., 1990, pp. 235-246.
[6] C. M. C. Duarte, and I. Barbi, “A Family of ZVS-PWM
Active-Clamping DC-to-DC Converters: Synthesis,
Analysis, Design, and Experimentation”, in IEEE
Transactions on Circuits and Systems, august 1997,
~01.44,NO.8. pp. 698-704.
(71 R. Torrico Bascope, “Isolated ZVS-PWM dc-dc
Converters with Two Input, Single Transformer and
Symmetrical Rectifier”, Doctoral Thesis in Preparation,
Power Electronic Institute-Federal University of Santa
Catarina, Brazil, 1998.
so
40
30
10 [AI
1.:
1.8
1.7
1.6
I .5
1.4
1.3
1.2
1.1
I
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
I
0.9
D
Fig. 12. Clamping characteristicof the converter.
’*
I%]
95
w
85
75
70
e5
09
55
I
0
I
12W
I
18MI
I
24au
Fig. 13. Measured efficiency of the converter.
REFERENCES
I
3wo
Po WI
601