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Published in IET Power Electronics
Received on 30th April 2013
Revised on 16th September 2013
Accepted on 23rd October 2013
doi: 10.1049/iet-pel.2013.0321
ISSN 1755-4535
Survey of modelling techniques used in optimisation
of power electronic components
Mehran Mirjafari1, Robert S. Balog2
1
Department of Electrical Engineering, Texas A&M University, 30C4 Zachry bldg., College Station 77843, TX, USA
Department of Electrical and Computer Engineering, Texas A&M University, 216D Zachry Engineering Bldg.,
College Station 77843, TX, USA
E-mail: sardis@gmail.com
2
Abstract: Design optimisation techniques for power electronic converters have been the subject of numerous research studies for
the past 15 years. Accurate modelling is the most important task in the optimisation, and, because the nature of optimisation
problem demands evaluating an objective function numerous times, fast and simplified modelling techniques are required.
The objective of this study is to categorise and analyse the previous studies related to modelling techniques incorporated in
design optimisation of power electronic converters. Common trends in modelling and optimisation of power electronic
converters are analysed and suggestions for future research in this field will be presented.
1
Introduction
Electricity represents 40% of the total energy consumption
worldwide, and the demand for electrical power is only
expected to increase [1]. This growth in demand is partly
because of increase in number of digital devices, and hence,
power electronic converters which must regulate power at
almost any arbitrary voltage, current and frequency. Thus,
power electronics can be found through the electrical
system as they enable efficient conversion generation,
storage and end-user applications. With technologies such
as all electric aircrafts [2] and electric vehicles [3, 4]
gaining more attention, it is expected that the number of
power electronic converters will continue to increase in the
coming years [5]. Increasing the number of digital devices
will also increase the demand for power electronic
converters. Cisco visual networking index forecast predicts
that by year 2015 the number of digital devices connected
to the network is twice the global population [6]. At the
same time, all electronics are expected to become ‘better,
faster and cheaper’ which require highly optimised designs.
Therefore effective design techniques are required to
achieve higher-performance indices for power electronic
converters, which include size, weight, efficiency, cost and
reliability.
Design optimisation of power electronic converters is
certainly not a new subject and dates back to the early days
of power electronics. The evolution of digital computers
made it possible to use advanced numerical and stochastic
techniques for optimisation of complex power electronic
circuits. Advances in modelling techniques also resulted in
more accurate models and therefore a more accurate
optimisation. However, despite advances in modelling
power electronic converters, only a limited class of models
can be used for optimisation since objective functions are
evaluated numerous times in the optimisation process,
which
makes
the
optimisation
problem
computation-intensive. In other words, modern optimisation
techniques, whether deterministic or stochastic, search for
the optimal point by calculating an objective function
repeatedly, moving from one candidate design point to the
other, which makes it nearly impossible to use highly
accurate detailed models such as those obtained from finite
element analysis or similar techniques. Therefore in power
electronic design optimisation, modelling usually comes
down to one or a set of algebraic (or, in rare cases,
differential or integral) equations which are much easier to
evaluate in a computation-intensive optimisation problem. It
should be mentioned that in some areas such as electrical
machines, it is now a common practice to use complex
finite element models [7, 8] or complex MATLAB models
[9–12] for optimisation; however, use of these complex
models are very limited in power electronics.
With a wide variety of simplified models for different
components, designers of power electronic converters face a
challenge for choosing the right models for optimisation of
their designs. The criteria for choosing models may be
based on the nature of the objective function, the design
variables of degrees of freedom for the design, or accuracy
of the models. This paper presents a study of the modelling
approaches used in the design optimisation of power
electronic converters published in IEEE-affiliated journals
and conferences after 1995. From 398 papers which deal
with one form of optimisation, 110 ‘design’ optimisation
papers were selected and analysed. This study will be
helpful for the designers of conventional power electronic
converters, as well as researchers and R&D engineers who
want to pick the right components and operating conditions
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(e.g. switching frequency) for a newly proposed converter
topology.
The remainder of this paper is organised as follows: in
Section 2, a definition of the optimisation problem is given
and different modelling approaches will be introduced, in
Section 3, loss modelling of different components will be
discussed, in Section 4, size modelling of converters and in
Section 5 cost modelling will be presented. Sections 6 and
7 contain recommendations for future work and conclusion,
respectively.
2
Problem definition
The ‘optimisation’ problem can be defined mathematically
and in a general form as [13]
minimise:
subject to:
f (x), x [ V
gi (x) ≤ 0, i = 1 . . . n
(1)
where f (x) is the ‘objective function’ defined in the space Ω
and gi (x) i = 1 … n are a number of ‘constraints’. This
definition establishes the scope of the optimisation
considered in this survey, which explicitly excludes three
other categories of optimisation found in the literature:
† incremental improvement to a specific performance index
and do not fall into a rigorous optimisation problem stated
in (1).
† optimisation of the controller and algorithm in which the
performance indices are limited to the controller itself.
Examples for this category are [14], in which parameters
such as steady-state error, settling time, overshoot etc. are
subject to optimisation, and [15] in which parameters such
as steady-state error, settling time etc. are combined to form
an objective function.
† optimisation of the performance indices of the whole
converter (efficiency, cost etc.) through changing controller
parameters (i.e. controller tuning). For example, in [16]
efficiency is optimised via tuning the switching frequency
and dead time, whereas in [17] harmonic content is
optimised via controlling the pulse width modulation
(PWM) sequence.
Papers included in this study pertain to optimising the
whole or a part of the power stage of the power electronic
circuit.
Objective function f(x) creates a mapping between design
variables and design objective. This mapping is created
using models of the components with regard to operation of
the converter. For example, if energy efficiency of a
converter is being considered as the objective function, loss
models of individual components with regard to effective
voltages and currents across the converter create a mapping
between design variables (e.g. component values) and
efficiency. Component models may also be used in defining
constraints. For example, in order to check if a certain LC
filter complies with IEEE 519 or any other harmonic
standard, a detailed model of the inductor which takes AC
resistance of the inductor winding for each harmonic
frequency is required. The optimisation problem is then
solved using either a deterministic (e.g. Newton’s method,
gradient descent method or sequential quadratic
programming etc. [13]) or stochastic (simulated annealing,
genetic algorithm, particle swarm optimisation etc. [18–20])
method. These methods ‘search’ for an optimal point by
means of an iterative approach, involving calculation of the
objective function one or more times for each iteration.
Similar to any other form of modelling, in power
electronics there is usually a tradeoff between the accuracy
of the model and the number of variables considered.
Dynamics of the system are usually simplified (or entirely
ignored) in order to develop a reduced-order, and hence
faster way of modelling. A model derived from finite
element analysis, for example, takes into account a fine
mesh inside of each different material in the component as
well as accurate material properties. Such highly accurate
models may not be useful for the purpose of the
optimisation since they are computation-intensive, and
therefore time consuming. Therefore optimisation problems
usually use simpler techniques which involve mostly
algebraic or simple differential or integral equations.
Finding and categorising such models is the subject of this
work and can be of a great help to anyone willing to work
in this area. A wide variety of techniques might be used in
order to find a reduced-order model for the optimisation.
For instance, the Steinmetz equation is derived from curve
fitting to a data series given by test measurements; Dowell
equation is derived from solving diffusion equation in
one-dimensional (1D) (and ignoring the 3D nature of the
problem) and considering a fixed forward voltage drop for a
power diode simply ignores the slight variation in the
voltage drop which can be calculated by using device
physics equations in [21].
In this paper, models have been categorised based on the
objective function, that is, loss, size etc. In the next
sections, the following aspects of models are discussed:
Section 3, loss mechanisms – Different phenomenas that
contribute to losses in power electronic circuits and
approaches to model those phenomena; Section 4, size
modelling – calculating weight and/or volume of the
converter from a set of design variables; and Section 5, cost
modelling – different factors which are considered to affect
the cost of the converter.
3
3.1
Loss mechanisms
Core losses in inductors and transformers
Inductors and transformers are very common in power
electronic circuits and contribute to the power losses
especially in high-frequency converters. There are two
mechanisms for the core losses: eddy current losses and
hysteresis losses. Although these losses are well studied
under single-frequency sinusoidal magnetic fields [22],
these models and results are not generally applicable to
switching power supplies. Owing to the non-linear nature of
the hysteresis losses, it is not possible to apply
superposition principle in the case of a non-sinusoidal field.
Therefore methods other than those applicable to sinusoidal
excitation are usually used to calculate core losses in
magnetic components.
3.1.1 Steinmetz equation: The Steinmetz equation is
used to calculate core losses when the magnetic field is
sinusoidal. The basic form of Steinmetz equation is
Pcore = K f a Bb
(2)
where Pcore is the volumetric core loss, f is the frequency of
sinusoidal excitation waveform, B is the peak flux density
of the core and α, β and K are coefficients specific to each
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core-geometry and usually determined by curve fitting to the
curve provided by the manufacturer. Once the Steinmetz
parameters have been identified, either given explicitly by
the manufacturer or found from curve fitting the
manufacturer’s data plots, it is straightforward to calculate
core losses. A main limitation is that this equation is only
good for sinusoidal excitation voltage and can be used
whenever applicable. In [23–26], the basic form of the
Steinmetz equation is used to calculate core losses in a
resonant module. In [27], this equation is used to calculate
core losses in the AC source side of a boost power factor
correction (PFC) converter. In [28], this equation is based
on an approximation. In [29], this equation is used to
calculate core losses in a DC–DC converter and it is
claimed that it is given in the datasheet, which is no longer
available in the provided web address, and finally in [30],
core losses in a high-frequency transformer is calculated
using this equation; however, magnetic field waveform of
this transformer is not specified. In [31], Steinmetz equation
is used to calculate core losses in a transformer. The flux
density is calculated from core geometry and excitation in
[32] and used in the equation.
3.1.2 Modifications to Steinmetz equation: In most
typical power electronic circuits, the magnetic cores are
exposed to non-sinusoidal magnetic fields. Thus, the basic
Steinmetz equation does not accurately predict core losses
under non-sinusoidal excitation.
In [33–39], a modified form of Steinmetz equation, which
is developed in [40] is used. In this modified form, instead of
using frequency, the time-rate of change of flux density
(dB/dt) is used to calculate the core loss
a
dB
Pcore = K1 (DB)b−a
(3)
dt
where ΔB is the peak-to-peak flux density and K1 is chosen to
be consistent with the basic Steinmetz (2) for sinusoidal
waveforms. In [41–44], another form of modified Steinmetz
equation, which is introduced by Albach et al. [45] was
used. An equivalent frequency is derived for the arbitrary
waveform to be used with the basic equation and the effects
of temperature are also considered. In [46–48], a
generalisation of Steinmetz equation based on [49], which
seeks to calculate core losses in discontinuous (DCM) and
continuous (CCM) conduction modes for a buck converter,
is used. In these calculations, core losses in DCM depend
only on frequency and maximum flux density while they
depend on frequency, maximum flux density and flux
density changes in CCM.
Jieli et al. [50] also used a generalisation of Steinmetz
equation based on their own work [51]. In this
generalisation, time average of core losses over a period is
calculated from equation below
Pcore =
1
T
a
dB b−a
K1 B(t)
dt
dt
0
T
(4)
where K1 is calculated such that (4) is consistent with the
basic Steinmetz equation (2) under sinusoidal excitation.
In [52], a modified Steinmetz equation, which is
introduced in [53], is used. In this modified equation, an
equivalent frequency is derived for non-sinusoidal
waveforms, which is basically an integral form of
piecewise linear equation which was presented in [45].
Table 1 Major modifications to Steinmetz equation
Designations
Additional
considerations
modified
Steinmetz
equation [45,
53]
dB/dt
generalised
Steinmetz
equation [51]
B(t) and dB(t)/dt
Formulas
feq =
2
DB 2 p2
a−1 b
P = k feq
B̂ fr
a
dB P(t) = K1 |B(t)|b−a
dt
P=
1
T
T
P(t) dt
0
natural
Steinmetz
equation [40,
55]
dB(t)/dt
waveform
coefficient
Steinmetz
equation [58]
a correction
factor (flux
waveform
coefficient)
T 2
dB
dt
dt
0
Pcore =
DB
2
b−a
KN
T
T a
dB dt
dt 0
P = FWC K f a B b ,
for example,
FWCsquare =
p
4
A quadratic term was also added to the basic Steinmetz
equation because of the geometry effects. In [54] an
equation is used, which is introduced in [55] and called
natural Steinmetz equation and uses the assumption that
core losses depend on flux density and its rate of change
instead of a single frequency
Pcore =
DB b−a KN T dBa
dt
T 0 dt 2
(5)
KN is calculated in a way that (5) is consistent with the basic
Steinmetz equation (2) for sinusoidal excitation. Another
modified version of Steinmetz equation was used in [56, 57]
Pcore = a k (b f )m DBn
(6)
Although this equation appears identical to the basic
Steinmetz (2), it is claimed that coefficients α and β
compensate for the non-sinusoidal excitation [56, 57].
Waveform coefficient Steinmetz equation is introduced in
[58], and, as the name implies, losses are calculated by
multiplying a factor to the basic Steinmetz equation. The
factor is calculated from the flux waveform. Table 1
summarises modifications to the Steinmetz equation.
Owing to the empirical nature of Steinmetz equation, all of
the modifications are also empirical. According to [59],
generalised Steinmetz equation is substantially less accurate
than modified Steinmetz equation and natural Steinmetz
equation. Natural Steinmetz equation is also more accurate
than modified Steinmetz equation since it does not use an
arbitrary averaging method. There is no direct comparison
between waveform coefficient Steinmetz equation and the
three aforementioned methods; however, since waveform
coefficient method only takes peak flux density into
account, it is expected that it is less accurate than the other
three.
3.2
Copper losses in windings
Copper losses are a considerable portion of the total losses of
the inductor. Generally, power losses in a conductor can be
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Table 2 Summary of copper losses
Reference(s)
Descriptions
Formulas
[25, 26, 30, 44,
54, 60]
calculated from Dowell equation
see (7) and (8)
[23, 33–37,
61–63]
equivalent resistance calculated from current wave shape and Dowell
equation
Reff
C
= 1 + A4
3
Rdc
2
dIrms /dt
vIrms
5Nl2 − 1
, see (7) and (8) for Nl and A
15
definitions
C=
[64–66]
equivalent frequency derived based on current wave shape, resistance
then calculated from Dowell equation
veff =
[27–29, 41, 50,
67–76]
Dc resistance used-high-frequency effects neglected
Rac = Rdc
[77]
single-frequency resistance used-higher-frequency effects neglected
Rac = Rac, f0
[46–48, 78]
comprehensive analysis done for a flyback transformer
see [78] for comprehensive analysis
[31, 32]
comprehensive analysis for a low-profile transformer
see [32] for comprehensive analysis
[39, 42, 43, 79,
80]
losses calculated from 2D solution of diffusion equation
P = FI 2 + GH 2
rms(d/dt)I(t)
Irms
n sinh n + sin n
4 cosh n − cos n
sinh n − sin n
G = w 2 Rdc n
cosh n + cos n
d
n=
dv
F = Rdc
w : conductor width
I : peak current
H : peak field
[56, 57, 81]
DC and eddy current losses calculated separately, superposition used for
eddy current losses
[82, 83]
an analytical technique used-claims to be faster than solving diffusion
equation 2D, but with a good accuracy
calculated by multiplying the resistance by the square of the
current. However, conductor current and current flowing in
adjacent conductors create a magnetic field which leads to
additional losses in the conductor. Additional losses
because of the conductor current and current flowing in
adjacent conductors are called skin and proximity effects,
respectively.
These
two
losses
are
highly
frequency-dependent, and, since high-frequency waveforms
are very common in power electronics, these effects must
be considered if an accurate loss prediction is needed.
Owing to the linear nature of eddy current losses,
superposition can generally be applied for copper loss
calculation, unlike in the case of core losses. Different
approaches taken in optimisation papers are reviewed below
and summarised in Table 2.
3.2.1 Dowell equation: The Dowell equation is a
generalised form of the solution for the diffusion equation
of rectangular conductors adapted and applied to round
conductors [22]. In this equation, instead of calculating
losses directly, the ‘AC resistance’ of the conductor is
calculated. The ratio of this resistance to the DC resistance
2
Pwinding = 3RIrms
+ Peddy
1 I(n) 2 2
Peddy = Peddy, R
n
IR
n=1
see [83] for comprehensive analysis
is given as
Rac
Rdc
sinh 2A + sin 2A 2(Nl2 − 1) sinh A − sin A
+
=A
cosh 2A − cos 2A
3
cosh A + cos A
(7)
FR =
where A is given
A=
p(3/4) d
4
dv
(8)
and d is the conductor diameter, δω is the skin depth and Nl
is the number of layers in a multilayer winding. This
equation is widely used in the literature along with
Fourier analysis and superposition of the current
waveform [25, 26, 30, 44, 54, 60]. In the case of a
non-sinusoidal current waveform, AC resistance should be
calculated separate for each frequency which requires that
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the circuit be solved for each frequency separately. The total
copper loss can be obtained using superposition principle,
that is, summing up losses of the circuits for each
individual frequency. This approach, while accurate,
increases the computing time and might be burdensome
for an optimisation algorithm.
Another approach, which is based on Dowell equation, is to
calculate an effective total resistance based on the current
waveform. The approach taken in [23, 24, 33–38], which is
based on an approach presented in [61], calculates an
effective resistance from the root-mean-square (RMS)
current and its derivative. However, this equation is only
useful when the current waveform and its derivatives are
known. In one other approach, which is based on 1D
solution of diffusion equation, an equivalent frequency is
calculated for a non-sinusoidal waveform [64–66]. Current
derivatives are also required in this approach.
3.2.2 Equivalent resistance: In the Dowell equation,
eddy current losses and therefore AC resistance are
frequency-dependent. However, some of the papers model
copper losses as a single equivalent resistance. In [50], the
DC resistance of the inductor was used, neglecting
high-frequency effects, reportedly because of low-ripple
current. In [27, 28], only DC resistance was used, stating
explicitly that the high-frequency effects are neglected. In
[77], transformer current waveform is considered to be
sinusoidal (and confirmed by measurement), and therefore an
equivalent resistance for sinusoidal waveform is used. In
[84], an equivalent resistance is used to model both core
losses and copper losses, and the resistance is calculated from
curve fitting. In [29, 41, 52, 67–69, 71, 74, 75, 85, 86],
equivalent resistance is used; however, no reason is specified
for neglecting high-frequency effects.
3.2.3 Other copper loss calculation methods: The
Dowell equation and series resistance approximation are the
most common approaches in the literature, other techniques
are also mentioned. In this section, these are reviewed.
Copper losses for a flyback transformer are calculated in
[46–48] based on the detailed analysis given in [78]. Main
loss mechanisms are studied in detail in [78] using an
analytical approach. In [31], an equation for calculating
power losses in low-profile transformers is given, but the
comprehensive analysis is given in [32]. In [39], copper
losses are calculated using a 2D solution of diffusion
equation presented in [80]. The approach of [80] is also
used in [79] which gives the detailed loss analysis for [42,
43]. In [56, 57, 81], DC losses and eddy current losses are
calculated separately and superposition is applied for eddy
current, and finally, in [82] an approach introduced in [83]
is used which is claimed to be more accurate than 1D
solution to diffusion equation while being faster than
solving the equation numerically.
From this study on the papers, it is evident that a 1D
solution to diffusion equation (i.e. Dowell equation)
remains the mostly used method to calculate winding losses
in power electronic converters. Although Dowell equation is
obviously more accurate than using the DC resistance, it is
less accurate (and also less complex and faster) than a 2D
solution to diffusion equation. Some other methods such as
the method used in [56, 57, 81] is less accurate than Dowell
equation since it ignores proximity losses. The method
mentioned in [83] is also shown to be more accurate than
Dowell equation; however, the computational speed of two
methods has not been compared.
3.3
Semiconductor losses
Calculating semiconductor losses should be performed based
on the type of the switch and the circuit. In power electronics,
metal oxide semiconductor field effect transistors
(MOSFETs) and insulated gate bipolar transistors (IGBTs)
are used widely as primary switches, whereas diodes are
mostly used for freewheeling and providing a return path
for the current for one-directional MOSFETs and IGBTs.
Losses in semiconductor switches are a considerable portion
of the total losses of a power electronic converter, and
therefore precise loss modelling techniques are necessary
for accurate loss calculation. Owing to the complex nature
of the semiconductor materials and the large number of the
parameters involved, modelling loss mechanisms based on
geometry or other device-level characteristics of the device
is challenging. Therefore most papers do not include these
characteristics as design variables and instead prefer to
choose a switch from a database, and hence calculate losses
from information provided on the specific datasheet. In [23,
24, 29, 33–36, 38, 44, 46, 50, 52, 67–69, 71, 75, 77, 85,
87–89], at least one portion of semiconductor losses are
calculated from values provided by datasheet and scaling
them with current and/or voltage.
3.3.1 MOSFET losses: MOSFET conduction losses are
usually calculated using a simple on state equivalent
resistance [23, 24, 27, 29, 33–38, 44, 46, 50, 52, 67, 71,
75, 77, 84–86, 90–92]. In most of the papers, this resistance
(Rds,ON) is obtained from the MOSFET datasheet and
multiplied by RMS current square to calculate conduction
losses [23, 24, 29, 33–36, 38, 44, 46, 50, 52, 67, 71, 75,
77, 84, 85, 93, 94]. Some of the other papers attempt to
calculate or scale Rds,ON based on some device-level
characteristics or operational characteristics of the
MOSFET. In [37], Rds,ON is obtained from the datasheet,
Table 3 Summary of MOSFET switching losses
Reference(s)
[67, 75, 98]
[29, 46, 68–72,
74]
[41, 44, 50]
[95]
[73, 90, 91]
[27]
[23, 33–37, 39,
62, 63]
[97]
Descriptions
from capacitance values obtained from
datasheet
from rise time and fall time obtained from
datasheet
switching energy is scaled with voltage and
current
capacitance values scaled with length and
width of MOSFET die
capacitance values from width of MOSFET
die
capacitance values calculated from chip area
empirical equation for soft-switched
converters
model for a series–parallel resonant
converter
Table 4 Summary of conduction losses in MOSFETs
Reference(s)
[37]
[72]
[27]
[73, 90]
[91]
[39, 41]
Descriptions
Rds,ON is scaled with junction temperature
Rds,ON is scaled with rated voltage
Rds,ON from MOSFET chip area
Rds,ON from MOSFET die width
Rds,ON from MOSFET die width and applied gate
voltage
Rds,ON from junction temperature and current
extracted from datasheet
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but is scaled with junction temperature of the MOSFET. In
[52], Rds,ON is scaled with maximum blocking voltage of
MOSFET. In [27], Rds,ON is calculated from MOSFET chip
area. In [86, 90], Rds,ON is calculated from the MOSFET
width, and in [91] Rds,ON is calculated from MOSFET
width and applied gate voltage. In [39, 41], Rds,ON is
calculated from junction temperature and load current based
on the values extracted from the datasheet. A summary of
conduction loss calculation for MOSFETs is given in Table 4.
MOSFET switching losses depend highly on the type of
the converter and its control strategy. In hard switched
converters, energy loss during one cycle is calculated using
either equivalent capacitance [27, 67, 75, 84, 86, 90, 91,
95] or rise time and fall time of the MOSFET voltage and
current [29, 46, 52, 68, 69, 71, 85]. In some other papers,
turn-on and/or turn-off energy is directly used to calculate
switching losses [41, 44, 50], scaling them with the voltage
or current. Like Rds,ON, equivalent parasitic capacitance is
taken only from the datasheet in some of the papers [67,
75, 84], whereas in some others, it is calculated or scaled
from the device-level characteristics. In [95], equivalent
capacitance changes with the width and length of the each
MOSFET. In [86, 90, 91], capacitance is calculated from
width of the MOSFETs, and in [27] it is calculated from
area of the MOSFET.
In soft-switched converters, however, calculating
switching losses cannot be performed using the
above-mentioned approaches. Therefore detailed loss
analysis or empirical equations are required for these types
of converters. In [23, 24, 33–39], empirical equations have
been derived from measurement and curve fit to express
switching losses, and in [96] a model for a series–parallel
resonant converter, presented in [97], is used. A summary
of methods for calculating MOSFET switching losses is
presented in Table 3.
Choosing a method for calculating MOSFET conduction
and switching losses depends highly on what the design
variables are for the optimisation. If parameters such as
MOSFET die area, drift region thickness etc. are among
design variables, the problem is entirely different from a
case where certain internal parameters of the MOSFET are
not subject to the optimisation. Therefore a direct
comparison between methods mentioned in Tables 3 and 4
is not meaningful. However, it can be said that if only
datasheet information is used to calculate losses, they have
to be adjusted to reflect changes because of operating
voltage and current. These equations are highly non-linear
and a simple scaling is not accurate [21].
3.3.2 IGBT losses: Unlike MOSFETs, IGBT forward
voltage drop is not purely resistive. Different ways of
modelling IGBT conduction losses in papers related to
power electronic optimisation can be summarised as
follows. In [87, 88], forward voltage drop of the IGBT has
a constant term and a non-linear term
B
VF = V0 + r0 IL con
(9)
where IL is the IGBT current. V0 is the fixed portion of
forward voltage drop, Bcon is a constant found from curve
fitting and r0 called ‘dynamical resistance’ is a function of
gate drive voltage. A similar equation is used in [99], which
is based on the model provided in [100], but details on
finding the parameters are not given. Considering Bcon = 1
the second term in forward voltage drop is only resistive,
which is the base of the approach used in [54]. In this
Table 5 Summary of loss calculation in IGBTs
Reference(s)
[87, 88, 99,
100]
[54]
[101–106]
[54, 68, 69, 87,
88]
[107, 108]
[109]
Descriptions
forward voltage drop: a fixed part and a
non-linear part
non-linear part is a function of gate resistance
and load current
switching losses from datasheet values and
parasitic component values
conduction and switching losses
inter-dependent
dependence of fixed part of forward voltage
drop to switching times
resistive part of forward voltage drop is a
function of maximum current
a comprehensive model using device-level
parameters
switching losses from datasheet values
switching energy from a non-linear equation
based on current
switching losses from linear interpolation
based on gate resistance
approach, fixed part of the forward voltage drop is derived,
based on switching characteristics of the IGBT, using a
surface fitting on available commercial samples. The
resistive part is derived from the commercial samples based
on maximum current of the IGBT.
A complete loss model for the IGBT and the diode is used
in [101–103], which is based on the model presented in [104–
106]. This model uses MATLAB/SIMULINK for modelling
losses based on certain physical attributes of the IGBT such
as active area and width of the IGBT die, doping level and
high-level carrier lifetime. The model is good for an IGBT
and a diode in a chopper cell; however, as explained in this
paper, most power electronic circuits can be reduced to a
chopper cell for the purpose of modelling and optimisation.
This model is able to calculate both conduction and
switching losses.
For switching losses, the usual approach is to find the
switching energy from the rise and fall time of the current
and voltage [54, 68, 69, 87, 88]. However, using non-linear
equations to find turn-on and turn-off energy is also
common [107, 108]. Linear interpolation is used in [109] to
find turn-on and turn-off energy losses considering the
effect of the gate resistance. Loss calculation for IGBTs is
summarised in Table 5.
Similar to MOSFETs, the differences between IGBT loss
calculation approaches are mostly because of the design
variables chosen for the modelling. It is evident from loss
calculation approaches both for MOSFETs and IGBTs that
loss modelling based on semiconductor design variables
(e.g. die area, doping concentration etc.) is still in its early
stages and more work is needed to be done in this area.
Table 6 Summary of diode losses
Reference(s)
[23, 27, 29, 33–37, 54, 62,
63, 70, 72, 77]
[39, 41, 46, 99]
[67]
[101–106]
Descriptions
fixed voltage drop from datasheet
fixed part and a resistive or
non-linear term
Shockley equation for diode voltage
drop
a comprehensive model using
device-level parameters
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Table 7 Summary of gate drive losses
Table 8 Summary of capacitor losses
Reference(s)
Reference(s)
[33–35, 90]
[91]
Descriptions
from gate capacitance, gate voltage and
frequency (from datasheet)
gate capacitance is calculated from geometry for
a monolithic buck converter
This will be explained more in Section 6. However, it can be
said that forward voltage drop and switching transition times
are highly non-linear [21] and any attempt that takes this
non-linearity into account (either via data fitting or physical
modelling) is considered more accurate.
3.3.3 Diode: Diode conduction losses are usually
calculated using a fixed forward voltage drop for the diode
in on state which is usually extracted from the datasheet
[23, 24, 27, 29, 33–38, 52, 54, 77, 85] and RMS current
2
(loss = voltage × drop × IRMS
). In some of the papers, a
resistive or non-linear term is also added to this fixed drop
[39, 41, 46, 99]. Other approaches used are using Shockley
equation for diode voltage drop instead of a fixed voltage
[67] and a comprehensive loss analysis for IGBT and diode
as explained in previous section [101–103]. A summary of
the diode losses calculation techniques is presented in
Table 6.
Considering fixed voltage drop for diode conduction losses
seems to be a good approximation; however, since diode
voltage drop is a non-linear term, any attempt to take this
non-linearity into consideration makes the modelling more
accurate. Depending on the design variables of the
optimisation problem, using Shockley equation yields the
best accuracy since it relies on semiconductor physics. In
addition, model used in [101–106] accurately models the
diode by solving the carrier distribution equation; however,
since it is used to model an IGBT-diode combination that
cannot be used directly in the circuits where diodes are not
used with IGBTs.
3.3.4 Gate drive losses: Even though gate drive losses
usually contribute little to the total power losses, they might
be significant, especially in a low-power [90, 91] or
high-efficiency [33–35, 37] converter. Gate drive losses are
almost exclusively calculated using the gate capacitance,
gate voltage and frequency [33–35, 90, 91]. In [91], this
capacitance is calculated from the geometry for a
monolithic buck converter. Gate drive losses are also
considered in [37], but the details are not given. A
summary of gate drive loss calculation is in Table 7.
Gate drive losses do not change significantly with load
conditions, and therefore gate drive loss calculation from
datasheet values yields a good accuracy. However, in
certain converters, such as monolithic converters, where
gate capacitances change significantly with design variables,
and there is no datasheet value for these capacitance values,
they are calculated in the optimisation process, and losses
are calculated accordingly [91].
3.4
Capacitor losses
Capacitor losses are usually calculated considering an
equivalent series resistance (ESR) for the capacitor [23–25,
34–38, 42, 43, 54, 71, 74, 75, 85, 107, 108]. This
resistance represents the power losses in the capacitor,
which is because of the resistance of conducting material
[23, 25, 34–37, 42, 43,
62, 63]
[54, 107, 108, 111, 112]
Descriptions
ESR calculated from tan δ
ESR calculated from tan δ and
capacitor geometry
and also dielectric losses. If the former part is neglected,
series resistance can be expressed as
ESR =
tan d
Cv
(10)
where C is the capacitance, ω is the frequency in radians and
tan δ is the loss angle which is nearly constant for each type of
dielectric. In [23–25, 34–38, 42, 43, 110], ESR because of the
dielectric losses is calculated from the above-mentioned
equation, whereas in [71, 74, 75, 85] no detail is given on
how to calculate the ESR. In [107, 108], a resistance is
added to the ESR to represent the losses because of
resistivity of the conducting parts, which is calculated from
the capacitor geometry for a wound metalised film
capacitor. A similar approach for the same type of capacitor
with different sets of equations is used in [54], which is
based on the analysis presented in [111, 112]. A summary
of capacitor loss calculation techniques is given in Table 8.
Capacitors are usually selected from a list of off-the-shelf
components; therefore it is customary to calculate capacitor
losses from tan δ, which is relatively fixed for a certain
dielectric [113]. However, tan δ only accounts for dielectric
losses, whereas capacitor losses also include conduction
losses in the metallic parts of the capacitor. Therefore, in
some of the references, a more detailed approach is taken to
calculate capacitor losses [54, 107, 108, 111, 112].
4
4.1
Size modelling
Inductors and transformers
Inductors and transformers are usually custom designed, and
therefore their size (weight or volume) can be calculated from
their geometry, which is a part of design variable set. This
approach is taken in [23–27, 33, 36, 38, 39, 42, 43, 54, 56,
57, 60, 114–121]. In another paper, volume of the inductor
is calculated from the area product of the inductor core
which can be considered indirect calculation from geometry
[39]. In [25, 42, 43], the volume of an integrated LC
module is calculated from the core and the winding geometry.
Table 9 Summary of modelling size of magnetic components
Reference(s)
[23, 25–27, 33, 36, 39, 42, 43,
54, 56, 57, 60, 62, 63, 114–
121]
[25, 42, 43]
[122, 123]
[46–48, 124]
[29]
Descriptions
from geometry
from geometry for an integrated
LC module
from stored energy
from inductance, maximum
current and maximum flux
density
directly from component catalog
1198
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If geometric parameters are not a part of the variable set,
the size of the magnetic components are calculated from
other approaches. In [122, 123], inductor volume is
calculated from the stored energy, whereas in [123] it also
depends on inductance and maximum current. In [46–48,
124], the inductor volume is calculated from an empirical
equation based on inductance, maximum current and
maximum flux density, and in [29] inductor volume is
directly extracted from a catalog of off-the-shelf
components. A summary of size modelling for magnetic
components is given in Table 9.
Calculating size from geometry is obviously the ultimate
way; however, in problems where magnetic components are
not detailed-designed, finding the volume from stored
energy can also yield good accuracy assuming that the
magnetic core is utilised efficiently, that is, magnetic core is
utilised in all four quadrants of the B–H loop, and up to its
maximum flux density.
4.2
Reference(s)
[46]
[23, 27, 33, 36, 62,
63, 125]
Descriptions
estimated from thermal resistance
a CSPI introduced for each heat sink,
optimisation looks for higher CSPI
optimisation papers. In [46], heat sink volume is estimated
from the required thermal resistance and is then compared
with some manufacturer data; however, the manufacturer
name and sample size is not known. In [47, 48], the size of
the heat sink is somehow estimated but not explained, and
in [23, 24, 27, 33, 36, 38], a concept called cooling system
performance index (CSPI) which is presented in [125] is
used. CSPI is defined as follows
CSPI =
Capacitors
Unlike inductors, capacitors are not usually custom designed,
and therefore their volume usually should be approximated, if
not extracted directly from a catalog, which is the case in [29,
33, 46, 56, 57]. Other approaches include calculating
capacitance volume from its stored energy [27, 122, 123],
or from an empirical formula based on its capacitance
obtained from a curve fit, or given by the manufacturer [23,
24, 36, 38, 48, 117–120, 124].
In some of the papers, however, capacitors are also custom
designed, and therefore their volume is calculated from their
geometry. In [115, 116], an integrated LC filter is designed,
and therefore total volume is calculated from the geometry
of the components including the capacitor. A planar
integrated passive module is designed in [42, 43], in which
total volume depends on geometry of the integrated
components, that is, the capacitor and the inductor, and in
[54], volume of a film capacitor is calculated directly from
its geometry. Capacitor modelling techniques are
summarised in Table 10.
Size approximations for capacitors are difficult to compare
since most of the approaches are mostly empirical and
application-specific. This may suggest that more research
should be conducted on size approximation for capacitors,
which will be explained more in Section 6.
4.3
Table 11 Summary of size modelling for heat sinks
Heat sink
Calculating heat sink size from analytical equations for heat
dissipation is very complicated, since heat sinks come in a
wide variety of shapes, which makes it difficult to tie their
thermal resistance to their weight or volume. Therefore
some estimation techniques are applied in power electronic
1
Rth, s−a VCS
(11)
where Rth,s−a is the surface-to-ambient thermal resistance and
VCS is the volume of the heat sink. According to [125], a
higher CSPI means a higher-power density for the converter
in which the heat sink is used. Therefore the approach in
[23, 24, 27, 33, 36, 38] is using a heat sink with higher
CSPI. Finding the volume of such a heat sink is then
reduced to find the surface-to-ambient thermal resistance
required by semiconductor switches. Size modelling
methods of heat sinks are listed in Table 11.
5
Cost modelling
Cost of the converter is an important objective function in
many of the designs. In fact, high-production costs may be
a barrier for using some technologies, which are desirable
for certain applications. Owing to complexity of the pricing
process, in which economics is involved, most of the power
electronic optimisation papers either use component cost
(i.e. price) from the catalogs or use a curve fit to find the
cost from certain attributes of the components. In [29, 107,
108, 126], price of the commercial off-the-shelf
components are used as their cost, whereas in [127–129]
cost of resistor, inductor and capacitor is approximated from
their resistance, inductance and capacitance, respectively. In
[130–133], cost of the components is approximated from
cost of actual off-the-shelf components; however, no detail
is given on which attributes have been taken into account.
In [65, 66, 82], cost of stranded wires is estimated from
their diameter and number, and in [39] cost of a
semiconductor chip is estimated from its surface area. A
summary of cost modelling methods is presented in Table 12.
Table 10 Summary of modelling size of capacitors
Table 12 Summary of cost modelling
Reference(s)
Descriptions
Reference(s)
[29, 33, 46, 56, 57]
[27, 122, 123]
[23, 36, 48, 62, 63, 117–
120, 124]
[115, 116]
[42, 43]
[54]
size extracted directly from catalog
from stored energy
empirical equation based on
capacitance
from geometry for an integrated LC
module
from geometry for a planar integrated
passive module
from geometry for a film capacitor
[29, 107, 108,
126]
[127–129]
[65, 66, 82]
[39]
Descriptions
from price of off-the-shelf components
cost of passive components is approximated
from value
cost of stranded wire estimated from strand
diameter and number
cost of a semiconductor chip is estimated from
surface area
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Given the difficulties of estimating economic value of a
certain component or converter, all of the cost modelling
approaches are only low-order approximations. Cost
modelling approaches in Table 12 are application-specific
and cannot be compared with each other directly.
6
Recommendations for future work
Even though many papers have been published on power
electronic design optimisation, there is still plenty of work
which can be done to make the design optimisation
techniques more effective. A list of recommendations to
improve power electronic design optimisation is as follows:
† Modelling of core losses: as explained in Section 3.1,
calculating hysteresis losses from physical attributes of the
core with non-sinusoidal flux waveforms is still based on
the Steinmetz equation approximation. Introducing a simple
and effective way of calculating losses because of minor
loops will enable a more accurate core loss calculation,
which leads to a better optimisation.
† Semiconductor modelling: because of the complex nature
of semiconductors, little work has been done that presents a
relationship between the device-level characteristics of
semiconductor devices and their circuit behaviour. For
instance, even though a tradeoff between IGBT speed and
forward voltage drop is known for many years, lack of an
easy way to estimate IGBT losses from its device-level
attributes forces researchers to limit their work to existing
semiconductor devices. Modelling semiconductor devices
with a deeper look into semiconductor physics will help the
researchers to explore the whole design space of
semiconductor devices and not only the commercial
off-the-shelf components.
† Capacitor modelling: capacitor losses have been calculated
from a very simple equation (9) for many years, which only
accounts for the dielectric losses. Conduction losses
because of the resistance of the conducting parts might be
significant especially in aluminium electrolytic capacitors,
where high losses results in the liquid electrolyte to dry out
gradually and capacitor to fail. Estimating these losses from
low-level characteristics of the capacitor such as dimensions
or characteristics of electrolyte will enable a better
estimation of losses and perhaps lifetime of the capacitor.
Moreover, (9) is only valid when capacitor is carrying a
sinusoidal current and superposition cannot be applied
because of the dielectric losses being non-linear by nature.
A solution to this problem will also be beneficial for power
electronic design optimisation.
† Modelling of thermal management devices: modelling of
heat sinks is very important in calculating the total size of
the converter, but little attention has been paid to cost and
size modelling of heat sinks. This might be because of
difficulties of modelling thermal conduction in heat sinks
and incorporating such analysis into a power electronic
design problem. However, because of significance of heat
sinks in total weight and volume of power converters, a
descriptive modelling technique can be really helpful.
† Modelling power electronic system behaviour: most of the
modelling techniques used in the optimisation use some kind
of technique to represent time-domain voltage and current
information by single or multiple algebraic values such as
RMS values, harmonic content etc. This may result in
oversimplification of some of the models. Using the
time-domain information by itself is usually challenging
because of its computational burden; however, with
computing power becoming less expensive every day, a
comprehensive converter modelling in time domain and
calculating performance indices (loss, size etc.) from these
models can be very beneficial.
7
Conclusion
Significance of electrical energy in global energy usage and
role of power electronics in processing electric power in
low and high levels requires effective methods for design of
power electronic converters. In this paper, a review of
modelling techniques used in design optimisation of the
power electronic converters was presented. Modelling
techniques for power losses, weight and volume and cost
were presented and analysed. Owing to the diversity of
converters and components in power electronics, analysis
presented in this paper would be beneficial for the
researchers in this area.
8
References
1 U.S. Energy Information Administration. Annual Energy Outlook
2011. Available at http://www.eia.gov/forecasts/aeo/pdf/0383(2011).
pdf
2 Cronin, M.J.J.: ‘The all-electric aircraft’, IEE Rev., 1990, 36, (8),
pp. 309–311
3 Madawala, U.K., Thrimawithana, D.J.: ‘A bidirectional inductive
power interface for electric vehicles in V2G systems’, IEEE Trans.
Ind. Electron., 2011, 58, (10), pp. 4789–4796
4 Pahlevaninezhad, M., Drobnik, J., Jain, P.K., Bakhshai, A.: ‘A load
adaptive control approach for a zero-voltage-switching DC/DC
converter used for electric vehicles’, IEEE Trans Ind. Electron.,
2012, 59, (2), pp. 920–933
5 Fahimi, B., Kwasinski, A., Davoudi, A., Balog, R.S., Kiani, M.:
‘Charge It!’, IEEE Power and Energy Magazine, 2011, 9, (4),
pp. 54–64
6 Cisco Systems. Cisco Visual Networking Index: Forecast and
Methodology, 2011–2016. Available at http://www.cisco.com/en/US/
solutions/collateral/ns341/ns525/ns537/ns705/ns827/
white_paper_c11-481360.pdf
7 Wen, O., Zarko, D., Lipo, T.A.: ‘Permanent magnet machine design
practice and optimization’. Industry Applications Conf., 2006. Proc.
41st IAS Annual Meeting Conf. Record of the 2006 IEEE, 2006,
pp. 1905–1911
8 Wenying, J., Jahns, T.M., Lipo, T.A., Taylor, W., Suzuki, Y.: ‘Machine
design optimization based on finite element analysis in a
high-throughput computing environment’. 2012 IEEE Energy
Conversion Congress and Exposition (ECCE), 2012, pp. 869–876
9 Koenig, A.C., Williams, J.M., Pekarek, S.D.: ‘Evaluation of alternative
evolutionary programming techniques for optimization of an
automotive alternator’, IEEE Trans. Veh. Technol., 2006, 55, (3),
pp. 933–942
10 Krizan, J.A., Sudhoff, S.D.: ‘A design model for salient
permanent-magnet machines with investigation of saliency and
wide-speed-range performance’, IEEE Trans. Energy Conv., 2013,
28, (1), pp. 95–105
11 Laldin, O., Sudhoff, S.D., Pekarek, S.D.: ‘An analytical design model
for wound rotor synchronous machines’. IEEE Electric Ship
Technologies Symp. (ESTS), 2013, pp. 228–236
12 Taher, A.A., Pekarek, S.D.: ‘Multi-objective design of
mechanically-commutated DC machines’. 2013 IEEE Int. Electric
Machines & Drives Conf. (IEMDC), 2013, pp. 1397–1404
13 Chong, E.K.P., Zak, S.H.: ‘An introduction to optimization’
(Wiley, New York, 2001)
14 Altinoz, O.T., Erdem, H.: ‘Evaluation function comparison of particle
swarm optimization for buck converter’. 2010 Int. Symp. Power
Electronics Electrical Drives Automation and Motion (SPEEDAM),
2010, pp. 798–802
15 Davoudi, A., Na, K., Hagen, M., Muegel, M., Chapman, P.L.: ‘A
general framework for automated tuning of digital controllers in
multi-phase Dc-Dc Converters’. IEEE Applied Power Electronics
Conf. Expo (APEC), 2009, pp. 626–630
16 Al-Hoor, W., Abu-Qahouq, J., Huang, L., et al.: ‘Multivariable
adaptive efficiency optimization digital controller’. IEEE Power
1200
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1192–1203
This is an open access article published by the IET under the Creative Commons Attributiondoi: 10.1049/iet-pel.2013.0321
NonCommercial-NoDerivs License (http://creativecommons.org/licenses/by-nc-nd/3.0/)
www.ietdl.org
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Electronics Specialists Conf., 2008 (PESC 2008), 2008,
pp. 4590–4596
Kouzou, A., Saadi, S., Mahmoudi, M.O., Boucherit, M.S.: ‘Particle
swarm optimization applied for the improvement of the PWM AC/
AC choppers voltage’. Compatibility and Power Electronics, 2009
(CPE ’09), 2009, pp. 146–152
Goldberg, D.E.: ‘Genetic algorithms in search, optimization, and
machine learning’ (Addison-Wesley Pubishing Co., Reading, Mass,
1989)
Kennedy, J., Eberhart, R.: ‘Particle swarm optimization’. IEEE Int.
Conf. Neural Networks, 1995, pp. 1942–1948
Kirkpatrick, S., Gelatt Jr., C.D., Vecchi, M.P.: ‘Optimization by
simulated annealing’, Science, 1983, 220, (4598), pp. 671–680
Baliga, B.J.: ‘Fundamentals of power semiconductor devices’
(Springer, Berlin, 2008)
Kazimierczuk, M.: ‘High-frequency magnetic components’ (J. Wiley,
Chichester, UK, 2009)
Badstuebner, U., Biela, J., Kolar, J.W.: ‘Power density and efficiency
optimization of resonant and phase-shift telecom DC-DC converters’.
IEEE Applied Power Electronics Conf. Exposition (APEC) 2008,
pp. 311–317
Biela, J., Badstubner, U., Kolar, J.W.: ‘Design of a 5 kW, 1U, 10 kW/
ltr. resonant DC-DC converter for telecom applications’. Proc. 29th Int.
Telecommunications Energy Conf. (INTELEC), 2007, pp. 824–831
Lingyin, Z., Strydom, J.T., van Wyk, J.D.: ‘Optimization and design of
an integrated LC resonant module for medium and high power
applications’. Power Electronics Specialists Conf. (PESC), 2001,
pp. 594–599
Sagawa, N., Sekiya, H., Kazimierczuk, M.K.: ‘Computer-aided design
for class-E switching circuits taking into account optimized inductor
designs’. IEEE Applied Power Electronics Conf. Exposition (APEC),
2010, pp. 2212–2219
Kolar, J.W., Biela, J., Minibock, J.: ‘Exploring the pareto front of
multi-objective single-phase PFC rectifier design optimization –
99.2% efficiency vs. 7 kW/din3 power density’. Int. Power
Electronics and Motion Control Conf. (IPEMC), 2009, pp. 1–21
Liffran, F.: ‘A procedure to optimize the inductor design in boost PFC
applications’. Power Electronics and Motion Control Conf.
(EPE-PEMC), 2008, pp. 409–416
Helali, H., Bergogne, D., Slama, J.B.H., et al.: ‘Power converter’s
optimisation and design. Discrete cost function with genetic based
algorithms’. European Conf. Power Electronics and Applications,
2005, pp. P.1–P.7
Hengsi, Q., Kimball, J.W., Venayagamoorthy, G.K.: ‘Particle swarm
optimization of high-frequency transformer’. Conf. IEEE Industrial
Electronics Society (IECON), 2010, pp. 2914–2919
Dai, N., Lee, F.C.: ‘An algorithm of high-density low-profile
transformers optimization’. IEEE Applied Power Electronics Conf.
Exposition (APEC), 1997, pp. 918–924
Dai, N.: ‘Modeling, analysis, and design of high-frequency
high-density low-profile power transformers’. PhD dissertation,
Virginia Polytechnic Institute and State University, Blacksburg, 2002
Badstuebner, U., Biela, J., Faessler, B., Hoesli, D., Kolar, J.W.: ‘An
optimized 5 kW, 147 W/in3 telecom phase-shift DC-DC converter
with magnetically integrated current doubler’. IEEE Applied Power
Electronics Conf. Exposition (APEC), 2009, pp. 21–27
Badstuebner, U., Biela, J., Kolar, J.W.: ‘An optimized, 99% efficient,
5 kW, phase-shift PWM DC-DC converter for data centers and
telecom applications’. Int. Power Electronics Conf. (IPEC), 2010,
pp. 626–634
Badstuebner, U., Biela, J., Kolar, J.W.: ‘Design of an 99%-efficient, 5
kW, phase-shift PWM DC-DC converter for telecom applications’.
IEEE Applied Power Electronics Conf. Exposition (APEC), 2010,
pp. 773–780
Biela, J., Badstuebner, U., Kolar, J.W.: ‘Impact of power density
maximization on efficiency of DC-DC converter systems’, IEEE
Trans. Power Electronics, 2009, 24, (1), pp. 288–300
Biela, J., Kolar, J.W., Deboy, G.: ‘Optimal design of a compact 99.3%
efficient single-phase PFC rectifier’. IEEE Applied Power Electronics
Conf. Exposition (APEC), 2010, pp. 1397–1404
Kolar, J.W., Biela, J., Badstubner, U.: ‘Impact of power density
maximization on efficiency of dc-dc converter systems’. Proc.
Seventh Int. Conf. Power Electronics, 2007, pp. 23–32
Waffler, S., Preindl, M., Kolar, J.W.: ‘Multi-objective optimization and
comparative evaluation of Si soft-switched and SiC hard-switched
automotive DC-DC converters’. Conf. IEEE Industrial Electronics
(IECON), 2009, pp. 3814–3821
Venkatachalam, K., Sullivan, C.R., Abdallah, T., Tacca, H.: ‘Accurate
prediction of ferrite core loss with nonsinusoidal waveforms using only
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Steinmetz parameters’. IEEE Workshop on Computers in Power
Electronics, 2002, pp. 36–41
Rigbers, K., Schroder, S., Durbaum, T., Wendt, M., De Doncker, R.W.:
‘Integrated method for optimization of power electronic circuits’.
Power Electronics Specialists Conf. (PESC), 2004, pp. 4473–4478
Strydom, J.T., van Wyk, J.D.: ‘Electromagnetic design optimization of
planar integrated power passive modules’. Power Electronics
Specialists Conf. (PESC), 2002, pp. 573–578
Strydom, J.T., van Wyk, J.D.: ‘Electromagnetic design optimization
tool for resonant integrated spiral planar power passives (ISP3)’,
IEEE Trans. Power Electronics, 2005, 20, (4), pp. 743–753
Yu, R., Pong, B., Ling, B., Lam, J.: ‘Two-stage optimization method
for efficient power converter design including light load operation’,
IEEE Trans. Power Electron., 2011, 27, (3), pp. 1327–1337
Albach, M., Durbaum, T., Brockmeyer, A.: ‘Calculating core losses in
transformers for arbitrary magnetizing currents a comparison of
different approaches’. Power Electronics Specialists Conf. (PESC),
1996, pp. 1463–1468
Ejjabraoui, K., Larouci, C., Lefranc, P., Marchand, C.: ‘A pre-sizing
approach of DC-DC converters, application to design a buck
converter for the automotive domain’. Int. Power Electronics and
Motion Control Conf. (IPEMC), 2009, pp. 517–523
Larouci, C., Didier, J.P., Aldebert, A., et al.: ‘Optimal design of a
synchronous DC-DC converter using analytical models and a
dedicated optimization tool’. Conf. IEEE Industrial Electronics
Society (IECON), 2003, pp. 1623–1628
Larouci, C., Ferrieux, J.P., Gerbaud, L., Roudet, J., Keradec, J.P.:
‘Volume optimization of a PFC flyback structure under
electromagnetic compatibility, loss and temperature constraints’.
Power Electronics Specialists Conf. (PESC), 2002, pp. 1120–1125
Larouci, C., Ferrieux, J.P., Gerbaud, L., Roudet, J., Catellani, S.:
‘Experimental evaluation of the core losses in the magnetic
components used in PFC converters. Application to optimize the
flyback structure losses’. IEEE Applied Power Electronics Conf.
Exposition (APEC), 2002, pp. 326–331
Jieli, L., Sullivan, C.R., Schultz, A.: ‘Coupled-inductor design
optimization for fast-response low-voltage’. IEEE Applied Power
Electronics Conf. Exposition (APEC), 2002, pp. 817–823
Jieli, L., Abdallah, T., Sullivan, C.R.: ‘Improved calculation of core
loss with nonsinusoidal waveforms’. Industry Applications Conf.,
2001, pp. 2203–2210
Kjaer, S.B., Blaabjerg, F.: ‘Design optimization of a single phase
inverter for photovoltaic applications’. Proc. 34th IEEE Annual
Power Electronics Specialist Conf. (PESC), 2003, pp. 1183–1190
Reinert, J., Brockmeyer, A., De Doncker, R.W.: ‘Calculation of losses
in ferro- and ferrimagnetic materials based on the modified Steinmetz
equation’. Industry Applications Conf., 1999, pp. 2087–2092
Mirjafari, M., Balog, R.S.: ‘Multi-objective design optimization of
renewable energy system inverters using a descriptive language for
the components’. IEEE Applied Power Electronics Conf. Exposition
(APEC), 2011, pp. 1838–1845
Van den Bossche, A., Valchev, V.C.: ‘Inductors and transformers for
power electronics’ (Taylor & Francis, Boca Raton, 2005)
Chen, G., Rentzch, M., Wang, F., et al.: ‘Analysis and design
optimization of front-end passive components for voltage source
inverters’. IEEE Applied Power Electronics Conf. Exposition
(APEC), 2003, pp. 1170–1176
Fei, W., Gang, C., Boroyevich, D.: ‘Analysis and design optimization
of diode front-end rectifier passive components for voltage source
inverters’, IEEE Trans. Power Electronics, 2008, 23, (5),
pp. 2278–2289
Shen, W., Wang, F., Boroyevich, D., Tipton, C.W.: ‘Loss
characterization and calculation of nanocrystalline cores for
high-frequency magnetics applications’, IEEE Trans. Power
Electronics, 2008, 23, (1), pp. 475–484
Sullivan, C.R.: (2012). Overview of core loss prediction for
non-sinusoidal waveforms. Available at http://engineering.dartmouth.
edu//inductor/Sullivan_APEC_2012_core_loss%20overview_with_
references.pdf
Daniel, L., Sullivan, C.R., Sanders, S.R.: ‘Design of microfabricated
inductors’, IEEE Trans. Power Electron., 1999, 14, (4), pp. 709–723
Hurley, W.G., Gath, E., Breslin, J.G.: ‘Optimizing the AC resistance of
multilayer transformer windings with arbitrary current waveforms’,
IEEE Trans. Power Electron., 2000, 5, (2), pp. 369–376
Biela, J., Badstubner, U., Kolar, J.W.: ‘Design of a 5 kW, 1U, 10 kW/
ltr. Resonant DC-DC converter for telecom applications’. Int.
Telecommunications Energy Conf. (INTELEC), 2007, pp. 824–831
Kolar, J.W., Biela, J., Badstubner, U.: ‘Impact of power density
maximization on efficiency of dc-dc converter systems’. Int. Conf.
Power Electronics, 2007, pp. 23–32
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1192–1203
1201
doi: 10.1049/iet-pel.2013.0321
This is an open access article published by the IET under the Creative Commons AttributionNonCommercial-NoDerivs License (http://creativecommons.org/licenses/by-nc-nd/3.0/)
www.ietdl.org
64 Sullivan, C.R.: ‘Optimal choice for number of strands in a litz-wire
transformer winding’, IEEE Trans. Power Electron., 1999, 14, (2),
pp. 283–291
65 Sullivan, C.R., Abdallah, T., Fujiwara, T.: ‘Optimization of a flyback
transformer winding considering two-dimensional field effects, cost
and loss’. IEEE Applied Power Electronics Conf. Exposition
(APEC), 2001, pp. 116–122
66 Sullivan, C.R., McCurdy, J.D., Jensen, R.A.: ‘Analysis of minimum
cost in shape-optimized litz-wire inductor windings’. Power
Electronics Specialists Conf. (PESC), 2001, pp. 1473–1478
67 Carli, D., Brunelli, D., Bertozzi, D., Benini, L.: ‘A high-efficiency
wind-flow energy harvester using micro turbine’. Int. Symp. Power
Electronics Electrical Drives Automation and Motion (SPEEDAM),
2010, pp. 778–783
68 Combrink, F.W., Mouton, H.de.T., Enslin, J.H.R.: ‘Design
optimisation of a new active resonant snubber for high power IGBT
converters’. Power Electronics Specialists Conf. (PESC), 2000,
pp. 1469–1475
69 Combrink, F.W., Mouton, H.T., Enslin, J.H.R., Akagi, H.: ‘Design
optimization of an active resonant snubber for high power IGBT
converters’, IEEE Trans. Power Electron., 2006, 21, (1), pp. 114–123
70 Gerber, M., Ferreira, J.A., Hofsajer, I.W., Seliger, N.: ‘Interleaving
optimization in synchronous rectified DC/DC converters’. Power
Electronics Specialists Conf. (PESC), 2004, pp. 4655–4661
71 Gezgin, C., Heck, B.S., Bass, R.M.: ‘Simultaneous design of power
stage and controller for switching power supplies’, IEEE Trans.
Power Electron., 1997, 12, (3), pp. 558–566
72 Kjaer, S.B., Blaabjerg, F.: ‘Design optimization of a single phase
inverter for photovoltaic applications’. Power Electronics Specialists
Conf. (PESC), 2003, pp. 1183–1190
73 Musunuri, S., Chapman, P.L.: ‘Design of low power monolithic
DC-DC buck converter with integrated inductor’. Power Electronics
Specialists Conf. (PESC), 2005, pp. 1773–1779
74 Oraw, B.S., Ayyanar, R.: ‘Voltage regulator optimization using
multiwinding coupled inductors and extended duty ratio
mechanisms’, IEEE Trans. Power Electron., 2009, 24, (6),
pp. 1494–1505
75 Xunwei, Z., Wang, T.G., Lee, F.C.: ‘Optimizing design for low voltage
DC-DC converters’. IEEE Applied Power Electronics Conf. Expo
(APEC), 1997, pp. 612–616
76 Farhangi, B., Butler-Purry, K.L.: ‘Transient study of DC zonal
electrical distribution system in next generation shipboard integrated
power systems using PSCAD™’. North American Power Symp.
(NAPS), 2009, pp. 1–8
77 Marxgut, C., Biela, J., Kolar, J.W., et al.: ‘DC-DC converter for gate
power supplies with an optimal air transformer’. IEEE Applied
Power Electronics Conf. Expo (APEC), 2010, pp. 1865–1870
78 Larouci, C., Keradec, J.P., Ferrieux, J.P., et al.: ‘Copper losses of
flyback transformer: search for analytical expressions’, IEEE Trans
Magn., 2003, 39, (3), pp. 1745–1748
79 Strydom, J.T., van Wyk, J.D.: ‘Improved loss determination for planar
integrated power passive modules’. IEEE Applied Power Electronics
Conf. Exposition (APEC), 2002, pp. 332–338
80 Ferreira, J.A.: ‘Analytical computation of AC resistance of round and
rectangular litz wire windings’, IEE Proc. Electr. Power Appl., 1992,
139, (1), pp. 21–25
81 Jensen, R.A., Sullivan, C.R.: ‘Optimal core dimensional ratios for
minimizing winding loss in high-frequency gapped-inductor
windings’. IEEE Applied Power Electronics Conf. Exposition
(APEC), 2003, pp. 1164–1169
82 Xu, T., Sullivan, C.R.: ‘Optimization of stranded-wire windings and
comparison with litz wire on the basis of cost and loss’. Power
Electronics Specialists Conf. (PESC), 2004, pp. 854–860
83 Sullivan, C.R.: ‘Computationally efficient winding loss calculation
with multiple windings, arbitrary waveforms, and two-dimensional or
three-dimensional field geometry’, IEEE Trans. Power Electron.,
2001, 16, (1), pp. 142–150
84 Haizoune, F., Bergveld, H.J., Popovic-Gerber, J., Ferreira, J.A.:
‘Topology comparison and design optimisation of the buck converter
and the single-inductor dual-output converter for system-in-package
in 65 nm CMOS’. Proc. Sixth Int. Power Electronics and Motion
Control Conf. (IPEMC), 2009, pp. 295–301
85 Gerber, M., Ferreira, J.A., Hofsajer, I.W., Seliger, N.: ‘Interleaving
optimization in synchronous rectified DC/DC converters’. IEEE
Power Electronics Specialists Conf. (PESC), 2004, pp. 4655–4661
86 Musunuri, S., Chapman, P.L.: ‘Design of low power monolithic
DC-DC buck converter with integrated inductor’. Proc. 36th Power
Electronics Specialists Conf. (PESC), 2005, pp. 1773–1779
87 Blaabjerg, F., Pedersen, J.K.: ‘Optimized design of a complete
three-phase PWM-VS inverter’. Power Electronics Specialists Conf.
(PESC), 1996, pp. 1272–1280
88 Blaabjerg, F., Pedersen, J.K.: ‘Optimized design of a complete
three-phase PWM-VS inverter’, IEEE Trans. Power Electron., 1997,
12, (3), pp. 567–577
89 Yeung, H.H.T., Poon, N.K., Lai, S.L.: ‘Generic optimization for SMPS
design with smart scan and genetic algorithm’. Int. Power Electronics
and Motion Control Conf. (IPEMC), 2006, pp. 1–5
90 Musunuri, S., Chapman, P.L.: ‘Optimization of CMOS transistors for
low power DC-DC converters’. Power Electronics Specialists Conf.
(PESC), 2005, pp. 2151–2157
91 Takayama, T., Maksimovic, D.: ‘A power stage optimization method
for monolithic DC-DC converters’. Power Electronics Specialists
Conf. (PESC), 2006, pp. 1–7
92 Farhangi, B., Toliyat, H.A.: ‘Modeling isolation transformer capacitive
components in a dual active bridge power conditioner’. IEEE Energy
Conversion Congress & Expo (ECCE), Denver, Colorado, 2013
93 Farhangi, B., Farhangi, S.: ‘Comparison of z-source and boost-buck
inverter topologies as a single phase transformer-less photovoltaic
grid-connected power conditioner’. IEEE Power Electronics
Specialists Conf. (PESC), 2006, pp. 1–6
94 Farhangi, B., Farhangi, S.: ‘Application of Z-source converter in
photovoltaic grid-connected transformer-less inverter’, Electr. Power
Qual. Utilisation, 2006, 12, (2), pp. 41–45
95 Chowdhury, I., Dongsheng, M.: ‘Design of reconfigurable and robust
integrated sc power converter for self-powered energy-efficient
devices’, IEEE Trans. Ind. Electron., 2009, 56, (10), pp. 4018–4028
96 Soeiro, T., Biela, J., Muhlethaler, J., et al.: ‘Optimal design of resonant
converter for electrostatic precipitators’. Int. Power Electronics Conf.
(IPEC), 2010, pp. 2294–2301
97 Ivensky, G., Kats, A., Ben-Yaakov, S.: ‘A novel RC model of
capacitive-loaded parallel and series-parallel resonant DC-DC
converters’. Power Electronics Specialists Conf. (PESC), 1997,
pp. 958–964
98 Haizoune, F., Bergveld, H.J., Popovic-Gerber, J., Ferreira, J.A.:
‘Topology comparison and design optimisation of the buck converter
and the single-inductor dual-output converter for system-in-package
in 65 nm CMOS’. Int. Power Electronics and Motion Control Conf.
(IPEMC), 2009, pp. 295–301
99 Kragh, H., Blaabjerg, F., Pedersen, J.K.: ‘An advanced tool for
optimised design of power electronic circuits’. Industry Applications
Conf., 1998, pp. 991–998
100 Clemente, S., Il, D.D.: ‘Accurate junction temperature calculation
optimizes IGBT selection for maximum performance and reliability’.
International Rectifier Corp., Technical Report, 1994
101 Bryant, A.T., Jaeggi, D.M., Parks, G.T., Palmer, P.R.: ‘The influence of
operating conditions on multi-objective optimization of power
electronic devices and circuits’. Industry Applications Conf., 2005,
pp. 1449–1456
102 Bryant, A.T., Yalan, W., Finney, S.J., Tee Chong, L., Palmer, P.R.:
‘Numerical optimization of an active voltage controller for
high-power IGBT converters’, IEEE Trans. Power Electron., 2007,
22, (2), pp. 374–383
103 Palmer, P.R., Bryant, A.T., Hudgins, J., Santi, E.: ‘Simulation and
optimisation of diode and IGBT interaction in a chopper cell using
MATLAB and Simulink’. Industry Applications Conf., 2002,
pp. 2437–2444
104 Bryant, A.T., Palmer, P.R., Santi, E., Hudgins, J.L.: ‘Simulation and
optimization of diode and insulated gate bipolar transistor interaction
in a chopper cell using MATLAB and Simulink’, IEEE Trans. Ind.
Appl., 2007, 43, (4), pp. 874–883
105 Leturcq, P.: ‘A study of distributed switching processes in IGBTs and
other power bipolar devices’. Power Electronics Specialists Conf.
(PESC), 1997, pp. 139–147
106 Palmer, P.R., Santi, E., Hudgins, J.L., et al.: ‘Circuit simulator models
for the diode and IGBT with full temperature dependent features’, IEEE
Trans. Power Electron., 2003, 18, (5), pp. 1220–1229
107 Pasterczyk, R.J., Guichon, J.M., Atienza, E.: ‘PWM inverter output
filter cost to losses trade off and optimal design’. IEEE Applied
Power Electronics Conf. Exposition (APEC), 2008, pp. 476–482
108 Pasterczyk, R.J., Guichon, J.M., Schanen, J.L., Atienza, E.: ‘PWM
inverter output filter cost-to-losses tradeoff and optimal design’,
IEEE Trans. Ind. Appl., 2009, 45, (2), pp. 887–897
109 Wang, F., Shen, W., Boroyevich, D., et al.: ‘Design optimization of
industrial motor drive power stage using genetic algorithms’. Int.
Power Electronics and Motion Control Conf. (IPEMC), 2006, pp. 1–5
110 Farhangi, B., Toliyat, H.A., Balaster, A.: ‘High impedance grounding
for onboard plug-in hybrid electric vehicle chargers’. IEEE Power
Engineering, Istanbul, Turkey, 2013
1202
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1192–1203
This is an open access article published by the IET under the Creative Commons Attributiondoi: 10.1049/iet-pel.2013.0321
NonCommercial-NoDerivs License (http://creativecommons.org/licenses/by-nc-nd/3.0/)
www.ietdl.org
111 Brown, R.W.: ‘Empirically-derived capacitor characteristic formulas
from distributed modelling’, IET Circuits Devices Syst., 2007, 1, (2),
pp. 117–125
112 Ho, J., Jow, T.R., Boggs, S., et al.: ‘Implications of advanced capacitor
dielectrics for performance of metallized film capacitor windings’,
IEEE Trans. Dielectr. Electr. Insul., 2008, 15, (6), pp. 1754–1760
113 Sarjeant, W.J., Zirnheld, J., MacDougall, F.W.: ‘Capacitors’, IEEE
Trans. Plasma Sci., 1998, 26, (5), pp. 1368–1392
114 Arab, M., Laboure, E., Costa, F.: ‘Design of an integrated
inductor-transformer LT component for power electronic
applications’. Power Electronics Specialists Conf. (PESC), 2004,
pp. 4861–4866
115 Gerber, M., Ferreira, J.A., Hofsajer, I.W.: ‘A volumetric optimization
of a low-pass filter’, IEEE Trans. Ind. Appl., 2002, 38, (5),
pp. 1432–1440
116 Gerber, M., Ferreira, J.A., Hofsajer, I.W., Seliger, N.: ‘A volumetric
optimization of a low pass filter’. Industry Applications Conf., 2001,
pp. 2224–2231
117 Griffo, A., Wang, J.: ‘Design optimization of passive DC filters for
aerospace applications’. IET Int. Conf. Power Electronics, Machines
and Drives (PEMD), 2010, pp. 1–6
118 Jourdan, L., Schanen, J.L., Roudet, J., et al.: ‘Design methodology for
non insulated DC-DC converter: application to 42 V-14 V ‘Powernet’.
Power Electronics Specialists Conf. (PESC), 2002, pp. 1679–1684
119 Tourkhani, F., Viarouge, P., Meynard, T.A.: ‘Optimal design and
experimental results of a multilevel inverter for an UPS application’.
Int. Conf. Power Electronics and Drive Systems, 1997, pp. 340–343
120 Tourkhani,
F.,
Viarouge,
P.,
Meynard,
T.A.:
‘A
simulation-optimization system for the optimal design of a multilevel
inverter’, IEEE Trans Power Electron., 1999, 14, (6), pp. 1037–1045
121 Wilmot, F., Laboure, E., Costa, F., et al.: ‘Design, optimization and
electromagnetic modeling of integrated passive components for
power electronic’. Power Electronics Specialists Conf. (PESC), 2001,
pp. 1932–1937
122 Chen, J.: ‘Minimizing input filter physical size subject to electrical
performance constraints [SMPS CAD]’. IEEE Applied Power
Electronics Conf. Exposition (APEC), 1996, pp. 347–353
123 Raggl, K., Nussbaumer, T., Kolar, J.W.: ‘Model based optimization of
EMC input filters’. Workshop on Control and Modeling for Power
Electronics (COMPEL), 2008, pp. 1–6
124 Barruel, F., Schanen, J.L., Retiere, N.: ‘Volumetric optimization of
passive filter for power electronics input stage in the more electrical
aircraft’. Power Electronics Specialists Conf. (PESC), 2004,
pp. 433–438
125 Drofenik, U., Laimer, G., Kolar, J.W.: ‘Theoretical converter power
density limits for forced convection cooling’. Int. PCIM Europe
Conf., 2005, pp. 608–619
126 Dialynas, E.N., Zafiropoulos, E.P.: ‘Reliability and cost optimization of
power electronic devices considering the component failure rate
uncertainty’. Bologna Power Tech Conf., 2003
127 He, N., Huang, L., Wu, J., Xu, D.: ‘Study on optimal design method for
passive power filters set at high voltage bus considering many practical
aspects’. IEEE Applied Power Electronics Conf. Exposition (APEC),
2008, pp. 396–401
128 Qiongq, C., Chen, Z., McCormick, M.: ‘The application and
optimization of C-type filter in a combined harmonic power filter’.
Power Electronics Specialists Conf. (PESC), 2004, pp. 1041–1045
129 Wei, Z., An, L., Ke, Z., Jingbin, W.: ‘Parameter design for improving
injection type hybrid active power filter performance in high power
grid’. Int. Power Electronics and Motion Control Conf. (IPEMC),
2009, pp. 1148–1154
130 Busquets-Monge, S., Crebier, C., Ragon, S., et al.: ‘Optimization
techniques applied to the design of a boost power factor correction
converter’. Power Electronics Specialists Conf. (PESC), 2001,
pp. 920–925
131 Busquets-Monge, S., Crebier, J.C., Ragon, S., et al.: ‘Design of a boost
power factor correction converter using optimization techniques’, IEEE
Trans Power Electron., 2004, 19, (6), pp. 1388–1396
132 Busquets-monge, S., Soremekun, G., Hefiz, E., et al.: ‘Power converter
design optimization’, IEEE Ind. Appl. Mag., 2004, 10, (1), pp. 32–38
133 Busquets-Monge, S., Soremekun, G., Hertz, E., et al.: ‘Design
optimization of a boost power factor correction converter using
genetic algorithms’. IEEE Applied Power Electronics Conf.
Exposition (APEC), 2002, pp. 1177–1182
IET Power Electron., 2014, Vol. 7, Iss. 5, pp. 1192–1203
1203
doi: 10.1049/iet-pel.2013.0321
This is an open access article published by the IET under the Creative Commons AttributionNonCommercial-NoDerivs License (http://creativecommons.org/licenses/by-nc-nd/3.0/)