Data Handling Processor Performance Test Results
Tetsuichi Kishishita, Bonn University DEPFET PXD ASIC Design Review, October 27-­‐28, 2014
Outline
• Verification results from prototype blocks (DHPT 0.1) – PLL & high speed serial link driver – Analog blocks (bias generator, temp. sensor) • DHPT 1.0 performance – Verification results – Known issues & mitigation strategies
DHP Design Review, Oct. 27, 2014
2
DHPT 0.1 Prototype Chip
PLL & GBIT DRIVER
DHP Design Review, Oct. 27, 2014
3
DHPT 0.1 -­‐ PLL & Gbit Driver
•
PLL –
–
•
Pseudo random bit sequence generator –
•
80 MHz reference clock 1.6 GHz, 800MHz & 320 MHz outputs 8 bit LFSR CML link driver with programmable pre-­‐emphasis –
–
Two differential pairs with adj. bias currents (tap weights a, b) Programmable delay dt
PLL_CML Test Chip,
T. Kishishita
320 MHz
CML driver TXO_P
TXO_N
320 MHz
80 MHz
PLL
50 Ω
800 MHz
1.6 GHz
LFSR
50 Ω
CML driver
TX1_P
TX1_N
pre
drv.
I0
I1
del
2
DHP Design Review, Oct. 27, 2014
dt
a
b
4
Driver Schematic
VDD
VDD
VSS
R12
VDD
R6
VDD
VDD
R13
R14
R15
VDD
"rnpolywo"
sumW=10u
sumL=12.9u
m:1
res=199.723
DON
"rnpolywo"
sumW:2u
sumL=12.9u
m:1
res=1.02364K
R16
R17
"rnpolywo"
sumW=10u
sumL=12.9u
m:1
res=199.723
DOP
VDD
R20
"rnpolywo"
sumW:2u
sumL=12.9u
m:1
res=1.02364K DON
VDD
VDD
VDD R19
R18
"rnpolywo"
"rnpolywo"
sumW=10u
sumW=10u
sumL=12.9u
sumL=12.9u
m:1
m:1
res=199.723 res=199.723
DOP
DON
main stage
INP
DOP
pre-­‐emphasis stage
DON
M11
M10
INP
INP
INP
VSS
VSS
M6
"nmos_rf_lvt"
totalW=45.0u
wr=1.5u
lr:60n
nr=30
CM_D m:1
M13
M12
VSS
VSS
VSS
CM_D
IBIAS_DRIVER
1 : 20
IBIAS_DRIVER
M2
M2
IBIAS_DRIVER
"nch_lvt_mac"
w=5u
l:60n
fingers=60
simM:1
totalM=60
DON
INPD
M4
"nmos_rf_lvt"
totalW=45.0u
net019
wr=1.5u
lr:60n
nr=30
m:1
M5
"nmos_rf_lvt"
totalW=45.0u
wr=1.5u
lr:60n
nr=30
m:1
DOP
INND
net019
INND
nr=30
m:1
ibias
INPD
CM_D
"nmos_rf_lvt"
totalW=45.0u
wr=1.5u
lr:60n
INN
M3
"nch_lvt_mac"
w=5u
l:60n
fingers=3
simM:1
totalM=3
DOP M7
INN
ibiasd
IBIASD_DRIVER
IBIASD_DRIVER
M9
"nch_lvt_mac"
w=5u
l:60n
fingers=30
simM:1
VSS
totalM=30
M8
1 : 2
IBIASD_DRIVER
M8
"nch_lvt_mac"
w=5u
l:60n
fingers=60
simM:1
totalM=60
VSS
DHP Design Review, Oct. 27, 2014
5
MHz output connected to the oscilloscope
Gbit
Link
Setup
GHz DHPT LFSR output
with
flexTest
& twisted
cables
0.1 – Tconnected
est setup
Signal Integrity
Analysis
DHPT 0.1
DHP Design Review, Oct. 27, 2014
Flex cable,
38cm
TWP cable,
10 (20) m
6
Differential Output Amplitude
Output amplitude vs. output stage bias current
Vout (mV)
• Linear function of bias current 1000
(IBIAS_DRIVER) • IBIAS_DRIVER ≈ I_DVDD 800
• Pre-­‐emphasis off 600
(IBIASD_Driver = 0) • Effective output resistance: 49.1 400
Ohm 200
• DC output resistance: 55 Ohm • ➔ ~3.5 Ohm Series resistance (chip 0
0
wiring, bond wire, PCB trace) slope = 49,1 Ohm
5
10
15
20
I_DVDD (mA)
(IBIAS_DRIVER)
➔ Output resistance Ok
DHP Design Review, Oct. 27, 2014
7
Main Output Current Mirror
Output stage bias current vs. external I_bias current
I_DVDD (mA)
20
(IBIAS_DRIVER)
• IBIAS_DRIVER current mirror • Design value IBIAS_DRIVER/Ibias = 20 • Non-­‐linear for Ibias > 0.7mA ➔ M2 not saturated? • Drive current limited to 20 mA ! Voutmax = 957 mV 15
10
5
mirror ratio: 1:20
0
0,0
0,5
1,0
1,5
2,0
2,5
Ibias (mA)
I_bias Current Mirror Input Characteristics
2,5
➔ Limited by current sink (M2) or switches M0/M1 (too high on resistance)?
Ibias (mA)
2,0
1,5
1,0
0,5
500
DHP Design Review, Oct. 27, 2014
600
700
800
900
V_Ibias (mV)
1000
1100
1200
1300
8
Boost Output Current Mirror
Output stage boost current vs. external I_bias current
6
5
I_VDD (mA)
(IBIASD_DRIVER)
• IBIASD_DRIVER current mirror • Design value IBIASD_DRIVER/Ibiasd = 2 • Fair linearity • Drive current limited to 6.12 mA ! Vboostmax ~300mV 4
3
2
mirror ratio: 1:2
1
0
0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
Ibias_b (mA)
Boost amplitude vs output current
➔ Make boost current sink M8 stronger
300
250
Vout (mV)
200
150
100
50
0
0,0
0,5
1,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
5,5
6,0
6,5
I_VDD (mA)
DHP Design Review, Oct. 27, 2014
9
L
✦Dummy poly layoutTXO_N
for impedance matching
driver
800 MHz
1.6 GHz
50
50
LFSR
Preemphasis
CML driver
PLL outputs
poly-res. with dummy structures
TX1_Pimplementation (DHP 0.2, DHPT 0.1)
Driver preemphasis
•
–
–
pre
drv.
TX1_N
First order digital filter, finite impulse response (FIR)
Adjustable filter coefficients (tap weights a, b, delay dt)
SVD-PXD, Vienna 2012, H. Krüger
1.6 GHz/
800 MHz
Setting I0
del
SW[1:0]
11
2
I1
Pulse Width [ps]
130
dt
300
10
470
00
615
dt
dt
a
a
01
75 µm
Delay Settings
320 MHz
2, H. Krüger
Boost Pulse Width [ps]
CML driver
b
-b
-11-
Delay settings variations
[waveform]
a=1
b = 0.3
dt = 600ps
b
a
a=1
b = 0.5
dt = 600ps
T. Kishishita
a=1
b = 0.5
dt = 300ps
-13/20-
Tap weight (bias) settings variations
➔ ~170 ps per delay buffer
SVD-PXD, Vienna 2012, H. Krüger
700
-10-
525
350
175
0
11
01
10
Delay SePng
DHP Design Review, Oct. 27, 2014
00
800 MHz clock, different delay settings
10
Signal Integrity Analysis
Signal Integrity Characterization
• Gbps,
1.6 Gbps ✦ 1.6
8bitLFSR-­‐8 LFSR sequence 38 cm flex (I.V.) + 10m Infiniband cable (LEONI, AWG 26)
• 30 cm kapton cable ✦ Max.
pre-emphasis
settings
+ 10m AWG26 twisted pair cable
200 mV
jitter: 25ps (1σ)
DHP Design Review, Oct. 27, 2014
11
Signal
Integrity
Signal Integrity Characterization
Analysis
Signal Integrity Analysis
8bit •LFSR
sequence
1.6 Gbps LFSR-­‐8 c8bit
m kapton csequence
able (I.V.)
+30 20m
Infiniband
cable
26)
1.6 •Gbps,
LFSR
38 cm (LEONI,
flex (I.V.) +AWG
20m Infiniband
cable (LEONI, AWG 26)
+ 20m AWG26 Max.
pre-emphasis
settings
mphasis:
1.8V
for Iboost, min. I0
twisted pair coverdrive
able
100 mV
jitter: 42ps (1σ)
Intrinsic rad. hardness (tox~1-2 nm) is attractive
DHP Design Review, Oct. 27, 2014
12
DHPT 0.1 X-­‐ray Irradiation
• TSMC 65nm TID tolerance: and nMOS only) Characterized
ASIC building block (DHPT0.1)
– V shift (wide pMOS Contents
Contents:
– PLL + Gbit link performance (with 15 m cable) Link Driver
Gigabit
Serial
THR
• Up to 100 Mrad (60keV X-­‐ray tube, Karlsruhe) • Dose rates: ~300 kRad/h (initial) ! ~2Mrad/h (end) • Annealing after each step: 80°C for 100 min
Belle II: 10 Mrad for 5 yr operation
No TID induced degradation observed up to 100 Mrad
140 mV
Dose = 0 MRad
DHP Design Review, Oct. 27, 2014
Jitter ~51 ps
140 mV
Dose = 100 MRad
Jitter ~54 ps
13
PLL output
Gigabit Serial Link Driver
Ref. Frequency
in MHz
Supply voltage in V
Reference frequency of 320MHz output node as a function of TID and supply voltage
default IO voltage
28
TID in MRad
PLL works even after 100 Mrad, slow outputs mainly come from CMOS driver (thick gate oxide).
DHP Design Review, Oct. 27, 2014
14
Summary DHPT 0.1 – CML Driver Characterization
• Delay settings Ok – minimum delay setting (SW[1:0]=11 ! 130 ps) shows best eye diagram for long cables – Possible optimization: make delay steps a bit smaller (170 ps ! 120 ps, 7 ! 5 inverter per delay) • Bias current settings can be optimized – Recommended adjustments: • Increase main current (+ 5-­‐10mA) ! higher signal amplitude • Increase boost current (+ 4mA) ! higher pre-­‐emphasis level, better damping compensation – Current configuration • Current sinks: M2 (main bias) same size as M8 (boost bias), but M2 sinks 20 mA and M8 6 mA. • Ratio of main and boost switches is 3:1 (Ok) • Good signal integrity driving 38cm kapton + 20m TWP cable @ 1.6Gbps • No sensitivity for TID of 100 Mrad
DHP Design Review, Oct. 27, 2014
15
DHPT 0.2
LVDS RX / TX
DHP Design Review, Oct. 27, 2014
16
LVDS RX / TX
LVDS Receiver
M11 M12
M13 M14
M9
M15
M16
M10
M17
M8
M14
RX
OUT
RX
M1
M2
M18
M19
M20
M3
M6 M7
M4 M5
M21
M22
LVDS Driver
M. Gronevald, T. Kishishita
Vbp
5pF
▪
▪
▪
▪
LVDS Reciver (1.8/2.5V) LVDS Transmitter (1.8/2.5V) Level Shifters 1.2V<-­‐>1.8/2.5V Custom IO (ARM compatible) D
D
CMOS
driver
M4
TX
CMFB
100k
D
5pF
DHP Design Review, Oct. 27, 2014
M3
M5
Vcm
100k
M6
Vofs
TX
Vbn
17
DHPT 0.2 – LVDS TX/RX Results
PRBS (27-­‐1) @ 320MHz -­‐ VDD 1.2V/1.8V
Both receiver and transmitter work as expected.
DHP Design Review, Oct. 27, 2014
18
Characterized ASIC building block
Differential Signaling Transmitter and Receiver
Contents
Contents:
DHPT 0.2 – LVDS TX/RX Results
B
C
Figure: Measurement for Iref=150uA with VDD = 1.33V
A
These values are lower
thresholds for the max.
frequency!!!
Max. frequency [MHz]
A [ps]
B [mV]
C [mV]
205
400
1010
212
128
856
200
2260
94
166
1401
120
2940
114
154
2125
100
2920
128
114
length [cm]
DHP Design Review, Oct. 27, 2014
24
19
DHPT 1.0
ANALOG BLOCKS
DHP Design Review, Oct. 27, 2014
20
Analog Blocks – Current Reference (1uA)
Bias module provides 8 bias current to PLL, CML, and LDVS (each 1-­‐255 uA with 8-­‐bit DAC). The core is Temperature Independent Current Reference (1uA) • Compliance ✓ • Trim functionality ✓ • Temperature sensitivity ✓
O.Alonso, University of Barcelona
DHP Design Review, Oct. 27, 2014
21
Analog Blocks – 8-­‐bit DAC
8-­‐bit DAC for bias current control (1-­‐255 uA) • Dynamic range ✓ • Linearity ✓
DHP Design Review, Oct. 27, 2014
O.Alonso, University of Barcelona
22
Analog Blocks – Temperature Sensor
Internal or external sensing diode + 16 bit Sigma-­‐Delta ADC • Measurement range -­‐20°C ... +60°C ✓ • Accuracy ±1°C ✓
O.Alonso, University of Barcelona
DHP Design Review, Oct. 27, 2014
23
DHPT 1.0, 2013, TSMC 65 nm
C 65 nm
AS and DEPFET
First production version
12 mm2
296 bumps
3Mbit memory
1.6 GHz data link
Barcelona)
TIPP 2014, 2-6 June. Amsterdam
DHPT 1.0
KNOWN ISSUES & LAYOUT IMPROVEMENT
✓ Serializer behaviors ✓ CML output swing
DHP Design Review, Oct. 27, 2014
24
Serializer
• Serializer works, but VDD and/or GCK have to be adjusted: – GCK= 80 MHz ! VDD= 1.6V (works but should not be applied for a long time) – GCK= 60 MHz ! VDD = 1.4V (ok) • Manufacturer test data ➔ wafer batch has „slow NMOS“ (too high threshold) • Issue within the Serializer localized ! can be fixed with a small design change DHP Design Review, Oct. 27, 2014
25
Schematic of the serializer
S1:L
S1:L
S1:H
S1:H
Y=A
Y=B
Y=C
Y=D
S1
TOP_PLL v2_dnw
S2
dout
ser_test
clk
clk
in<0:19>
load
load
VSS
VDD
counter
FB2FAST
S0:L Y=A
S0:H Y=B
ICP
IBIAS_VCO
IBIAS
SerClk
S0
DHP Design Review, Oct. 27, 2014
A
Y
BS0
CK
Serializer
load
F1P6GHz F80MHz
REF2FAST
RefClk
(80MHz)
F80M
ToCore
cnt20_test
F1P6G
F800M
F320M
F1P6G
VDD
VSS
S0
S1
S2
S_I
din
VSS
VDD
DesClk
I6 D_S0
D_S1
A D_S2
B Y D_SI
C
D
delay_test
buf_out
A Y
BUF_X6M_A9TR_dnw
I37
MX2_X0P5B_A9TR_dnw
I5
rb
VSS
VDD
MXT4_X3M_A9TR_dnw
S0:L
S0:H
S0:L
S0:H
DFFQN_X3M_A9TR_dnw
D QN I38<19:0>
lfsr_test
out
out
IBIAS_DRIVER: 1mA (typical)
and 5mA (max.)
IBIASD_DRIVER: 1mA (typical)
and 5mA (max.)
MXT4_X3M_A9TR_dnw
S0:L
S0:L
S0:H
S0:H
out
clk
rb
S1:L
S1:H
S1:L
S1:H
A I0
B Y
C S1
DS0
Y=A
Y=C
Y=B
Y=D
CML_TX v3_dnwRF
DOP
D
DON
SW1SW2
VSS
VDD
VDD: 1.2 V
VSS: 0 V
IBIAS: 40uA
ICP: 10uA
IBIAS_VCO: 100 uA (typical),
range: 10uA - 200uA
[Parameters for delay element]
S0:L S1:L S2:H (min delay, 0.3ns tt)
S0:L S2:H S2:H
S0:H S1:L S2:H
S0:H S2:H S2:H
S0:L S1:L S2:L
S0:H S1:L S2:L
S0:L S2:H S2:L
S0:H S2:H S2:L (max delay, 2.3ns tt)
data<0:19>
S5
S6
S7
S8
IBIAS_DRIVER
IBIASD_DRIVER
26
Simulation result
SERIALIZER:TB_TOP_Serializer:1 : SERIALIZER TB_TOP_Serializer config
10:16:17 Fri Dec 6 2013
Transient Response
Name
Vis
Corner
/I0/buf_out
V (V)
nom
4 more ...
/I0/net038
ss
/I0/net038
sf
/I0/net038
nom
V (V)
V (V)
out
/I0/load
/I0/load
V (V)
load
V (V)
clk
fs
V (V)
/I0/net038
FF
ff
V (V)
/I0/net038
1.25
.75
.25
-.25
1.25
.75
.25
-.25
1.25
.75
.25
-.25
1.25
.75
.25
-.25
1.25
.75
.25
-.25
1.25
.75
.25
-.25
1.25
.75
.25
-.25
17.5
signal merged
correct pattern
20.0
22.5
25.0
time (ns)
27.5
30.0
32.5
Timing of “load” is not provided correctly, except fast-­‐fast corner.
Printed on
by kisisita
DHP Design Review, Oct. 27, 2014
Page 1 of 1
27
counter circuit
D
I0
VSS
VDD
F1P6GHz
cnt10_mod
cnt10
VSS
D-FF2_dnw
CK
cnt10
VSS
VDD
VSS
VDD
clk
Q
QB
dff_out
VSS
VDD
VDD
VSS
VSS
F80MHz
VDD
RB
I18
TIE1
AND2_X3M_A9TR
B
DFFYQ_X4M_A9TR
D
Q
VDD
VSS
CK
I15
DHP Design Review, Oct. 27, 2014
DFFYQ_X4M_A9TR
VDD
VSS
D
Q
I16
VDD
INV_X4M_A9TR
VSS
VDD
VSS
I13
BUFH_X6M_A9TR
VDD
load
VSS
I7
CK
I9
28
Simulation result (after modification)
SERIALIZER:TB_TOP_Serializer:1 : SERIALIZER TB_TOP_Serializer schematic
14:41:35 Wed Oct 22 2014
Transient Response
clk
Corner
1.25
nom
ss
ff
/I0/load
out
/I0/net038
/I0/net038
/I0/net038
/I0/net038
/I0/net038
1.0
.25
.75
.25
-.25
1.5
nom
ss
ff
fs
V (V)
/I0/load
/I0/load
/I0/load
/I0/load
/I0/load
1.0
.25
-.25
1.25
nom
ss
ff
fs
V (V)
load
.25
-.25
1.25
sf
V (V)
out
/I0/net038
.75
-.25
1.5
sf
V (V)
load
Vis
V (V)
Name
/I0/buf_out
/I0/buf_out
/I0/buf_out
/I0/buf_out
2 more ...
.75
.25
-.25
27.5
30.0
32.5
Correct pattern can be obtained in all corners.
Printed on
by kisisita
DHP Design Review, Oct. 27, 2014
35.0
time (ns)
37.5
40.0
42.5
Page 1 of 1
29
Schematic of the CML driver
M2 is out of saturation with smaller bias current than expected.
VDD
VDD
VSS
R12
VDD
R6
VDD
VDD
R13
R14
R15
VDD
"rnpolywo"
sumW=10u
sumL=12.9u
m:1
res=199.723
DON
"rnpolywo"
sumW:2u
sumL=12.9u
m:1
res=1.02364K
R16
R17
"rnpolywo"
sumW=10u
sumL=12.9u
m:1
res=199.723
DOP
VDD
VDD
VDD
R20
"rnpolywo"
sumW:2u
sumL=12.9u
m:1
res=1.02364K DON
VDD R19
R18
"rnpolywo"
"rnpolywo"
sumW=10u
sumW=10u
sumL=12.9u
sumL=12.9u
m:1
m:1
res=199.723 res=199.723
DOP
DON
DOP
INP
DON
M11
M10
INP
INP
INP
VSS
VSS
M6
"nmos_rf_lvt"
totalW=45.0u
wr=1.5u
lr:60n
nr=30
CM_D m:1
M13
M12
VSS
VSS
VSS
M3
"nch_lvt_mac"
w=5u
l:60n
fingers=3
simM:1
totalM=3
CM_D
M2
IBIAS_DRIVER
DON
INPD
M4
"nmos_rf_lvt"
totalW=45.0u
net019
wr=1.5u
lr:60n
nr=30
m:1
M5
"nmos_rf_lvt"
totalW=45.0u
wr=1.5u
lr:60n
nr=30
m:1
DOP
INND
net019
INND
nr=30
m:1
M3
INPD
CM_D
"nmos_rf_lvt"
totalW=45.0u
wr=1.5u
lr:60n
INN
IBIAS_DRIVER
DOP M7
INN
IBIASD_DRIVER
M2
"nch_lvt_mac"
w=5u
l:60n
fingers=60
simM:1
totalM=60
M9
"nch_lvt_mac"
w=5u
l:60n
fingers=30
simM:1
VSS
totalM=30
IBIASD_DRIVER
M8
"nch_lvt_mac"
w=5u
l:60n
fingers=60
simM:1
totalM=60
VSS
DHP Design Review, Oct. 27, 2014
30
test_local:TB_CML_abs:1 : test_local TB_CML_abs config
Schematic simulation (ideal)
Corner
Name
Vis
Corner
10:00:30 Fri Oct 24 2
15.0
20.0
15.0
10.0
5.0
M2/D
0.0
IBIAS_DRIVER
I (mA)
Id~20 mA
-5.0
3.5
without any output connection
test_local:TB_CML_abs:1 : test_local TB_CML_abs config
After parasitic extraction (realistic)
DC Response
25.0
I (mA)
IBIAS_DRIVER
14:14:03 Fri Dec 6 2013
/I0/I1/M2/D
30.0
12.5
10.0
Id~10 mA
7.5
5.0
2.5
M2/D
0.0
-2.5
2.5
/I0/I1/M3/D
3.0
2.0
2.5
1.5
ibias
I (mA)
I (mA)
2.0
ibias
s
Simulation results
1.5
1.0
M3/D
.5
0.0
1.0
.5
M3/D
0.0
-.5
-.5
0.0
50.0
100.0
150.0
dc (uA)
200.0
250.0
300.0
0.0
50.0
100.0
150.0
dc (uA)
200.0
250.0
The difference comes from “voltage drop due to large serial resistance” between current source and switching transistor.
Printed on
by kisisita
Page 1
Page 1 of 1
Layout can be improved in the next submission. The ideal output swing is two times larger.
DHP Design Review, Oct. 27, 2014
3
31
Modification plan
current mirror
long metal length here!
Modification plan
current mirror
Metal length can be reduced to 30% of current design.
DHP Design Review, Oct. 27, 2014
Output swing will be improved at least 50%.
32
Thank you very much.
DHP Design Review, Oct. 27, 2014
33
SCHEMATIC DETAILS (BACKUP)
DHP Design Review, Oct. 27, 2014
34
Package
From Filter
Antenna PC board
Zo
trace
Interface
and
Bandpass
Overview of PLL architecture
Package
Filter
Zo
Interface
LNA
Charge-pump PLL
LNA
PLL generates 1.6 GHz from 80 MHz reference VCO clock.
RF in
Mixer
LO signal
IF out
To Filter
To Filter
LO signal with variable
✦ Voltage
Controlled
Oscillator
(VCO)
provides
oscillating
waveform
ref(t)
v(t)
out(t)
Reference
Frequency
VCO
frequency
Frequency
Synthesizer
ref(t)
v(t)
out(t)
Reference
Frequency
✦ PLL synchronizes VCO frequency to input reference freq. through feedback
Frequency
Synthesizer
✦ Use digital counter structure to divide VCO frequency
UP(t)
v(t)
e(t) Charge
out(t)
Loop
DN(t)
PFD
Pump ICP Filter V
fREF=80MHz
v(t)
ref(t)
e(t) Charge
out(t)
ctrl
Loop
1.6 GHz
VCO
PFD
Filter
Pump
Divider
div(t)
VCO
ref(t)
div(t)
fFB=80MHz+δ
N=20
Divider
N
N
N=2
N=5
800 MHz
320 MHz time, low powe
Design Issues: low noise, fast settling
DHP Design Review, Oct. 27, 2014
35
-9/20
more schematic details...
PFD, Charge pump, and Loop filter
PFD
CP
delay
Ref2Fast
D
Q
I CP
Q
f REF Frequency
= 80MHz Detectors (PFD)
Phase
R
Example: Tristate PFD
1
Q
D
ref(t)
Q
RQ
R
C pole
I CP
D
Q
Ref(t)
fREF
(t)
Div(t)
fFB
(t)
Q
Q
f FD
Up(t)
UP(t)
Down(t)
DN(t)
E(t)
C notch
C ripple
VCT RL
Fb2Faste(t)
down(t)
VCO
✦ Phase-Frequency Detector (PFD):
classical two flipflops structure,
FD
additional error detection circuit
:5
✦ Charge-pump
(CP): differential
1.6 GHz
structure with dummy branch
:2 structures,
✦ Loop-filter (LPF): MIM
320 MHz
800 MHz
well-tuned parameters for PLL stability
1
0
:2
:2
-1
Perrott
R notch
20 · f REF
R
VCO
R ripple
CP OU T
VCO=
div(t)
D
R
f
1
LF
UP
DN R
up(t)
delay
fFB=80MHz+δ
Cpole: 3.86 pF
ICP: 10 uA
η: 0.98
DHP Design Review, Oct. 27, 2014
34
-10/2036
Voltage-Controlled Oscillator (VCO)
Voltage-­‐Controlled Oscillator (VCO)
✦ three inverters connected as a ring oscillator
✦ differential pairs with PMOS loads with cross-coupled stages for rail-to-rail switching
[800 MHz vs.Vctrl]
Periodic Steady State Response
VCT RL
In+
In-
+
- Out-
- + Out+
+
-
+
VCT RL
-+
-+
In+
1.2 V
-
In-
+
- Out-
- + Out+
+
-
-+
Power:1.25 mW
1.6 GHz
Outfor
Out+
OutOut+
InIn+
In-
VCT RL
DHP Design Review, Oct. 27, 2014
Output frequency (GHz)
2.0
+
slow (ss), 40°C
typical, 27°C
fast (ff), 0°C
1.5
-
-+
800 MHz
1.0
0.5
0
0.25
0.5
0.75
Vctrl (V)
1.0
1.25
✦ wide tuning range of the output frequency
✦ oscillation freq. of 1.6 GHz is secured under
3σ process variations.
-11/2037
PLL
Settling
PLL Settling BehaviorBehavior
✦ The Vctrl settles to the final value in tsettle~750 ns within accuracy of 2%.
✦ Stable behavior for all process corners.
✦ Layout parasitics are included in the simulation.
1.0
Transient Response
Vctrl (V)
0.75
0.5
0.25
0
0
DHP Design Review, Oct. 27, 2014
slow (ss), 40°C
typical, 27°C
fast (ff), 0°C
0.25
0.5
time (μs)
0.75
1.0
38
-12/20-
CML Driver with pre-emphasis
CML driver with pre-­‐emphasis
PLL
PFD
MHz outputs
nce generator
h adj. bias
currents
(tap weights
b) bias
✦ Two
differential
pairs:a, adj.
Hz
PLL_CML Test Chip,
Predriver circuit
Decoupl.
C
50
Preemphasis
CML driver
poly-res. with dummy structures
TX1_Pimplementation (DHP 0.2, DHPT 0.1)
Driver preemphasis
•
PLL outputs
–
–
pre
drv.
TX1_N
First order digital filter, finite impulse response (FIR)
Adjustable filter coefficients (tap weights a, b, delay dt)
SVD-PXD, Vienna 2012, H. Krüger
1.6 GHz/
800 MHz
I0
75 µm
CML driver
50
LFSR
Layout
105 µm
- tap weights (a & b),
T. Kishishita
320 MHz
- delay (dt) upto 600ps with 4 fixed steps
CML
✦Dummy poly layoutTXO_P
for impedance matching
TXO_N
MHz
MHz
VCO
currents:
driver
LPF
DIV
✦ Differential current mode logic (CML):
driver (phase control) + differential pair post driver
ammable preemphasis
r
CP
I1
dt
dt
a
del
-b
[waveform]
a=1
b = 0.3
dt = 600ps
b
a
a=1
b = 0.5
dt = 600ps
2
dt
DHP Design Review, Oct. 27, 2014
a
b
-11-
-13/2039
T
PLL+Serializer+CML
MXT4_X3M_A9TR_dnw
S0:L
S0:H
S0:L
S0:H
S1:L
S1:L
S1:H
S1:H
Y=A
Y=B
Y=C
Y=D
S1
TOP_PLL v2_dnw
S2
clk
in<0:19>
load
VSS
VDD
lfsr_test
FB2FAST
ICP
IBIAS_VCO
IBIAS
SerClk
S0
DHP Design Review, Oct. 27, 2014
A
Y
BS0
rb
buf_out
BUF_X6M_A9TR_dnw
I37
MX2_X0P5B_A9TR_dnw
I5
A Y
IBIAS_DRIVER: 1mA (typical)
and 5mA (max.)
IBIASD_DRIVER: 1mA (typical)
and 5mA (max.)
out
MXT4_X3M_A9TR_dnw
S0:L
S0:L
S0:H
S0:H
out
clk
rb
S1:L
S1:H
S1:L
S1:H
A I0
B Y
C S1
DS0
Y=A
Y=C
Y=B
Y=D
CML_TX v3_dnwRF
DOP
D
DON
SW1SW2
VSS
VDD
S0:L Y=A
S0:H Y=B
CK
ser_test
load
F1P6GHz F80MHz
REF2FAST
RefClk
(80MHz)
dout
cnt20_test
F1P6G
F800M
F320M
F1P6G
VDD
VSS
S0
S1
S2
S_I
din
F80M
ToCore
VSS
VDD
DesClk
I6 D_S0
D_S1
A D_S2
B Y D_SI
C
D
delay_test
DFFQN_X3M_A9TR_dnw
D QN I38<19:0>
VSS
VDD
VDD: 1.2 V
VSS: 0 V
IBIAS: 40uA
ICP: 10uA
IBIAS_VCO: 100 uA (typical),
range: 10uA - 200uA
[Parameters for delay element]
S0:L S1:L S2:H (min delay, 0.3ns tt)
S0:L S2:H S2:H
S0:H S1:L S2:H
S0:H S2:H S2:H
S0:L S1:L S2:L
S0:H S1:L S2:L
S0:L S2:H S2:L
S0:H S2:H S2:L (max delay, 2.3ns tt)
data<0:19>
S5
S6
S7
S8
IBIAS_DRIVER
IBIASD_DRIVER
40
LVDS TX5.7.
I/O CIRCUITRY AND PAD FRAME
M15
115
M16
M17
Common-Mode Feedback
CMOS driver
D
D
M3
M4
R1
TX
M10
M9 M8
R2
Vcm
D
M12
M1
M7 M6
M2
M13
TX
M11
Vofs
C1
R3 M5
Vbn
M14
Fig. 5.35: Schematic of the LVDS driver with common-mode feedback and adjustable signal
transistors with common-­‐mode feedback circuit. ✓four switching current
✓adjustable signal current from 0.6—3 uA. in the range
of 1.125
- 1.275
V. However, the
FE-I4
I/O circuit supply
hm tstandard
ermination resistors are implemented with poly-­‐resistors.
✓100 OIEEE
voltage has been chosen to be in a range of of 1.2 - 1.5 V due to the restriction of the
thin-gate transistors and other considerations with respect to the chip architecture. For
this reason, deviating from the LVDS standard, the value of the offset voltage has been
DHP Design Review, Oct. 27, 2014
chosen to be the half of the FE-I4 power supply voltage. Nevertheless it is possible to
41
LVDS RX
5.7. I/O CIRCUITRY AND PAD FRAME
M11 M12
M9
Vbn
119
M13 M14
M15
M16
M10
M17
M8
IN
M18
IN
Vbp
M2
M4 M5
M1
OUT
M19
M20
✓NMOS & PMOS diff. pair for wide common-­‐mode input range ✓positive feedback circuit M4~M7, M11~M14 for higher speed and hysteresis. ✓high-­‐gain 2nd-­‐stage amp. for full CMOS output
M3
M6 M7
M21
M22
Fig. 5.40: LVDS receiver with a low voltage rail-to-rail input stage
input signal
NMOS
stage stops operating since the bias transistor M8
DHP whereas
Design Rthe
eview, Oct. 2input
7, 2014
is driven out of saturation. Both stages are equipped with a positive feedback decision
42
BIAS_MODULE
It provides 8 bias currents to PLL, CML, and LVDS. An 8-­‐bit current-­‐steering DAC provides a programmable current (1 to 255 uA).
binary weighted DACs 1-­‐256 uA
VDD
VDD
VDD
VBIAS1
…
VBIAS2
…
DAC[7]
DAC[0]
PLL, CML, LVDS
DHP Design Review, Oct. 27, 2014
43
Temperature sensor (designed by UB)
✓Operating temperature of -­‐20℃~70℃, with ΔT=0.2℃ accuracy.
✓based on Voltage Proportional To Absolute Temperature (VPTAT) method.
✓drop voltage of the diode is digitalized by ΣΔ-­‐ADC and temperature.
current mirrors
on-­‐chip diode (PNP bipolar)
Vdiff proportional to the absolute temperature.
off-­‐chip diode (known temp.)
R2R ladder
DHP Design Review, Oct. 27, 2014
+
-­‐
Vcm
ΣΔ-­‐ADC
44