Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Eye opening monitor for
optimized self-adaptation of low-power equalizers
in multi-gigabit serial links
Master Thesis in Division of Electronics Systems
at Linköping Institute of Technology
by
Anand Narayanan
LiTH-ISY-EX--13/4732--SE
22 November, 2013
TEKNISKA HÖGSKOLAN
LINKÖPINGS UNIVERSITET
Department of Electrical Engineering
Linköping University
S-581 83 Linköping, Sweden
Linköpings tekniska högskola
Institutionen för systemteknik
581 83 Linköping
Master thesis performed at
Fraunhofer Institute for Integrated circuits (IIS)
Erlangen, Germany
Eye opening monitor for
optimized self-adaptation of low-power equalizers
in multi-gigabit serial links
Master thesis in Division of Electronics Systems
at Linköping Institute of technology
by
Anand Narayanan
LiTH-ISY-EX--13/4732--SE
Supervisor:
Examiner:
Conrad Zerna, Dipl.-Ing.,
Optical Sensors And Communications
Fraunhofer Institute for Integrated circuits (IIS)
Erlangen, Germany
conrad.zerna@iis.fraunhofer.de
Dr J. Jacob Wikner
Department of Electrical Engineering
Linköping University
Linköping, Sweden
jacob.wikner@liu.se
Linköping, 22 November 2013
Presentation Date
Department and Division
22-November-2013
Publishing Date (Electronic version)
Department of Electrical Engineering
Language
English
Other (specify below)
Number of Pages
81
Type of Publication
Licentiate thesis
Degree thesis
Thesis C-level
Thesis D-level
Report
Other (specify below)
ISBN (Licentiate thesis)
ISRN: LiTH-ISY-EX--13/4732--SE
Title of series (Licentiate thesis)
Series number/ISSN (Licentiate thesis)
URL, Electronic Version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106580
Publication Title
Eye opening monitor for optimized self-adaptation of low-power equalizers in multi-gigabit serial links
Author(s)
Anand Narayanan
Abstract
In modern day communication systems, there is a constant demand for increase in transmission rates. This is
however limited by the bandwidth limitation of the channel. Inter symbol interference (ISI) imposes a great
threat to increasing data rates by degrading the signal quality. Equalizers are used at the receiver to compensate
for the losses in the channel and thereby greatly mitigate ISI. Further an adaptive equalizer is desired which can
be used over a channel whose response is unknown or is time-varying.
A low power equalizing solution in a moderately attenuated channel is an analog peaking filter which boosts the
signal high frequency components. Such conventional continuous time linear equalizers (CTLE) provide a
single degree of controllability over the high frequency boost. A more complex CTLE has been designed which
has two degrees of freedom by controlling the high frequency boost as well as the range of frequencies over
which the boost is applied. This extra degree of controllability over the equalizer response is desired to better
adapt to the varying channel response and result in an equalized signal with a wider eye opening.
A robust adaptation technique is necessary to tune the equalizer characteristics. Some of the commonly used
techniques for adaptation of CTLEs are based on energy comparison criterion in the frequency domain. But the
adaptation achieved using these techniques might not be optimal especially for an equalizer with two degrees of
controllability. In such cases an eye opening monitor (EOM) could be used which evaluates the actual signal
quality in time domain. The EOM gives an estimate on the signal quality by measuring the eye opening of the
equalized signal in horizontal and vertical domain. In this thesis work a CTLE with two degrees of freedom with
an EOM based adaptation system has been implemented.
Keywords
Inter-symbol interference , Adaptive Equalizer, Eye opening monitor, Receiver, Continuous time linear equalizer.
Linköping University Electronic Press
Upphovsrätt
Detta dokument hålls tillgängligt på Internet – eller dess framtida ersättare –från
publiceringsdatum under förutsättning att inga extraordinära omständigheter
uppstår.
Tillgång till dokumentet innebär tillstånd för var och en att läsa, ladda ner,
skriva ut enstaka kopior för enskilt bruk och att använda det oförändrat för ickekommersiell forskning och för undervisning. Överföring av upphovsrätten vid
en senare tidpunkt kan inte upphäva detta tillstånd. All annan användning av
dokumentet kräver upphovsmannens medgivande. För att garantera äktheten,
säkerheten och tillgängligheten finns lösningar av teknisk och administrativ art.
Upphovsmannens ideella rätt innefattar rätt att bli nämnd som upphovsman i
den omfattning som god sed kräver vid användning av dokumentet på ovan beskrivna sätt samt skydd mot att dokumentet ändras eller presenteras i sådan form
eller i sådant sammanhang som är kränkande för upphovsmannens litterära eller
konstnärliga anseende eller egenart.
För ytterligare information om Linköping University Electronic Press se förlagets hemsida http://www.ep.liu.se/
Copyright
The publishers will keep this document online on the Internet – or its possible
replacement –from the date of publication barring exceptional circumstances.
The online availability of the document implies permanent permission for
anyone to read, to download, or to print out single copies for his/hers own use
and to use it unchanged for non-commercial research and educational purpose.
Subsequent transfers of copyright cannot revoke this permission. All other uses
of the document are conditional upon the consent of the copyright owner. The
publisher has taken technical and administrative measures to assure authenticity,
security and accessibility.
According to intellectual property law the author has the right to be
mentioned when his/her work is accessed as described above and to be protected
against infringement.
For additional information about the Linköping University Electronic Press
and its procedures for publication and for assurance of document integrity,
please refer to its www home page: http://www.ep.liu.se/.
© Anand Narayanan
Acknowledgement
Firstly I would like to thank God Almighty for his grace and blessings throughout the
tenure of my studies.
I would like to thank my supervisor Dipl.-Ing. Conrad Zerna and Fraunhofer IIS for
this wonderful thesis opportunity. His guidance, inspiration and constructive criticism have
been the main driving force for successful completion of this thesis work. I would like to
thank him for all the time he has spent with me between his busy schedules.
I would also like to extend my sincere thanks to Dr. Jacob Wikner, for his support
and advice throughout the course of the project. It is an honour for me to have him as my
supervisor.
Finally, I would like to express my gratitude to all my friends and family for their
support during my studies at Linkoping University.
v
Abstract
In modern day communication systems, there is a constant demand for increase in transmission rates. This is however limited by the bandwidth of the channel. Inter symbol
interference (ISI) imposes a great threat to increasing data rates by degrading the signal
quality. Equalizers are used at the receiver to compensate for the losses in the channel and
thereby greatly mitigate ISI. Further an adaptive equalizer is desired which can be used
over a channel whose response is unknown or is time-varying.
A low power equalizing solution in a moderately attenuated channel is an analog
peaking filter which boosts the signal high frequency components. Such conventional continuous time linear equalizers (CTLE) provide a single degree of controllability over the
high frequency boost. A more complex CTLE has been designed which has two degrees of
freedom by controlling the high frequency boost as well as the range of frequencies over
which the boost is applied. This extra degree of controllability over the equalizer response
is desired to better adapt to the varying channel response and result in an equalized signal
with a wider eye opening.
A robust adaptation technique is necessary to tune the equalizer characteristics. Some
of the commonly used techniques for adaptation of CTLEs are based on energy comparison
criterion in the frequency domain. But the adaptation achieved using these techniques
might not be optimal especially for an equalizer with two degrees of controllability. In
such cases an eye opening monitor (EOM) could be used which evaluates the actual signal
quality in time domain. The EOM gives an estimate on the signal quality by measuring
the eye opening of the equalized signal in horizontal and vertical domain. In this thesis
work a CTLE with two degrees of freedom with an EOM based adaptation system has
been implemented.
vi
Contents
Acknowledgement
v
Abstract
vi
1
Introduction
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Thesis Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
3
3
2
Continuous time linear Equalizers
2.1 Basics of Equalization . . . .
2.2 CTLE Target specification . .
2.3 Selected CTLE Architectures .
2.3.1 Equalizer-I . . . . . .
2.3.2 Equalizer-II . . . . . .
2.3.3 Equalizer-III . . . . .
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Equalizer adaptation techniques
3.1 Least mean square adaptation . . . . . . . . . . . . . . . .
3.2 Non data aided techniques . . . . . . . . . . . . . . . . .
3.2.1 Conventional continuous time adaptation technique
3.2.2 Spectrum balancing technique . . . . . . . . . . .
3.3 Eye opening monitor for adaptive equalization . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
5
5
9
9
9
12
14
.
.
.
.
.
18
18
19
19
20
22
Eye Opening Monitor
24
4.1 EOM principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 EOM architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1 Differential difference amplifier . . . . . . . . . . . . . . . . . . . 26
vii
Chapter0
CONTENTS
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
CML latch . . . . . . . . . .
DC offset . . . . . . . . . . .
4.2.3.1 Offset simulation .
4.2.3.2 Offset compensation
4.2.3.3 Offset deviation . .
CML latch kickback noise . .
Synchronization Unit . . . . .
Clock Data Recovery . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
28
29
30
30
33
33
34
34
5
Adaptation Controller
37
5.1 Algorithm for Equalizers-I and II . . . . . . . . . . . . . . . . . . . . . . . 38
5.2 Algorithm for Equalizer-III . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6
Layout and Simulation Results
6.1 Data Generation and Channel modeling
6.1.1 Data Generation . . . . . . . .
6.1.2 Channel Modeling . . . . . . .
6.2 Equalizer layout and results . . . . . . .
6.2.1 Equalizer-I . . . . . . . . . . .
6.2.2 Equalizer-II . . . . . . . . . . .
6.2.3 Equalizer-III . . . . . . . . . .
6.3 EOM layout and results . . . . . . . . .
6.4 Equalizer with adaptation system results
7
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
43
43
43
44
45
45
45
47
48
54
Conclusion
58
7.1 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
A Appendix
61
A.1 Cadence SKILL code for Eye-width measurement . . . . . . . . . . . . . . 61
A.2 Eye width values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Bibliography
68
viii
List of Tables
2.1
CTLE target specification . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Adaptation algorithm control parameters for equalizers-I & II . . . . . . . . 39
6.1
6.2
Characteristics of channel models used for simulation . . . . . . . . . . .
Simulation results over corner variations for equalizer-I with digitally tunable source degeneration capacitance . . . . . . . . . . . . . . . . . . .
Simulation results over corner variations for equalizer-II with source degeneration MOS resistor . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation results over corner variations for equalizer-III with two parallel
input source degeneration stages . . . . . . . . . . . . . . . . . . . . . .
Simulation results over corner variations for fully differential difference
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation results over corner variations for CML Latch . . . . . . . . .
6.3
6.4
6.5
6.6
9
. 44
. 47
. 49
. 49
. 51
. 53
A.2 Eye width values measured at 150mV reference level over corner variations
for equalizer-III with corresponding control settings . . . . . . . . . . . . . 65
A.4 Eye width values measured at 150mV reference level over corner variations
for equalizer-II with corresponding control settings . . . . . . . . . . . . . 66
A.6 Eye width values measured at 150mV reference level over corner variations
for equalizer-I with corresponding control settings . . . . . . . . . . . . . . 67
ix
List of Figures
1.1
1.2
Basic communication system . . . . . . . . . . . . . . . . . . . . . . . . .
Channel-Equalizer frequency response . . . . . . . . . . . . . . . . . . . .
2.1
2.2
2.3
2.4
2.5
Effect of eye-closure due to over-compensation and under-compensation . .
Conventional source degenerated differential pair equalizer structure . . . .
Frequency response of first order CTLE . . . . . . . . . . . . . . . . . . .
Schematic of equalizer-I with digitally tunable source degeneration capacitor
Frequency response of equalizer-I for different degeneration capacitance
settings (Cs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Schematic of equalizer-II with source degeneration MOS resistor . . . . . .
2.7 Frequency response of equalizer-II for different degeneration resistance
settings (Vctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Schematic of equalizer-III with two parallel input source degenerated differential pair stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Equalizer-III frequency response for different degeneration capacitance
settings (<Bi > sweep) of both stages . . . . . . . . . . . . . . . . . . . . .
2.10 Equalizer-III frequency response for different degeneration resistance settings (Vctrl sweep) of stage2 . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
1
2
6
8
8
10
11
12
13
15
16
17
3.3
3.4
Block diagram of conventional continuous time adaptation technique . . .
Effect of under-equalization and over-equalization on spectrum of NRZ
coded ideal random binary sequence [1] . . . . . . . . . . . . . . . . . .
Block diagram of spectrum balancing equalization technique . . . . . . .
Difference in eye diagram of signal with and without ISI . . . . . . . . .
4.1
4.2
Mask error detection in a two dimensional EOM with rectangular mask . . 25
Architecture of the two dimensional EOM designed . . . . . . . . . . . . . 27
x
. 20
. 21
. 21
. 22
Chapter0
LIST OF FIGURES
4.3
Schematic of the fully differential difference amplifier used for reference
subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Schematic of CML latch . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Offset simulation technique used to measure the input referred offset voltage of the latched comparator . . . . . . . . . . . . . . . . . . . . . . .
4.6 Module for combined offset compensation of latched comparator . . . . .
4.7 Offset voltage deviation with temperature drift after calibration at 25o C .
4.8 Neutralization technique for CML latch kickback noise reduction . . . .
4.9 Synchronization unit block diagram and timing . . . . . . . . . . . . . .
4.10 CDR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
5.2
5.3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
. 28
. 29
.
.
.
.
.
.
31
32
33
34
35
35
Block diagram of equalizer adaptation system . . . . . . . . . . . . . . . . 37
Surface plot of eye-width measured at 150mV reference level for equalizerIII control setting sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Flowchart of algorithm used for adaptation of Equalizer-III . . . . . . . . . 41
Block diagram of LFSR used to generate PRBS-7 . . . . . . . . . . . . .
Simulation testbench setup block diagram . . . . . . . . . . . . . . . . .
Layout of equalizer-I . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response of equalizer-I over channel models for control setting
yielding the widest eye opening . . . . . . . . . . . . . . . . . . . . . .
Layout of equalizer-II . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response of equalizer-II over channel models for control setting
yielding the widest eye opening . . . . . . . . . . . . . . . . . . . . . .
Layout of equalizer-III . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency response of equalizer-III over channel models for control setting
yielding the widest eye opening . . . . . . . . . . . . . . . . . . . . . .
Layout of fully differential difference amplifier . . . . . . . . . . . . . .
Layout of CML latch . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Eye width comparison for each equalizer on different channels with and
without the adaptation algorithm for typical corner . . . . . . . . . . . .
Eye width comparison for each equalizer on different channels with and
without the adaptation algorithm for fast corner . . . . . . . . . . . . . .
Eye width comparison for each equalizer on different channels with and
without the adaptation algorithm for slow corner . . . . . . . . . . . . . .
Eye width range achieved for equalizers-II & III over corner variations .
xi
. 44
. 44
. 45
. 46
. 48
. 50
. 51
. 52
. 53
. 54
. 55
. 56
. 56
. 57
Chapter 1
Introduction
In modern day broadband communication systems a major bottleneck in increasing datarates is imposed by the bandwidth limitation of transmission channels. A basic data communication system consists of 3 blocks namely, the transmitter, channel and receiver as
shown in figure 1.1. A fundamental issue that needs to be addressed in such systems is the
frequency dependent attenuation experienced by a signal which is transmitted through a
bandwidth limited channel. Such losses distort the signal and hinder proper data recovery
at the receiver.
1.1
Motivation
In high speed digital communication, inter-symbol interference(ISI) plays a crucial role in
degrading the bit error rate (BER) for multi-gigabit transmission. ISI is a form of distortion
of a signal in which one symbol interferes with the subsequent symbols. Many practical
channels have a low-pass behavior and are bandwidth-limited due to inherent losses in
the channel. For example, in electrical channels like unshielded twisted pair(UTP) cables,
shielded twisted pair (STP) cables and coaxial cables, the main contribution to bandwidth
limitation is caused by skin effect and dielectric losses[2]. Skin effect is the phenomenon
Figure 1.1: Basic communication system
1
Chapter1
1.1. MOTIVATION
Figure 1.2: Channel-Equalizer frequency response
in which the induced magnetic field in an electrical channel when a high frequency signal
passes through it causes the current to flow through the surface of the conductor and
current density decreases exponentially towards the interior. Dielectric loss is the loss of
electromagnetic power (e.g. in the form of heat) due to the non-ideal characteristics of the
dielectric material during electromagnetic wave propagation. The bandwidth limitation of
the channel due to these losses causes ISI. Another dominant source of ISI is multi-path
propagation, where the transmitted signal reaches the receiver through different paths with
different delays. An example for this is the modal dispersion occurring in multi-mode fiber
(MMF), where the signal is spread in time since the different components of the signal
arrive at different times.
Equalizers provide a simple and cheap solution to compensate for the loses due to ISI
imposed by the channel in a communication system and facilitate error free data recovery.
The equalizer is ideally supposed to provide the inverse frequency response of the channel such that the channel-equalizer combination achieves a flat frequency response up-to
Nyquist frequency as shown in figure 1.2.
The channel characteristics are subject to variations due to various factors like temperature, material properties etc, which are discussed in detail in Chapter 2. So it is desired
to have an equalizer whose properties can also be varied/adapted to compensate for the
changing channel response. Such an adaptive equalizer is preferred also because it can be
used over a wide range of channel types and lengths.
2
Chapter1
1.2. THESIS OBJECTIVE
Many techniques exist for the adaptation of equalizer characteristics. The principle
behind the operation of these techniques is to generate an error signal that is related to the
signal quality and try to tune the equalizer transfer function so as to minimize this error.
Some of these techniques evaluate the signal quality in frequency domain and some others
in time domain. A study on the various architectures is done and one of them has been
selected for implementation in this work. The results of the work focus on how well the
adaptation circuit performs in tuning the equalizer to a setting which yields the best signal
quality over various channel models.
1.2
Thesis Objective
The objectives of this thesis are as follows:
• Investigate different architectures of continuous time linear equalizers
• Implement an Eye diagram monitoring circuit, which provides information on the
received signal quality
• Develop an iterative algorithm to set the equalizer characteristics using the information from the eye diagram monitor
The ultimate goal of this work is to study how well a two dimensional eye opening monitor
based adaptation system can perform in adapting a continuous time linear equalizer to a
setting were inter symbol interference is minimal. Different equalizer architectures will be
used for this purpose. The results discussed in this thesis focus on this goal.
1.3
Thesis Organization
The thesis is organized into the following chapters:
• Chapter 2 gives a background to the equalization techniques and further discusses
the CTLE architectures that have been implemented in this work.
• Chapter 3 gives an overview of the various adaptation techniques that can be used
with CTLE.
• In Chapter 4 the basic operation principle and architecture of the eye-opening monitor (EOM) built in this work is discussed. It also elaborates on the various design
considerations for the EOM.
3
Chapter1
1.3. THESIS ORGANIZATION
• Chapter 5 discusses the operation of the adaptation algorithm used for each equalizer
designed.
• Chapter 6 deals with the layout and results of the equalizer and the EOM. Towards
the end a comparison on the performance of the EOM with the adaptation algorithm
on each equalizer is made.
• Finally, Chapter 7 concludes the thesis work and also gives proposals for future work.
In the appendix section, cadence SKILL codes developed to extract some of the results
have been provided.
4
Chapter 2
Continuous time linear Equalizers
Equalizers are used to combat the distortion in the signal caused by inter-symbol interference (ISI). Many variants of the equalizers exist based on the application. They can be
at the transmitter and/or receiver, can be linear or non-linear, can be continuous time or
discrete time. Our goal is to build a continuous time linear equalizer which can provide
effective equalization over a wide range of mildly attenuated channels for which different
architectures have be analyzed. This chapter introduces the concept of equalization and
different types of equalizers. Further, few of the continuous time linear equalizer (CTLE)
architectures selected in this work are discussed and compared.
2.1
Basics of Equalization
Equalizers try to undo the effect of ISI by providing the inverse frequency response of
the channel in-order to compensate for the bandwidth limitation of the channel due to
various losses. In reality, the exact characteristics of the channel are not known in advance
and they are also susceptible to huge variations due to factors like temperature, material
properties, length of channel and other effects like bends, connectors etc. It is desired to
have an equalizer that can be used with a wide range of channels (e.g. copper, optical
fiber) and channel lengths. Therefore, an adaptive equalizer is required to compensate
for the variations in the channel characteristics. An adaptive equalizer is also necessary
to avoid over-compensation or under-compensation of the system. Figure 2.1 shows the
effect of over-compensation and under-compensation on the signal in time-domain. It can
be noticed that both result in the reducing the effective symbol period or in other words
5
Chapter2
2.1. BASICS OF EQUALIZATION
Figure 2.1: Effect of eye-closure due to over-compensation and under-compensation
reduce the eye width. This effect can be used to estimate the quality of the signal.
Channel equalizers can be implemented at the transmitter end and/or the receiver end.
Transmitter equalizers (pre-emphasis) are relatively simpler when compared to receiver
ones in terms of complexity of implementation. They amplify the high frequency components of the signal in advance to compensate for the losses in the channel. The attraction
of using this technique is that it does not amplify any noise which will be added to the
signal during transmission. But this technique also has some serious disadvantages such as,
adaptation of such equalizers require back-channel (feedback from receiver to transmitter)
mechanism which can be very complex and difficult to implement. Transmitter equalizers
can also contribute to cross-talk with neighboring transmission lines in a parallel link due
to the strength of the high frequency components. Hence, transmitter equalizers are often
used in combination with receiver equalizers.
Receiver equalizers provide easier adaptability to channels especially when the response is unknown or varies with time. A problem with using receiver equalizers is that it
amplifies in-band channel noise, but in cases where the SNR of the received signal is not
bad, ISI imposes a greater threat to the quality of the signal than the noise.
Receiver equalization approaches can be classified into linear and non-linear equalization. Linear equalizers have finite impulse response and non-linear equalizers have infinite
impulse response. Linear equalizers have a feed forward structure, where the equalized data
is not fed-back to adapt the equalizer. Whereas in non-linear equalization, the equalized
6
Chapter2
2.1. BASICS OF EQUALIZATION
data is fed-back to change the subsequent outputs of the equalizer. Non-linear equalizers
are mainly used in cases where the channel distortion is too severe where they are often
combined with linear equalizers so as to zero out the residual ISI at the output of the linear
equalizer.
Linear equalizers can be further classified into:
• Discrete time equalizer
• Continuous time equalizer
Discrete time equalizers which are based on FIR filter structures, require clocks recovered from the received data. This creates a cross dependency between the equalizer and
the CDR (clock-data recovery) unit. These equalizers are normally power hungry and
their power consumption increases drastically with increase in data rates due to the large
number of taps in the FIR filters. Continuous time equalizers on the other hand consume
less power and area, mainly due to their simple structure. They normally do not require
sampling clocks but the re-timing of the signal for data recovery needs a sampling clock.
The adaptation system might require a sampling clock based on the architecture used. In
this work, we choose to build an adaptive continuous time linear equalizer (CTLE) whose
response can be controlled by an adaptation loop such that effective equalization can be
achieved for a channel whose response is unknown or time varying.
Many CTLEs are based on the conventional source degenerated differential pair structure shown in figure 2.2 [3, 4, 5, 6]. The transfer function for this circuit is given by
equation (2.1), where gm is the transconductance of the input transistors, RL and CL are
the load resistance and capacitance, RS and CS are the source degeneration resistance and
capacitance. This system has two poles and a zero. The zero provides a +20dB/decade
slope and each pole provides -20dB/decade as shown in figure 2.3. The basic requirement
of such an equalizer is to provide a high frequency boost whose peak can be controlled.
This is done by tuning the zero of the system. By changing the degeneration capacitance
(CS ) the zero of the system can be moved thereby varying the high frequency boost. The
zero can also be tuned by varying the degeneration resistance (RS ), but this also changes
the DC gain of the system.
A(s) =



gm RL
∗

1 + gm RS /2

1 + sRSCS


sRSCS
(1 + sRLCL ) 1 +
1 + gm RS /2
7
(2.1)
Chapter2
2.1. BASICS OF EQUALIZATION
RL
RL
Vout
Vin
RS
CS
Figure 2.2: Conventional source degenerated differential pair equalizer structure
Gain (dB)
A0 *ωP1
ωZ
+20dB/Dec
-20dB/Dec
A0
ωZ
ωP1 ωP2
Frequency
Figure 2.3: Frequency response of first order CTLE
Many variants based on the above concept of the source degenerated differential pair
equalizer exist. In this work, three equalizer architectures have been implement and their
performance have been studied. This is discussed in detail in the following sections.
Table 2.1 gives the target specifications of the CTLE to be built.
8
Chapter2
2.2
2.2. CTLE TARGET SPECIFICATION
CTLE Target specification
Parameter
Value
Technology
65nm
Supply voltage
1.05 - 1.35 V
Sampling frequency
3 GHz
Min high frequency boost
0 dB
Max high frequency boost
~ 30dB (for given channel models) @ ~1.5GHz
DC gain
0 dB
Input common mode voltage
0.7875 - 1.012 V
Output common mode voltage
0.7875 - 1.012 V
Table 2.1: CTLE target specification
2.3
Selected CTLE Architectures
Three CTLE architectures based on the source degenerated differential pair structure were
selected for implementation in this work and their performance was compared. They are:
• Equalizer-I: With digitally tunable source degeneration capacitors
• Equalizer-II: With voltage controlled NMOS source degeneration resistance
• Equalizer-III: Consists of two capacitively coupled parallel input stages
Equalizers I and II provide one degree of controllability over the high frequency boost
whereas equalizer-III has two degrees of freedom for controlling the high frequency boost
as well as the range of frequencies that are boosted. The design and operation of the
equalizers are discussed in detail in the following sections.
2.3.1
Equalizer-I
In this architecture the degeneration capacitor (CS ) is replaced by a digitally tunable capacitor array so that the effective capacitance can be varied digitally. As shown in figure 2.4,
9
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
RL
RL
Vout
Vin
RS
B0
CS
B1
2CS
B2
4CS
Figure 2.4: Schematic of equalizer-I with digitally tunable source degeneration capacitor
the capacitor array consists of 3 parallel capacitors with each of them being digitally controlled by NMOS switches. Two switches have been placed on each side of the capacitor
to ensure symmetry. The capacitance value is controlled by 3 binary bits <b2 ,b1 ,b0 > which
are connected to the gates of the NMOS switches. Since we use binary coding for the
control bits, the capacitor values should be in a geometric progression with common ratio
2. This results in 8 different possible linear settings for the degeneration capacitance.
The zero frequency of the system can be reduced by increasing the source degeneration
capacitance thereby resulting in an increase in the high frequency boost. With 3 parallel
stages of capacitors we can have 8 different settings for the high frequency boost. More
parallel capacitor stages can be added to increase the granularity of the change in the
capacitance value. The bias current for the equalizing filter is generated from an external
biasing circuit which is not shown here.
Another feasible alternative that is commonly used to realize a variable capacitor is the
MOS gate-bulk capacitor, where the source, drain and bulk of two transistors are shorted
and the capacitance between the gates of the two transistors are controlled by a voltage
connected to the bulk of the transistors. This technique was not an attractive option for this
work as it was difficult to realize very low capacitance (~0 F) which was necessary to have
zero or no high frequency boost. Hence digitally tunable capacitors have been used with
10
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
AC Response
Name
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
v (/outp /outn); ac dB20(V)
Vis
a
20.0
0
1
2
3
4
5
6
7
10.0
V (dB)
0.0
-10.0
-20.0
-30.0
4
10
5
6
10
10
7
10
freq (Hz)
8
10
9
10
10
10
11
10
Figure 2.5: Frequency response of equalizer-I for different degeneration capacitance settings (Cs)
which zero peaking can be achieved by switching off all the NMOS switches.
The maximum high frequency gain that can be achieved with this circuit cannot exceed
the DC gain of a non-degenerated differential pair. Hence multiple cascade stages of this
equalizer have to be used to meet the maximum relative peaking requirements. Three cascade stages were used to get the necessary equalization for the channel models in this work.
Figure 2.5 shows the frequency response of equalizer-I for different capacitor values.
It can be noticed that increasing the capacitor values results in increased high frequency
boost but the peaking frequency also gets shifted. This is because changing CS also results
in the shifting of one of the poles of the system, which is a drawback of this equalizer.
The MOS switches have also been sized in a geometric progression as the capacitors,
such that the effects due to parasitics and their ON resistance also get doubled for each
parallel stage. This has been done to ensure a linear increase in the total capacitance and
thereby the high frequency boost when sweeping the control bits.
11
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
RL
RL
Vout
Vin
Vctrl
CS
Figure 2.6: Schematic of equalizer-II with source degeneration MOS resistor
2.3.2
Equalizer-II
The max high frequency boost that could be achieved with equalizer-I was not sufficient,
so a modification to the architecture was made by controlling the source degeneration
resistance (RS ) instead of the capacitance (CS ). A MOS resistor is used to realize the
variable resistor whose resistance is controlled by varying the gate voltage. Figure 2.6
shows the schematic of equalizer-II. The source degeneration capacitance is fixed.
It can be seen from equation 2.1 that varying RS moves the zero of the system. But
the gain and the zero are tightly coupled i.e., varying RS also changes the DC gain of the
system. This architecture takes advantage of this property in order to get more relative
peaking. Increasing RS decreases the zero frequency as well as reduces the DC gain of
the filter. We are more interested in the high frequency boost relative to the DC gain,
so decreasing the DC gain also increases the relative boost achieved. An issue with this
technique is that the DC gain could drop below one (A0 <1). But this loss could be compensated using limiting amplifier stages after the equalizing filter to ensure A0 >=1 over PVT
variations. The maximum attenuation of the signal at the input to the limiting amplifier is
limited by the SNR of the equalized signal and offset of the limiting amplifier. Attenuation
beyond these levels increases the BER of the system. So in-order to achieve a peaking
beyond this limit, multiple stages of the equalizer could be used. In this work, we have
12
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
AC Response
Vis
V_ctrl_R
30.0
-0.18
-0.17
-0.16
-0.15
-0.14
-0.13
-0.12
-0.11
-0.1
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
V (dB)
Name
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
...p /outn); ac dB20(V)
20.0
10.0
0.0
-10.0
-20.0
-30.0
4
10
5
10
6
10
7
10
8
freq (Hz)
10
9
10
10
10
11
10
Figure 2.7: Frequency response of equalizer-II for different degeneration resistance settings
(Vctrl)
used 2 stages of the equalizer which creates a 40dB/decade slope.
The voltage controlling the resistance of the NMOS transistor is generated from a
DAC. Each DAC setting corresponds to a different resistance value, so the peaking of the
equalizer is adjusted by controlling the DAC input. Fine variations to the peaking can be
made using smaller step size for the control voltage change which requires a fine resolution
DAC. Figure 2.7 shows the frequency response of equalizer-II for different control voltage
settings. A step size of 10mV is used here over a range of 200mV which needs a 5-bit
DAC. The DAC has not been implemented as it is not the focus of this work and hence
stays as behavioral model.
Equalizer-I and equalizer-II have similar structures but different control variables.
Equalizer-II could be used achieve higher relative peaking when compared to equalizer-I.
Also unlike equalizer-I, in equalizer-II changing the control variable (RS ) resulted in different peaking at the same peak frequency. This is because changing RS does not move the
pole frequency too much due to the presence of the RS term in the numerator and denominator of the pole in equation 2.1. This makes Equalizer-II a more preferred architecture.
13
Chapter2
2.3.3
2.3. SELECTED CTLE ARCHITECTURES
Equalizer-III
Equalizers-I and II have only one degree of freedom and the controllability was limited to
the high frequency boost. There was no control over the shape/width of the peak. To better
adapt to the different channel models which have different responses(roll-off slopes), it is
desired to have more controllability on the equalizer response which controls the width of
the peak without affecting the peak gain.
In this architecture, two stages of the source degenerated differential pair with parallel
input stages and capacitively coupled output stages are used. The structure is similar to
the first equalizing stage used in [7]. The equalizer architecture proposed in this work
is shown in figure 2.8. Stage-2 has a variable MOS degeneration resistor to control the
high frequency boost. Both stages of the equalizer have a 4 stage digitally tunable source
degeneration capacitance with common control bits , <B0 ,B1 ,B2 ,B3 >. In this way the high
frequency boost of the 2 stages can be increased evenly. Similar to equalizer-I, binary
control bits bits are used and hence the capacitor values for each parallel stage is double
that of the succeeding stage.
The output of the equalizer is taken from stage-1 and stage-2 is capacitively coupled
the output. The transfer function for the circuit has been derived and is given by equation 2.2, where gm1 and gm2 are the transconductance of the input transistor of stages 1
and 2 respectively. The pole and zero positions can be moved by varying the degeneration
capacitance CS1 and CS2 of stages 1 and 2 and the degeneration resistance (RS2 ) of stage
2. We have gm2 > gm1 ; RL1 >RL2 ; with strong coupling so that stage-2 dominates stage-1 at
higher frequencies when coupling capacitor Cc couples together the outputs of the parallel
input stages. Additional poles and zeroes are added to the system. Since pole-zero analysis
with this equation is extremely complex, a simpler approach to understand the behavior of
the circuit is required, which is described as follows:

A(s) =

gm1 RL1
∗

1 + gm1 RS1 /2


1 + sRS1CS1


sRS1CS1
(1 + sRL1CL1 ) 1 +
1 + gm1 RS1 /2
1 + sRL2 (CL2 +CC X)
∗
(2.2)
1 + s [RL2CL2 +CC (RL1 + RL2 )Y ]
14
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
RL
RL
Cc
RL
RL
Vout
Cc Vin
Vin
Vctrl
RS
B0
CS
CS
B1
2CS
2CS
B2
4CS
4CS
B3
8CS
8CS
Stage1
Stage2
Figure 2.8: Schematic of equalizer-III with two parallel input source degenerated differential pair stages

sRS1CS1
 (1 + sRS2CS2 ) 1 + 1 + gm1 RS1 /2 
gm2 (1 + gm1 RS1 )

∗
X = 1+


sRS2CS2
gm1 (1 + gm2 RS2 )
(1 + sRS1CS1 ) 1 +
1 + gm2 RS2 /2


RL1 RL2 (CL1 +CL2 )
1 + s

RL1 + RL2

Y =


1 + sRL1CL1
(2.3)

(2.4)
• At low frequencies stage-2 is completely isolated from the circuit due to the coupling
capacitor CC ; so the low frequency gain of the equalizer is set by stage-1 alone.
• At higher frequencies, coupling capacitor CC can be considered as a short, and the
extra transconductance of the stage-2 is added to that of stage-1.
• Varying the source degeneration capacitance of both stages equally results in different peak gain for the equalizer whilst not changing the low frequency gain.
15
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
ac
Name
Vis
B
40.0
ac
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30.0
20.0
V (dB)
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
10.0
0.0
-10.0
5
10
6
10
7
10
8
freq (Hz)
10
9
10
10
10
Figure 2.9: Equalizer-III frequency response for different degeneration capacitance settings
(<Bi > sweep) of both stages
• Varying the degeneration resistance of stage-2 (RS2 ) moves the zero and also changes
the DC gain of stage-2. But the effect of these changes reflects only in the high
frequency region of the equalizer response due to the coupling capacitor. This results
in different peaking responses with different peak widths (in other words peaking
over a wider frequency range) while the low frequency gain of the equalizer remains
unchanged.
• The degeneration resistance of stage-1 is kept fixed so that the low frequency gain of
the equalizer remains unchanged for all control settings unlike equalizer-II where the
different control settings have different DC gains.
This equalizer inherits the main advantages of equalizer-I and equalizer-II by controlling the high frequency boost of the 2 stages using variable degeneration capacitance
and resistance and combines it with the coupling of 2 stages. Equalizer-III provides two
degrees of freedom for better adaptability to a wide range of channels. The high frequency
boost can be controlled with the bits <B0 ,B1 ,B2 ,B3 > connected to the digitally tunable
capacitors as shown in figure 2.9. Width of the peak can be controlled by varying the
degeneration resistance of stage-2 using a control voltage generated from a DAC as shown
in figure 2.10. Both these controls are independent of each other.
16
Chapter2
2.3. SELECTED CTLE ARCHITECTURES
ac
Name
Vis
V_ctrl_R
40.0
ac
-0.24
-0.22
-0.2
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
30.0
V (dB)
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
ac
20.0
10.0
0.0
4
10
5
10
6
7
10
10
8
freq (Hz)
10
9
10
10
10
11
10
Figure 2.10: Equalizer-III frequency response for different degeneration resistance settings
(Vctrl sweep) of stage2
The required high frequency boost for the given channel models is achieved by cascading two stages of the equalizer followed by limiting amplifiers such that the low frequency
gain is greater than one (A0 >=1) over corners.
Three different architectures of the continuous time linear equalizer have been analyzed
and implemented in this work. Equalizer-I and II provide controllability over the high frequency boost whereas equalizer-III provides controllability over the high frequency boost
as well as the peak width. The extra degree of freedom in equalizer-III comes at the expense of additional hardware. The simulation results for the equalizers are discussed in
chapter 6.
17
Chapter 3
Equalizer adaptation techniques
It is desired to have an adaptive equalizer for various reasons discussed in Chapter 2. In
order to tune the equalizer to its best setting so as to get the right amount of equalization,
an error signal related to the quality of the received data must be generated. The adaptation technique used tries to set the equalizer to a value which minimizes this error. Many
different adaptation techniques exist, some of which work in the frequency domain by comparing energies or in time domain by measuring the eye-opening. Some of the mainly used
adaptation techniques for linear equalizers are discussed in this chapter.
3.1
Least mean square adaptation
Least mean square (LMS) adaptation is one of the many adaptation techniques used with
discrete time equalizers to tune the equalizing filter taps. The aim is to minimize the
mean square error J, where In is the transmitted symbol and zn is the sampled output of
the equalizer shown in equation 3.1. The error en represents a discrepancy between the
transmitted and the received symbol. The necessity of the transmitted symbol In to be
known at the receiver makes this technique to be used with known training sequences.
Another alternative is to use the receivers estimate of the transmitted symbol, but this is
often used after the training sequence. In this way any slight variations in the channel can
be adapted.
en = In h− zn i
J = E |e|2
18
(3.1)
Chapter3
3.2. NON DATA AIDED TECHNIQUES
The main drawback of this technique is that the error (en ) is a function of the decision
made by the adaptation technique itself at the receiver. This cross dependency might cause
convergence issues when the bit error rate (BER) is high.
LMS adaptation can also be used for certain complex continuous time structures, like
the “complex graphic equalizer” consisting of a summation of several bandpass filters covering different frequency bands whose outputs are weighted by a complex coefficient and
summed, as demonstrated in [1]. But this technique cannot be used on continuous time
equalizer structures chosen for implementation in this work. The other popular adaptation
techniques for continuous time equalizers are discussed below.
3.2
Non data aided techniques
Some of the popular adaptation techniques for CTLEs are based on comparison of signal
energies. The main attraction of using such a technique is that it does not require a sampling
clock (with very accurate phase), as they use continuous time analog circuits to compare
the signal in frequency domain. Some of the common architectures using this technique
are discussed below.
3.2.1
Conventional continuous time adaptation technique
This approach compares the high frequency signal components (slope of the data transitions) of the equalizer output and the slicer output [8]. When equalized correctly the
waveforms at the input and output of the slicer should have the same transition energies
which is the high frequency part of the spectrum. The error between the transition energies
at the input and output of the slicer can be used to tune the equalizer high frequency boost.
The block diagram for this technique is shown in figure 3.1.
A drawback of this technique is that when the amplitude of the signal at the input and
the output of the slicer is different, the comparison of their high frequency energies will
generate an error. But this is not desired as it would result in an incorrect equalizer setting.
Advanced techniques to control the swing of the slicer by comparing the low frequency
energies also exist as shown in [9].
19
Chapter3
3.2. NON DATA AIDED TECHNIQUES
Figure 3.1: Block diagram of conventional continuous time adaptation technique
3.2.2
Spectrum balancing technique
Consider a random binary sequence with NRZ code whose spectrum is shown in figure 3.2.
A frequency can be chosen based on the data transmitted such that it divides the spectrum
into two parts with equal powers. The spectrum balancing techniques works by comparing
the powers of the low frequency and high frequency band (divided by a known frequency).
The equalizer high frequency boost is set such that the error between the two powers is
minimum. Figure 3.2 also shows the effect of having unequal powers in the two bands,
which result in under equalization or over equalization.
Figure 3.3 shows the block diagram of the spectrum balancing technique. One issue to
be addressed in this method is that the data transmitted need not be ideal random binary
sequence. It may contain large amount of low frequency content which might result in
under or over-compensation. To overcome this, advanced techniques to adaptively select
the frequency that splits the spectrum into two parts need to be used [10]. Another possible
alternative to this is the use of line codes.
All these non data aided techniques which compare the power in frequency domain have
some drawbacks. The aim is to have the biggest possible eye opening after equalization
which can be obtained by having a flat response until the Nyquist frequency. But, there
could be multiple responses corresponding to different equalizer settings which have same
20
Chapter3
3.2. NON DATA AIDED TECHNIQUES
Figure 3.2: Effect of under-equalization and over-equalization on spectrum of NRZ coded
ideal random binary sequence [1]
Figure 3.3: Block diagram of spectrum balancing equalization technique
21
Chapter3
3.3. EYE OPENING MONITOR FOR ADAPTIVE EQUALIZATION
eyeDiagra...aud") )
eyeDiagra...aud") )
Name
... 15n 60n 1/VAR("fbaud") )
Name
400.0
... 15n 60n 2/VAR("fbaud") )
750.0
300.0
500.0
200.0
250.0
V (mV)
V (mV)
100.0
0.0
0.0
-100.0
-250.0
-200.0
-500.0
-300.0
-400.0
-750.0
0.0
50.0
100.0
150.0
200.0
time (ps)
250.0
300.0
350.0
(a) Unequalized eye
0.0
100.0
200.0
300.0
time (ps)
400.0
500.0
600.0
700.0
(b) Equalized eye
Figure 3.4: Difference in eye diagram of signal with and without ISI
powers in the high frequency part. In such cases, it is highly probable that the adaptation
loop would set the equalizer to a value which need not be the best possible that can be
achieved using the equalizer. The decision made by these techniques also involves the non
ideal behaviors of the devices like rectifiers, integrators and band-pass or high-pass filters
which have a small linear input range when working at GHz range. Thus the resulting
equalizer adaptation using these techniques might not be optimal.
3.3
Eye opening monitor for adaptive equalization
The Eye Opening Monitor(EOM) gives a quantitative measure of the equalized signal eye
diagram in time domain. Eye diagram or eye pattern is generated by dividing the signal
into frames where each has a length of an integer multiple of the symbol period. Then
all the frames are overlapped to create a single diagram with one/two frame length that
contains several traces of the signal. The shape of the eye diagram and the received signal
quality are highly correlated. This information regarding the signal quality can be extracted
from the eye diagram using an EOM and used for adaptive equalization.
The distortion of the signal due to ISI causes closure of the eye diagram. Figure 3.4
shows the eye diagram of an unequalized signal and an equalized signal. EOM captures
the information regarding signal quality by sampling the signal and analyzing its characteristics in time domain. For channels where ISI not very severe (e.g. Short channels), the
22
Chapter3
3.3. EYE OPENING MONITOR FOR ADAPTIVE EQUALIZATION
received signal will have open eyes. In these cases a comparison on the signal quality with
different signals corresponding to different equalizer settings can be made by measuring
the eye opening in vertical and horizontal dimensions.
The EOM generates an error signal related to the quality of the eye diagram. This error
information is passed on to an adaptation algorithm which tunes the equalizer. The tuning
of the equalizer is only based on the equalized signal eye opening. This is useful when
there are no training sequences used and when BER is high.
EOMs can be classified into the following [11]:
• One dimensional EOM: They measure either the vertical or the horizontal opening
of the eye. These are simple in configuration and low in power consumption but do
not provide a good picture of the quality of eye.
• Two dimensional EOM: Quantifies the signal quality by measuring the vertical and
horizontal eye opening. They consume moderate hardware and power. The signal is
sampled at different points within a single sample period and any mismatch in the
sampled data is considered as a violation. They usually consist of latched comparators, DACs and phase interpolators [12].
• Data edge based EOM: Quantifies the signal quality by examining the edges of data
using multiple samples. The edge information of the data eye is extracted by sampling the data transition using many samplers. XOR gates and counters are used to
record the number of transitions at each sampling point. An histogram based on this
is generated which gives an idea of the quality of the signal.
• Multi-Sampling EOM: Here the data eye is scanned using large number of samples
per sample period at various points horizontally and vertically. This method requires
multiple sampling clocks and high precision phase shifters and hence is very power
hungry. The sampling point with maximum eye-opening margin is used for data
recovery.
The various advantages of evaluating the actual signal quality in time domain makes eyeopening monitors a very attractive technique for equalizer adaptation. From the different
types of EOMs discussed, two dimensional EOM provides a good balance between cost
and efficiency. In this work we have implemented a two dimensional EOM for adaptive
equalization which is discussed in chapter 4.
23
Chapter 4
Eye Opening Monitor
A two dimensional Eye Opening Monitor (EOM) based adaptation technique has been
implemented in this work. The EOM evaluates the signal quality by making periodic
observations of the equalized signal in time domain. This is done by sampling the signal at
different points within a symbol and compare theses data to measure the eye-opening. A
two dimensional EOM measures the eye-opening in horizontal and vertical domain. This
needs the signal to be sampled at at-least 4 points within a symbol. Also these sampling
points have to be movable in both the dimensions.
In this chapter we discuss the architecture and implementation of the EOM which acts
as a ’sense unit’ in the adaptation system by extracting information regarding quality of
the signal. The EOM is enabled by the adaptation controller which is discussed in chapter 5.
4.1
EOM principle of operation
Our implementation of the EOM samples the signal at 5 different points within a single
symbol period. One at the center and four different points around the center. The data
sampled at the center of the symbol period is also used by the clock data recovery unit
(CDR) for phase aligning the base clock to the received data and for data recovery. The
remaining four sampling points are used to measure the eye opening of the signal.
The four sampling points are set by two variable reference voltage levels and two
sampling clocks whose phase can be varied. The four points form a rectangular mask as
shown in figure 4.1. The mask size can be varied by varying the phase of the early and late
24
Chapter4
4.1. EOM PRINCIPLE OF OPERATION
SH,early
clklate
clkearly
SH,late
Vhigh
Mask
Mask error
Vlow
SL,early
SL,late
SH,early
SL,early
SH,late
SL,late
Figure 4.1: Mask error detection in a two dimensional EOM with rectangular mask
sampling clocks and the reference voltage levels. Early and late clocks are generated from
the CDR base clock using phase interpolators. Reference voltage levels are generated from
a DAC whose setting can be controlled. The design of the DAC and phase interpolators
are not discussed in this work as they are not the focus of this thesis and stay as behavioral
models.
Any transition within the mask can be easily detected using an XOR operation on the
sampled data [12]. A difference in the sampled data at two points in mask (for the same
bit) can be used to detect any transitions between the two points. Such transitions within
the mask are considered as mask violations and are counted as mask errors. Mask errors
are counted for a specific duration, for example we have used one period of the PRBS7
sequence (127 symbols) in this work mainly due to simulation time constraints. The total
number of errors counted for a particular mask size is sent to the adaptation controller
to tune the equalizer. The adaptation controller also sets the mask size of the EOM by
controlling the phase input to the interpolator and the input to the DAC which generates
the reference voltages. The working of the adaptation controller is discussed in chapter 5.
25
Chapter4
4.2
4.2. EOM ARCHITECTURE
EOM architecture
Figure 4.2 shows the architecture of the EOM used. The basic building blocks of the EOM
are the fully differential difference amplifiers (DDA) and the CML latches which together
form the latched comparator. Two DDAs compare the differential input data with the differential reference voltage levels (Vhigh,Vlow). As the reference voltages are symmetric
across common mode, the reference level for the 2nd DDA is generated by swapping the
signals Vhigh and Vlow which are driven by a DAC.
The CDR block aligns the base clock to the received data using the sampled data at the
edge (SM,~clk ) and the center (SM,clk ) of the symbol period. The early and late clocks are
generated using phase interpolators from the base clock. CML latches are used to build the
differential flip-flops which are triggered at different sampling clocks. The ’Sync block’
synchronizes the data sampled at different clocks to the base clock (φclk ).
4.2.1
Differential difference amplifier
DDAs are used to subtract the reference voltage levels from the input signal. Figure 4.3
shows the schematic of a DDA. It consists of two differential input stages of amplifiers
which convert the input voltage into current. The currents of the two stages are subtracted
and the difference is converted into voltage over the load resistors. Equation 4.1 gives the
formula for the output of the DDA, where A0 represents the DC gain of the DDA and the
output is effectively A0 times the difference between the input and reference levels. The
equation has been rearranged because, as Vrefp and Vrefn are DC signals (change is very
slow when compared to the input data), they are connected to different input stages as
shown in the schematic.
Vout p −Voutn = A0 (Vinp −Vinn ) − Vre f p −Vre f n
Vout p −Voutn = A0 Vinp −Vre f p − Vinn −Vre f n
(4.1)
The output of the DDA is thus the amplified difference between the input data and
the reference levels. This output is fed to a flip-flop for sampling the equalized signal at
different points of the eye diagram. The reference inputs are driven by a DAC which is set
26
Chapter4
4.2. EOM ARCHITECTURE
Figure 4.2: Architecture of the two dimensional EOM designed
27
Chapter4
4.2. EOM ARCHITECTURE
Figure 4.3: Schematic of the fully differential difference amplifier used for reference subtraction
by the adaptation controller. Two DDAs are used of which one has a positive reference
level and the other has a symmetric negative reference level.
4.2.2
CML latch
The output of the difference amplifier is sampled by a CML D-flip-flop (DFF) using the
sampling clocks generated from the CDR unit. A CML DFF is built using master and slave
CML latches. A rising edge triggered DFF is built by enabling the 1st latch at the negative
phase of the clock and the 2nd latch at the positive phase of the clock. CML latches can
operate at much higher speeds than their CMOS counterparts. This is mainly due to the
reason that the output swing is only a fraction of the supply voltage. The schematic of the
CML latch is shown in figure 4.4[15].
The CML Latch operates in two phases: capture and hold. During the capture phase
(clock is high) the input differential pair (M1 & M2) are ON and the input is transferred
to the output. During the hold phase (clock is low), the input is detached from the output
and the cross-coupled pair (M3 & M4) are ON and help retain the output value, forming a
28
Chapter4
4.2. EOM ARCHITECTURE
Figure 4.4: Schematic of CML latch
positive feedback.
4.2.3
DC offset
The latched comparator designed suffers from a DC offset due to the presence of device
mismatches. The DC offset is measured as the value observed at output when the input is
zero. A more common measure is the input referred offset which is defined as the input
voltage that causes the output to go to zero. This input referred offset has to be reduced for
the proper operation of the latched comparator.
For a differential pair, the input referred offset is given by equation 4.2 [16], where VGS Vth is the overdrive voltage and W/L is the width to length ratio of the input transistors and
RD is the load resistance. So in order to minimize the effect of variations in RD , W/L and
Vth due to device mismatches, the devices have to be sized such that the input transistor
pair has a lower overdrive voltage. This can be achieved by reducing the tail current or
sizing up the W/L of the input pair. Such careful design considerations help minimizing
the offset. But there are other limitations on such design like bandwidth/speed and output
29
Chapter4
4.2. EOM ARCHITECTURE
common mode level. For e.g. decreasing tail current decreases the bandwidth and increases
output common-mode level.
"
#
VGS −Vth 2
∆RD 2
∆ (W /L) 2
VOS,in =
+ ∆Vth2
(4.2)
+
2
RD
(W /L)
4.2.3.1
Offset simulation
The input referred offset has been measured using the simulation technique mentioned in
[17]. The offset of the latched comparator can be characterized as shown in figure 4.5(a).
Figure 4.5(b) shows the offset simulation technique where the output of the comparator is
fed back to the input through a differential amplifier and integrator. The output of the differential amplifier with unity gain is, VOD = Vp −Vn . This voltage is integrated and added
to common mode voltage VCM and fed to VB . Also, VA =VCM . Voltage at VB is increased
or decreased based on the polarity of VOD in-order to reach level VA . At equilibrium the
comparator output should have equal number of ones and zeroes over time. The average
value of VA -VB is calculated as the input referred offset. The transient waveforms are
shown in figure 4.5(c). The offset simulation blocks namely, the integrator and the differential amplifier which form the feedback loop are modeled in verilog-A for the simulations.
4.2.3.2
Offset compensation
To further reduce the offset voltage, dynamic offset cancellation techniques are used.
Conventionally, pre-amplifiers have been used preceding the CML latch stage to reduce
the effect of offset. It amplifies the small input voltage difference to a large value in-order
to overcome the offset voltage of the latch. But these amplifiers are very power consuming
for large bandwidth and the delay due to these stages need to be taken into consideration.
The technique we have used handles the offset of the DDA and latch separately. The
calibration of the DDA is done by changing the reference voltages by a value equal to the
offset so as to cancel its effect. For the latch, current calibration is used where current is
drawn from one of the output terminals to compensate for the offset. These two techniques
are used because if only current calibration is used, there can be a huge shift in the output
common level after offset compensation. To reduce this, separate calibration of the DDA
is done first. Also, DDA calibration alone wont be sufficient since one DDA is connected
30
Chapter4
4.2. EOM ARCHITECTURE
Figure 4.5: Offset simulation technique used to measure the input referred offset voltage of
the latched comparator
to two different latches which might have offsets with different polarity.
For the DDA, from the model shown in figure 4.5(a), Vout p − Voutn =
A0 (Vinp −Vinn ) − Vre f p −Vre f n +VOS . It can been seen that a positive voltage offset at the input of DDA can be canceled by reducing the reference level by a voltage
equivalent to the offset. This idea is used by an offset calibration control block which
during the calibration phase (Vin =VCM & Vref =VCM ) changes the reference voltage (Vref )
in small steps (2.34 mV in our case) using a DAC, until the output of the comparator
toggles (as in figure 4.5(c)) and then changes the direction of varying Vref . In this way
the average value of Vref is stored and later added to the actual reference level during the
operation phase.
For the CML latch offset compensation, a current calibration technique is used. Here,
the DC offset is canceled by drawing a specific amount of current from positive output
(Voutp ) or negative output (Voutn ) node such that the outputs have the same common mode
level. The amount of current drawn is proportional to the current on the load resistors
due to the output offset voltage (VOS_out /Rload ). The current to be drawn from the output
nodes is copied from a current mirror which is fed by a current steered DAC. In this way
31
Chapter4
Vref’
Data
4.2. EOM ARCHITECTURE
Latch
early
Ip1
Ip2
10/23/2013
Out Out I_early I_late
early late (Ip1-In1) (Ip2-In2)
In1
DDA
Latch
late
I_early
I_late
Out_early
Offset
Calibration
Vref’
1
1
Up
Up
Up
Out_late
0
0
Down
Down
Down
In2
1
0
Up
Down
-
0
1
Down
Up
-
Vref
Anand Narayanan
1
Figure 4.6: Module for combined offset compensation of latched comparator
the current drawn can be incremented/decremented in small steps (3.75uA in our case)
by changing the DAC input. The current drawn from a particular output (say positive) is
incremented until the output voltage of the latch toggles. Then, the current at positive node
is decrease in steps until it is 0 and then the current on the negative output is increased
until the output voltage toggles again. Finally the average is taken over a period of time
and settles to a particular value which ideally results in zero offset.
In our EOM architecture, a DDA is connected to two latches triggered at different
clocks. An algorithm has been used to calibrate the Vref of DDA and the offset currents of
two latches separately. This is required because the two latches can have different offsets
and the DDA calibration need to be done by monitoring the flip-flop outputs working on
the early and late clocks. Figure 4.6 shows the block diagram of the offset calibration
module and a table describing the operation of the offset control algorithm. Ip1 , In1 , Ip2 ,
In2 are the calibration currents drawn from the positive and negative terminals of the two
latches respectively. Vref is the actual reference level and V’ref is the calibrated reference
level. Initially only Vref calibration is done by monitoring the out_early and out_late
signals. This is done until the two signals move in opposite directions, such that the offset
common to the both data paths are compensated. Next, current calibration is done at the
outputs of the two latches in-order to cancel the offset of the latches. For the Monte-carlo
simulations, an offset of 18.65 mV was measured before compensation which reduced to
1.81 mV at 1σ after calibration using this technique.
32
Chapter4
4.2. EOM ARCHITECTURE
Offset voltage (mV) at 1σ
14
12
10
Without
BGR
8
6
With
BGR
4
2
0
0
25 50 75 100 125
Temperature (°C)
Figure 4.7: Offset voltage deviation with temperature drift after calibration at 25o C
4.2.3.3
Offset deviation
A deviation in the offset was noticed with drift in temperature after calibration at 25o C.
This occurs due to the variation in threshold voltages of the transistors with temperature.
These Vth variations cause the offset calibration currents to vary with temperature change.
To overcome this effect, a band-gap reference based reference current was used for offset
calibration. This limited the variations to the offset with change in temperature. Figure 4.7
shows the graph for change in offset measured at 85o C and 125o C after calibration at 25o C,
with and without use of band-gap reference.
4.2.4
CML latch kickback noise
The CML latch suffers from a kickback noise issue which affects the performance of the
latched comparator. Consider the configuration shown in figure 4.8, if the clk_early and
clk_late have a 180o phase shift, then latch_early would be in hold phase when latch_late
is in capture phase and vice-versa. Due to the parasitic capacitance CGD , when latch_early
is in hold phase, the large voltage variations at its output (Ve ) are coupled to its input(Vd )
through CGD . At this time latch_late is in capture phase and it captures the distorted signal
(Vd ). This might result in an erroneous sampling of the data.
33
Chapter4
Vref
Data
4.2. EOM ARCHITECTURE
Latch
early
DDA
Out_early
clk_early
Latch
late
Out_late
clk_late
Figure 4.8: Neutralization technique for CML latch kickback noise reduction
A neutralization technique has been used to eliminate the effect of kick-back noise[18].
In this technique, two nulling capacitors (CN ) are added between the input and output nodes
of the CML latch which can cancel the effect of CGD as shown in figure 4.8. The capacitor
CN can be realized using the CGD of a NMOS transistor with source and drain shorted. The
transistor should be sized with half the width of the input differential pair since CGD and
CGS of the transistor are added (in parallel) as its source and drain are shorted.
4.2.5
Synchronization Unit
This block synchronizes the sampled data at different sampling points using different clocks
to the base clock (φclk ). It consists of a series of flip-flops triggered at positive edge of the
base clock. The block diagram and timing diagram of this unit is as shown in figure 4.9.
The sampled data at the early and late clocks are aligned to the base clock (φclk ). For
the proper functioning of this unit, the time difference between the early and late clock
edges (te +tl ) should not be too small, which might cause setup/hold time violations. This
introduces a lower limit on the minimum horizontal mask opening that the sense unit can
be operated on.
4.2.6
Clock Data Recovery
The data recovery from the received signal requires a synchronous clock which is used
to sample the received signal. The clock used at the transmitter can be transmitted with
the data, using separate channels, but due to different delays of the channels the phase
alignment between the data and clock is lost. Hence in many high speed systems the
receiver generates the clock from a frequency reference and phase aligns it to the received
34
Chapter4
4.2. EOM ARCHITECTURE
Figure 4.9: Synchronization unit block diagram and timing
Figure 4.10: CDR block diagram
data.
A commonly used CDR architecture is shown in figure 4.10 [19]. It consists of a phase
detector, loop filter and a voltage controlled oscillator (VCO). The phase detector detects
the phase difference between the data and the clock by sampling the received signal at the
rising and falling edge of the clock and comparing them. The clock phase is shifted in small
steps according to the phase difference. Data recovery is done by sampling the received
signal at the center of the eye-diagram using the base clock.
The early and late clocks for the EOM are generated using phase interpolators from
the CDR base clock. The phase interpolator input is also tunable in-order to generate early
and late clocks with different phases resulting in different mask sizes. The CDR block and
35
Chapter4
4.2. EOM ARCHITECTURE
the phase interpolators have been kept as a behavioral models in this work.
So far, the architecture of the two dimensional EOM and the various design challenges
involved have been discussed. For every given mask setting the EOM counts the number of
mask errors over a specific duration of time. This mask error information is then passed on
to the adaptation controller which then makes a decision on changing the equalizer setting.
The function of the adaptation controller is discussed in detail in chapter 5.
36
Chapter 5
Adaptation Controller
The mask error information extracted by the EOM from the signal eye diagram is passed
on to the adaptation controller. The controller works on an algorithm and tries to set
the equalizer based on the information from the EOM. The controller also sets the EOM
horizontal mask size by tuning the sampling phase for the early and late clocks and the
vertical opening by varying the reference voltage levels. In this chapter we discuss how
this algorithm works for each of the equalizers designed. The controller is optimized for
each of the equalizers and is discussed separately.
The adaptation controller basically consists of two blocks, one which acts as the ’actuator unit’ to control the equalizer setting and another ’mask control unit’ which sets the
mask size for the EOM. The block diagram on how the system works is shown in figure 5.1.
Data
Equalizer
Equalized Data
CDR
Boost Control
Adaptation controller
Actuator
Unit
Mask
Control
Unit
EOM
Clock
Mask Control
Figure 5.1: Block diagram of equalizer adaptation system
37
Chapter5
5.1
5.1. ALGORITHM FOR EQUALIZERS-I AND II
Algorithm for Equalizers-I and II
Since the equalizers-I and II have similar architectures and share a single degree of freedom by having control over the high frequency boost, both of them use the same algorithm
which is discussed in this section. The only difference would be, for equalizer-I the source
degeneration capacitance has to be tuned by setting the binary control bits <b0 ,b1 ,b2 >.
While for equalizer-II the source degeneration resistance has to be tuned by setting the
DAC driving the gate voltage of the MOS resistor.
The adaptation algorithm works as follows:
• The aim is to find the equalizer setting which gives the maximum eye opening. When
coming from a bigger mask size to a small mask size, the equalizer setting which
gives zero mask errors first is the desired one.
• Initial mask size is set to 300mV (differential) vertical opening and 300ps horizontal
opening. It is more important to have a wider eye-opening at a particular vertical
mask size, as the vertical opening could be increased by increasing the gain of the
limiting amplifier stages after equalization. So initially the mask size is reduced only
by controlling the horizontal opening of the mask until its threshold level and then
further mask size is reduced by controlling the reference voltage levels.
• Since the range of control settings is less for equalizers-I and II, a full sweep through
all the settings are done and the mask errors corresponding to each setting is counted.
If none of the settings yield zero mask errors, the mask size is reduced by one step
in time, and the process is repeated again until one of the settings converge to zero
mask errors.
• If multiple settings converge to zero mask errors, the average of the control settings
is taken and rounded to the next higher control value.
In this way the algorithm converges to a particular equalizer setting that gives the maximum
eye opening. Table 5.1 shows the parameters used in the adaptation algorithm. The results
obtained are discussed in chapter 6.
5.2
Algorithm for Equalizer-III
A more complex approach is required for the adaptation of equalizer-III as it has two
degrees of controllability. Equalizer-III has 192 possible equalizer settings, which cannot
38
Chapter5
5.2. ALGORITHM FOR EQUALIZER-III
Parameter
Value
Horizontal Mask step size
20 ps
Vertical Mask step size
30 mV
Initial mask size (Horizontal)
300 ps
Initial mask size (Vertical)
300 mV
CDR step size
11.9 ps
Table 5.1: Adaptation algorithm control parameters for equalizers-I & II
be swept through to find the one that gives optimum equalization. An iterative approach
has been developed which allows the algorithm to converge to a setting in minimum time.
The flowchart for the algorithm is given in figure 5.3. The plot of eye-width measured
at 300 mV of vertical mask size over control settings (Rs and Cs ) sweep for equalizer-III
with one of the channel models for typical corner is shown in figure 5.2. The algorithm
works as follows:
• Start control setting is chosen at the middle of each control variable (shown by the
white spot in figure 5.2) such that the average distance to all the other points is minimum. Start mask size is also set to a vertical opening of 300 mV and horizontal
opening of 300 ps. The only change to algorithm parameters shown in table 5.1
for equalizer-III is the horizontal mask step size is reduced to 10 ps to have better
precision in tracking mask errors.
• Even though it is expected that a setting with wider eye opening should have less
number of mask errors than one with smaller eye opening it need not be always true.
This is because the number of mask errors need not vary in similar fashion for each
control setting. For a given mask size, a setting with less mask errors might actually
have a smaller eye opening than one with more mask errors. So it is not possible
to conclude which setting has a wider eye opening just by comparing the number of
mask errors. The only way to compare two settings is to find out which one first gives
zero mask errors when coming down in mask size. Hence we come down in mask
size by controlling the horizontal width of the mask until number of mask errors
(denoted by ME in flowchart) is less than 20 and then start comparing with other
39
Chapter5
5.2. ALGORITHM FOR EQUALIZER-III
points to find the one with zero mask errors. This also reduces the convergence time
of the algorithm.
• A comparison on the number of mask errors is done for all four neighboring settings by increasing/decreasing the source degeneration resistance/capacitance one at
a time. If any one of them has less number of mask errors when compared to the current setting, then it is made the current setting. If none of them have less number of
mask errors, the mask size is reduced by one step and check for neighboring settings
with less mask errors is repeated. This step is repeated until one of the settings gives
zero mask errors.
• Once a setting with zero mask errors is found, the mask size increased by two steps
and the above steps to converge to a zero mask error setting is repeated. This is done
so that there is a possibility for the algorithm to come out of any local minima that
might be present by evaluating for mask errors at a different mask size.
• In this manner the algorithm converges to the equalizer setting with the widest possible eye opening. For example, the path of the control setting changes is shown by
arrows and the final point is shown by the triangle in figure 5.2.
Equalizer-III eye width surface plot
Eye width @ 150mV (ps)
2.80E-010
2.60E-010
2.40E-010
2.20E-010
2.00E-010
1.80E-010
-4.00E-002
-6.00E-002
-8.00E-002
-1.00E-001
-1.20E-001
-1.40E-001
Rs
-1.60E-001
-1.80E-001
-2.00E-001
1.60E-010
1.40E-010
1.20E-010
1.00E-010
4
5
6
7
8
9
10
11
12
13
Cs
Figure 5.2: Surface plot of eye-width measured at 150mV reference level for equalizer-III
control setting sweep
40
Chapter5
5.2. ALGORITHM FOR EQUALIZER-III
Find best Equalizer
setting
Set Rs, Cs, Tmask,
Vmask, Run=1
Count mask errors(ME)
Tmask- -
False
ME<=20
True
min_err=ME
min_Rs=Rs
min_Cs=Cs
Rs++
Rs--
Cs++
Cs--
Count ME1
Count ME2
Count ME3
Count ME4
False
True
Rs=Rsi
Cs=Csi
MEmin<=
min_err
True
MEmin=0
False
True
DONE
Tmask--
Run=2
False
Rs=Rsi ; Cs=Csi
Run=2
Tmask+=2
Count ME
Figure 5.3: Flowchart of algorithm used for adaptation of Equalizer-III
41
Chapter5
5.2. ALGORITHM FOR EQUALIZER-III
The adaptation controller works on different algorithms for different equalizers. The
algorithm is independent of the operation of the EOM which is an advantage of this system
as the same EOM can be used for all types of equalizers. The algorithm for equalizer-III
uses a more complex approach than the ones used for equalizers-I and II due to the more
number of equalizer control settings. The simulation results showing the efficiency of these
algorithms are discussed in chapter 6.
42
Chapter 6
Layout and Simulation Results
In this chapter, the performance of the three equalizers and EOM implemented in layout
with the adaptation system is evaluated and a comparison on the results obtained is made.
The results shown focus on the performance of the three equalizers over corner variations
and the efficiency of the EOM and the adaptation controller in adapting the equalizer to
a setting which yields the largest eye opening or in other words the least ISI. For this a
3Gb/s pseudo-random binary source is used. The equalizer performance is analyzed over
different channel models which are discussed in section 6.2.
6.1
6.1.1
Data Generation and Channel modeling
Data Generation
A 3Gb/s random binary data need to be generated to verify the functionality of the equalizer.
But it is very difficult to generate an ideal random sequence. Hence a pseudo random binary
sequence (PRBS) is used as an alternative which also provides repeatability of the sequence
after a specific period. A PRBS is generated using linear feedback shift registers (LFSR).
The block diagram of the LFSR used to generate the PRBS-7 sequence used is shown in
figure 6.1. The polynomial for the PRBS7 = X 7 + X 6 + 1 and it generates a sequence with
127 (i.e 27 - 1) elements. A Verilog-A model has been used for generation of this PRBS
sequence.
43
Chapter6
6.1. DATA GENERATION AND CHANNEL MODELING
Figure 6.1: Block diagram of LFSR used to generate PRBS-7
Model Name
Type
-3dB Bandwidth
Attenuation
@ 1.5GHz
Length
Numerical
Aperture
mmf26NA19m
Plastic MMF
256.7 MHz
-18.06 dB
19 m
26
mmf36NA19m
Plastic MMF
214.28 MHz
-19.26 dB
19 m
36
LPF180MHz
RC LPF
179.49 MHz
-18.48 dB
-
-
Copper15m
Copper
224.7 MHz
-29.37 dB
15 m
-
Table 6.1: Characteristics of channel models used for simulation
6.1.2
Channel Modeling
Four different channel types were used in this work. Two of them being plastic multi mode
fibers (MMF) with different numerical apertures, a copper channel and an ideal RC low
pass filter (LPF). The wide range of channel types were used to study the performance
of the equalizers with different channel losses occurring in optical and electrical media.
Different models of each channel type for varying lengths have also been used.
Table 6.1 shows the parameters for each channel type with the longest length used.
It also gives specifics about the channel frequency response like the 3dB bandwidth and
the attenuation at Nyquist (1.5 GHz) frequency. The basic testbench setup is shown in
figure 6.2.
PRBS
source
Channel
model
Adaptive
Equalizer
Data out
Figure 6.2: Simulation testbench setup block diagram
44
Chapter6
6.2
6.2.1
6.2. EQUALIZER LAYOUT AND RESULTS
Equalizer layout and results
Equalizer-I
Figure 6.3 shows the layout for equalizer-I. Metal fringe capacitors have been used
for source degeneration capacitance. MOS switches which are controlled by the bits
<b0 ,b1 ,b2 > are also sized in a geometric progression for each parallel stage, such that
the parasitics of these transistors have a linear effect on the high frequency boost of the
equalizer when changing the control bits.
Figure 6.3: Layout of equalizer-I
Table 6.2 shows the RC extracted simulation results of a 3 stage cascaded equalizer
over PVT variations. Figure 6.4 gives the frequency response of each channel and the corresponding equalized signal for the equalizer setting yielding the maximum eye opening.
The best equalizer setting in these simulations have been found by sweeping through each
control setting and comparing the measured eye-width at 300mV vertical opening. All the
frequency responses given correspond to the typical corner.
6.2.2
Equalizer-II
Figure 6.5 shows the layout for equalizer-II. A NMOS transistor has been used to realize
the source degeneration resistance which is controlled by a voltage driven by a DAC. A
45
Chapter6
6.2. EQUALIZER LAYOUT AND RESULTS
AC Response
Name
Vis
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
V1
AC Response
V1
Name
20.0
-1.814275dB
-18.14429dB
Vis
V1
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
V1
20.0
-2.888565dB
-19.21858dB
Equalized signal response
0.0
M2: 32.35937kHz 313.127mdB
Equalized signal response
0.0
M3: 22.38721kHz 464.1238mdB
-1.814275dB
-2.888565dB
Channel response
Channel response
-18.14429dB
-40.0
-40.0
-60.0
-60.0
-80.0
-80.0
1.499456GHz
-100
4
10
5
10
6
10
7
10
8
1.499456GHz
-100
9
10
freq (Hz)
-19.21858dB
-20.0
V (dB)
V (dB)
-20.0
10
10
10
4
11
10
10
(a) Channel mmf26NA19m
7
10
8
10
freq (Hz)
9
10
10
10
11
10
(b) Channel mmf36NA19m
V1
Name
V1
10.0
-1.102512dB
-18.47827dB
Vis
V1
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
V1
25.0
-2.845128dB
-19.16876dB
Equalized signal response
0.0
M4: 18.40772kHz 425.5101mdB
-1.102512dB
Equalized signal response
Channel response
0.0
-10.0
-2.845128dB
M5: 22.69865MHz -2.879466dB
-18.47827dB
-20.0
-19.16876dB
Channel response
-25.0
-30.0
V (dB)
Vis
V (dB)
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
6
10
AC Response
AC Response
Name
5
10
-40.0
-50.0
-50.0
-60.0
-75.0
-70.0
1.499456GHz
-80.0
4
10
5
10
6
10
7
10
8
10
freq (Hz)
9
10
1.496602GHz
-100
10
10
7
11
10
10
(c) Channel LPF180MHz
8
10
9
10
freq (Hz)
10
10
11
10
(d) Channel Copper15m
Figure 6.4: Frequency response of equalizer-I over channel models for control setting yielding the widest eye opening
46
Chapter6
6.2. EQUALIZER LAYOUT AND RESULTS
Parameter
min
typ
max
Max relative peak gain (dB)
15.39
18.53
20.56
Peak frequency (GHz)
1.28
1.71
2.4
3dB Bandwidth (GHz)
12.65
17.01
21.86
Power consumption (mW)
-
1.38
-
Input transient amplitude (Vp-p)
-
0.8
-
Input common mode voltage (V)
0.7875
0.9
1.012
Output common mode voltage (V)
0.7875
0.9
1.012
Area consumed (um2 )
-
2373
-
Table 6.2: Simulation results over corner variations for equalizer-I with digitally tunable
source degeneration capacitance
Metal fringe capacitor has been used for the source degeneration capacitance.
Table 6.3 shows the RC extracted simulation results of a 2 stage cascaded equalizer
followed by 2 stages of limiting amplifiers over PVT variations. Limiting amplifiers
have to be used to ensure the DC gain of the equalizer stays above 1. Limiting amplifier
stages are made of simple non degenerated differential pair. The area consumed includes
the equalizer and limiting amplifier stages. Figure 6.6 gives the frequency response of
each channel and the corresponding equalized signal for the equalizer setting yielding the
maximum eye opening. The best equalizer setting in these simulations have been found by
sweeping through each control setting and comparing the measured eye-width at 300mV
vertical opening. All the frequency responses given correspond to the typical corner.
6.2.3
Equalizer-III
Figure 6.7 shows the layout for equalizer-III. A NMOS transistor has been used to realize
the source degeneration resistance of the first parallel input stage which is controlled by a
voltage driven by a DAC. Metal fringe capacitors have been used for the source degeneration capacitance of the two stages and for the coupling capacitance.
47
Chapter6
6.3. EOM LAYOUT AND RESULTS
Figure 6.5: Layout of equalizer-II
Table 6.4 shows the RC extracted simulation results of a 2 stage cascaded equalizer
followed by 3 stages of limiting amplifiers over PVT variations. Figure 6.8 gives the frequency response of each channel and the corresponding equalized signal for the equalizer
setting yielding the maximum eye opening. The best equalizer setting in these simulations
have been found by sweeping through each control setting and comparing the measured
eye-width at 300mV vertical opening. All the frequency responses given correspond to the
typical corner.
It can be noted that equalizer-III provides a more flat frequency response for the equalized signal upto Nyquist frequency when compared to equalizer-I and II. This is due to the
extra degree of freedom in equalizer-III where the range of frequencies over which an high
frequency boost is obtained can be controlled.
6.3
EOM layout and results
The main building blocks of the EOM are the fully differential difference amplifier and the
CML latch. The layout for the difference amplifier is given in figure 6.9. Table 6.5 gives
the results for the C-extracted simulation of the difference amplifier over PVT corners.
The results shown correspond to simulation with a 300mV reference input to the difference
amplifier. The input capacitance gives an estimate on how much loading is caused to the
preceding stages which are connected to the difference amplifier. The input capacitance
48
Chapter6
6.3. EOM LAYOUT AND RESULTS
Parameter
min
typ
max
Max relative peak gain (dB)
18.06
29.05
35.8
Peak frequency (GHz)
1.46
1.77
2.46
3dB Bandwidth (GHz)
12.7
29.6
62.7
Power consumption (mW)
-
3.4622
-
Input transient amplitude (Vp-p)
-
0.8
-
Input common mode voltage (V)
0.7875
0.9
1.012
Output common mode voltage (V)
0.7875
0.9
1.012
Area consumed (um2 )
-
1080.47
-
Table 6.3: Simulation results over corner variations for equalizer-II with source degeneration MOS resistor
Parameter
min
typ
max
Max relative peak gain (dB)
14.15
17.54
18.73
Peak frequency (GHz)
1.28
1.66
2.33
3dB Bandwidth (GHz)
8.74
11.64
15.37
Power consumption (mW)
-
6.8562
-
Input transient amplitude (Vp-p)
-
0.8
-
Input common mode voltage (V)
0.7875
0.9
1.012
Output common mode voltage (V)
0.7875
0.9
1.012
Area consumed (um2 )
-
7271.8
-
Table 6.4: Simulation results over corner variations for equalizer-III with two parallel input
source degeneration stages
49
Chapter6
6.3. EOM LAYOUT AND RESULTS
AC Response
AC Response
Name
Vis
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
V1
Name V1
25.0
9.5490744dB
-18.204282dB
Vis
V1
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
V1
25.0
8.6912987dB
-19.22308dB
Equalized signal response
9.5490744dB
M1: 22.908677kHz 10.445193dB
0.0
M3:
0.0 31.141056kHz 8.4314874dB
M4: 28.840315kHz 38.616393mdB
M2: 21.544347kHz -112.38071mdB
8.6912987dB
Channel response
-19.22308dB
-25.0
-18.204282dB
-25.0
V (dB)
V (dB)
-50.0
-50.0
-75.0
-75.0
-100.0
-100.0
-125.0
1.50199GHz
-125.0
4
10
5
10
6
10
7
10
8
10
freq (Hz)
1.50086GHz
-150.0
9
10
10
10
11
10
12
4
10
5
10
10
(a) Channel mmf26NA19m
AC Response
8
10
freq (Hz)
9
10
10
11
10
10
12
10
(b) Channel mmf36NA19m
V1
Name
25.0
9.5768796dB
-18.489401dB
V1
Vis
V1
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
Equalized signal response
V1
25.0
8.9151435dB
-19.133927dB
Equalized signal response
9.5768796dB
8.9151435dB
M5:
0.021.544347kHz 6.1149196dB
Channel response
M6: 20.26127kHz -53.417032ndB
0.0
M7: 23.095609MHz 2.7827688dB
M8: 22.868136MHz -3.3801376dB
-18.489401dB
Channel response
-25.0
-19.133927dB
-25.0
V (dB)
v (/outp /outn); ac dB20(V)
v (/cha_outp /cha_outn); ac dB20(V)
7
10
AC Response
Vis
V (dB)
Name
6
10
-50.0
-50.0
-75.0
-75.0
-100.0
-100.0
1.50138GHz
-125.0
4
10
5
10
6
10
7
10
8
10
freq (Hz)
9
10
1.49408GHz
-125.0
10
10
11
10
12
7
10
10
(c) Channel LPF180MHz
8
10
9
10
freq (Hz)
10
10
11
10
12
10
(d) Channel Copper15m
Figure 6.6: Frequency response of equalizer-II over channel models for control setting
yielding the widest eye opening
50
Chapter6
6.3. EOM LAYOUT AND RESULTS
Figure 6.7: Layout of equalizer-III
is calculated by taking the derivative w.r.t frequency of the AC current drawn from the
input source with an AC amplitude of 1V. Equation 6.1 shows the calculation of input
capacitance.
1 dIAC C=
(6.1)
2π d f VAC =1
Parameter
min
typ
max
DC gain (dB)
0.043
2.028
3.45
Bandwidth (GHz)
5.62
6.19
7.41
Input capacitance (fF) (single ended)
6.74
6.96
7.62
Power consumption (mW)
-
0.7946
-
Area consumed (um2 )
-
241.68
-
Table 6.5: Simulation results over corner variations for fully differential difference amplifier
51
Chapter6
6.3. EOM LAYOUT AND RESULTS
AC Response
Name
AC Response
Vis
ac
v (/cha_outp /cha_outn); ac dB20(V)
V1
V1
Name
25.0
15.62202dB
-13.5125dB
Equalized signale response
Vis
V1
ac
v (/cha_outp /cha_outn); ac dB20(V)
15.62202dB
M5: 31.98895kHz 17.28881dB
Equalized signal resposne
M3: 23.26305kHz 17.43981dB
Channel response
0.0
V1
25.0
12.66753dB
-19.21858dB
Channel response
0.0
M6: 35.48134kHz -112.3804mdB
12.66753dB
M4: 19.95262kHz 38.61632mdB
-13.5125dB
-19.21858dB
-25.0
V (dB)
V (dB)
-25.0
-50.0
-50.0
-75.0
-75.0
1.0GHz
-100
4
10
5
10
6
10
7
10
8
1.499456GHz
-100
9
10
freq (Hz)
10
10
10
11
4
10
5
10
10
(a) Channel mmf26NA19m
AC Response
8
9
10
freq (Hz)
10
10
10
11
10
AC Response
Vis
V1
V1
Name
20.0
14.63446dB
-18.47827dB
Equalized signal response
M7: 38.01894kHz 17.4012dB
Vis
V1
ac
v (/cha_outp /cha_outn);14.63446dB
ac dB20(V)
12.93773dB
-19.01676dB
25.0
Channel response
0.0
V1
50.0
Equalized signal response
M8: 30.66667kHz -122.3713ndB
12.93773dB
M9: 23.62291MHz 14.3597dB
0.0
-18.47827dB
-20.0
Channel response
M10: 23.33458MHz -3.442968dB
V (dB)
ac
v (/cha_outp /cha_outn); ac dB20(V)
7
10
(b) Channel mmf36NA19m
V (dB)
Name
6
10
-19.01676dB
-25.0
-40.0
-50.0
-60.0
-75.0
1.499456GHz
-80.0
4
10
5
10
6
10
7
10
8
10
freq (Hz)
9
10
1.485596GHz
-100
10
10
7
11
10
10
(c) Channel LPF180MHz
8
10
9
10
freq (Hz)
10
10
11
10
(d) Channel Copper15m
Figure 6.8: Frequency response of equalizer-III over channel models for control setting
yielding the widest eye opening
52
Chapter6
6.3. EOM LAYOUT AND RESULTS
Figure 6.9: Layout of fully differential difference amplifier
Parameter
min
typ
max
DC gain (dB)
4.6
6.62
8.44
Bandwidth (GHz)
4.4
5.79
7.64
Input capacitance (fF) (single ended)
4.86
5.042
5.25
Power consumption (mW)
-
0.3946
-
Area consumed (um2 )
-
98.01
-
Table 6.6: Simulation results over corner variations for CML Latch
Figure 6.10 shows the layout for CML latch. Table 6.6 gives the results for C-extracted
simulation of CML latch over PVT corners. As per the EOM architecture discussed in
chapter 4, the equalizer output is connected to 2 difference amplifiers and a CML latch.
The input capacitance of the latch and the difference amplifier give an estimate on the
required driving capacity for the equalizer output and has been designed accordingly.
53
Chapter6
6.4. EQUALIZER WITH ADAPTATION SYSTEM RESULTS
Figure 6.10: Layout of CML latch
6.4
Equalizer with adaptation system results
This section gives a comparison on the EOM based adaptation loop performance with all
the three different equalizer architectures discussed earlier. Figures 6.11, 6.12 and 6.13
show the eye width values measured for each equalizer for simulations done at typical, fast
and slow corners respectively. The results corresponding to each channel model have been
shown.
The following inferences can be drawn from these results:
• For each equalizer, two curves have been plotted of which one indicates the maximum eye width that can be achieved for the equalizer. This value has been found by
comparing the eye widths for all possible equalizer setting (i.e. without the adaptation loop). The second curve shows the eye width measured for the equalizer setting
which is set by the adaptation loop. The comparison of these two curves gives an estimate on the performance of the EOM and the adaptation algorithm used. It shows
how well the adaptation loop can converge to the best equalizer setting. All the eye
width values have been measured at 300mV vertical mask opening.
• It can be noted that for all the corners, equalizer-I yields the least eye width which is
due to the limited controllability and the maximum boost that can be achieved with
the equalizer.
54
Chapter6
6.4. EQUALIZER WITH ADAPTATION SYSTEM RESULTS
Eye width @ 150mV [UI]
Corner: Typical
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Eq3-Best equalizer
setting2
Eq3-Equalizer set by
algorithm
Eq2-Best equalizer
setting
Eq2-Equalizer set by
algorithm
Eq1-Best equalizer
setting
Eq1-Equalizer set by
algorithm
Channel model
Figure 6.11:
10/21/2013
Eye width comparison for
each
equalizer on different channels with and1withAnand
Narayanan
out the adaptation algorithm for typical corner
• Equalizer-II provides a wider eye opening than equalizer-I due to the higher relative
peaking that equalizer-II can produce and more finer control over the high frequency
boost.
• For equalizer-I and II the adaptation loop almost works perfect by setting it to the
best possible control parameter value. The reason for this is the algorithm in these
cases works by sweeping through all the control settings and finds the one with zero
mask errors.
• It is very evident from these graphs that equalizer-III provides a wider eye opening for all channel models in all corners when compared to equalizer-I or II. The
higher degree of controllabilty in equalizer-III accounts for this better performance.
Equalizer-III with the adaptation loop provides an eye opening of above 65% (UI) at
300mV vertical mask opening over channel model and PVT variations.
• Maximum eye width is measured at slow corner and the least eye width is measured
at the fast corners. These give the best and worst case performance of the equalizer
over corners.
55
Chapter6
6.4. EQUALIZER WITH ADAPTATION SYSTEM RESULTS
Comparison Results
Eye width @ 150mV [UI]
Corner: Fast
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Eq3-Best equalizer
setting2
Eq3-Equalizer set by
algorithm
Eq2-Best equalizer
setting
Eq2-Equalizer set by
algorithm
Eq1-Best equalizer
setting
Eq1-Equalizer set by
algorithm
Channel model
10/21/2013
Anand
Narayanan
1 withFigure
6.12: Eye width comparison for
each
equalizer on different channels with and
out the adaptation algorithm for fast corner
Comparison Results
Eye width @ 150mV [UI]
Corner: Slow
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Eq3-Best equalizer
setting2
Eq3-Equalizer set by
algorithm
Eq2-Best equalizer
setting
Eq2-Equalizer set by
algorithm
Eq1-Best equalizer
setting
Eq1-Equalizer set by
algorithm
Channel model
10/21/2013
Anand
Narayanan
Figure
6.13: Eye width comparison for
each
equalizer on different channels with and1 without the adaptation algorithm for slow corner
56
Chapter6
6.4. EQUALIZER WITH ADAPTATION SYSTEM RESULTS
Figure 6.14: Eye width range achieved for equalizers-II & III over corner variations
10/21/2013
Anand Narayanan
1
Figure 6.14 shows the range of eye width measured over corners for equalizer-II and
III. It can been seen that equalizer-III not only provides a wider eye opening but also reduces the variation in the eye width (shown by the height of each bar) with PVT variations
when compared to equalizer-II. This is an advantage of having two degrees of freedom in
equalizer-III, which makes it adapt better to PVT variations.
Appendix A.1 gives the cadence SKILL function used to measure the eye-width and
find the control setting with widest eye-opening for equalizer-III. Appendix A.2 gives the
measured eye width values corresponding to figures 6.11, 6.12 and 6.13.
From the results discussed it is evident that equalizer-III outperforms equalizer-I and
II in effectively mitigating ISI. The efficiency of the adaptation system is also shown by
comparing the eye opening that can be achieved for each equalizer with and without the
adaption system. The lesser this difference is the better is the efficiency of the EOM and
the adaptation controller.
57
Chapter 7
Conclusion
Adaptive equalizers form an integral part of a digital communication system used to overcome the losses due to ISI and facilitate error free data recovery. In this thesis work, an
adaptive equalizer which works on a data rate of 3Gbps has been implemented in 65nm
CMOS technology.
Three different CTLE architectures based on the source degenerated differential pair
structure have been designed and compared. The first two equalizers provide limited
controllability over the equalizer response by just varying the high frequency boost. The
high frequency boost is controlled by moving the zero of the system which is done by
varying the source degeneration capacitance or resistance. The single degree of freedom
in these equalizers is not sufficient to have effective equalization over a wide range of
channel types and lengths which also vary with time. A third equalizer architecture with 2
degenerated differential pair stages with parallel inputs and capacitively coupled outputs is
designed. This equalizer provides 2 degrees of freedom by controlling the high frequency
boost as well as the width of the peak i.e. the range of frequencies which are boosted. This
enables the equalizer to provide a wider eye opening and better adapt to channel variations
and also to be used over a wider range of channel types and lengths.
An adaptation loop that generates an error signal related to equalized signal quality
is required to set the equalizer characteristics. In this work a two dimensional EOM
based adaptation system has been implemented. The EOM based technique has many
advantages over other similar techniques which work based on energy comparison in the
frequency domain. The EOM evaluates the actual signal quality in time domain as opposed
to spectrum balancing techniques which work in the frequency domain that might not be
58
Chapter7
7.1. FUTURE WORK
optimal due to various reasons. EOM provides a greater flexibility by being independent
of the adaptation algorithm which can be customized to suit the equalizer being used.
The adaptation algorithm takes information on the signal quality from the EOM and sets
the equalizer accordingly. This flexibility of using an EOM is specially advantageous for
equalizer-III which has 2 degrees of freedom.
Simulation results indicate that equalizer-III with the adaptation system yield the best
results over PVT variations for all channel models. It provides the maximum eye opening
when compared to equalizer-I and II with the adaptation system.
7.1
Future work
There are few advances that can be made to this work. One of them is to implement the
following blocks in hardware which have been kept behavioral in this work due to time
limitations:
• Clock data recovery (CDR)
• Adaptation controller
• Offset calibration controller
An important aspect that would be worth investigating in detail in the future is the sensitivity of the EOM. A deviation in the mask size and the actual eye opening was noticed
during simulations. For example, when the eye opening was 290 ps wide at a vertical
opening of 300mV for a particular equalizer setting, zero mask errors were measured only
for a mask size of 250 ps at 300mV vertical opening. This deviation was not observed in
the behavioral model simulations of the EOM. It is suspected to be because of the setup
and hold time violations in the flip-flops of the EOM. This can be investigated in future.
Another improvement that could be made is to the adaptation controller for equalizerIII. Preliminary simulations showed variations in results when changing some of the parameters in the algorithm such as the wait time between changing the equalizer settings
and start of counting the mask errors. Also in our implementation, we count the mask
errors for a single period of the PRBS7 sequence (i.e. 127 symbols), but this could be
increased to two or three or even more. Changing such parameters of the algorithm caused
small deviations in the results. The optimal value for these parameter need to be found
59
Chapter7
7.1. FUTURE WORK
and this can be done in hardware by setting these parameters through control registers and
monitoring the output. Doing this task in simulation is very time consuming.
60
A
Appendix
A.1
Cadence SKILL code for Eye-width measurement
The eyeMeasurement function in Cadence was initially used to measure the eye opening
of the equalized signal, but this function measures the eye width by taking the mean time
of the transitions and subtracting the 3σ (standard deviation) for each edge in the eye
diagram. Even-though this would give an approximate value of the eye width, we are more
interested in the actual eye width at 150 mV vertical opening on each side. To measure this
custom SKILL code was used which is shown below.
;SKILL function to measure the eye_width for corner simulations
with parametric sweep of 2 control variables for Equalier-3
;=item myskill_eyeWidth(wave_crossing_pts start_time)
; 2levels of control settings: B and V_ctrl_R
; get eye width (fbaud=3GHz)
;=cut
;
procedure(myskill_eyeWidth(fwve fst)
let( (nn yvec ll width mymax mymin st wve v0 v wfam0 wfam1)
if(famIsFamily(fwve) then
wfam0 = famCreateFamily( famGetSweepName(fwve) ’string )
;create new family
foreach( v0 famGetSweepValues( fwve ) ; first loop over
corners
fwve1= famValue(fwve v0)
fst1= famValue(fst v0)
wfam2 = famCreateFamily( "Control" ’double ) ;
foreach( v1 famGetSweepValues( fwve1 ) ; second loop over
control setting ’B_Cs’
61
A
A.1. CADENCE SKILL CODE FOR EYE-WIDTH MEASUREMENT
fwve2=famValue(fwve1 v1) ;select a wave from family (for a
particular B_Cs)
fst2=famValue(fst1 v1) ; select a wave from family (for a
particular B_Cs)
foreach( v famGetSweepValues( fwve2 ) ; third loop over
control setting V_ctrl_R
wve=famValue(fwve2 v) ;select a wave from family (for a
particular Vctrl_Rs)
st=famValue(fst2 v) ; select a wave from family (for a
particular Vctrl_Rs)
yvec=drGetWaveformYVec(wve) ; take y values
yvec_type = drGetWaveformYType(wve) ; get data type
nn=drVectorLength(yvec) ; vector length
ll=list()
for(i 0 nn-1 ll=cons( modf(( drGetElem( yvec i)-st+166.66p),333.33p)
ll )) ; stuff all values into the list
reverse(ll) ; right order
mymax = car( sort(ll ’greaterp)) ;max value in list
mymin = car( sort(ll ’lessp)) ;min value in list
width = 333.33p - (mymax-mymin) ;eyewidth=(1/fbaud)
-non_eyewidth
famAddValue( wfam2 v1-v width ) ;add width values to
family
)
)
famAddValue( wfam0 v0 wfam2 ) ;add width values to family
)
wfam0
)
)
)
The above function takes two inputs, one which gives the cross times for the signal at
150mV and other with the start time of evaluating the eye diagram. Both these inputs are
family of waves with a depth of 3 which corresponds to corner, Vctrl_Rs, B_Cs parameters
sweep. The output is a similar family of waves which gives the eye width corresponding to
each simulation but here the 2 control variables are combined into a single variable. The
62
A
A.1. CADENCE SKILL CODE FOR EYE-WIDTH MEASUREMENT
inputs can be generated using the commands below:
start_eye=cross(clip(VT("/outp")-VT("/outn") 15n 60n ) 0.0 1
"falling" nil nil );;
cross_150mV=cross(clip(VT("/outp")-VT("/outn") (start_eye-166.66p)
60n) 0.19 0 "either" t nil);;
eye_width1=myskill_eyeWidth(cross_150mV start_eye);; //command
to call the SKILL function
Similar SKILL function was used to extract the best control setting corresponding
to the largest eye opening. This function takes the eye-width values measured using the
previous SKILL function as input and finds the control setting (Vctrl_Rs and B_Cs) which
yields the largest eye width for each corner. It takes two inputs for the eye widths measured
at 150mV and 0mV vertical level and the code is given below.
;SKILL function to find the control setting corresponding to
widest eye
;=item myskill_ctrl_sel(select the best control voltages)
;
; get best control voltages (fbaud=3GHz)
;=cut
;
procedure(myskill_ctrl_sel(eyew1 eyew2)
let( (nn yvec ll width mymax mymin st wve v0 v wfam0 wfam1)
if(famIsFamily(eyew1) then
wfam0 = famCreateFamily( famGetSweepName(eyew1) ’string )
;create new family
foreach( v0 famGetSweepValues( eyew1 ) ; first loop over
corners
feyew1= famValue(eyew1 v0)
feyew2= famValue(eyew2 v0)
wfam1 = famCreateFamily( "Control" ’double ) ;
foreach( v famGetSweepValues( feyew1 ) ; second loop over
control setting "Control"
w1=famValue(feyew1 v) ;select a wave from family (for a
particular control setting)
w2=famValue(feyew2 v) ;select a wave from family (for a
particular control setting)
63
A
A.2. EYE WIDTH VALUES
best=if((w2>w1) w1 0.0)
famAddValue( wfam1 v best ) ;add width values to family
)
famAddValue( wfam0 v0 xmax(wfam1) ) ;add best control setting
values to family
)
wfam0
)
)
)
A.2
Eye width values
This section gives the eye width values measured for each equalizer with and without
the adaptation system and their corresponding control setting which gives the best eye
opening. The values correspond to typical, slow and fast corners for simulations done with
different channel models.
64
A
A.2. EYE WIDTH VALUES
Equalizer-III
Channel
model
mmf26NA19m
mmf36NA19m
LPF180MHz
Copper15m
Without Adaptation system
Corner
Vctrl_Rs B_Cs
(mV)
Width @
150 mV
With adaptation system
Vctrl_Rs B_Cs
(mV)
Width @
150 mV
Typical
-120
7
269.3 ps
-140
6
254.7 ps
Slow
-180
8
284.8 ps
-220
8
266.5 ps
Fast
-100
13
232.3 ps
-100
12
227.7 ps
Typical
-120
8
281.6 ps
-140
8
276.3 ps
Slow
-180
11
291.5 ps
-180
12
286.7 ps
Fast
-100
14
245.9 ps
-140
13
230.7 ps
Typical
-140
10
295.3 ps
-140
10
295.3 ps
Slow
-220
14
302 ps
-220
12
294.5 ps
Fast
-140
15
270
-140
15
270 ps
Typical
-80
8
269.5 ps
-100
7
254.7 ps
Slow
-120
10
276.1 ps
-120
11
272.5 ps
Fast
-20
12
224.9 ps
-40
11
217.1 ps
Table A.2: Eye width values measured at 150mV reference level over corner variations for
equalizer-III with corresponding control settings
65
A
A.2. EYE WIDTH VALUES
Equalizer-II
Channel
model
mmf26NA19m
mmf36NA19m
LPF180MHz
Copper15m
Corner
Without Adaptation system
With adaptation system
Vctrl_Rs Width @
(mV)
150 mV
Vctrl_Rs Width @
(mV)
150 mV
Typical
-130
234.6 ps
-130
234.6 ps
Slow
-170
247.6 ps
-180
238.6 ps
Fast
-90
168.9 ps
-90
168.9 ps
Typical
-140
239.8 ps
-140
239.8 ps
Slow
-180
255.5 ps
-190
251.8 ps
Fast
-90
164.6 ps
-100
158.3 ps
Typical
-150
269.2 ps
-150
269.2 ps
Slow
-200
285.8 ps
-190
277.4 ps
Fast
-110
231 ps
-110
231 ps
Typical
-130
246.6 ps
-130
246.6 ps
Slow
-170
260.4 ps
-180
258.2 ps
Fast
-90
184.7 ps
-90
184.7 ps
Table A.4: Eye width values measured at 150mV reference level over corner variations for
equalizer-II with corresponding control settings
66
A
A.2. EYE WIDTH VALUES
Equalizer-I
Channel
model
mmf26NA19m
mmf36NA19m
LPF180MHz
Copper15m
Without Adaptation system
With Adaptation system
Corner
B_Cs
Width @
150 mV
B_Cs
Width @
150 mV
Typical
4
165.3 ps
4
165.3 ps
Slow
5
222.1 ps
7
204 ps
Fast
7
69.58 ps
6
65.7 ps
Typical
4
168.4 ps
5
166.3 ps
Slow
5
223.5 ps
7
209.4 ps
Fast
7
59.93 ps
7
59.93 ps
Typical
5
238.1 ps
5
238.1 ps
Slow
6
269.3 ps
7
265.8 ps
Fast
7
137.6 ps
7
137.6 ps
Typical
4
174.7 ps
5
173.5 ps
Slow
4
215.2 ps
6
200.4 ps
Fast
7
78.45 ps
7
78.45 ps
Table A.6: Eye width values measured at 150mV reference level over corner variations for
equalizer-I with corresponding control settings
67
Bibliography
[1] J. Lee, “A 20Gb/s adaptive equalizer in 0.13/spl mu/m CMOS technology,” in SolidState Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, 2006, pp. 273–282.
[2] J. Liu and X. Lin, “Equalization in high-speed communication systems,” Circuits and
Systems Magazine, IEEE, vol. 4, no. 2, pp. 4–17, 2004.
[3] S. Gondi and B. Razavi, “Equalization and clock and data recovery techniques for
10-Gb/s CMOS serial-link receivers,” Solid-State Circuits, IEEE Journal of, vol. 42,
no. 9, pp. 1999–2011, 2007.
[4] J.-S. Choi, M.-S. Hwang, and D.-K. Jeong, “A 0.18- mu/m CMOS 3.5-Gb/s
continuous-time adaptive cable equalizer using enhanced low-frequency gain control
method,” Solid-State Circuits, IEEE Journal of, vol. 39, no. 3, pp. 419–425, 2004.
[5] C. Gimeno, C. Aldea, S. Celma, F. Aznar, and C. Sanchez-Azqueta, “A CMOS
continuous-time equalizer for short-reach optical communications,” in Circuit Theory and Design (ECCTD), 2011 20th European Conference on, 2011, pp. 154–157.
[6] C. H. Lee, M. Mustaffa, and K. H. Chan, “Comparison of receiver equalization using first-order and second-order continuous-time linear equalizer in 45 nm process
technology,” in Intelligent and Advanced Systems (ICIAS), 2012 4th International
Conference on, vol. 2, 2012, pp. 795–800.
[7] J. Bulzacchelli, T. Beukema, D. Storaska, P. Hsieh, S. Rylov, D. Furrer, D. Gardellini,
A. Prati, C. Menolfi, D. Hanson, J. Hertle, T. Morf, V. Sharma, R. Kelkar, H. Ainspan,
W. Kelly, G. Ritter, J. Garlett, R. Callan, T. Toifl, and D. Friedman, “A 28Gb/s 4-tap
FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology,” in SolidState Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, 2012, pp. 324–326.
68
A
BIBLIOGRAPHY
[8] A. Baker, “An adaptive cable equalizer for serial digital video rates to 400 Mb/s,”
in Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC.,
1996 IEEE International, 1996, pp. 174–175.
[9] S. Gondi, J. Lee, D. Takeuchi, and B. Razavi, “A 10Gb/s CMOS adaptive equalizer for
backplane applications,” in Solid-State Circuits Conference, 2005. Digest of Technical
Papers. ISSCC. 2005 IEEE International, 2005, pp. 328–601 Vol. 1.
[10] H.-Y. Joo, K.-S. Ha, and L.-S. Kim, “A data pattern-tolerant adaptive equalizer using
spectrum balancing method,” in VLSI Circuits, 2009 Symposium on, 2009, pp. 220–
221.
[11] R. Samrai and F. Yuan, “An overview of design techniques for on-chip eye-monitors
of Gbps data links,” International Proceedings of Computer Science and Information
Tech, vol. 50, p. 343, November 2012.
[12] B. Analui, A. Rylyakov, S. Rylov, M. Meghelli, and A. Hajimiri, “A 10Gb/s eyeopening monitor in 0.13 mu/m CMOS,” in Solid-State Circuits Conference, 2005.
Digest of Technical Papers. ISSCC. 2005 IEEE International, 2005, pp. 332–602 Vol.
1.
[13] T. Suttorp and U. Langmann, “A 10Gb/s CMOS serial-link receiver using eye-opening
monitoring for adaptive equalization and for clock and data recovery,” in Custom
Integrated Circuits Conference, 2007. CICC ’07. IEEE, 2007, pp. 277–280.
[14] D. Bhatta, K.-H. Lee, H.-S. Kim, E. Gebara, and J. Laskar, “A 10Gb/s two dimensional scanning eye opening monitor in 0.18um CMOS process,” in Microwave Symposium Digest, 2009. MTT ’09. IEEE MTT-S International, 2009, pp. 1141–1144.
[15] B. Razavi, Design of Integrated Circuits for Optical Communications. Wiley, 2012.
[Online]. Available: http://books.google.co.in/books?id=AcqwbVZWVzAC
[16] B. Razavi, Ed., Design of Analog CMOS Integrated Circuits.
McGraw-Hill, Inc., 2001.
New York, NY, USA:
[17] T. Matthews and P. Heedley, “A simulation method for accurately determining DC
and dynamic offsets in comparators,” in Circuits and Systems, 2005. 48th Midwest
Symposium on, 2005, pp. 1815–1818 Vol. 2.
69
A
BIBLIOGRAPHY
[18] P. Figueiredo and J. Vital, “Kickback noise reduction techniques for CMOS latched
comparators,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 53,
no. 7, pp. 541–545, 2006.
[19] H. Noguchi, N. Yoshida, H. Uchida, M. Ozaki, S. Kanemitsu, and S. Wada, “A 40Gb/s CDR circuit with adaptive decision-point control based on eye-opening monitor
feedback,” Solid-State Circuits, IEEE Journal of, vol. 43, no. 12, pp. 2929–2938,
2008.
70