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February 27, 2004
Table of Contents
Maxim
MAX3780CCQ
Quad 2.5Gbps
Cable Transceiver
Partial Circuit Analysis
Table of Contents
Introduction ............................................................................................... Page 1
List of Figures ........................................................................................... Page 2
Device Summary Sheet............................................................................. Page 7
Top Level Diagram ...................................................................................... Tab 1
TX PLL (Clock Multiplier)............................................................................ Tab 2
RX PLL (Clock Recovery ............................................................................ Tab 3
RX DLL (Phase Recovery) .......................................................................... Tab 4
Receiver Output Stage................................................................................ Tab 5
Lock Indicator Output ................................................................................. Tab 6
Reference Current Sources........................................................................ Tab 7
Signal Naming Conventions ...................................................................... Tab 8
Signal Cross-Reference List ...................................................................... Tab 9
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Maxim MAX3780CCQ Quad 2.5Gbps Cable Transceiver
Page 3
List of Figures
0.1.1
0.1.2
0.1.3
0.1.4
Package Markings
Package X-Ray
Pin Configuration
Die Markings
0.2.0
Die Photograph
0.2.1
Annotated Die Photograph
0.2.2
Die Architecture
0.2.3
Inductor – Metal 2 and Metal 3
0.2.4
NPN Transistor Type A1
0.2.5
NPN Transistor Type A2
0.2.6
NPN Transistor Type A3
0.2.7
NPN Transistor Type A4
0.2.8
NPN Transistor Type B1
0.2.9
NPN Transistor Type B2
0.2.10
NPN Transistor Type B3
0.2.11
NPN Transistor Type B3 with Four Emitters
0.2.12
NPN Transistor Type B4 with Two Emitters
0.2.13
PNP Transistor
0.3.0
I/O Protection
0.4.1
CML Inverter / Buffer Definitions I
0.4.2
CML Inverter / Buffer Definitions II
0.4.3
CML Inverter / Buffer Definitions III
0.5.1
CML NAND / AND Definitions I
0.5.2
CML NAND / AND Definitions II
0.6.1
CML OR / NOR Definitions I
0.6.2
CML OR / NOR Definitions II
0.7.1
CML XOR / XNOR Definition
0.8.1
CML Multiplexer Definitions I
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Maxim MAX3780CCQ Quad 2.5Gbps Cable Transceiver
0.8.2
CML Multiplexer Definitions II
0.8.3
CML Multiplexer Definitions III
0.8.4
CML Multiplexer Definitions IV
0.9.1
CML Latch Definition I
0.9.2
CML Latch Definitions II
0.10.1
CML Flip-Flop Definition I
0.10.2
CML Flip-Flop Definition II
0.10.3
CML Flip-Flop Definition III
0.10.4
CML Flip-Flop Definition IV
0.10.5
CML Flip-Flop Definition V
0.10.6
CML Flip-Flop Definition VI
0.11.1
CML Level Shifter Definitions I
0.11.2
CML Level Shifter Definitions II
0.11.3
CML Level Shifter Definitions III
0.11.4
CML Level Shifter Definitions IV
0.12.1
CML-to-BIAS Converter Definition
0.12.2
Bias Generator Definition
1.0.0
Top Level Diagram
2.0.0
TX PLL (Clock Multiplier)
2.1.0
Reference Clock Interface
2.2.0
Phase Frequency Detector
2.3.0
Charge Pump
2.4.0
Loop Filter Amplifier
2.5.0
VCO Control Amplifier
2.6.0
Voltage Controlled Oscillator
2.7.0
VCO Frequency Divider I
2.8.0
Start-up/ Test Frequency Divider
2.9.0
VCO Frequency Divider II
2.10.0
Control Logic
Page 4
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Maxim MAX3780CCQ Quad 2.5Gbps Cable Transceiver
2.11.0
Bias Generator I
2.12.0
Bias Generator II
2.13.0
VCO Bias Generator
3.0.0
RX PLL (Clock Recovery)
3.1.0
Data Gate
3.2.0
Phase Detector
3.2.1
Phase Detector and Data Retiming
3.2.2
Additional Charge Pump
3.2.3
Buffer
3.3.0
Loop Filter Amplifier
3.4.0
VCO Control Amplifier
3.4.1
VCO Bandgap Reference II
3.5.0
Voltage Controlled Oscillator
3.6.0
VCO Bias Generator
3.7.0
VCO Bandgap Reference I
3.8.0
Recovered Clock Test MUX
3.9.0
VCO Frequency Divider
3.9.1
Frequency Divider-by-4
3.9.2
Frequency Divider-by-5
3.9.3
Frequency Divider-by-16
3.9.4
Programmable Delay
3.9.5
Frequency Divider-by-2
3.10.0
Prelock State Machine
3.10.1
Quadrature Generator
3.10.2
Lock Detector
3.10.3
Prelock Register I
3.10.4
Prelock Register II
3.10.5
Prelock Register III
3.10.6
Lock State Decoder
3.10.7
Divide-by-2 Counter
Page 5
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Maxim MAX3780CCQ Quad 2.5Gbps Cable Transceiver
3.10.8
High State Delay
3.10.9
High State Delay Cell
3.10.10
Logic
3.10.11
Sweep Control
3.10.12
Sweep Enable Register
3.11.0
Sweep Enable Control
3.12.0
Control Logic
4.0.0
RX DLL (Phase Recovery)
4.1.0
Controlled Delay Line
4.1.1
Controlled Delay Cell
4.2.0
Phase Detector
4.2.1
Phase Detector and Data Retiming
4.2.2
Additional Charge Pump
4.3.0
Delay Control Amplifier
4.4.0
Delay Control Enable
5.0.0
Receiver Output Stage
5.1.0
LVDS Transmitter
5.1.1
Data/Clock Buffer
5.1.2
LVDS Output Driver
5.2.0
Common Mode Feedback Circuit
5.3.0
Shunt Circuit
5.4.0
Bias Current Sources
6.0.0
Lock Indicator Output
7.0.0
Reference Current Sources
7.1.0
Reference Current Source
A.1.0
A.1.1
A.2.0
A.3.0
A.4.0
Page 6
Symbol Conventions - 1
Symbol Conventions - 2
Logic Gate Size Notation
Transistor Size Notation
Capacitor Size Notation
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