Data Acquisition Subsystems
General Considerations
Operation
Each subsystem, when provided with a DC 5V power rail and 0V ground rail, will, by
default, be activated. This design decision was made because of the expected short
duration of centrifuge operation and the very small power consumption of each system.
Of course the VGA-to-NTSC conversion system will require a valid VGA input in order
to produce an NTSC television signal, but both the AD725 and oscillator will be active as
soon as they PCB terminal block is connected to the DC power input. Hence, in order to
operate any or all of the three subsystems, power merely needs to be connected, and valid
data will be available immediately (or as soon as the VGA signal is available, in the case
of the converter).
Power Consumption
A single 5V-0V DC power supply provided via the slip ring is adequate for running all
three subsystems. Lab evaluations of each subsystem have found power dissipation
consistent with what is suggested by manufacture datasheets. The accelerometer system,
the ADXL202 IC being the only component that dissipates power, draws about 1mA
during operation. The VGA-to-NTSC conversion board draws about 35mA during
operation, approximately what the datasheet of the AD725 performing the conversion
lists. Finally, an individual strain gage bridge with amplification circuitry draws about
10mA. With 24 strain gages, two accelerometers and a single video conversion circuit,
the total current draw from a common 5V DC supply should be less than 300mA. The
5V and ground power supply channels of the slip ring should have more than adequate
capability to handle this current, as well as the additional current that will be drawn by
the microcomputer used for processing video, strain and acceleration readings.
1. Accelerometers
Figure 1.1 PCB Layout of Accelerometer Circuitry
Figure 1.2 Schematic of Accelerometer Circuitry
The Accelerometer hardware for detecting low frequency vibration in the centrifuge arms
consists of Analog Devices ADXL202 accelerometer on a printed circuit board. The
ADXL202 provides a pulse width modulated signal measuring acceleration along the X
and Y axes of the part (see datasheet). The accelerometer PCBs should be affixed to the
very end of each centrifuge arm, and oriented such that one axis is perpendicular to the
ground, and the other is tangential to the direction of the centrifuge’s rotation.
A nominal duty cycle of 50% represents zero acceleration. A 12.5% variation in the
duty cycle corresponds with 1G change in acceleration. Calibration should be done to
confirm the exact variation in duty cycle due to acceleration as described in the
ADXL202 datasheet. The period T2 of the PWM signal is set using a potentiometer (Rset
in Figure 1.1) between the ADXL202 pin 5 and ground. The value of the period T2 is
described by equation (1).
(1) T 2 =
Rset (Ω)
sec
125MΩ
A Bourns Series 3006P potentiometer (Digi-key part number: 3006P-254-ND) with a
maximum 250K resistance was chosen as Rset for the initial design, allowing a maximum
T2 period of 2ms that can be decreased as desired.
A 4 input terminal block provides the circuit with output paths for the PWM signal for
the X and Y axis measurements, as well as 5V power rail and 0V ground for the IC. A
shielded four conductor cable should be used to provide these connections to the system
power supply and the data acquisition unit. The Digi-key part number for the four input
terminal block is ED2221, and the appropriate connections with the PCB layout are
shown in Figure 1 below. A .1uF power supply filter capacitor should be connected to
C1 as shown in Figure 1. Capacitors Cx and Cy allow the signal bandwidth of the
respective output channels to be set by adding a capacitor. The low pass filter created at
this stage has a 3dB frequency described in equation (2):
(2) F−3dB =
5uF
C ( X ,Y )
It should be noted that the internal resistor of the ADXL202 that determines the
bandwidth of this low pass filter can vary significantly, the actual bandwidth should be
empirically verified if it is a significant concern.
The ADXL202 is rated to measure acceleration of up to ±2G. If a higher measurements
of acceleration are desired, an ADXL210, which has an identical package and pinout, can
be used to detect acceleration values of up to ±10G .
ADXL202:
http://www.analog.com/UploadedFiles/Data_Sheets/ADXL202_210.pdf
Terminal Blocks:
http://dkc3.digikey.com/PDF/T071/P0284.pdf
2. VGA to NTSC Conversion
Figure 2.1: PCB Layout of Video Conversion Circuitry
Figure 2.2: Schematic of Video Conversion Circuitry
Hardware
The VGA to NTSC is achieved on a single printed circuit board by taking the standard
VGA output from a computer and a 15DB connector, and converting it via an Analog
Devices AD725AR. After filtering, the composite NTSC is available via a BNC
connector. In addition to a male/female 15DB cable connected to the VGA source (the
connector on the PCB in the current design is male), the board only requires a 5V power
rail and 0V ground rail from the system power supply, which can be connected via a two
input terminal block (see Figure 2.1).
Any standard 15DB-to-PCB connector should suffice. Either a male or female connector
can be chosen, as this will determine the gender of the PCB end of the VGA cable.
Horizontal and vertical sync signals as well as ground from the VGA connector are traced
directly to the appropriate connections on the AD725. The red, green and blue VGA
inputs should be terminated to ground with 75Ω via the resistors Rr, Rg, and Rb,
respectively, and then each passed in series through .1uF capacitors CR, CG and CB.
Both the analog and digital power pins requires separate filter capacitance networks
connected to ground. .1uF capacitors should be connected across CA1 and CD1 and
10uF tantalum capacitors should be connected across CA2 and CD2. The 5V and 0V volt
rails should be connected to the two input terminal block (Digikey part number ED1623ND) as shown in the Figure 1.
Resistor Ron provides a path to the 5V rail for pins 1 and 5 on the AD725. A logic high
value on pin 1 selects NTSC encoding for the output signal (as is desired) and the logic
high value on pin 5 asserts the chip enable signal. Since these are both digital logic
inputs, a large resistance should be chosen for Ron. 10KΩ is used for the current design
iteration. The AD725 requires a 4FSC clock signal from an oscillator. A 4 pin CTS
MXO45 oscillator (OSC1) is utilized (Digikey part number CTX165-ND). Pin 8 is
connected to the 5V rail, pin 4 to the 0V ground, and pin 5 connects the 14.318180Mhz
clock frequency directly the AD725 4FSC input (pin 3). If desired, the via adjacent to
pin 8 of OSC1 can be connected with a .1uF capacitor to ground to provide power supply
filtering for the part. Pin 1 of OSC1 is left open, which enables the clock output.
The AD725 provides three analog video outputs: chroma, luminance and composite.
Each output requires, in series, a polarized 220uF capacitor connected at Ccr, Cl and Ccp,
respectively, and then 75Ω resistors Rcr, Rl and Rcp. The composite output is available
from a BNC connector (BNC1). The ground of BNC1 is connected to the common
ground rail of the conversion circuitry. Both the signal and ground from the BNC cable
should be connected to separate channels of the slip ring, that is, the system power supply
ground provided from the slip ring should not be used as the ground for the video input of
the television with which the NTSC signal is viewed.
The only unconnected pin on the AD725 in this implementation is YTRAP, pin 12. A
notch filter can be implemented on this pin to improve the quality of the composite video,
however, this feature is not utilized currently. A connection is available to this pin from
the via labeled YTRAP and a network of vias is available close by on the board if it is
desired to implement this feature in the future. Consult the AD725 datasheet for specific
details.
Software
With the video from the several cameras multiplexed into a single VGA frame, a couple
additional considerations are required for the AD725 to properly convert the VGA signal.
First, the resolution of the VGA output should be set as low as possible (generally 640 x
480) to closely match the resolution of the NTSC output (400lines/frame) in order to
minimize losing a portion of the image. Second, the refresh rate of the VGA signal
should be set to 60Hz in order to sync up with the 60Hz vertical sync of the NTSC
output. Further modification of the VGA controller driver may be required in order to
achieve the interlacing of 60Hz on the R,G and B signals. Consult the AD725 datasheet
and appropriate video controller manufacturer for more information.
Oscillator:
http://rocky.digikey.com/WebLib/CTS/Web%20Data/MXO45,45T,45HS,45HST.pdf
AD725:
http://www.analog.com/UploadedFiles/Data_Sheets/AD725.pdf
3. Strain Gages
Figure 3.1: PCB Layout of Strain Gage Circuitry
Figure 3.2: Schematic of Strain Gage Circuitry
Hardware
The Omega SG-3/350-LY11 strain gages used have a nominal (unstrained) resistance of
350Ω. With a gage factor of approximately 2, the relationship between strain (ε) and
resistance is described in equation (3.1).
 ∆R 


350Ω 
(3.1) ε = 
2
The strain gage is used as one resistor of a four resistor Wheatstone bridge, and is
connected to the 5V rail and one output node of the bridge. The two resistors connected
to ground in the bridge, RS2 and RS4, are 350Ω resistors. The remaining resistance,
connected between the 5V rail and the output node opposite the strain gage is divided in
series between a 250Ω (RS1) resistor and a 200Ω potentiometer (Rvs, Digikey part
number 3006P-201-ND). With the potentiometer Rvs, any voltage differential between
the output nodes of the Wheatstone bridge caused by variation from nominal values in the
other resistors can be zeroed out during calibration while the strain gage is unstrained. A
voltage difference of less than a tenth of a millivolt at the inputs of the AD620
instrumentation amplifier should be achievable simply by using a flat head screwdriver to
adjust the wiper position of the potentiometer Rvs.
An AD620 Instrumentation Amplifier is used to amplify the difference between the
Wheatstone bridge output nodes such that the central data acquisition computer’s analog
to digital converters can detect much smaller changes in strain. The AD620 operates
from the 5V system power supply, and has a gain that can be set via a 500Ω
potentiometer (Rvg, Digikey part number 3006P-501-ND). Equation (3.2) shows the
gain equation of the AD620 as determined by potentiometer Rvg.
 49.4kΩ 
(3.2) G = 
+ 1V / V
 Rvg

The PCB layout in Figure 3.2 shows the proper connections to the 5 input terminal block
(Digikey part number ED2222-ND) of the strain gage circuit. 5V, Vout and 0V should
be connected to a shielded 3 conductor cable. Vout should be evaluated at the data
acquisition analog-to-digital converters with respect to the 0V system ground. S+ and Sshould be connected to the leads of the strain gage, and the strain gage affixed to the
device under test or centrifuge structure as determined by the mechanical analysis.
Theory
The differential output voltage of the Wheatstone bridge is described in equation (3.3),
where Vb- represents the node voltage on the side connected with the strain gage, and Vb+
the opposite side.
(3.3) Vdiff = Vb + − Vb−
Where
RS 4
RS 4 + RSTRAIN + ∆RSTRAIN
RS 2
(3.5) Vb + = Vcc *
RS 2 + RS1 + RVS
Vcc represents the 5V rail and RSTRAIN represents the nominal resistance of the unstrained
gage. Rearranging equation (3.1) in terms of ∆RSTRAIN for (3.6), equation (3.4) yields
(3.7)
(3.4) Vb − = Vcc *
 ∆RSTRAIN

R
ε =  STRAIN
2
(3.6) ∆RSTRAIN
(3.7) Vb − = Vcc



= 2 * ε * RSTRAIN
RS 4
RS 4 + RSTRAIN + 2 * ε * RSTRAIN
Solving (3.3) and (3.7) for strain ε yields:

( RS 4 + RSTRAIN ) 
 + Vdiff ( RS 4 + R STRAIN )
Vcc RS 4 − RS 2
( RS 2 + RS1) 

(3.8) ε =
 Vcc * RS 2


− Vdiff 2 * RSTRAIN
 ( RS 2 + RS1)

Assuming all resistors have a nominal value of 350Ω, and the 5V rail is used (3.8)
simplifies to:
(3.9) ε =
Vdiff
2.5V − Vdiff
Using either (3.9) or (3.8) the value of Vdiff can be used to determine the strain
experienced by the gage. The AD620 provides amplification of Vdiff such that much
smaller degrees of strain can be detected. To extract the value of strain from the output
of the AD620 (as provided to the terminal block output connection and eventually to the
analog-to-digital converter), the Vout voltage can simply be divided by the gain value of
the amp determined by the potentiometer Rvg (equation (3.2)) .

( RS 4 + RSTRAIN )  Vout
+
Vcc RS 4 − RS 2
( RS 4 + RSTRAIN )
( RS 2 + RS1)  G

(3.10) ε =
 Vcc * RS 2
V 

− out 2 * RSTRAIN
 ( RS 2 + RS1) G 
Caution should be taken to determine the exact value of gain from the AD620 for a given
setting of Rvg and to compensate for any DC offset that may appear on the output.
AD620:
http://www.analog.com/UploadedFiles/Data_Sheets/AD620.pdf
Strain Gages
http://www.omega.com/Pressure/pdf/gen_purpose_strain_SG.pdf