TM
September 2013
•
The T4240QDS system is a T4240 based development
system architecture developed to serve the internal silicon
validation, performance, test and application teams. This
system is offered stand alone for lab and board farm use or
in a 4u chassis for FAE, marketing and customers. This
common platform replaces both the test card and
development systems used in the past, thus promoting
cost savings and environment for multi-team codevelopment.
TM
2
•
•
Block Diagram of T4240
Block Diagram of T4240QDS
T4240QDS Features
Photos
SERDES
DDR
•
Local Bus (IFC)
•
TSEC SPI SDHC USB UART and General IO
I2C
System Clocking
T4240 Requirements and System Power Implementation
Software Support : SDK v1.4
Q&A
•
•
•
•
•
•
•
•
•
TM
3
12 x 64-bit, dual-threaded cores w/ AltiVecTM – up to 1.8GHz
Power Arch™ Power Arch™ Power Arch™
Power Arch™
Power
Arch™ Power
Arch™ Power
Arch™
Power
Arch™
e6500
e6500
e6500
e6500
Power
Arch™ Power
Arch™ Power
Arch™
Power
Arch™
e6500
e6500
e6500
e6500
e6500
e6500
e6500
e6500
2133+ MT/s
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KBI-Cache
32 KBD-Cache
32 KBI-Cache
32 KBD-Cache
32 KBI-Cache
32 KB
32 KBI-Cache
32 KBD-Cache
D-Cache
32 KB I-Cache
32 KB
32 KB I-Cache
32 KB D-Cache
32 KB I-Cache
32 KB
32 KB I-Cache
32 KB D-Cache
D-Cache
D-Cache
D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache
2MB Banked L2
2MB Banked L2
2MB Banked L2
512KB
Plat Cache
64b DDR3
w/ECC
512KB
Plat Cache
64b DDR3
w/ECC
512KB
Plat Cache
64b DDR3
w/ECC
eOpenPIC
PreBoot Loader
CoreNet™
Security Monitor
Internal BootROM
Coherency Fabric
PAMU Peripheral
Access Mgmt Unit
PAMU
PAMU
Data Path Acceleration
Architecture
• FMan
Parse/Class/Distribute/Policing
• QMan Queuing, Scheduling,
Shaping
• BMan Buffer Manager
• Rman RapidIO Manager
• PME Reg-ex Pattern Matcher
• SEC Wireless, SSL and IPSec
Encryption
• DCE Data Compression Engine
• TCP/IP offload
• 40Gbps IPv4 @ 64B
• 20Gbps IPSec @ IMIX
• 10Gbps RegEx @ IMIX
• 20Gbps Compression @ 4KB
Power Mgmt
1G 1G 1G
2 x USB2.0 w/PHY
10G 10G
1G 1G 1G
1G 1G 1G
DCE
Clocks/Reset
32 Lanes up to 10GHz SerDes
GPIO
CCSR
TM
4
SATA 2.0
1G 1G 1G
SATA 2.0
10G 10G
sRIO
RMan
RMAN
PCIe
PreFetch
Buffer
Buffer
DMAx2
sRIO
IFC
BMan
PME
Parse, Classify,
Distribute
Real Time
Debug
PCIe
2x I 2C
Parse, Classify,
Distribute
FMan
PCIe
2x DUART
QMan
Interlaken LA-1
SPI
SEC
PCIe
FMan
Complex
FMan
SD/MMC
Watchpoint
Cross
Trigger
Perf CoreNet
Monitor Trace
Aurora
XAUI / HiGig / (Q)SGMII
XAUI / HiGig / (Q)SGMII
Slot 1: x8
XBAR
SD1
Slot 2: x8
DDR1
DDR3/3LP 240p
DDR3/3LP 240p
DDR2
DDR3/3LP 240p
DDR3/3LP 240p
DDR3
DDR3/3LP 240p
DDR3/3LP 240p
1.5V/1.35V
XAUI / HiGig / (Q)SGMII / XFI
Slot 3: x8
XAUI / HiGig / (Q)SGMII
Slot 4: x8
XBAR
PEX / Interlaken
PEX / SRIO
Slot 5: x16
XBAR
SD2
GVDD
PMBus PWR
DVDD/
etc.
LDO PWR
VDD
VID 4Φ PWR
SD3
Slot 6: x8
SVDD/
XVDD
PEX
Slot 7: x16
XBAR
PEX / SRIO /
SATA
I2C1
SD4
LDO PWR
PMBus,
Slots, Devs,
etc.
I2C Route +
Volt. Trans
Slot 8: x8
JTAG
PromJet
QIXIS
FPGA
ADM NOR
SDxCLKx
NOR
IDT
IDT
841NT
IDT
IDT
841NT
841NT
841NT4
cfg_xyz
CCS
NAND
SATA
RMT
MUX
Aurora
T4240
IDT
840NT4
SYSCLK
DDRCLK
Symmetricom
IEEE 1588
1588_CLKOUT
1588_CLKIN
IDT
840NT4-01
GTX_CLK125x
USBCLK
ISO
IFC
Card
DDRCLK
(option)
IFC
XCVR
UART
NET1
PHYs
TSEC
SPI
NET2
USB
SDHC
eMMC
TM
5
SER2
SPI
SPI
PROT
USB2
PROT
USB1
SER1
SDHC
•
T4240 Silicon - Supported with JD socket, Tyco socket and direct attach.
•
DDR Controllers
•
−
Three independent DDR3 controllers supporting data rates up to 2133 MHz.
−
Two DDR3/DDR3LP 64-bit/ECC UDIMM or RDIMMs per controller.
−
DDR power supplies 1.5V or 1.35V nominal to all devices with automatic tracking of VTT/VREF.
SerDes
−
−
Two 8x “front side” banks with high-speed crosspoint switch fabric routable to two slots or four
iPass x4 connectors.

SGMII / QSGMII.

HiGig / XAUI / XFI.

iPass connectors allow evaluation via Cisco RDS or board-to-board traffic.
Two 8x “back side” banks with high-speed crosspoint switch fabric routable to four slots or
Aurora/SATA connectors.

PCI Express 2.0/3.0.

sRIO 2.0.

Interlaken LA.

SATA 2.0.
TM
6
•
IFC/Local Bus
− High-speed side.
 NAND flash: 8-bit, async or sync, up to 2GB, interposer-based sockting, 16 virtual banks.
 NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB.
 GASIC: Minimal target (within Qixis FPGA).
 IFC Debug/Development card.
− Low-speed side (de-multiplexing handled within FPGA).
 NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB, 16 virtual banks.
 PromJET rapid memory download support.
•
Ethernet
− TSEC1/TSEC2 connect using RGMII to 10/100/1G PHY: VSC8641.
− IEEE-1588 support via Symmetricom board.
•
Other IO
− Two USB 2.0 ports with integrated PHYs: one type-A, one micro-AB.
− eSDHC card slot and on-board eMMC device.
− eSPI bootable memory.
− Serial ports (2), I2C ports (4)
TM
7
•
Clocks
−
System and DDR clock (SYSCLK, “DDRCLK”): IDT co-developed.

−
SERDES clocks.

•
Switch selectable to one of 16 common settings in the interval 33MHz-166MHz, SW selectable
to 1MHz increments.
Provides 100.00, 125.00 or 156.25 MHz clocks to all SerDes blocks and slots.
QIXIS System Logic FPGA
−
Manages system power and reset sequencing.
−
Manages DUT, board, clock, etc. configuration for dynamic shmoo.
−
Collects V-I-T data in background for code/power profiling.
−
General fault monitoring and logging.
−
Runs from ATX “hot” power rails allowing operation while system is off.
−
Remote control/configuration via I2C (Komodo).
TM
8
•
Power Supplies
−
Sourced by either Sparkle 750 ATX or 700 1U bulk supplies.
−
Dedicated regulator for VDD (Cores + Platfrom).
−

Adjustable from (0.7V to 1.2V) at ~120A.

Regulators can be controlled by VID via software.
Dedicated regulator for GVDD (DDR) : 1.35/1.5V at 40A.

•
Linear regulators provide VTT/MVREF automatically track operating voltage.
−
Dedicated regulators/filters for SERDES AVDD supplies.
−
POVDD (now called PROG_SFP) (fuse security or repair) support.
−
Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, etc.
Re-use and scalability
−
−
Interface strategy allows for scalable re-use and high coverage for IP validation.
Design was highly reused on B4860 for a co-validation and support environment.
TM
9
TM
10
TM
11
•
SERDES for T4240QDS was co-designed with B4860. Both
share common strategy.
•
Challenge of the SERDES design:
−
−
Pin out optimization reduced number of layer to two for all four SERDES blocks.
40 db per lane noise requirement.
−
PLL and SVDD/XVDD power required 50KHZ – 500MHZ 10mv p-p maximum noise.
Needed to use independent filters and dedicated power supplies to reduce
fundamental and cross conducted noise.
−
Stack up and material FR408 was highly optimized for best simulation results for the
SERDES and DDR.
TM
12
Gbps
T4240 – 32 lanes
2.5 / 5
Up to 4 x1 x2 x4 or Dual x8
8
Dual x4
SRIO Gen 1&2
1.25** / 2.5 / 3.125 / 5
Dual x1 x2 x4
Interlaken – LA
10.3125 / 6.25
up to Eight x1
SATA Gen 1&2
1.5 / 3
Dual x1
Aurora
2.5 / 3.125 / 5
x1 x2 x4
SGMII
`
up to 16 x1
3.125
up to 12 x1
5
up to 4 x1
4-lanes @ 3.125
up to 4 x4
4-lanes @ 3.125 / 3.75
up to 4 x4
10.3125
up to 4 x1
PCI Express Gen 1&2
PCI Express Gen 3
2.5X SGMII
QSGMII
XAUI
HiGig / HiGig+ / HiGig2
XFI
13
TM
** Test Mode only
SD 1
SD 3
SD 2
A-H
A-H
A-H
“Front Side”
Ethernet
•
SD 4
A-H
“Back Side”
Others
T4240 has 32 lanes SERDES
−4
SERDES Modules with 8 lanes in each Module (Lynx 26)
− “Front
Side” SD 1 & 2 are Ethernet protocols
− “Back
Side” SD 3 & 4 are other protocols
(PEX/SRIO/SATA/Interlaken/Aurora)
TM
14
A
B
0
1
XAUIa
HiGiga
HiGiga
XAUIa
XAUIa
XAUIa
XAUIa
XAUIa
HiGiga
HiGiga
HiGiga
HiGiga
• Each SERDES Module (1
HiGiga
& 2) consists of 8 lanes HiGiga
SGMIIe
shown
• New for T4 SERDES IP:SGMIIe
SGMIIe
• HiGig, HiGig+,
SGMIIe
HiGig2, XFI, QSGMIISGMIIe
X
• Lane Reversal
SGMIIe
supported in XAUI SGMIIe
and HiGig/+ (softwareSGMIIe
SGMIIe
controlled)
2xSGMIIe
• Polarity inversion for
XAUIa
any Ethernet protocolHiGiga
(software controlled) XFIc
XFIc
XFIc
XFIc
X
X
X
T4240 “FRONT SIDE”
SERDES Modules 1 / 2
TM
XAUIa
HiGiga
HiGiga
XAUIa
XAUIa
XAUIa
XAUIa
XAUIa
HiGiga
HiGiga
HiGiga
HiGiga
HiGiga
HiGiga
SGMIIf
SGMIIf
SGMIIf
SGMIIf
SGMIIf
X
SGMIIf
SGMIIf
SGMIIf
SGMIIf
2xSGMIIf
XAUIa
HiGiga
XFId
XFId
XFId
XFId
XFId
XFId
XFId
C
D
E
F
G
H
Module ;
Protocol
XAUIa
XAUIa
XAUIb
XAUIb
XAUIb
XAUIb
1;1
HiGiga
HiGiga
HiGigb
HiGigb
HiGigb
HiGigb 1;1a :2;1a
HiGiga
HiGiga
XAUIb
XAUIb
XAUIb
XAUIb 1;1b : 2;1b
XAUIa
XAUIa
SGMIIa SGMIIb SGMIIc SGMIId
XAUIa
XAUIa
SGMIIa 2xSGMIIb SGMIIc SGMIId
1;2
XAUIa
XAUIa 2xSGMIIa SGMIIb SGMIIc SGMIId
XAUIa
XAUIa 2xSGMIIa 2xSGMIIb SGMIIc SGMIId
XAUIa
XAUIa 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId
HiGiga
HiGiga SGMIIa SGMIIb SGMIIc SGMIId
HiGiga
HiGiga SGMIIa 2xSGMIIb SGMIIc SGMIId
1;2a
HiGiga
HiGiga 2xSGMIIa SGMIIb SGMIIc SGMIId
HiGiga
HiGiga 2xSGMIIa 2xSGMIIb SGMIIc SGMIId
HiGiga
HiGiga 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId
1;2b
HiGiga
HiGiga SGMIIa SGMIIb SGMIIc SGMIId
SGMIIh SGMIIg SGMIIa SGMIIb SGMIIc SGMIId
1;3
SGMIIh SGMIIg SGMIIa 2xSGMIIb SGMIIc SGMIId
1;4
SGMIIh SGMIIg 2xSGMIIa SGMIIb SGMIIc SGMIId
1;5
SGMIIh SGMIIg 2xSGMIIa 2xSGMIIb SGMIIc SGMIId
2;9
SGMIIh SGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId
1;6 : 2;10
QSGMIIb
X
X
X
QSGMIIa
X
SGMIIh SGMIIg
X
X
QSGMIIa
X
SGMIIh 2xSGMIIg
X
X
QSGMIIa
X
1;7
2;11
2xSGMIIh SGMIIg
X
X
QSGMIIa
X
1;8
2xSGMIIh 2xSGMIIg
X
X
QSGMIIa
X
2xSGMIIh 2xSGMIIg
X
X
QSGMIIa
X
1;9 : 2;13
XAUIa
XAUIa
X
X
QSGMIIa
X
1;9 : 2;13
HiGiga
HiGiga
X
X
QSGMIIa
X
XFIb
XFIa
SGMIIa SGMIIb SGMIIc SGMIId
2;3
2;4
XFIb
XFIa 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId
XFIb
SGMIIg SGMIIa SGMIIb SGMIIc SGMIId
2;5
XFIb 2xSGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId 2;6 : 2;7
SGMIIh SGMIIg SGMIIa SGMIIb SGMIIc SGMIId
2;8
2xSGMIIh 2xSGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId
2;12
XFIb
X
X
X
QSGMIIa
X
2
3
4
5
15
6
7
Freq mapping
XAUI 3.125
HiGig 3.125 / HiGig+ 3.75
HiGig 3.125 / HiGig+ 3.75; XAUI 3.125
XAUI 3.125; SGMII 1.25
XAUI 3.125; SGMIIa,c-d 1.25; SGMIIb 3.125
XAUI 3.125; SGMIIa 3.125; SGMIIb-d 1.25
XAUI 3.125; SGMIIa-b 3.125; SGMIIc-d 1.25
XAUI 3.125; SGMII 3.125
HiGig 3.125; SGMII 1.25
HiGig 3.125; SGMIIa,c-d 1.25; SGMIIb 3.125
HiGig 3.125; SGMIIa 3.125; SGMIIb-d 1.25
HiGig 3.125; SGMIIa-b 3.125; SGMIIc-d 1.25
HiGig 3.125; SGMII 3.125
HiGig+ 3.75; SGMII 1.25
SGMIIa-h 1.25
SGMIIa,c-h 1.25; SGMIIb 3.125
SGMIIa 3.125; SGMIIb-h 1.25
SGMIIa-b 3.125; SGMIIc-h 1.25
SGMIIa-d 3.125; SGMIIe-h 1.25
QSGMII 5
SGMIIe-h 1.25; QSGMII 5
SGMIIe-f,h 1.25; SGMIIg 3.125; QSGMII 5
SGMIIe-g 1.25; SGMIIh 3.125; QSGMII 5
SGMIIe-f 1.25; SGMIIg-h 3.125; QSGMII 5
SGMIIe-h 3.125; QSGMII 5
XAUI 3.125; QSGMII 5
HiGig 3.125 / HiGig+ 3.75; QSGMII 5
XFI 10.3125; SGMII 1.25
XFI 10.3125; SGMII 3.125
XFI 10.3125; SGMII 1.25
XFI 10.3125; SGMII 3.125
XFI 10.3125; SGMII 1.25
XFI 10.3125; SGMII 3.125
XFI 10.3125; QSGMII 5
T4240 “BACK SIDE” -- SERDES Modules 3 / 4
A
0
B
1
C
2
D
3
E
4
F
5
G
6
H
7
PEXa
PEXa
PEXa
PEXa
PEXa
PEXa
PEXa
PEXa
SOC PRTCL
T4240;3/4;1
PEX 5/2.5
T4240;3/4;2
PEXa 5/2.5; PEXb 8/5/2.5
PEXa
PEXa
PEXa
PEXa
PEXb
PEXb
PEXb
PEXb
PEXa
PEXa
PEXa
PEXa
SRIOa
SRIOa
SRIOa
SRIOa
PEXa
PEXa
PEXa
PEXa
SRIOa
SRIOa
SRIOa
SRIOa
LA
LA
LA
PEXa
LA
LA
LA
PEXa
LA
LA
LA
LA
LA
LA
PEXa
PEXa
LA
PEXb
SRIOa
PEXb
LA
PEXb
SRIOa
PEXb
LA
PEXb
SRIOa
SATAa
LA 10.3125 / 6.25
PEXb
LA 10.3125 / 6.25; PEX 8/5/2.5
SRIOa
T4240;3;6
LA 10.3125 / 6.25; SRIO 5 / 3.125 / 2.5
SATAb
T4240;4;4
PEX 5/2.5; SATA 3/1.5
T4240;4;5
PEX 5/2.5; Aurora 5/2.5; SATA 3/1.5
PEXa
Aurora
Aurora
SATAa
SATAb
PEXa
PEXa
PEXa
PEXa
Aurora
Aurora
SRIOa
SRIOa
PEXa
PEXa
PEXa
PEXa
Aurora
Aurora
SRIOa
SRIOa
PEXa
Aurora
Aurora
Aurora
• Each SERDES Module (3 & 4) consists of 8 lanes shown above
• New for T4 SERDES IP:
Aurora
T4240;4;6
PEX 5/2.5; Aurora 5/2.5; SRIO 5/2.5/1.25
PEX 8/5/2.5; Aurora 3.125; SRIO 3.125
T4240;4;7
PEX 5/2.5; Aurora 5/2.5
• Improved Lane Reversal Support:
• Auto-negotiated Lane Reversal for PEX native x4 or x8
• Software programmable Lane Reversal for PEX
(x2/x4/x8), SRIO (x2/x4)
• Lane mapping control in software for Interlaken LA (x4/x8)
• No lane swapping support for Aurora !
• PEX Gen3 (8Gb), Interlaken (LA)
• Downgrading is feasible both for PEX and for SRIO (e.g. if 4x is
supported, then downgrading for 2x and 1x is possible).
• Polarity inversion for any protocol (software controlled, except PEX
is auto-negotiated)
TM
PEX 8/5/2.5; SRIO 3.125
T4240;3;5
PEXa
PEXa
PEX 5/2.5; SRIO 5/2.5/1.25
LA
PEXa
PEXa
T4240;3/4;3
T4240;3;4
PEXa
PEXa
Freq mapping
16
•
Vitesse 3316 Crossbar Switch:
−
Up to 11.5 Gbps.
−
Arbitrary lane assignment provides flexible muxing solution.
−
Supports 10Gb XFI (10GBASE_KR), PEX Gen3, and Out-of-Band signal
forwarding for SATA.
−
Signal conditioner ( programmable input equalization up to 26dB and output
pre-emphasis up to 9dB.
−
LOS (Loss of Signal) Detector on every port.
−
I2C and SPI programming interfaces.
−
Static Hardware pin strapping of select modes.
•
~ $50.
•
196 pins 15x15mm BGA package.
TM
17
TM
18
TM
19
•
Three controllers pushed DDR on two sides of the pin out.
−
−
−
•
Power delivery of memory and termination is spread out.
Escape of vertical routes other than DDR are challenged.
One side of pin out with dual controllers drives overall system layer count.
Top speed of 2133 is very challenging for DDR3 technology.
−
Voltage swing at 1.5V very wide.
−
Timing budget pushes more burden on the T4240 controller, while less margin for
system.
TM
20
•
•
Provides a high speed and a low speed segments.
−
High speed is lighter loaded and designed to run full speed synchronous or non
synchronous devices.
−
Low speed is fully separated and buffered by FPGA, like many customers will
implement. Asynchronous devices and Promjet ROM emulation on this segment.
Add-in card on high speed side.
−
Supports various wide path and or fast synchronous devices such as synchronous
NAND.
−
Supports Test port validation card.
TM
21
IFC connectivity
1.8V Muxed Bus
Banks= 16
T4240
IFC
ADDR
DATA
ADM Mux
NOR FLASH
64MB/128MB
25 ADDR/16 DATA
AD[0:24]
AD[27:31]
AD[0:31],A[26:31]
A[26:31]
CBT
CTRL
NAND FLASH
1/2-1GB
0n socket
FBGA-63
AD[0:7]
AD[0:31],A[26:31]
DeMux
ADDR
GAsic
Target (n regs)
data
ctrl
RCW
BCSR regs
IFC CARD/ Test port Connector
FPGA
 Minimal GAsic support (IO to ~2 registers)
 Dynamic boot reassignment of chip selects (All CS route to FPGA)
NOR/PromJet demux inside.
POR CFG bits
TM
22
Banks = 1
Banks = 16
FPGA
NOR FLASH
64MB/128MB
ADDR
data
AMC
Total Bus
Loads: 4
AD[0:31],A[26:31]
CTRL
AVD
CLE
WE0
WE1
WE2
WE3
CS0
CS1
CS2
CS3
...
OE
ctrl
PromJet
•
•
Fundamentally the same as P5020/P5040 functionally
−
TSECs(RGMII) are on LVDD voltage rail, which is 2.5V or 1.8V(when acting as
GPIOs only).
−
I2C and UART are on DVDD voltage rail, which is 2.5 or 1.8V.
−
OVDD voltage rail at only 1.8V encompasses a much larger set of interfaces besides
miscellaneous types:
•
IFC
•
SPI
•
SDHC
•
Miscellaneous types like SYSCLK, DDRCLK, DMA, IRQ, JTAG , etc….
1.8V is becoming predominate general IO voltage
−
Adds challenge to open drain bi-directional busses like I2C, when means special
provisions for more complicated sub-systems.
−
Many OVDD based signals needed translation to work with rest of system.
TM
23
OVDD
1.8V domain
LVDD
2.5V domain
DUT
IRQ[0:11]
TRANS
IRQ_OUT_B
TMP_DETECT_B
PHY_INT_B (2.5V)
SYMMETRICOM_INT_B (
TRANS
LP_TMP_DETECT_B
3.3V
3.3V domain
LP_VDD
QIXIS
TM
24
QIXIS
DVDD-to-3V
POST/
IRS
OCM
HOT3.3V
LEVEL SHFT
RS232 Transceivers
DUT
DVDD
UART 2
UART 1
TM
25
Port #2
Top port
Port #1
Bottom port
Secondary
QDS
COP
QIXIS
cfg_jtag_cascade
COP_xyz
sw_jtag_route[0:2]
eCWTAP/
Amphisbaena
TM
DUT
JTAG_Route
Mux
eCWTAP
uTAP/
COP/
etc.
COP
Aurora
Pod
AURORA
CASCADE_xyz
26
TAP
TDI
TCK
TMS
TDO
TRST_B
•
Very extensive on this implementation
−
Clocks, crossbars, power supply, add-in cards, power measuring features and more
controlled through I2C.
−
Processor and remote host capability
−
•
Dual system validation control link
Primary I2C bus is 3.3V, but voltage translated and buffered to
T4240 as either 2.5V or 1.8V. A big challenge.
TM
27
I2C Monitoring
for Background
Data C ollection
(I-V-T )
LVL
Komodo
Controller
(3.3V I2C)
HDR
QIXIS
RST_I 2C_B
LVL
I2C1_CH7
PCA9547
...
I2C1_CH1
I2C1_CH0
HDR
LVL
I2C1
I2C1_CH6
HDR
HDR
LVL
I2C3
HDR
I2C2
LVL
DUT
I2C4
DVDD:
1.8 or 2.5V
TM
Headers to Remote Systems
Note that I2C4 is NOT translated.
3.3V
28
PCA9547
I 2C1_CH7_CH7
I 2C1_CH7_CH6
...
I 2C1_CH7_CH1
I 2C1_CH7_CH0
T4240
IFC CLK1
IFC CLK0
IFC NDDDR CLK
IDT840NT
33 – 200 MHz
Δf = 0.5M
0x60
I2C
25MHz Ref CLK
I2C1 CH1
Config
Switches
N2
QIXIS (FPGA)
CFG CLKS OE
VCC_3.3_HOT
33.333
MHz
OSC
N1
PLL
(SSC)
8/16
Test Port
1.8 V
SYSCLK
3.3 V
DDRCLK
1.8 V
1.8 V
RTC
SYSCLK_PIXIS
1.8V
Optional
25.78125
MHz
XTAL
0x6C
25 MHz
XTAL
LVPECL
25MHz
Fanout Buffer
N1
100
125
156.25
N2 161.13
MHz
Synthesizer Mode
PLL
I2C
LVDS
SD1_REFCLK 1
LVDS
SD1_REFCLK 2
Optional
25.78125
MHz
XTAL
0x6D
N1
100
125
156.25
N2 161.13
MHz
I2C
Optional
25.78125
MHz XTAL
ICS871S1022
0x6E
HCSL
HCSL
N1
100
125
156.25
N2 161.13
MHz
PLL
I2C
SD1 REFCLK2
Front Side SERDES
(ENET)
LVDS
SD2_REFCLK 1
LVDS
SD2_REFCLK 2
SD2 REFCLK1
SD2 REFCLK2
IDT6V31021
LVDS
LVDS
SD3_REFCLK1_PB
N1
100
125
156.25
N2 161.13
MHz
PLL
0x6F
I2C
SD3 REFCLK1
Slot 5 (x16)
SMA
SD3_REFCLK2_PB
SD3_REFCLK 2
HCSL
Slot 6 (x8)
IDT8T49N222i-yyy
100 MHz
Spread Spectrum Source
SD3_REFCLK 1
HCSL
High Bandwidth Mode
HCSL
100 MHZ
SD1 REFCLK1
IDT8T49N222i-xxx
PLL
CLK OUT
Synthesizer Mode
CFG
CLK_IN_SEL
100 MHz
RT CLK
SMA
ICS8535I-31
/
6
PLL
(SSC)
DDR CLK
RTCCLK_DUT (3.125 MHz typ)
CLK125M_DDR (125MHz)
IDT8T49N222i-yyy
25 MHz
XTAL
SYS CLK
DDRCLK_DUT (133.3 MHz typ)
IDT8T49N222i-xxx
CFG SPREAD
EXT
CLK IN
SMA
SYSCLK_DUT (66.67 MHz typ)
SD4_REFCLK 1
LVDS
SD4_REFCLK1_PB
LVDS
SD4_REFCLK2_PB
HCSL
Slot 7 (x16)
SMA
HCSL
High Bandwidth Mode
SD3 REFCLK2
Back Side SERDES
(PCIe, etc)
SD4 REFCLK1
Aurora
SD4_REFCLK 2
SD4 REFCLK2
Slot 8 (x8)
LEGEND
IDT840NT-01
= SMA injection/monitoring point
PLL
= injection/monitoring point
HCSL differential clock
LVDS differential clock
1.8V CLK125M_DDR
V-div
125 MHz
2.5V
N2
25/125 MHz
3.3V 125MHz
Nfrac
24MHz
1.8V
N1
LVCMOS single-ended clock
(SSC) = Spread Spectrum Clocking Option
TM
125 MHz
125 MHz (modulated)
CLK USB
12.5 MHz typ
I2C
2
LVPECL differential clock
EC[1:2]_GTX_CLK125
/
3
RGMII
PHYs
29
EC[1:2] GTX CLK125
1588 CLK IN
1588 CLK OUT
1588 Module
24 MHz
USB CLK
•
Slew rate requirement for All rails except for PROG_SFP is
24V/ms max. PROG_SFP is 18V/ms max.
•
VDD (Cores + Platfrom) has a DC and AC component at 1.0V.
•
−
+- 30mv DC.
−
+- 50mv AC (general transient deviation).
−
+ 100mv AC transient for up to 1us.
−
+- Load step static to full on estimated at 30A. (should be the goal for VDD
regulator).
−
Customer should plan for a di/dt on the load step of 12A/us. Speculative until
characterization.
SVDD/XVDD require independent filtering of noise to a max of
10mvp-p from 50KHZ – 500MHZ.
TM
30
•
•
A specific method of selecting the optimum voltage-level to
guarantee performance and power targets.
−
QorIQ device contains fuse block registers defining required voltage level. This
EFUSE definition is accessed through the Fuse Status Register (DCFG_FUSESR).
−
Customer system must use the VID to change the voltage regulators in the system in
a reliable and safe methodology.
QorIQ Chassis Architecture Specification, Generation 2 Revision 0.9
defines the general EFUSE definition.
−
A set of 24 efuses ([0-23]) that determine the speed bin and voltage requirements for
the device domains.
−
The range and steps are much more flexible than actually needed by manufacturing;
only the fuses necessary to provide the required voltages will be implemented.
TM
31
FUSESR - Current Chassis Definition
Bits
Field
0-1
-
2-3
BIN
4-8
PLAT_V
Definition
Reserved
2’b00 - Speed bin 1 (low)
2’b01 - Speed bin 2 (medium)
2’b10 - Speed bin 3 (high)
2’b11 - Speed bin 4 (premium)
5’b00000 – 0.8000V
5’b00001 – 0.8125V
5’b00010 – 0.8250V
5’b00011 – 0.8375V
5’b00100 – 0.8500V
5’b00101 – 0.8625V
5’b00110 – 0.8750V
5’b00111 – 0.8875V
5’b01000 – 0.9000V
5’b01001 – 0.9125V
5’b01010 – 0.9250V
5’b01011 – 0.9375V
5’b01100 – 0.9500V
5’b01101 – 0.9625V
5’b01110 – 0.9750V
5’b01111 – 0.9875V
5’b10000 – 1.0000V
5’b10001 – 1.0125V
5’b10010 – 1.0250V
5’b10011 – 1.0375V
5’b10100 – 1.0500V
5’b10101 – 1.0625V
5’b10110 – 1.0750V
5’b10111– 1.0875V
5’b11000 – 1.1000V
5’b11001 – reserved
…
5’b11111 – reserved
9-13
DA_V
Same as PLAT_V
14-18
DB_V
Same as PLAT_V
19-23
DC_V
Same as PLAT_V
24-31
-
Reserved
TM
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
11000
11001
11010
11011
11100
11101
11110
32
11111
1.2000
1.1875
1.1750
1.1625
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
Reserved
=1.1+n*12.5mV
=1V+n*12.5mV
(MSB=1)
Default
=1V-n*12.5mV
(MSB=0)
Reserved
=0.8V-n*12.5mV
(consider change of
resolution to 6.25mV, and
use the >1.0V options)
Use ALT field
•
At power up time zero, regulator must come up at default voltage as
defined per product. For T4240, that is 1.0V.
•
VERY EARLY in the boot code and before many high speed or other
power hungry features or interfaces are turned on, the
DCFG_FUSESR register is read for the VID information. This value is
translated into whatever commands to program up the new voltage
value for the regulator.
•
Once the regulator is sent the new values, a period of time needs to
pass to allow the regulator to change values BEFORE power hungry
features and higher clock rates are enabled/changed.
TM
33
GPIOs.
• Typically a parallel port, simple VRM type regulator. Older AMD and VR11 Intel
type regulators are typical, but many other companies.
• Default voltage (in this case 1.0V for T4240), must be configured when GPIOs
are at tier one power sequence using pull-up and pull-down resistors.
• Out of reset and into the boot code, new VID is translated and thus GPIOs are
programmed and driving regulator to new value.
• May have to use a voltage translator or a open-drain approach to adapt 1.8V
GPIOs of T4240.
• Software is responsible for guarding any erroneous voltage values etc…
I2C bus or Power Management Bus (PMBus)
•
•
•
More sophisticated and perhaps digital control loop device with telemetry.
Program EEprom or use resistor strapping for default voltage.
Out of reset, serial commands to regulator to set new voltage level determined
by VID.
IFC (Local Bus). Same as GPIOs or even I2C, but with the help of a FPGA
or ASIC as the host interface via IFC.
TM
34
Regulator voltage change delay and over current protection (OCP).
•
Voltage delay is the time from the regulator receiving a new VID value and changing to the
new voltage. Going too fast can cause a fault = shutdown.
•
Many regulators, especially later model PMBus, SVID and VR12 types automatically
change voltage gradually and in many case the time can be programmable.
•
Older VR11 parallel type Intel regulators have to be stepped by software to avoid an OCP
event.
Voltage resolution
•
Programmable regulators have a resolution from 50mv to 3.25mv steps.
•
It costs more to support large VID ranges at 3% percent regulation. Our teams should be
careful to not have too broad of range for the customer to have to validate of temperature,
load and voltage. The lower the voltage, the more difficult it is to obtain 3% tolerance.
Default Voltage may not be programmable.
•
VR11 regulators have a default of 1.1V, which is ok for T4240, but perhaps not for other
products.
TM
35
TM
36
•
•
Provide ample power for schmooing up to 1.2V and a 3 percent
goal.
−
120A VR11 Intel analog VERY FAST response time 4 phase regulator. 6.25mv
resolution.
−
Since di/dt of T4240 is not known or characterized, PDN included several low ESR
POSCAPS at 5mohm and 47uf 0805 ceramic XR5 capacitors.
−
Current sensing was added on each phase and on a IMON total current
representation.
Placement and layout was very challenging.
−
Since pin out implemented very high speed signals on all four corners, had to place
VDD regulator 3.5 inches away, which limits response due to inductance.
−
Use of three power layers to approach inner C5s of T4240. Two 2oz and one 1oz
power plane splits with matching grounds.
−
Since heat sinks take up space and cost, optimum output stage FETS and adequate
placement spreading was used to handle thermal loss across system pcb.
TM
37
•
Provide very low noise power and PLL filtering. 10mv p-p
50KHZ-500MHZ requirement.
−
Use of Low Drop Out regulators exclusive to SVDD and XVDD.
−
Filters were chosen to reduce droop and reduce cross IP block noise.
−
Coordinated heavily with SERDES team for implementation.
−
Added hooks to allow SERDES team to experiment with filtered version of VDD for
SVDD and GVDD for XVDD.
TM
38
T4240 requires programmable regulator at 12.5mv min
steps.
There are four sets of sense pins ganged and
balanced with 10ohm resistors.
VCC_12_BULK
PWM Control
T4240
Current includes 10% adder for schmooing and worst case silicon.
I2C
Power
Monitor
IMON is a current from
regulator that
represents a sum of all
four phase current.
ISL6334IRZ
PHASE1_CPLVDD
ISL6620CR
I2C
Power
Monitor
8 BIT VID control
VR11 style.
PHASE2_CPLVDD
ISL6620CR
Total Power capability
is 120A 0.9V-1.1V.
3% percent. Based on
25A step with
estimated slew of
15A/us.
I2C
Power
Monitor
PHASE3_CPLVDD
ISL6620CR
I2C
Power
Monitor
PHASE4_CPLVDD
ISL6620CR
VCC_xxx = Source of Power
I2C
Power
Monitor
VDD_xxx/AVDD_xxx = Power Rail for Device
TM
39
VDD_CORE_PL
VDD 0.90 – 1.2V
100A
Cores & Platfrom
Cores & Platfrom
VCC_5 (ATX PS)
VCC_1.8
To Devices
VDD_OVDD
To Devices
Integrated Module
VCC_DVDD
1.8/2.5V 5%
VCC_1.8
To Devices
Integrated Module
1.8V 5%
To
Integrated Module
(ATX PS)
VCC_12_BULK
VDD_DVDD
2.5V 5%
40A Switcher
VCC_1.8
VDD_BVDD
VCCA_2.5To power LVDD plane and phys
etc.. There is another version called
Devices
VCC2_2.5 for other stuff.
VDD_LVDD
To DIMMs /MVREF/M_VTT
VCC_GVDD
VCC_GVDD_S
1.3 – 2.1 V 5%
VDD_GVDD
.
I2C
Power
Monitor
PM
Bus
0.6
General I/O / SPI / SDHC
A
T4240
DVDD 1.8 / 2.5V
UART/ I2C
GPIO mode tested on TESTER/HSSI thus no 1.8V needed.
ZL6105
OVDD 1.8V
0.15 A
BVDD 1.8V
0.5 A
Integrated Flash Controller
LVDD 1.8V GPIO / 2.5V
ENET
0.35 A
G1VDD – G3VDD 1.35/1.5
DDR I/O
3.4 A V
(ATX PS)VCC_3.3
VDD_USB12_VDD_3P3
f2
* Ferrite Bead is specifially Murata BLM18PG121SH1.
3.3V
USB1/2_VDD_3P3
Ferrite Bead
USB IO
VDD_CORE_PL
C = 2.2 uF
C = 2.2 uF
C = 0.003 uF
VCC_1.8
f2
VDD_USB12_VDD_1P0
f2
USB1/2_ VDD_1P0
USB Core
VCC_xxx = Source of Power
VDD_USB12_VDD_1P8
f2
USB1/2_VDD_1P8
USB IO
VDD_xxx/AVDD_xxx = Power Rail for Device
TM
40 MA
40
1.0V
40 MA
1.8V
40MA
VDD_GVDD
T4240
LDOs primary due to uncertain noise requirements and separation.
Red resistors are optional stuff in lieu of primary .
VCC_1.8
f4
VDD_X1VDD
X1VDD
1.35/1.5V 0.6A
Linear Reg
1.35/1.5 V
VCC_X12_VDD
VCC_X12_VDD_S
f4
VDD_X2VDD
X2VDD
1.35/1.5V 0.6A
Linear Reg
1.35/1.5 V
LT3070
VCC_X34_VDD
VCC_X34_VDD_S
f4
VDD_X3VDD
X3VDD
1.35/1.5V 0.6A
f4
VDD_X4VDD
X4VDD
1.35/1.5V 0.6A
Ferrite Bead
* All SERDES filter and power noise requirement =
10mv p-p from 50khz to 500MHZ..
Ferrite Bead
C = 2.2 uF
C = 2.2 uF
C = 0.003 uF
f4
* Ferrite Bead is specifially Murata BLM18PG121SH1.
VCC_xxx = Source of Power
VDD_xxx = Power Rail for Device VDD_CORE_PL
VCC_1.8
Linear Reg
1.0V
Linear Reg
1.0V
VCC_S12_VDD
VCC_S34_VDD
VCC_S12_VDD_S
f4
VCC_S34_VDD_S
f4
LT3070
TM
41
VDD_S1VDD
VDD_S2VDD
S1VDD
1.0V 0.34A
S2VDD
1.0V 0.34A
f4
VDD_S3VDD
S3VDD
1.0V 0.34A
f4
VDD_S4VDD
S4VDD
1.0V 0.34A
T4240
VCC_X1234_VDD_S
f3
f3
f3
* All SERDES filter and power noise requirement =
10mv p-p from 50khz to 500MHZ..
f3
AVDD_SRDS1_PLL1
Group1_ PLL1
AVDD_SRDS1_PLL2
f3
C = 4.7 uF
f3
AVDD_SRDS3_PLL1 1.35-1.5V
AVDD_SRDS3_PLL2
f3
40mA
AVDD_SRDS3_PLL2 1.35-1.5V
Group3_ PLL2
f3
40mA
AVDD_SRDS3_PLL1
Group3_ PLL1
Grounds
need
isolation
40mA
AVDD_SRDS2_PLL2 1.35-1.5V
Group2_ PLL2
C = 47 uF
40mA
AVDD_SRDS2_PLL1 1.35-1.5V
Group2_ PLL1
AVDD_SRDS2_PLL2
40mA
AVDD_SRDS1_PLL2 1.35-1.5V
Group1_ PLL2
AVDD_SRDS2_PLL1
R = 0.33 ohm
C=
0.003uF
AVDD_SRDS1_PLL1 1.35-1.5V
40mA
AVDD_SRDS4_PLL1
AVDD_SRDS4_PLL1 1.35-1.5V
AVDD_SRDS4_PLL2
AVDD_SRDS4_PLL2 1.35-1.5V
Group4_ PLL1
40mA
f3
Group4_ PLL2
VCC_xxx = Source of Power
VDD_xxx = Power Rail for Device
TM
42
40mA
T4240
VCC_1.8
f1
f1
f1
R = 5 ohm
AVDD_CGA3
AVDD_CGA2 1.8V
3mA
AVDD_CGA3 1.8V
GroupA_PLL3
3mA
AVDD_CGB1 1.8V
GroupB_PLL1
C = 1 uF
AVDD_CGB2
f1
f1
3mA
GroupA_PLL2
f1
f1
AVDD_CGA1 1.8V
GroupA_ PLL1
AVDD_CC2
AVDD_CGB1
C = 10 uF
f1
AVDD_CC1
3mA
AVDD_CGB2 1.8V
GroupB_PLL2
AVDD_DDR
AVDD_DDR
3mA
1.8V
DDR_PLL
AVDD_PL
VDD_CORE_PL
AVDD_PL
3mA
1.8V
Platform_PLL
3mA
FA_VDD
FA_VDD
VCC_xxx = Source of Power
VDD_LP
VDD_xxx = Power Rail for Device
Process Detect
VDD_LP
VCC_1.8
1.0V
0.05A
1.0V
Low Power Security Monitor
VDD_IRS_VDD
IRS_VDD 1.8V
IR Sense analog
VCC_POVDD
Linear Reg
GND / 1.89 V
VDD_POVDD
Strict timing and rise time requirements..
TM
43
POVDD
Fuse Prgm
0.05A
GND (read)
150mA
1.89V (write)
VCC_5
(ATX PS)
VCC_EPHY_1.2
Integrated Module
1.2V 5%
VCCB_2.5
Integrated Module
2.5V 5%
VCC_HOT_5
(ATX PS)
VCC_HOT_3.3
Integrated Module
3.3V 5%
VCC_HOT_1.5
Integrated Module
1.5V 5%
VCC_xxx = Source of Power
VDD_xxx = Power Rail for Device
TM
44
•
T4240/4160 rev 1
•
BSC9131 rev 1 and BSC9131RDB
•
BSC9132 rev 1 and BSC9132QDS
•
G4860 rev 1
•
TWR-P1025
•
P1020RDB-PD
•
P1023RDB-PA
•
P1010RDB 1 GHz
•
MPC85xx processor and board support removed
•
P1020UTM, P1020MBG, P1020RDB-PC, P1024RDB,
P1025RDB, P1023RDS support removed
TM
45
•
•
•
U-Boot Boot Loader

U-Boot 2013.01

Secure Boot for T4240 and B4860

Cryptographic blob generation commands in ESBC
Linux Kernel and Virtualization

Linux kernel 3.8.13

Linux Preempt Real-Time (RT) - v3.8.13-rt9

Preempt RT support for B4860QDS and TWR-P1025

Linux Container (LXC) 0.9.0

Libvirt 1.0.3

Kernel-based Virtual Machine (KVM) features:

KVM: e6500 - T4240 and B4860

KVM: QEMU 1.4

KVM: USB pass through
Yocto and Toolchain

Yocto/Poky 1.4 "Dylan"

gcc-4.7.2, eglibc-2.15, binutils-2.23.1, gdb-7.5.1

Mixed mode builds - ability to build both 32-bit and 64-bit applications with same toolchain
TM
46
•
DPAA Offloading driver added [P4080, B4860/4420]
• Ethernet DPAA: ethtool update relating to 3.8 kernel upgrade
• Ethernet DPAA: PAUSE frame run-time control using ethtool
• Ethernet DPAA: netpoll support
• Ethernet DPAA: Linux standard API for hardware timestamping (IEEE1588)
• Ethernet DPAA: Removed the Qdisc support bypass from the standard SDK configuration
• FMan: Virtual Storage Profile using chosen node
• FMan: Pre-silicon support for T4240 and B4860 rev 2
• FMan: Microcode version update
• IEEE1588 driver: P5040 and 64-bit
• PCIe: hot remove/rescan
• PCIe: End Point (EP) support [P4080, T4240]
• QMAN: Pre-silicon support for T4240 and B4860 rev 2
• SEC: QMan Interface for DPAA processors
• Thermal Monitor support [using on-board sensors for T4240QDS, B4860QDS, P1022DS]
• XFI support on B4860QDS
TM
47
TM