a
Wideband Voltage
Feedback Amplifier
AD9621*
FEATURES
350 MHz Small Signal Bandwidth
130 MHz Large Signal BW (4 V p-p)
High Slew Rate: 1200 V/ms
Fast Settling: 11 ns to 0.01%/7 ns to 0.1%
63 V Supply Operation
APPLICATIONS
ADC Input Driver
Differential Amplifiers
IF/RF Amplifiers
Pulse Amplifiers
Professional Video
DAC Current-to-Voltage
Baseband and Video Communications
Pin Diode Receivers
Active Filters/lntegrators/Log Amps
CONNECTION DIAGRAM
1
8
NC #
–INPUT
2
7
+V S
+INPUT
3
6
OUTPUT
4
5
NC
–VS
OBS
GENERAL DESCRIPTION
NC #
AD9621
# OPTIONAL CAPACITOR CB CONNECTED HERE
DECREASES SETTLING TIME
OLE
The AD9621 is one of a family of very high speed and wide
bandwidth amplifiers utilizing a voltage feedback architecture.
These amplifiers define a new level of performance for voltage
feedback amplifiers, especially in the categories of large signal
bandwidth, slew rate, settling, and low noise.
Proprietary design architectures have resulted in an amplifier
family that combines the most attractive attributes of both current feedback and voltage feedback amplifiers. The AD9621 exhibits extraordinarily accurate and fast pulse response
characteristics (7 ns settling to 0.1%) as well as extremely wide
small and large signal bandwidth previously found only in current feedback amplifiers. When combined with balanced high
impedance inputs and low input noise current more common to
voltage feedback architectures, the AD9621 offers performance
not previously available in a monolithic operational amplifier.
*Protected by U.S. Patent 5,150,074 and others pending.
TE
Other members of the AD962X amplifier family are the
AD9622 (G = +2), AD9623 (G = +4), and the AD9624
(G = +6). A separate data sheet is available from Analog Devices for each model. Each generic device has been designed for
a different minimum stable gain setting, allowing users flexibility
in optimizing system performance. Dynamic performance specifications such as slew rate, settling time, and distortion vary
from model to model. The table below summarizes key performance attributes for the AD962X family and can be used as a
selection guide.
The AD9621 is offered in industrial and military temperature
ranges. Industrial versions are available in plastic DIP, SOIC,
and cerdip; MIL versions are packaged in cerdips.
PRODUCT HIGHLIGHTS
1. Wide Large Signal Bandwidth
2. High Slew Rate
3. Fast Settling
4. Output Short-Circuit Protected
Parameter
AD9621
AD9622
AD9623
AD9624
Units
Minimum Stable Gain
Harmonic Distortion (20 MHz)
Large Signal Bandwidth (4 V p-p)
SSBW (0.5 V p-p)
Slew Rate
Rise/Fall Time (0.5 V Step)
Settling Time (to 0.1%/0.01%)
Input Noise (0.1 MHz – 200 MHz)
+1
–52
130
350
1200
2.4
7/11
80
+2
–66
160
220
1500
1.7
8/14
49
+4
–64
190
270
2100
1.6
8/14
36
+6
–66
200
300
2200
1.5
8/14
32
V/V
dB
MHz
MHz
V/µs
ns
ns
µV rms
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD9621–SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS (6V = 65 V, R
S
Parameter
Conditions
LOAD
= 100 Ω; AV = 1, unless otherwise noted)
Temp
Test
Level
AD9621AN/AQ/AR
Min
Typ Max
+25°C
Full
+25°C
Full
Full
+25°C
Full
Full
+25°C
+25°C
Full
+25°C
+25°C
Full
Full
+25°C
I
VI
I
VI
V
I
VI
V
V
V
VI
I
V
VI
VI
V
–12
–15
Min
AD9621SQ
Typ Max
Units
1
DC SPECIFICATIONS
Input Offset Voltage
Input Bias Current
Input Bias Current TC
Input Offset Current
Offset Current TC
Input Resistance
Input Capacitance
Common-Mode Range
Common-Mode Rejection Ratio
Open Loop Gain
Output Voltage Range
Output Current
Output Resistance
∆VCM = 1 V
VOUT = ± 2 V p-p
FREQUENCY DOMAIN
Bandwidth (–3 dB)
Small Signal
Large Signal
Amplitude of Peaking
Amplitude of Roll-off
Phase Nonlinearity
2nd Harmonic Distortion
3rd Harmonic Distortion
Common-Mode Rejection Mode
Spectral Input Noise Voltage
Spectral Input Noise Current
Average Equivalent Integrated
Input Noise Voltage
VOUT ≤ 0.4 V p-p
VOUT ≤ 4.0 V p-p
Full Spectrum
≤ 100 MHz
DC to 100 MHz
2 V p-p; 20 MHz
2 V p-p; 20 MHz
@ 20 MHz
1 to 200 MHz
1 to 200 MHz
Full
Full
Full
Full
+25°C
Full
Full
+25°C
+25°C
+25°C
II
V
II
II
V
II
II
V
V
V
0.1 to 200 MHz
+25°C
V
VOUT = 5 V Step
VOUT = 0.5 V Step
VOUT = 5 V Step
VOUT = 2 V Step
Full
+25°C
Full
Full
IV
V
IV
IV
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 4 V Step
VOUT = 4 V Step
1.5x to ± 2 mV
RL = 150 Ω
RL = 150 Ω
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
V
IV
V
V
V
V
V
Full
IV
Full
Full
+25°C
VI
VI
I
OBS
TIME DOMAIN
Slew Rate
Rise/Fall Time
Overshoot
Settling Time
To 0.1%
To 0.01%
To 0.1%2
T0 0.012
Overdrive Recovery
Differential Gain (4.3 MHz)
Differential Phase (4.3 MHz)
±2
7
–20
–2.0
–3.0
± 3.0
46
± 3.0
60
+12
+15
16
+20
35
± 0.3 +2.0
+3.0
2.5
500
1.2
± 3.4
49
56
± 3.4
70
0.3
–12
–15
–20
–2.0
–3.0
± 3.0
46
OLE
± 3.0
60
POWER SUPPLY REQUIREMENTS1
Supply Voltage (± VS)
Quiescent Current
+IS
+VS = +5 V
–IS
–VS = –5 V
Power Supply Rejection Ratio
∆VS = 0.5 V
230
350
130
0.1
0
1.1
–55
–52
+28
5.6
3.6
1.2
0.6
–44
–43
1200
2.4
4.8
7
0
15
5.0
5.5
29
29
54
23
23
66
mV
mV
7
µA
µA
35
nA/°C
+2.0 µA
+3.0 µA
2.5
nA/°C
500
kΩ
1.2
pF
± 3.4
V
49
dB
56
dB
± 3.4
V
70
mA
0.3
Ω
350
130
0.1
0
1.1
–55
–52
+28
5.6
3.6
1.2
0.6
–44
–43
MHz
MHz
dB
dB
Degree
dBc
dBc
dB
nV/√Hz
pA/√Hz
80
µV rms
1200
2.4
4.8
7
0
15
V/µs
ns
ns
%
7
11
15
9
13
50
0.01
<0.01
ns
ns
ns
ns
ns
%
Degree
3.0
5.0
5.5
V
29
29
54
23
23
66
mA
mA
dB
850
7
11
15
9
13
50
0.01
<0.01
3.0
+12
+15
16
+20
TE
230
80
850
±2
NOTES
1
Measured at AV = 21.
2
Measured with a 0.001 µF CB capacitor connected across Pins 1 and 8.
Specifications subject to change without notice.
–2–
REV. 0
AD9621
ABSOLUTE MAXIMUM RATINGS 1
THEORY OF OPERATION
Supply Voltages (± VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 90 mA
Operating Temperature Ranges
AN, AQ, AR . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
SQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature
Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction Temperature
Ceramic3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Soldering Temperature (1 minute)4 . . . . . . . . . . +220°C
The AD9621 is a wide bandwidth, unity gain stable voltage
feedback amplifier. Since its open-loop frequency response follows the conventional 6 dB/octave roll-off, its gain bandwidth
product is basically constant. Increasing its closed-loop gain results in a corresponding decrease in small signal bandwidth. The
AD9621 typically maintains a 55 degree unity loop gain phase
margin. This high margin minimizes the effects of signal and
noise peaking.
Feedback Resistor Choice
At minimum stable gain (+1), the AD9621 provides optimum
dynamic performance with RF ≅ 51 Ω. This resistor acts only as
a parasitic suppressor against damped RF oscillations that can
occur due to lead (input, feedback) inductance and parasitic capacitance. For settling accuracy to 0.1% or less, this resistor
should not be required if layout guidelines are closely followed.
This value for RF provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time.
OBS
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Output is short-circuit protected; for maximum reliability, 90 mA continuous
current should not be exceeded.
3
Typical thermal impedances (part soldered onto board; no air flow):
Ceramic DIP: θJA = 100°C/W; θJC = 30°C/W
Plastic SOIC: θJA = 125°C/W; θJC = 45°C/W
Plastic DIP:
θJA = 90°C/W; θJC = 45°C/W
4
Temperature shown is for surface mount devices, mounted by vapor phase
soldering. Throughhole devices (ceramic and plastic DIPs) can be soldered at
+300°C for 10 seconds.
ORDERING GUIDE
OLE
When the AD9621 is used in the transimpedance (I-to-V)
mode, such as for photo-diode detection, the value for RF and
diode capacitance (CI) are usually known. See Figure 1. Generally, the value of RF selected will be in the kΩ range, and a shunt
capacitor (CF) across RF will be required to maintain good amplifier stability. The value of CF required to maintain < 1 dB of
peaking can be estimated as:
TE
Model
Temperature
Range
Package
Description
Package
Option
AD9621AN
AD9621AQ
AD9621AR
AD9621SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8-Pin Plastic DIP
8-Pin Cerdip
8-Pin SOIC
8-Pin Cerdip
N-8
Q-8
R-8
Q-8
|R
F
≥ 1 kΩ
As an example, choosing RF of 10 kΩ and CI of 5 pF, requires
CF to be 1.1 pF (Note: CI includes both the source and parasitic
circuit capacitance). The bandwidth of the amplifier can be estimated using the CF calculated as:
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing of “A” grade devices
done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature extremes for commercial/industrial devices.
1.6
2 π RF C F
f 3 dB ≅
For general voltage gain applications, the amplifier bandwidth
can be estimated as:
f 3 dB ≅
ωο
 RF 
1+ 

 RG 
This estimation loses accuracy for gains approaching +2/–1 or
lower due to the amplifier’s damping factor. For these “low
gain” cases, the bandwidth will actually extend beyond the calculated value. See Closed Loop BW plots.
OUTPUT
+V
S
As a rule of thumb, capacitor CF will not be required if:
54mils
– INPUT
46.5mm
–V
S
(R
F
CB–
)
RG CI ≤
NG
4ω ο
where NG is the Noise Gain (l + RF/RG) of the circuit. For most
voltage gain applications, this should be the case.
–INPUT +INPUT
46.5mils
Chip Layout
REV. 0
2
where ωo is equal to the unity gain bandwidth product of the
amplifier in RAD/sec, and CI is the equivalent total input capacitance at the inverting input. Typically ωo is 700 × 106
RAD/sec (See Open Loop Frequency Response curve).
EXPLANATION OF TEST LEVELS
CB+
2
C F ≅ [(2ω οC I RF −1)ω ο RF ]1 2
–3–
AD9621
+VS
+VS
6.8µF
6.8µF
0.1µF
RF
RG
0.1µF
7
3
7
CB (OPTIONAL)
8
6
RG
OBS
AV =
VOUT
VOUT
CF
4
CF
Pulse Response
1
RF
500Ω
0.1µF
Figure 1. Transimpedance
Configuration
2
4
VIN
CI
6
CF
1
CB (OPTIONAL)
8
VOUT
2
RF
3
VIN
0.1µF
RG
–R F
RF
500Ω
AV = 1+
RG
6.8µF
RF
RG
6.8µF
–VS
–V S
Figure 2. Inverting Gain Connection
Diagram
Figure 3. Noninverting Gain Connection
Diagram
OLE
Unlike a traditional voltage feedback amplifier in which slew
speed is dictated by its front end dc quiescent current and gain
bandwidth product, the AD9621 provides “on demand” transconductance current that increases proportionally to the input
“step” signal amplitude. This results in slew speeds (1200 V/µs)
comparable to wideband current feedback designs. This, combined with relatively low input noise current (3.6 pA/√Hz), gives
the AD9621 the best attributes of both voltage and current feedback amplifiers.
Bootstrap Capacitor (CB)
In most applications, the CB capacitor will not be required.
Under certain conditions, it can be used to further enhance settling time performance.
The CB capacitor (0.001 µF) connects to the internal high impedance nodes of the amplifier. Using this capacitor will reduce
the large signal (4 V) step output settling time by 3 to 5 ns for
0.05% or greater accuracy. For settling accuracy less than
0.05% or for smaller step sizes, its effect will be less apparent.
Under heavy slew conditions, this capacitor forces the internal
signal (initial step) amplitude to be controlled by the “on”
(slewed) transistor, preventing its complement from completely
turning off. This allows for faster settling time of these internal
nodes and also the output.
In the frequency domain, total (high frequency) distortion will
be approximately the same with or without CB. Typically, the
3rd harmonic will be greater than the 2nd without CB. This will
be reversed with CB in place.
APPLICATIONS
The AD9621 is a voltage feedback amplifier and is well suited
for such applications as photo-detector preamp, active filters,
and log amplifiers. The device’s wide bandwidth (350 MHz),
phase margin (55°), low noise current (3.6 pA/√Hz), and slew
rate (1200 V/µs) give higher performance capabilities to these
applications over previous voltage feedback designs.
TE
With a settling time of 11 ns to 0.01% and 7 ns to 0.1%, the device is an excellent choice for DAC I/V conversion. The same
characteristics, along with low harmonic distortion, make it a
good choice for ADC buffering/amplification. With its superb
linearity at relatively high signal frequencies, it is an ideal driver
for ADCs up to 14 bits.
Layout Considerations
As with all wide bandwidth components, printed circuit layout
is critical to obtain best dynamic performance with the AD9621.
The ground plane in the area of the amplifier and its associated
components should cover as much of the component side of the
board as possible (or first interior layer of a multi layer surface
mount board).
The ground plane should be removed in the area of the inputs
and RF and RG to minimize stray capacitance at the input. The
same precaution should be used for CB, if used. Each power
supply trace should be decoupled close to the package with a
0.1 µF ceramic capacitor, plus a 6.8 µF tantalum nearby.
All lead lengths for input, output, and feedback resistor should
be kept as short as possible. All gain setting resistors should be
chosen for low values of parasitic capacitance and inductance,
i.e., microwave resistors and/or carbon resistors.
Microstrip techniques should be used for lead lengths in excess
of one inch. Sockets should be avoided if at all possible because
of their high series inductance. If sockets are necessary, individual pin sockets such as AMP p/n 6-330808-3 should be used.
These contribute far less stray reactance than molded socket
assemblies.
An evaluation board is available from Analog Devices for a
nominal charge.
–4–
REV. 0
Typical Performance (R = 100 Ω; A = +1, unless otherwise noted) – AD9621
+180
+2
+45
+45
+30
+15
0
–15
–30
0
0
–45
AV = –1
–4
–6
1M
10M
FREQUENCY – Hz
–180
V OUT = 2V p-p
2nd HARMONIC
RL = 500Ω
3rd HARMONIC
RL = 100Ω
–100
–110
–120
3rd HARMONIC
RL = 500Ω
1
2
40
+2
30
0
60
RLOAD = 50Ω
AV = 1
RF = 51Ω
–135
–180
–8
50 100 150 200 250 300 350 400
FREQUENCY – MHz
100
10
8
8
CMRR
TE
+55
+60
PSRR
100Ω
6pF
0
–0.02
–0.04
CURRENT
2
2
V OUT = 2V STEP
10 5
10 6
1k 10k 100k 1M
FREQUENCY – Hz
10M 100M 1G
0
–0.02
–0.08
10
20
30
TIME – ns
40
–0.1
50
Figure 11. Short-Term Settling
Time
MEASURING
POINT
–0.04
–0.06
0
V OUT = 2V STEP
+0.02
–0.08
4
VOLTAGE
23
3
CURRENT
TEST CIRCUIT
100Ω
1
10
+2V
0
6pF
10K
100
1K
TIME – ns
1
Figure 13. Input Spectral Noise
Density
100K
Figure 12. Long-Term Settling Time
30
26
40
RS
RS
30
1k
CL
22
51
18
20
tSETTLING
14
10
19
10 4
FREQUENCY – Hz
100
+0.04
–0.06
SUPPLY CURRENT – mA
4
4
Hz
6
10
50
NOISE CURRENT – pA
VOLTAGE
1
Figure 9. CMRR and PSRR vs.
Frequency
+0.06
27
Hz
+50
+0.08
+0.02
–0.1
450 500
10
NOISE VOLTAGE – nV/
+45
TEST CIRCUIT
+0.04
Figure 10. Frequency Response
vs. RLOAD
REV. 0
+40
+0.1
+0.06
SETTLING PERCENTAGE
0
–90
10 3
+35
+70
+0.1
+0.08
PHASE – Degrees
RLOAD = 500Ω
–45
1
10 2
+30
Figure 8. Third Order Intercept
+45
–4
10
FREQUENCY – MHz
1
+90
0
MAGNITUDE – dB
20
10
+135
6
+25
OUT
50
+180
–6
+20
50
+65
4 6
10
20
FREQUENCY – MHz
Figure 7. Harmonic Distortion
vs. Frequency
–2
100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
Figure 6. Noninverting Frequency
Response
40
INTERCEPT – +dBm
dBc
–80
–90
50
OLE
–70
–180
–8
Figure 5. Inverting Frequency
Response
OBS
–60
AV = 2
AV = 4
50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
–50
2nd
2ndHARMONIC
HARMONIC
RRLL==100Ω
100Ω
–90
–6
–8
Figure 4. Open-Loop Gain and
Phase
–45
–4
AV = –2
–60
600M
100M
0
AV = 1
–135
SETTLING PERCENTAGE
100k
–90
–2
RS – Ohms
–20
10k
+45
–135
–45
+90
0
POWER SUPPLY AND COMMON
MODE REJECTION RATIOS – dB
PHASE
–2
OUTPUT LEVEL – ± Volts
20
MAGNITUDE – dB
40
+180
+135
+90
0
PHASE – Degrees
OPEN-LOOP GAIN – dB
+60
MAGNITUDE – dB
GAIN
60
+2
+135
+75
2
0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE – ±Volts
5.5
Figure 14. Output Level and
Supply Current vs. Supply Voltage
–5–
1
10
CLOAD – pF
Figure 15. Settling Time vs.
Capacitive Load
10
100
tSETTLING TO 0.01% – ns
+90
PHASE – Degrees
80
V
PHASE – Degrees
L
AD9621
50
0.2V
2V
TO 0.01%
0
RLOAD = 100Ω
V OUT = 0.4V p-p
RLOAD = 100Ω
VOUT = 2V p-p
30
20
–0.2V
–2V
INPUT RISE/FALL TIME = 0.3ns
INPUT RISE/FALL TIME = 1.6ns
10
5ns/DIV
5ns/DIV
Figure 16. Large Signal Pulse
Response
OBS
Figure 17. Small Signal Pulse
Response
1
3
NONINVERTING GAIN
5
C1721–24–10/92
RLOAD = 100Ω
V OUT = 5V p-p
SETTLING TIME – ns
0
V OUT –40mV/DIV
V OUT –0.2V/DIV
40
Figure 18. Settling Time vs.
Noninverting Gain
MECHANICAL INFORMATION
Cerdip (Suffix Q)
0.055 (1.4) MAX
8
5
PIN 1
0.310 (7.87)
0.220 (5.59)
1
4
OLE
Plastic DIP (Suffix N)
8
1
0.360 (9.144)
0.400 (10.16)
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.140
(3.556)
MIN
0.015 (0.38)
0.008 (0.20)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
4
0.200
(5.08)
MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.045 (1.143)
0.065 (2.667)
0.100
(2.54)
BSC
SEATING
PLANE
0.290 (7.366)
0.310 (7.874)
0.120 (3.048)
0.140 (3.556)
0.015 (0.381)
0.008 (0.204)
0.016 (0.406)
0.020(0.508)
0° TO 15°
TE
0.240 (6.096)
0.260 (6.604)
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
5
PIN 1
0°-15°
SEATING
PLANE
Plastic SOIC (Suffix R)
0.196 (5.00)
0.188 (4.75)
0.244 (6.20)
0.228 (5.80)
0.050
(1.27)
TYP
TOP
VIEW
PRINTED IN U.S.A.
0.005 (0.13) MIN
Dimensions shown in inches and (mm).
0.158 (4.00)
0.150 (3.80)
0.180 (0.46)
0.014 (0.36)
0.206 (5.20)
0.181 (4.60)
0.069 (1.75)
0.053 (1.35)
0.010 (0.25)
0.004 (0.10)
0.015 (0.38)
0.007 (0.18)
–6–
0.045 (1.15)
0.020 (0.50)
REV. 0