Institute for
Electronic Design Automation
Technische Universität München
Symmetry Computation for Hierarchical Analog
Designs
Michael Eick, Devanathan Sridharan and Helmut Graeb
Institute for Electronic Design Automation, Technische Universität München, Arcisstr. 21, 80333 Munich, Germany
{eick,deva.sridharan,graeb}@tum.de
Method
Constraint-Driven Design
symmetry computation
ip
R5
R1
+
R7
R3
symmetry
(user input)
- state of the art: computation for flat netlists,
e.g., [1,2,4,5]
- BUT: real designs use a design hierarchy
+
-
hierarchical netlist
in
I1
+
o
I3
-
+
R2
I2
R4
R6
building block analysis, e.g., [6]
...
building blocks
-
differential
pair
simple
current mirror
Challenge: modelling of
subcircuits in ESFG
symmetry allowed or
forbidden among
generated edges
+
ESFG
-
+
ESFG
in
o
Comparison
net
Investigated circuit: instrumentation amplifier (see right)
symmetry pairs
(transistor level)
Challenge: multiple
instances of same
subcircuit
different conditions may
arise for different instances
ip
runtime
symmetries in ESFG
in
10
o
3.8x
between I1 - I2
5s
ip
symmetries in ESFG
computed
symmetries
inside I3
-
+
top level
new flat [1]
new flat [1]
+
-
I1
R5
R3
R1
ip
+
R7
+
R2
I2
R4
R6
I3
o
-
+
symmetries
in circuit
[1] M. Eick and H. Graeb. MARS: Matching-driven Analog Sizing. IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems. August 2012.
[2] M. Eick and M. Strasser and K. Lu and U. Schlichtmann and H. Graeb. Comprehensive Generation of Hierarchical
Placement Rules for Analog Integrated Circuits. IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems. February 2011.
[3] M. Eick and H. Graeb. Unified Generation of Analog Sizing and Placement Constraints. Frontiers in Analog
Circuit (FAC) Synthesis and Verification. July 2011.
[4] M. E. Kole, J. Smit, and O. E. Herrmann. Modeling symmetry in analog electronic circuits. In IEEE International
Symposium on Circuits and Systems (ISCAS). May 1994.
[5] J. Liu, S. Dong, X. L. Hong, Y. Wang, O. He, and S. Goto. Symmetry constraint based on mismatch analysis for
analog layout in SOI technology. In Asia and South Pacific Design Automation Conference, 2008.
[6] T. Massier, H. Graeb, and U. Schlichtmann. The Sizing Rules Method for CMOS and Bipolar Analog Integrated
Circuit Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. 2008.
[Example circuit] P. Horowitz and W. Hill. The art of electronics. Cambridge university press, 1989.
in