SE555-SP
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SGLS401 – FEBRUARY 2010
QML CLASS V PRECISION TIMER
Check for Samples: SE555-SP
FEATURES
1
•
•
•
•
•
•
•
(1)
Timing From Microseconds to Hours
Astable or Monostable Operation
Adjustable Duty Cycle
TTL-Compatible Output Can Sink or Source up
to 100 mA
QML-V Qualified, SMD 5962-98555
Military Temperature Range (-55°C to 125°C)
Rad-Tolerant: 25 kRad (Si) TID (1)
JG PACKAGE
(TOP VIEW)
GND
TRIG
OUT
RESET
1
8
2
7
3
6
4
5
VCC
DISCH
THRES
CONT
Radiation tolerance is a typical value based upon initial device
qualification with dose rate = 10 mrad/sec. Radiation Lot
Acceptance Testing is available - contact factory for details.
DESCRIPTION/ORDERING INFORMATION
The SE555 is a precision timing circuit capable of producing accurate time delays or oscillation. In the time-delay
or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor
network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two
external resistors and a single external capacitor.
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing current up to 100 mA. Operation is specified for supplies of
4.5 V to 16.5 V. With a 5-V supply, output levels are compatible with TTL inputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SE555-SP
SGLS401 – FEBRUARY 2010
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ORDERING INFORMATION (1)
PACKAGE (2)
TA
–55°C to 125°C
(1)
(2)
CDIP - JG
ORDERABLE PART NUMBER
TOP-SIDE MARKING
5962-9855501VPA
5962-9855501VPA
Tube of 50
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. FUNCTION TABLE
(1)
RESET
TRIGGER
VOLTAGE (1)
THRESHOLD
VOLTAGE (1)
OUTPUT
DISCHARGE
SWITCH
Low
Irrelevant
Irrelevant
Low
On
High
<1/3 VCC
Irrelevant
High
Off
High
>1/3 VCC
>2/3 VCC
Low
On
High
>1/3 VCC
<2/3 VCC
As previously established
Voltage levels shown are nominal.
FUNCTIONAL BLOCK DIAGRAM
VCC
8
CONT
5
6
THRES
2
TRIG
Î
Î
Î Î
Î
Î Î
Î Î
RESET
4
Î
Î
Î
Î
Î
Î
Î
R1
R
3
OUT
1
S
7
DISCH
1
GND
A.
2
RESET can override TRIG, which can override THRES.
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SGLS401 – FEBRUARY 2010
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage (2)
VI
Input voltage
IO
Output current
qJC
Package thermal impedance (3)
45
°C/W
TJ
Operating virtual junction temperature
150
°C
Lead temperature 1, 6 mm (1/16 in) from case for 60 s
300
°C
150
°C
Tstg
(1)
(2)
(3)
(4)
18
CONT, RESET, THRES, TRIG
V
±200
mA
(4)
Storage temperature range
V
VCC
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Maximum power dissipation is a function of TJ(max), qJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) - TC)/qJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with MIL-STD-883.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VI
Input voltage
IO
Output current
TA
Operating free-air temperature
MIN
MAX
UNIT
4.5
16.5
V
VCC
V
±100
mA
125
°C
CONT, RESET, THRES, and TRIG
–55
ELECTRICAL CHARACTERISTICS
VCC = 4.5 V to 16.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC
Power supply current
TEST CONDITIONS
VCC = 16.5 V, RL = ∞
TA = 25°C, 125°C, –55°C
20
Trigger voltage
Trigger current
VCC = 16.5 V for
VTR = 5 V
VCC = 4.5 V
VTH
Threshold voltage
VCC = 16.5 V
ITH
Threshold current
MAX
5
VCC = 16.5 V
ITR
TYP
TA = 25°C, 125°C, –55°C
VCC = 4.5 V
VTR
MIN
VCC = 4.5 V, RL = ∞
VCC = 16.5 V
TA = 25°C
1.30
1.80
TA = 125°C
1.30
2.10
TA = –55°C
1.15
1.80
TA = 25°C
5.20
5.80
TA = 125°C
5.20
6.10
TA = –55°C
5
5.80
TA = 25°C, 125°C, –55°C
–5
UNIT
mA
V
mA
TA = 25°C
2.70
3.30
TA = 125°C, –55°C
2.60
3.40
TA = 25°C
10.70
11.30
TA = 125°C, –55°C
10.60
11.40
V
TA = 25°C, 125°C
250
nA
TA = –55°C
2.5
mA
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ELECTRICAL CHARACTERISTICS (continued)
VCC = 4.5 V to 16.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOL
Low level output voltage
VOH
TEST CONDITIONS
MIN
TYP
MAX
VCC = 4.5 V,
ISINK = 5 mA
TA = 25°C
0.25
TA = 125°C, –55°C
0.35
VCC = 4.5 V,
ISINK = 50 mA
TA = 25°C, 125°C
2.20
TA = –55°C
2.60
VCC = 16.5 V,
ISINK = 10 mA
TA = 25°C, –55°C
0.15
TA = 125°C
0.25
VCC = 16.5 V,
ISINK = 50 mA
TA = 25°C, –55°C
0.50
TA = 125°C
0.70
VCC = 16.5 V,
ISINK = 100 mA
TA = 25°C
2.20
TA = 125°C, –55°C
2.80
VCC = 4.5 V,
ISOURCE = –100 mA
TA = 25°C, 125°C
TA = –55°C
2.20
VCC = 16.5 V,
ISOURCE = –100 mA
TA = 25°C, 125°C
14.60
High level output voltage
TA = –55°C
UNIT
V
2.60
V
14
TA = 25°C, –55°C
100
nA
3
mA
ICEX
Discharge transistor
leakage current
VCC = 16.5 V
VSAT
Discharge transistor
saturation voltage
VCC = 16.5 V,
ID = 50 mA
TA = 25°C, –55°C
VR
Reset voltage
VCC = 16.5 V
TA = 25°C, 125°C, –55°C
0.10
1.30
V
IR
Reset current
VCC = 16.5 V, VR = 0 V
TA = 25°C, 125°C, –55°C
–1.60
0
mA
tPLH
Propgation delay time,
low to high level output
(monostable)
4.5 V ≤ VCC ≤ 16.5 V,
RT = 1 kΩ, CT = 0.1 mF
tTLH
Transition time,
low to high level output
(monostable)
tTHL
Transition time,
high to low level output
(monostable)
tD(OH)
Time delay, output high
(monostable)
TA = 125°C
TA = 125°C
800
900
4.5 V ≤ VCC ≤ 16.5 V,
RT = 1 kΩ, CT = 0.1 mF
TA = 25°C, 125°C, –55°C
300
ns
4.5 V ≤ VCC ≤ 16.5 V,
RT = 1 kΩ, CT = 0.1 mF
TA = 25°C, 125°C, –55°C
300
ns
106.70
113.30
ms
10.67
11.33
ms
–220
220
ns/V
12
ms
–11
11
ns/°C
120
156
ms
11.30
15
ms
57.50
80
ms
5.40
7.70
ms
4.5 V ≤ VCC ≤ 16.5 V,
RT = 1 kΩ, CT = 0.1 mF
4.5 V ≤ VCC ≤ 16.5 V,
RT = 100 kΩ, CT = 0.1 mF
TA = 25°C
tPHL
Propogation delay time,
threshold to output
4.5 V ≤ VCC ≤ 16.5 V,
RT = 1 kΩ
TA = 25°C, 125°C, –55°C
ΔtD(OH) /
ΔT
Temperature coefficient
of time delay
(monostable)
VCC = 16.5 V,
RT = 1 kΩ, CT = 0.1 mF
TA = 125°C, –55°C
tdis
4
4.5 V ≤ VCC ≤ 16.5 V,
RTA = RTB = 1 kΩ,
CT = 0.1 mF
4.5 V ≤ VCC ≤ 16.5 V,
RTA = RTB = 100 kΩ,
CT = 0.1 mF
4.5 V ≤ VCC ≤ 16.5 V,
RTA = RTB = 1 kΩ,
CT = 0.1 mF
4.5 V ≤ VCC ≤ 16.5 V,
RTA = RTB = 100 kΩ,
CT = 0.1 mF
ns
TA = 25°C, 125°C, –55°C
ΔVCC = 12 V,
RT = 1 kΩ, CT = 0.1 mF
Capacitor discharge time
(astable)
V
TA = 125°C
Drift in time delay versus
change in supply voltage
(monostable)
tch
1
TA = 25°C, –55°C
ΔtD(OH) /
ΔVCC
Capacitor charge time
(astable)
0.80
TA = 25°C, 125°C, –55°C
TA = 25°C, 125°C, –55°C
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SGLS401 – FEBRUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
VCC = 4.5 V to 16.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Δtch /
ΔVCC
Drift in capacitor charge
time versus change in
supply voltage (astable)
ΔVCC = 12 V,
RTA = RTB = 1 kΩ,
CT = 0.1 mF
TA = 25°C
–820
820
ns/V
Δtch / ΔT
Temperature coefficient
of capacitor charge time
(astable)
ΔVCC = 16.5 V,
RTA = RTB = 1 kΩ,
CT = 0.1 mF
TA = 125°C, –55°C
–68
68
ns/°C
tres
Reset time
VCC = 16.5 V
TA = 25°C, –55°C
1.50
TA = 125°C
2
ms
100
Estimated Life (Years)
Electromigration Fail Mode
10
1
80
90
100
110
120
130
140
150
160
Continuous T J (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. SE555 8/JG Package Operating Life Derating Chart
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TYPICAL CHARACTERISTICS
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LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
2
1
0.7
0.4
0.2
0.1
0.07
10
7
VCC = 5 V
TA = −55°C
TA = 25°C
TA = 125°C
0.04
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
10
7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.02
VCC = 10 V
4
2
TA = 25°C
1
0.7
TA= −55°C
TA = 125°C
0.4
0.2
0.1
0.07
0.04
0.02
0.01
0.01
1
2
4
7
10
20
40
70 100
1
IOL − Low-Level Output Current − mA
2
4
TA = −55°C
1.8
TA = −55°C
2
1
0.7
TA = 25°C
0.2
TA = 125°C
0.1
0.07
0.04
1.6
1.2
0.8
0.6
0.4
0.2
4
7
10
20
40
IOL − Low-Level Output Current − mA
70 100
TA = 125°C
1
0.01
2
TA = 25°C
1.4
0.02
1
0
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VCC = 5 V to 15 V
1
Figure 4.
6
70 100
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2.0
VCC = 15 V
0.4
40
DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT
vs
HIGH-LEVEL OUTPUT CURRENT
( VCC − VOH) − Voltage Drop − V
VOL − Low-Level Output Voltage − V
4
20
Figure 3.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
10
7
10
IOL − Low-Level Output Current − mA
Figure 2.
ÏÏÏÏ
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ÏÏÏÏ
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7
2
4
7 10
20
40
70 100
IOH − High-Level Output Current − mA
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
SUPPLY VOLTAGE
10
Pulse Duration Relative to Value at VCC = 10 V
Output Low,
No Load
9
I CC − Supply Current − mA
8
TA = 25°C
7
6
5
TA = −55°C
4
TA = 125°C
3
2
1
0
5
6
7
8
9
10
11
12
13
14
15
1.015
1.010
1.005
1
0.995
0.990
0.985
0
VCC − Supply Voltage − V
5
10
15
20
VCC − Supply Voltage − V
Figure 6.
Figure 7.
PROPAGATION DELAY TIME
vs
LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
FREE-AIR TEMPERATURE
1000
VCC = 10 V
900
TA = 125°C
1.010
t PD – Propagation Delay Time – ns
Pulse Duration Relative to Value at TA = 255C
1.015
1.005
1
0.995
0.990
800
700
TA = 70°C
600
500
TA = 25°C
400
300
TA = 0°C
200
TA = –55°C
100
0
0.985
−75
−50
−25
0
25
50
100 125
75
0
TA − Free-Air Temperature − °C
Figure 8.
0.05 0.1 0.15
0.2 0.25 0.3 0.35
Lowest Level of Trigger Pulse – ×VCC
0.4
Figure 9.
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APPLICATION INFORMATION
Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 10. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold
comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
VCC
(5 V to 15 V)
5
RA
8
CONT
4
7
6
Input
2
VCC
RL
RESET
DISCH
OUT
3
Output
THRES
TRIG
GND
1
Figure 10. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high at the end of the timing interval. Because of the threshold level and
saturation voltage of Q1, the output pulse duration is approximately tw = 1.1RAC. Figure 12 is a plot of the time
constant for various values of RA and C. The threshold levels and charge rates both are directly proportional to
the supply voltage, VCC. The timing interval is, therefore, independent of the supply voltage, so long as the
supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
8
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SGLS401 – FEBRUARY 2010
10
RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9
RA = 10 MΩ
tw − Output Pulse Duration − s
1
Voltage − 2 V/div
Input Voltage
ÏÏÏÏÏÏ
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ÏÏÏÏÏÏ
Output Voltage
RA = 1 MΩ
10−1
10−2
10−3
RA = 100 kΩ
RA = 10 kΩ
10−4
RA = 1 kΩ
10−5
Capacitor Voltage
0.001
0.01
0.1
1
10
100
C − Capacitance − µF
Time − 0.1 ms/div
Figure 11. Typical Monostable Waveforms
Figure 12. Output Pulse Duration vs Capacitance
Astable Operation
As shown in Figure 13, adding a second resistor, RB, to the circuit of Figure 10 and connecting the trigger input
to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through
RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and
RB.
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ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(Ⅹ0.67 × VCC) and the trigger-voltage level (Ⅹ0.33 × VCC). As in the monostable circuit, charge and discharge
times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.
VCC
(5 V to 15 V)
4
CONT
8
VCC
RL
RESET
7
RB
6
2
C
DISCH
OUT
3
Output
t
H
THRES
TRIG
RL = 1 kW
See Figure 12
Voltage − 1 V/div
RA
0.01 mF
Open
(see Note A) 5
RA = 5 kW
RB = 3 kW
C = 0.15 µF
tL
GND
Output Voltage
1
Capacitor Voltage
NOTE A: Decoupling CONT voltage to ground with a capacitor
can improve operation. This should be evaluated for
individual applications.
Figure 13. Circuit for Astable Operation
Time − 0.5 ms/div
Figure 14. Typical Astable Waveforms
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Figure 13 shows typical waveforms generated during astable operation. The output high-level duration tH and
low-level duration tL can be calculated as follows:
tH = 0.693 (RA + RB) C
(1)
tL = 0.693 (RB) C
(2)
Other useful relationships are shown in the following equations.
period = tH + tL = 0.693 (RA + 2RB) C
(3)
1.44
frequency » ¾
(RA + 2RB) C
(4)
tL
RB
Output driver duty cycle = t¾
= R¾
+
2RB
H + tL
A
tH
RB
Output waveform duty cycle = t¾
=1 - ¾
+
t
RA + 2RB
H
L
tL
RB
Low-to-high ratio = ¾
tH = R¾
A + RB
(5)
(6)
(7)
100 k
RA + 2 RB = 1 kΩ
f − Free-Running Frequency − Hz
RA + 2 RB = 10 kΩ
10 k
RA + 2 RB = 100 kΩ
1k
100
10
1
RA + 2 RB = 1 MΩ
RA + 2 RB = 10 MΩ
0.1
0.001
0.01
0.1
1
10
100
C − Capacitance − µF
Figure 15. Free-Running Frequency
10
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Missing-Pulse Detector
The circuit shown in Figure 16 can be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is retriggered continuously by
the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing, missing
pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an output pulse
as shown in Figure 17.
4
Input
RESET
2
RL
8
VCC
3
OUT
RA
Output
TRIG
7
DISCH
5
0.01 mF
CONT
THRES
GND
1
6
VCC = 5 V
RA = 1 kΩ
C = 0.1 µF
See Figure 15
Voltage − 2 V/div
VCC (5 V to 15 V)
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Input Voltage
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
Output Voltage
C
A5T3644
Capacitor Voltage
Time − 0.1 ms/div
Figure 16. Circuit for Missing-Pulse Detector
Figure 17. Completed Timing Waveforms for
Missing-Pulse Detector
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Frequency Divider
By adjusting the length of the timing cycle, the basic circuit of Figure 10 can be made to operate as a frequency
divider. Figure 18 shows a divide-by-three circuit that makes use of the fact that retriggering cannot occur during
the timing cycle.
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Voltage − 2 V/div
VCC = 5 V
RA = 1250 Ω
C = 0.02 µF
See Figure 9
Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.1 ms/div
Figure 18. Divide-by-Three Circuit Waveforms
12
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SGLS401 – FEBRUARY 2010
Pulse-Width Modulation
The operation of the timer can be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 19 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 20 shows the resulting output pulse-width modulation. While a sine-wave modulation
signal is shown, any wave shape could be used.
VCC (5 V to 15 V)
RESET
VCC
2
OUT
RA
Modulation Input Voltage
Output
TRIG
DISCH
Modulation
Input
(See Note A)
3
RA = 3 kΩ
C = 0.02 µF
RL = 1 kΩ
See Figure 18
5
CONT
THRES
7
6
GND
1
C
Voltage − 2 V/div
Clock
Input
RL
8
4
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
NOTE A: The modulating signal can be direct or capacitively coupled to CONT.
For direct coupling, the effects of modulation source voltage and
impedance on the bias of the timer should be considered.
Clock Input Voltage
Output Voltage
Capacitor Voltage
Time − 0.5 ms/div
Figure 19. Circuit for Pulse-Width Modulation
Figure 20. Pulse-Width-Modulation Waveforms
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SE555-SP
SGLS401 – FEBRUARY 2010
www.ti.com
Pulse-Position Modulation
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
As shown in Figure 21, any of these timers can be used as a pulse-position modulator. This application
modulates the threshold voltage and, thereby, the time delay, of a free-running oscillator. Figure 22 shows a
triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
VCC (5 V to 15 V)
8
RESET
2
RL
RA
VCC
3
OUT
Output
TRIG
DISCH
Modulation
Input
(See Note A)
5
CONT
THRES
7
6
RB
GND
1
C
Voltage − 2 V/div
4
RA = 3 kΩ
RB = 500 Ω
RL = 1 kΩ
See Figure 20
Modulation Input Voltage
Output Voltage
NOTE A: The modulating signal can be direct or capacitively coupled to CONT.
For direct coupling, the effects of modulation source voltage and
impedance on the bias of the timer should be considered.
Capacitor Voltage
Time − 0.1 ms/div
Figure 21. Circuit for Pulse-Position Modulation
14
Figure 22. Pulse-Position-Modulation Waveforms
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SGLS401 – FEBRUARY 2010
Sequential Timer
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits can be
connected to provide such sequential control. The timers can be used in various combinations of astable or
monostable circuit connections, with or without modulation, for extremely flexible waveform control. Figure 23
shows a sequencer circuit with possible applications in many systems, and Figure 24 shows the output
waveforms.
VCC
4
8
VCC
3
OUT
RESET
2
TRIG
S
DISCH
5
RA
2
4
RESET
8
VCC
3
OUT
TRIG
0.001 mF
7
DISCH
5
CONT
CONT
THRES 6
GND
0.01 mF
33 W
0.01 mF
1
CA = 10 mF
RA = 100 kW
Output A
4
RESET
33 kW
2
TRIG
0.001 mF
7
8
VCC
3
OUT
DISCH
5
6
THRES
GND
1
CA
RB
CONT
0.01 mF
CB
CB = 4.7 mF
RB = 100 kW
7
6
THRES
GND
1
CC
CC = 14.7 mF
RC = 100 kW
Output B
RC
Output C
NOTE A: S closes momentarily at t = 0.
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏÏÏÏ ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏ
ÏÏÏÏÏ
ÏÏÏÏ
ÏÏ ÏÏÏÏÏ
ÏÏÏÏ
ÏÏ ÏÏÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÏÏÏ
Figure 23. Sequential Timer Circuit
See Figure 22
Voltage − 5 V/div
Output A
twA
twA = 1.1 RACA
twB
Output B
twB = 1.1 RBCB
Output C
twC
twC = 1.1 RCCC
t=0
t − Time − 1 s/div
Figure 24. Sequential Timer Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
5962-9855501VPA
Package Type Package Pins Package
Drawing
Qty
ACTIVE
CDIP
JG
8
1
Eco Plan
Lead/Ball Finish
(2)
TBD
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
A42
N / A for Pkg Type
(4)
-55 to 125
59629855501VPA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SE555-SP :
• Catalog: SE555
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Military: SE555M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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