mapping combinational gates to rtl

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MAPPING COMBINATIONAL GATES TO
RTL USING ENCOUNTER® CONFORMAL
EQUIVALENCE CHECKER
SEPTEMBER 2, 2015
TIM PUZEY
MAPPING COMBINATIONAL GATES TO RTL
INTRODUCTION
 As designs have grown to over 1 billion transistors,
the reliance on synthesis auto place and route
(SAPR) has increased.
 Once hand crafted logic implementation is now
synthesized with no thought from the user.
 Poor implementation is only discovered when the
design constraints such as timing aren’t met.
 Determining what SAPR implemented in order to
adjust the tool constraints is challenging given the
size and complexity of current designs.
 Designers need better visibility into what the
SAPR tool is doing!
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What is it doing?
MAPPING COMBINATIONAL GATES TO RTL
IDEAL SOLUTION
 Every combinational gate that corresponds to rtl would be annotated.
 Sample Timing Report:
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MAPPING COMBINATIONAL GATES TO RTL
TRADITIONAL SOLUTIONS
 Tracing fan-in and fan-out cones to isolate logic.
‒ This is a manual, time-consuming process.
 Adding ports to the logic.
‒ Requires a separate run which doubles compute time and
will alter how the tool builds the logic.
 Running synthesis in a mode that preserves hierarchy.
‒ Modules still have deep and wide logical cones.
‒ Opportunities for optimization may be lost.
 More recently SAPR tools have added mappings to the
design.
‒ These properties are challenging to maintain through the
transformations that occur during synthesis.
‒ The information that is tracked by these properties can be
incomplete as usually only the rtl line is retained.
‒ None of these mappings are maintained when the design
database is written to a file to be passed between tools.
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MAPPING COMBINATIONAL GATES TO RTL
ENCOUNTER® CONFORMAL EQUIVALENCE CHECKER SOLUTION
 OBSERVATION: Traditional formal verification tools map sub
cones of logic between rtl and gates all the time.
 Do the formal verification tools have a way to accesses the
sub cone mappings?
‒ Yes, Encounter® Conformal Equivalence Checker does!
 How do you use Encounter® Conformal Equivalence Checker
to get the mappings between rtl and the physical design?
‒ What are the methods to use?
‒ What do you need to consider?
‒ How do you use the mappings once you have them?
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MAPPING COMBINATIONAL GATES TO RTL
BACKGROUND
 Rtl code is compiled and synthesized into a
golden model.
‒ This golden model is a one for one implementation
of the rtl code.
‒ You can think of it as ‘What you see is what you get’
as highlighted in Figure 1.
‒ Any design constraints, such as illegal states, are
added to the golden synthesis as muxes that
propagate don’t care values into the cone.
RTL:
Z = AB + CD + EF
Synthesis (exactly matches coding style):
A
B
C
Z
D
E
F
Figure 1 What you see is what you get
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MAPPING COMBINATIONAL GATES TO RTL
BACKGROUND
 The tool compares the golden model to the
revised design which in this case is the physical
design.
 The revised design is composed of instantiated
library cells with functional definitions for the
‘primitives’ inside the library cell as
demonstrated in Figure 2 Primitive cells.
G1 instantiation of Library Cell:
A
B
G1
Y
C
D
Three Primitives:
A
G1/U1
B
C
G1/U2
D
G1/U3
Y
Figure 2 Primitive cells
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MAPPING COMBINATIONAL GATES TO RTL
BACKGROUND
 The tool maintains two views of the revised
design: hierarchical and flat.
 Hierarchical vs. flat design:
TOP
L2
G2
TOP/L2/G2
Flat design
Hierarchical design
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MAPPING COMBINATIONAL GATES TO RTL
BACKGROUND ON ENCOUNTER® CONFORMAL EQUIVALENCE CHECKER MAPPING
 Tracking is done by function instead of nets which
better helps equivalence debug.
‒ Mapping functions allows for more potential matches
than just mapping the rtl net as all the sub terms are
exposed.
‒ For example Z = AB + CD + EF
‒ One net Z
‒ 5 sub terms: AB, CD, EF, AB + CD, (AB + CD) + EF
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MAPPING COMBINATIONAL GATES TO RTL
BACKGROUND ON ENCOUNTER® CONFORMAL EQUIVALENCE CHECKER MAPPING
 Golden primitives have a mapping to the rtl line and the character
position of the function that created them.
 Example of golden mappings to rtl code:
RTL(line 1 of example.v rtl):
Z = AB + CD + EF
Golden Mapping to rtl showing file, line number, and character position:
U1 Mapping -> example.v 1,8 # This points to the ‘+’ between AB and CD on the rtl line.
U2 Mapping -> example.v 1,13 # This points to the ‘+’ between CD and EF on the rtl line.
Equation rewritten with inferred precedence: Z = (AB + CD) + EF
Synthesis (exactly matches rtl coding style):
A
B
U1
C
Z
D
U2
E
F
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MAPPING COMBINATIONAL GATES TO RTL
METHOD
1.
Each revised library cell is mapped to its primitives. This is done once.
2.
For each revised primitive of the gate to be mapped, do the following:
A.
B.
3.
Retrieve the correspondence. This is a list of potential matches in the golden design.
Sample command: report_gate -revised -correspondence -noshort_list $RevisedId
Apply a prove command between the rtl and each correspondence item until you get a match or inverse match or
you run out of items.
If the prove succeeds, do the following:
A.
B.
Determine the driving gate of all primitive inputs. Trace the input through the gate netlist until the gate isn’t the
same parent as the mapped primitive. This is used when annotating a timing report to tell which mapped
primitives of the physical gate are actually being exercised by the timing path.
Get the netname of the mapped golden output pin. Record the name if it is meaningful and not synthesis
generated. Trace through down stream inverters and buffers in case they have a meaningful name. This netname
is especially helpful for determining which bit of arrayed logic is being mapped. Note that the mapping most likely
will not include the for loop or generate statement that created the instances, and it may be desirable to include
several lines before the mapping when annotating reports.
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MAPPING COMBINATIONAL GATES TO RTL
RESULTS FOR FIRST METHOD
 If only it were this simple.
 Mapping the whole design can take days as the
average mapping takes over a second per net.
‒ Runtimes for the correspondence command vary
from cone to cone and can be over a minute for just
one cone.
‒ The number of objects on the correspondence list
varies widely from cone to cone.
‒ The prove command run time also has large variation.
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MAPPING COMBINATIONAL GATES TO RTL
ENHANCED METHOD
 Two remedies for runtime:
‒ Break up the list of nets to map and run on parallel machines.
‒ This can be done by making new directories and just linking the verilog
and other files needed by LEC.
‒ Unfortunately, this is compute intensive.
‒ It is also usually not necessary. Most of the mappings created by this
approach will never be used.
‒ Determine and map only nets of interest.
‒ An excellent source is harvesting the nets out of timing reports.
‒ Any net that isn’t a flop, inverter, or buffer is placed in a hash.
‒ Multiple timing reports can be harvested.
‒ The final resulting unique items then are attempted to be mapped.
 Limiting how hard the tool tries to map the gate also helps
runtime.
‒ Attempt only the first twenty correspondence objects before moving on to
the next rtl gate.
‒ Skip proves for corresponds points that are not primitives. This would be
points like PO(Primary Output), PI(Primary Input), DFF(State Point), and Cut.
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MAPPING COMBINATIONAL GATES TO RTL
RESULTS FOR ENHANCED METHOD
 Using this approach, I was able to reduce the run
time down to hours instead of days.
‒ Remember that this time can be brought down by
reducing the total number of nets being mapped or
running parallel jobs.
 Results:
BLOCK
RUN
SECONDS /
INSTANCES
Name
TIME (Hours)
PROCESSED INSTANCE
Mapped
Attempted
Percent Mapped
Attempted
Percent
LS
5.5
2.7
2424
7202
33%
3383
13436
25%
IC
1.6
2.1
729
2770
26%
925
5037
10%
DC
9.8
5.6
2026
6242
32%
2708
9831
27%
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PRIMITIVES
MAPPING COMBINATIONAL GATES TO RTL
APPLYING MAPPINGS OVERVIEW
 Using the mappings for:
‒ Annotating timing.
‒ Annotating rtl.
‒ Assisting with planning a manual errata fix.
‒ Guiding SAPR work by identifying nets to work on. For example,
placing a bounds on tag hit logic.
‒ Isolating smaller cones of logic for measuring power or some
other metric.
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MAPPING COMBINATIONAL GATES TO RTL
APPLYING MAPPINGS TO TIMING REPORTS
 Timing annotation of gate mappings:
‒ Custom gui script.
‒ Pop ups, listbox, notebooks, or your favorite tk objects.
‒ Inside of EDA tool.
‒ Using tcl wrapper to read and apply mappings and dump new formatted
timing report.
‒ Annotating instances with user properties.
‒ Adding annotation text to view window.
‒ Via text report.
‒ Detailed example on next slide.
‒ Especially useful to use unix raw text in order to color code comments.
‒ Parse existing timing report and use ANSI escape sequences to add color codes to
mapping annotation.
‒ Use command like ‘less –R’ to view file and see color codes.
‒ Search web for syntax of ANSI escape sequences and for color codes.
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MAPPING COMBINATIONAL GATES TO RTL
APPLYING MAPPINGS TO TEXT TIMING REPORTS USING UNIX RAW TEXT

The line after a mapped gate has a comment with the rtl code followed by the polarity ‘+’ or ‘-’, source file name, line number, and position.

The color of the logical operator is determined by whether the timing path is exercising the mapped logic or not.
‒ Green to indicate that the logic is active.
‒ Blue to indicate it is inactive.

Multiple primitives can map to the same gate and be active or inactive in the timing path.

If the net name was mapped as well, it will appear on the line after the rtl code.
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MAPPING COMBINATIONAL GATES TO RTL
APPLYING MAPPINGS TO RTL
 Rtl annotation is similar just done on the other side of the street.
‒ You can color your rtl code by slack or net arrival times.
‒ Create a searchable file of slack or net arrival times.
‒ Or create a gui with bindings to open popups with mapping and timing
information.
Late Arriving!
RTL:
Z = AB + CD + EF
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MAPPING COMBINATIONAL GATES TO RTL
APPLYING MAPPINGS TO GUIDE SAPR OR GAIN INSIGHT
 Mappings can be used to give SAPR tools guidance on how to constrain the
design.
‒ Critical signals such as tag hits can be identified and given preferential treatment.
‒ Routing early and with wide metal routes.
‒ Placement can be guided through bounds.
‒ Preferential timing weights can be assigned to the logic.
 The absence of mappings indicates when the SAPR tool is completely reworking
your rtl code. Restructuring the rtl should improve optimization.
 Power for portion of a timing cone can be reported by tracing from or to a
mapped point.
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MAPPING COMBINATIONAL GATES TO RTL
APPLYING MAPPINGS TO MANUAL ERRATA FIX
 Manual bug fixes are implemented when the design is desired
to have minimal changes in order to maintain the quality of
the design without slipping schedule or introducing extra risk.
‒ Rtl mappings to gates help pinpoint the logic that needs to be
changed.
‒ Errata fixes quite often only involve adding or replacing a qualifier
to an existing enable.
‒ Running synthesis to generate a patch file for the bug fix may touch
many gates leading to potential timing and electrical failures.
‒ Using combinational mappings allows the logic for the enable to be
identified quickly and a controlled manual edit to the design.
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MAPPING COMBINATIONAL GATES TO RTL
CONCLUSION
 Encounter® Conformal Equivalence Checker can be used to
map physical combinational gates to the matching rtl code.
‒ The mappings are precise down to the logical operator, not just
the rtl line number.
‒ Limiting the attempted mappings to a small list such as timing
critical cones keeps the run time to a couple of hours.
‒ Running this right after synthesis should allow place and route
steps access to the combinational mappings.
‒ Mappings can be created at any flow stage. All that is needed is
an Encounter® Conformal Equivalence Checker run.
 Combinational gate mappings between rtl and physical
design can help speed design closure.
‒ Timing paths can be understood without even opening a tool.
‒ Rtl writers have insight into timing of their rtl code.
‒ Physical design teams can communicate timing failures with
precise locations in the rtl code to the rtl team.
‒ Drastic reduction in the time to plan a manual errata fix.
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MAPPING COMBINATIONAL GATES TO RTL
REFERENCES
 Encounter® Conformal® Equivalence Checking Command Reference
‒ Conformal L, Conformal XL, and Conformal GXL
‒ Product Version 13.1
‒ November 2013
‒ Command reference section
‒ Tcl Command Entry Mode Support section
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MAPPING COMBINATIONAL GATES TO RTL
ACKNOWLEDGEMENTS
 I would like to thank my employer, AMD, for financially supporting this endeavor and providing the title
page art. I am also appreciative of their striving for excellences in computer design. I am grateful for
the AMD management which encouraged solutions above and beyond the norm. I would like to thank
Jim Dorsey, Mike Bates, and Shane Southard for allowing the time needed to develop innovative
solutions while working on a tight schedule.
 I would like to thank Shreyas Parnekar and Chakra Tallury for their tcl tutorials.
 I would like to thank Joshua Bell for improving the clarity of this paper as he served as technical advisor.
 I would like to thank my family for patience while I wrote this document.
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