IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 9, SEPTEMBER 2001
1929
Electric-Field-Related Reliability of AlGaAs/GaAs
Power HFETs: Bias Dependence and Correlation
With Breakdown
Domenico Dieci, Giovanna Sozzi, Roberto Menozzi, Erika Tediosi, Claudio Lanzieri, and
Claudio Canali, Member, IEEE
Abstract—This work shows experimental and simulated data
of hot electron degradation of power AlGaAs/GaAs HFETs with
different gate lengths and recess widths, and uses them to infer
general indications on the bias and geometry dependence of the
device high-field degradation, the meaningfulness of the breakdown voltage figure of merit from a reliability standpoint, and the
physical phenomena taking place in the devices during the stress
and leading to performance degradation. Possible formulations of
a voltage-acceleration law for lifetime extrapolation are also tested.
Index Terms—Electric breakdown, FETs, Gallium compounds,
hot carriers, microwave power FETs, reliability.
I. INTRODUCTION
P
OWER amplification at microwave frequencies is
presently a major industrial challenge, due to the exploding
number of amplifiers required for wireless telecommunications
portable units and base stations. Getting power outputs in the
range of Watts or tens of Watts at C, X, and Ku bands and above
with good efficiencies is a must for technologies competing in
this market, like GaAs MESFETs, GaAs-based Pseudomorphic
HEMTs (PHEMTs) and Heterostructure FETs (HFETs). In this
respect, AlGaAs/GaAs HFETs (where a relatively low-doping
AlGaAs Schottky layer is grown on top of a doped GaAs
channel) show promising features and a good cost/performance
tradeoff compared to power MESFETs and PHEMTs [1]–[3].
Another vital concern for product success is of course reliability. Unfortunately, enhancing the output current capability by
using large gate widths has the drawback that the FETs input
impedance gets too low and mismatch losses ensue. Consequently, the need arises to push the drain voltage as high as
possible, and due to hot electron and impact ionization and the
attending degradation mechanisms, the power and reliability
Manuscript received January 18, 2001; revised March 9, 2001. This work
was supported by Consiglio Nazionale delle Ricerche through P.F. MADESS II
and by Ministero dell’Università e della Ricerca Scientifica e Tecnologica. This
paper was presented in part at the 2000 IEEE International Reliability Physics
Symposium. The review of this paper was arranged by Editor G. Groeseneken.
D. Dieci was with the Dipartimento di Scienze dell’Ingegneria and INFM,
University of Modena and Reggio Emilia, Modena 41100, Italy. He is
now with Ferrari Gestione Sportiva, Maranello (MO) 41053, Italy (e-mail:
tediosi@dsi.unimo.it).
G. Sozzi and R. Menozzi are with the Dipartimento di Ingegneria dell’Informazione, University of Parma, Parma 43100, Italy.
E. Tediosi and C. Canali are with the Dipartimento di Scienze dell’Ingegneria
and INFM, University of Modena and Reggio Emilia, Modena 41100, Italy.
C. Lanzieri is with Alenia Marconi Systems, Roma 00131, Italy.
Publisher Item Identifier S 0018-9383(01)07331-2.
requisites end up conflicting with each other. Nevertheless, although a number of papers and quite a lot of industrial effort
have been dedicated to these high-field reliability issues, the
approaches followed by researchers and reliability engineers of
different companies and institutions are extremely diverse, and
a comprehensive picture is still lacking.
This work expands and deepens the preliminary report of [4]
and brings a novel contribution to this field by showing a wide
set of data obtained on power AlGaAs/GaAs HFETs with different gate lengths, and using them to infer general indications
on the bias point and geometry dependence of the hot-electron
degradation and the meaningfulness of the most popular indicator of device high-field robustness, namely, the breakdown
voltage, from a reliability point of view. An attempt is also
made at extracting field-acceleration laws for the device degradation, which, although extremely important for practical reliability evaluation, are not available yet in the open literature for
microwave compound semiconductor FETs. With the help of
numerical device simulations, we also investigate the degradation mechanism underlying the experimental stress results.
II. DEVICES AND EXPERIMENTS
The devices under test are Al Ga As/GaAs power
HFETs fabricated by Alenia Marconi Systems. They have a
200 m gate width and two different gate lengths: 0.25 m and
0.7 m. The two lots of HFETs share the same process up to
the deposition of 1 m-long Al/Ti gates in the deep 1 m-wide
recess. Then, the gate length is reduced, by selective lateral
dry etching of the Ti, down to 0.7 m for the long-gate HFET
wafer and to 0.25 m for the short-gate one. Consequently,
the nominal drain-gate (as well as the source-gate) distance
is 2.15 m for the 0.7 m devices and 2.375 m for the
mA/mm,
0.25 m ones. For short-gate devices,
mS/mm,
V, while long-gate ones feature
mA/mm,
mS/mm,
V. The
, measured
off-state drain-source breakdown voltages (
mA/mm) are about 17 V and 13 V, respectively,
at
while the corresponding drain-gate off-state breakdown volt) are 19–20 V (0.25 m) and 15–16 V (0.7 m).
ages (
At 10 GHz and 1-dB compression, the typical power density
and gain are 0.6 W/mm and 9.6 dB for the 0.25 m devices,
and 0.5 W/mm and 8.5 dB for the 0.7 m ones (these features
can be compared with those of the widely-used commercial
TriQuint 0.5 m HFET process, which yields at 10 GHz
0018–9383/01$10.00 © 2001 IEEE
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 9, SEPTEMBER 2001
(a)
Fig. 2. Output characteristics of a 0.7 m (solid lines) and a 0.25 m (dotted
lines) HFET. For both devices the maximum V
is 1 V and the V
step is
0.5 V. Constant I contours are drawn for the two samples at (left to right)
I = 0.1 mA/mm, 0.25 mA/mm, 0.5 mA/mm, and 1 mA/mm. The
values. Maximum power load lines assume a
vertical arrows mark the BV
safety limit of I = 0:1 mA/mm.
0
(b)
Fig. 1. Schematic cross section of (a) a short-gate (L
long-gate (L = 0:7 m) HFET.
= 0:25 m) and (b) a
0.6 W/mm output power and has
mA/mm,
mS/mm,
V, and a breakdown voltage
of 22 V [5]). The cross section of a 0.25 m device is sketched
in Fig. 1(a), while Fig. 1(b) shows that of a 0.7 m HFET.
Fig. 2 shows the output characteristics of both a 0.7 m and a
of the 0.25 m device is smaller than
0.25 m HFET. The
( 2 V versus
that of the 0.7 m one due to a less negative
2.7 V). Another possible contribution to this reduction may
be the surface-state charge on the source-gate and drain-gate access regions exposed by the gate dry etching process, which increases the access resistances (we measured an average of about
for the source/drain resistances in the 0.25 m devices,
7
). On the other
while for the 0.7 m ones
hand, a beneficial effect of the wider drain-gate separation is
is larger for the short-gate
that, as quoted above, the
HFETs (17 V versus 13 V), as marked by the two vertical arrows in Fig. 2.
Since the gate current is one of the main parameters characterizing the high-field regime [6], and both off-state [7] and
on-state [8] breakdown are defined fixing a threshold for ,
we also plotted in Fig. 2 the constant gate current contours
0.1 mA/mm, 0.25 mA/mm,
taken at (left to right)
0.5 mA/mm, 1 mA/mm. Provided that
can be taken as
an indicator of high-field reliability issues (a statement that will
be discussed in this paper), these contours represent boundaries
of increasingly dangerous regions for the HFETs and, once a
0
0
0
0
0
safety limit has been set for , a maximum power load line
should be drawn, as shown in Fig. 2, so that it lies entirely on
the left of the corresponding contour. Moreover, such a representation gives a single and visually effective picture of both
off-state and on-state breakdown.
In order to evaluate the differences between long-gate and
short-gate devices also in terms of hot-electron reliability, and to
and the drain-gate voltage (
,
study the influence of both
roughly proportional to the peak electric field between gate and
drain) on the degradation of the HFETs under test, we have
performed room temperature dc accelerated stress experiments
under several different bias conditions, as shown in Table I. The
and
values. In general, we
bias points feature different
and
values during the stress; as a result of defixed the
vice degradation (in particular, the effect known as breakdown
tends to increase somewhat during the stress,
walkout [9]),
values in Table I are those measured at the beginso the
constant throughout the stress,
ning of the stress. By keeping
we can assume that the impact ionization rate, and the electric
field that originates it, are roughly constant, too [6]. On the conbeen fixed, the breakdown walkout would have
trary, had
caused a progressive self-alleviation of the stress. It is finally
worth mentioning that we have restricted ourselves to a region
is low enough for self-heating to
of the output plane where
be ruled out as a possible cause of device degradation. This by
no means limits the validity of our conclusions, since, during
device operation, high-field conditions are encountered in the
low- region of the RF sweep (see for instance the load lines
of Fig. 2).
III. STRESS RESULTS AND ACCELERATION LAWS
A. Measured Device Degradation
Figs. 3 and 4 show the variation of the open-channel drain
, measured at
V,
V) during
current (
the hot-electron stress for the different bias conditions and for
the long-gate and short-gate HFETs, respectively. While the
DIECI et al.: ELECTRIC-FIELD-RELATED RELIABILITY OF AlGaAs/GaAs POWER HFETs
1931
TABLE I
HFET STRESS BIAS CONDITIONS
Fig. 3. I
degradation of 0.7 m HFETs stressed as mapped in Table I.
is measured at V
0 V, V
= 2 V.
I
=
former show very little degradation, the latter degrade significantly under the bias conditions considered. For the 0.25 m devices, the degradation approximately follows a square-law time
dependence, as indicated by the reference lines in Fig. 4 (this
time dependence will be discussed later on). Similar trends are
observed for the transconductance degradation of the 0.25 m
and the
are tightly correlated
HFETs, and both the
with an increase of the drain access resistance ( ), as measured using an end resistance technique [10] (i.e., for each single
,
and
are about the
device,
same). In the case of the 0.25 m HFETs, a remarkable breakincreasing by 2–6 V for
down walkout exists, too, with
the different devices (see of [4, Fig. 6]).
The first important point to make is that the larger breakdown
voltage of the 0.25 m HFETs does not imply improved hot
electron reliability. On the contrary, short-gate devices stressed
as the long-gate ones show a much
with the same values of
larger degradation, as well as a dramatic bias point dependence
reduction. Therefore, it is obvious that the inforof the
mation on the breakdown voltage (either off-state or on-state)
is not helpful when it comes to defining a safe operating area.
More than this, a reverse correlation exists between the breakdown voltage and the hot-electron reliability, as recently shown
for InP HEMTs [11].
Second, when the device works in a critical region, such as the
0.25 m HFETs at the stress points of Table I, the degradation
varies dramatically with bias (Fig. 4), even though the bias conditions are quite close to one another in the output plane. This
I
degradation of 0.25 m HFETs stressed as mapped in Table I.
is measured at V
= 0 V, V
= 2 V. Square-law reference lines are
also drawn.
Fig. 4.
I
points out to the need of a thorough bias-dependent assessment
of the possible hot electron degradation effects.
and
(which are
As far as the relative influences of
not independent of one another) are concerned, the data of Fig. 4
(together with consideration of the bias values of Table I) indivalues lead to
cate that both factors play a role: while larger
(and
) degradation, it is also true that for
more severe
is
the same value of , off-state stress conditions, where
larger, damage the HFETs more severely than on-state ones.
B. Field-Acceleration Laws
From a practical standpoint, accelerated stress results need to
be correlated with the device operating conditions for lifetime
extrapolations. While field-acceleration laws are widely used
for Si MOSFETs, no indications can be found in the open literature for compound semiconductor and heterostructure devices
for microwave applications. In this section we explore three possibilities for lifetime extrapolation.
In order to extract a mathematical relationship linking the
and
, we established a failure
HFET degradation with
% and extracted, for each decriterion at
vice, the corresponding failure time ( ). The set of failure time
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 9, SEPTEMBER 2001
points (see Table I) can be interpolated by the following function:
(1)
h (mA/mm)
V ,
V.
where
A physical meaning can be attributed to (1) by making some
very basic assumptions and simplifications.
1) The degradation is proportional to the energy the carriers
acquire between gate and drain, i.e.,
, where
is a threshold energy for device
damage.
electric field
.
2)
is also proportional to the number of hot
3)
carriers which are responsible for the damage; therefore,
assuming that the reverse gate current is a linear indicator
.
of that [6],
4) The degradation is proportional to the square of the stress
time (this is true for the data of Fig. 4, at least in the central
part of the stress).
The hypotheses 2) and 4) are supported and explained by numerical simulation results, as will be described in the next section.
From 1)–4) follows (1).
The fit is good, as shown in Fig. 5, and indicates a sort of
acceleration. Equation (1) is useful in
threshold-activated
that it allows to indicate for our 0.25 m HFETs a conserva(
), in the proximity of which
tive safety limit for
the failure time soars to infinity and the device behaves reliably.
are to be considered technologyThe parameters and
and geometry-dependent, and should be extracted for a particular device lot through accelerated stressing. It is worth pointing
out that a threshold behavior for the high-field degradation was
observed by other groups [12], [13].
As stated above, field-acceleration laws have been routinely
used for digital Si MOSFETs for many years. We then tried to
check whether two of the simplest and most widely accepted
MOSFET laws could be used in our case.
and the peak
Based on the linear dependence between
drain-gate field, a voltage-acceleration law can be written as
[14]
(2)
The fit of our data with (2) yields the results of Fig. 6 (
h,
V). Although most of the data points can
be reasonably interpolated, the highest- ones clearly lie far
from the predicted behavior, again indicating a threshold voltage
(hence a threshold energy) for device degradation.
Another popular MOSFET acceleration law links the degradation and the failure time to the impact ionization ratio, which
ratio [15]
in Schottky-gate FETs is proportional to the
(3)
The fit of our data given by (3) is shown in Fig. 7 (
h mA/mm,
). In this case the whole data set (including
the low-stress points) matches well with the fit, pointing out to
1
= 020
Fig. 5. Experimental (points) failure times ( I
=I
%)
multiplied by the square root of the stress gate current, versus the stress
drain-gate voltage, for the 0.25 m HFETs. The interpolation given by (1) is
also shown (line).
1
Fig. 6. Experimental (points) failure times ( I
=I
the inverse of the stress drain-gate voltage, for the 0.25
interpolation given by (2) is also shown (line).
= 020%) versus
m
HFETs. The
the importance of impact ionization in the device degradation.
This could also indicate that, as happens in MOSFETs, holes
play a pivotal role in the hot-carrier degradation. It has to be
noted, however, that although (3) models the experimental behavior well, it is of little practical use for our devices. While
in digital circuits the on-state current values are typically welland
known, for analog applications it is very hard to link the
values used for the dc stress with those instantaneously attained during the RF sweep. Thus, even though (3) can indicate
which bias conditions lead to a satisfactory dc lifetime, a correlation with RF conditions is very difficult to achieve.
In conclusion, our preliminary investigation of field-acceleration laws indicates the importance of impact ionization in the
degradation process, and the existence of a voltage threshold
for device degradation. The future work will have to focus on
how design and process choices influence the position of this
threshold.
IV. DISCUSSION AND NUMERICAL SIMULATIONS
As an aid for the physical interpretation of the experimental
results, we have performed numerical simulations using a
two-dimensional (2-D) drift-diffusion commercial tool [16].
Since the nonmonotonic drift-velocity versus field relationship
DIECI et al.: ELECTRIC-FIELD-RELATED RELIABILITY OF AlGaAs/GaAs POWER HFETs
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1933
= 020
Fig. 7. Experimental (points) failure times ( I
=I
%)
multiplied by the stress drain current, versus the gate current over drain current
ratio, for the 0.25 m HFETs. The interpolation given by (3) is also shown
(line).
of GaAs hindered the numerical convergence, we adopted a
monotonic Silicon-like dependence instead. A fixed negative
cm was placed at the
surface charge density of
semiconductor–SiN interface on both sides of the gate recess
in order to account for surface damage (e.g., due to the gate
dry-etching process). A view of the simulated 0.25 m HFET
cross section is given in Fig. 8.
A. Breakdown Voltage
As briefly mentioned above, the difference between the
breakdown voltages measured on the long-gate and short-gate
devices are due to the different recess widths. In particular,
in the short-gate HFETs, the lateral dry etch of the Ti layer
exposes a wider AlGaAs area on the gate sides. Consequently,
the gate edge and the high-doping GaAs cap on the drain
side are further apart compared with the long-gate devices.
Moreover, the surface states localized in this area lower the
surface potential, thereby increasing the depletion. A lower
surface potential flattens out the longitudinal electric field
profile between gate and drain [17], [9] and results in larger
off-state and on-state breakdown voltages in the short-gate
devices.
The numerical simulations support this explanation. Fig. 9
V,
shows the horizontal electric field profile (at
V) in the channel of both a long-gate and a short-gate
HFET. The peak field is significantly lower in the latter, due
to the wider (and negatively charged) recess surface between
gate and drain. This implies enhanced breakdown voltage for
the 0.25 m HFET, as was experimentally observed.
B. Hot-Electron Reliability
It is generally accepted that the main degradation mechanism
triggered by high-field conditions in compound semiconductor
FETs is the creation of traps at the semiconductor–passivation
interface over the gate-drain access region [18]–[25]. Electrons are then captured by these centers, which lowers the
surface potential, increases the drain access resistance and,
degradation and gain compression
consequently, leads to
strictly correlated with the
(power slump). An increase of
and
degradation was indeed measured on our samples
Fig. 8.
Simulated 0.25 m HFET cross section (dimensions in m).
Fig. 9. Simulated horizontal electric field profile in the GaAs channel of both
a long-gate and a short-gate HFET (“before stress” conditions).
(see Table I, where relative changes of
corresponding
degradation are shown in the last column).
to 20%
Moreover, the enhanced surface state density on the gate side
frequency dispersion measurements (an
is confirmed by
example of which is given in Fig. 10 of [4]; see also Fig. 7 of
[25] for different but related results). A remarkable increase of
dispersion is observed after the stress, which
the negative
is a signature of enhanced surface state density on the gate
side [17]. A temperature-dependent analysis carried out on the
HFETs under test allowed to attribute these traps an activation
energy of 0.3–0.4 eV.
In order to validate this surface charge hypothesis (SCH) on
the device degradation, we compared the results of the simulation of standard (i.e., “before stress”) devices with those of
the same HFETs where the negative surface charge density was
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 9, SEPTEMBER 2001
(a)
(a)
(b)
Fig. 10. Output characteristics of a 0.25 m HFET before and after the stress.
(a) Measurements. (b) Simulations.
raised to
cm between gate and drain (“after stress”
simulations). The simulation results for a 0.25 m HFET are
shown and compared with measured ones in Figs. 10 and 11.
The agreement between measurements and simulations indicates that the SCH can account for the experimental stress results. It is also worth mentioning that the simulated stress does
not produce any significant degradation on the 0.7 m HFET
characteristics.
The measured breakdown walkout is also reflected in the simulations. A 20% reduction of the peak field observed in the
post-stress simulation (not shown here) is consistent with the
experimental breakdown walkout.
Finally, the simulations also support and explain some of the
assumptions made in the discussion of (1). In particular, the
simulated peak electric field (both the longitudinal field in the
channel and the gate-edge field at the device surface) turns out
to be, under the bias conditions considered for the stress, very
, as hypothesis ii) holds. See for inlinearly-dependent on
stance Fig. 12, where we plot the simulated peak channel lonfor different
values.
gitudinal field as a function of
As far as the square-law time dependence of the degradation of
hypothesis iv) is concerned, the simulations show that, down to
degradation, there is a quadratic dependence
about 50%
between the drain current change and the negative charge stored
between gate and drain, as illustrated by Fig. 13. If a simple
linear time dependence of the charge storage is then assumed,
(b)
Fig. 11.
V
Transconductance versus gate-source voltage of a 0.25 m HFET at
= 4 V, before and after the stress. (a) Measurements. (b) Simulations.
the observed proportionality of
to the square of stress
time is explained.
In conclusion, our simulations indicate that the SCH can
consistently explain all the stress effects that were experimentally observed. However, as far as a direct comparison between
measurements and simulations is concerned, some caution is
in order, due to the limitations of the drift-diffusion model
and the simplicity of the simulated degradation mechanism.
In particular, a uniform charge distribution over the whole
AlGaAs–SiN interface between gate and drain has been used
in our simulations, which certainly represent a simplification
with respect to physical reality. Another simplification required
by numerical convergence is the use of fixed charge, while
probably a combination of fixed charge and surface states
would be more realistic. Finally, a small threshold voltage shift
appearing in the post-stress measurements, and possibly due to
some charge trapping under the gate [26], was neglected in the
simulations, since we wanted to focus on the main degradation
mechanism. These considerations help explaining the discrepancy between the measured and simulated results. However,
insofar as we aimed at supporting the SCH with simulations that
could replicate the basic features of the observed degradation,
without playing with too many parameters in search of the best
fit with the measurements, the results are satisfactory.
It is also worth pointing out that our experimental results are
consistent with those of several published reports dealing with
DIECI et al.: ELECTRIC-FIELD-RELATED RELIABILITY OF AlGaAs/GaAs POWER HFETs
1935
Once more, the SCH outlined above is able to give an explanation to the observed behavior. As we said before, the reason
why the breakdown voltage is larger in the short-gate HFETs
is the wider exposed AlGaAs surface between gate and drain.
On the other hand, this same surface region is the origin of the
hot-electron degradation according to the SCH, since electron
storage between the AlGaAs and the SiN between gate and drain
increases the drain resistance and lowers
and
(and
leads to breakdown walkout). This explanation is also consistent with the data of [11], where InP HEMTs with different gate
recess widths (obtained by varying the duration of the selective
wet-etch of the cap layer) showed breakdown voltages linearly
increasing with the etch time (i.e., with the recess width) but at
the same time also a growing hot-electron degradation.
Fig. 12. Simulated peak longitudinal electric field in the channel versus the
drain-gate voltage, for different values of the gate bias.
Fig. 13. Simulated drain current degradation (dots) versus the increase of the
negative charge density at the AlGaAs–SiN interface between gate and drain. A
square-law fit is also shown (solid line).
different technologies and processes. See for instance refs. [27],
[12], [13], [28] for recent high-field reliability investigations
of GaAs power technologies (mostly PHEMTs) showing power
slump and invoking trap creation and electron capture between
gate and drain to explain it. If one considers that MESFETs [18],
[19] and InP HEMTs [23], [24] were also shown to be prone to
this degradation mechanism, it can be concluded that the basic
features of the degradation described here have a very general
nature, although qualitative differences obviously exist due to
different device technology, design and process features.
V. CONCLUSIONS
In summary, the main results of this work can be summarized
as follows.
1) By comparing HFETs with different gate lengths, we
have observed a clear reverse correlation between the
breakdown voltage (both off-state and on-state) and the
hot-electron reliability. This finding diverges from conventional wisdom, but can be explained by the Surface
Charge Hypothesis for hot-electron degradation. We
believe this represents a very significant addition to the
knowledge of high-field-related reliability issues.
2) When a HFET is biased under high-field conditions that
degrade its characteristics, a strong bias dependence
of the degradation exists, pointing out to the need of
a careful bias-dependent reliability evaluation. The
experimental failure times were linked to the corresponding stress bias conditions using a simple equation
that indicates a rather sharp voltage-threshold behavior
for the device degradation. Together with failure-time
fits using classical MOSFET models, this represents a
first-time attempt at extracting a voltage-acceleration law
for microwave FETs.
3) Numerical simulations have shown that the Surface
Charge Hypothesis, whereby it is assumed that, during
the hot-electron stress, interface traps are created (possibly by hot holes generated by impact ionization), and
electrons are captured, at the semiconductor–SiN interface over the drain-gate access region, can consistently
account for all the effects of the stress that were experimentally observed, as well as for the different behavior
of the long-gate and short-gate HFETs.
C. Correlation Between Reliability and Breakdown
One of the main achievements of our investigation lies in
the observation that the low-breakdown, long-gate HFETs show
a better hot-electron reliability than the high-breakdown, short
gate ones, when stressed at the same levels of gate reverse current. Since the breakdown voltage is universally defined at a
fixed , were it an indicator of hot-electron robustness, as it
is generally considered, the same reverse gate current levels
should damage the 0.7 m HFETs more than the 0.25 m ones.
Instead, our experiments give the opposite result, in agreement
with recently published data obtained on InP HEMTs [11].
ACKNOWLEDGMENT
The authors would like to thank Dr. E. Zanoni and Dr. G.
Meneghesso (University of Padova, Padova, Italy) for the temperature-dependent frequency dispersion measurements.
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Domenico Dieci was born in Reggio Emilia, Italy, in
1968. He received the Laurea degree in electronic engineering from the University of Parma, Parma, Italy,
in 1995.
In 1997, he worked for one year at the R&D
Department, Siemens AG, Munich, Germany, on the
reliability issues of power transistors of engineering
science, University of Modena, Modena, Italy,
in 2001. His major research interests are in the
field of reliability revaluation of III–V compound
semiconductor devices.
Giovanna Sozzi received the Laurea degree
(with honors) in electronic engineering from the
University of Parma, Parma, Italy, in 1997 where
she is currently pursuing the Ph.D. degree in the
Department of Information Technology.
During 1998, she was with FIAT, Torino, Italy. Her
main research interest is in the numerical simulation
of semiconductor devices, with special emphasis
on compound semiconductor and heterostructure
devices such as MESFETs, HEMTs, and HFETs.
Roberto Menozzi was born in Genova, Italy, in 1963.
He received the Laurea degree (with honors) in electronic engineering from the University of Bologna,
Bologna, Italy, in 1987 and the Ph.D. degree in information technology from the University of Parma,
Parma, Italy, in 1994.
After serving in the army, he joined a research
group at the Department of Electronics, University
of Bologna. Since 1990, he has been with the
Department of Information Technology, University
of Parma, where he became Research Associate in
1993 and Associate Professor in 1998. His research activities have covered the
study of latch-up in CMOS circuits, IC testing, power diode physics, modeling
and characterization, and the dc, rf, and noise characterization, modeling, and
reliability evaluation of compound semiconductor and heterostructure electron
devices such as MESFETs, HEMTs, HFETs, and HBTs.
Erika Tediosi was born in Modena, Italy, in 1976.
She received the Laurea degree (with honors)
in electronic engineering from the University of
Modena and Reggio Emila, Modena, in 2000.
Since 2000, she has been with the Department
of Engineering Science, University of Modena. Her
major research interests are in the field of reliability
evaluation and in the numerical simulation of III–V
compound semiconductor devices.
DIECI et al.: ELECTRIC-FIELD-RELATED RELIABILITY OF AlGaAs/GaAs POWER HFETs
Claudio Lanzieri was born in Rome, Italy, in 1959.
He received the degree in physics from the University
of Rome, Rome, Italy, in 1985.
In 1985, he joined Alenia Research Laboratories,
Rome, where he is responsible for GaAs integrated
circuits production. He has co-authored more than 50
technical papers in international journals, mainly in
the fields of semiconductor materials and device fabrication.
1937
Claudio Canali (M’71) was born in Reggio Emilia,
Italy, in 1945. He received the Laurea degree in
physics from the University of Bologna, Bologna,
Italy in 1968.
In 1969, he joined the Physics Institute of Modena
as a Research Assistant and in 1971 as Assistant
Professor. In 1974 and 1975, he was a Visiting
Researcher at the California Institute of Technology,
Pasadena. From 1980 to 1983, he was with Dipartimento di Elettronica ed Elettrotecnica, University
of Bari, Italy, as a Full Professor of electronic
components. From 1984 to 1991, he was Professor of applied electronics at
the Dipartimento di Elettronica ed Informatica, University of Padova, Italy.
From 1985 to 1989, he was a Director of Microelectronics Division, TECNOPOLIS-CSTAS, Bari, Italy, a division devoted to testing and failure analysis of
electronic components and integrated circuits. Since 1991, he has been with the
University of Modena as a Full Professor of applied electronics. His research
interests and activities cover high field transport properties in semiconductor
materials, solar energy conversion, thin-film interaction, silicides, solid-phase
epitaxial growth, solid state transducers, nuclear detectors, electronic device
characterization, reliability, failure mechanisms, and hot electron effects in Si
and III–V based devices. He has authored or co-authored several book chapters,
more than one hundred technical papers in international journals, and more
than one hundred conference papers in the above mentioned fields.
Dr. Canali is a member of AEI. He has been a member of the Technical Program Committees of several international conferences.