Towards an Automatic Generation of Diagno stic In­
Field SB S T for Processor Components
Mario Scholzel, Tobias Koal, Stephanie ROder, Heinrich Theodor Vierhaus
Computer Engineering Group
Brandenburg University of Technology
Cottbus, Germany
{mas I tkoal l htv} @informatik.tu-cottbus.de
Abstract
-
This paper deals with a diagnostic software-based
self-test program for m u ltiplexer based components in a proces­
sor. These are in particular the read ports of a m u lti-ported
register file and the bypass structures of an instruction pip eline.
Based on the d etailed analysis of both m u ltiplexer structures,
first a manually coded diagnostic test program is presented. This
test program can detect all single and m u ltiple stuck-at data- and
address faults in a m u ltiplexer structure. But it does not fully
cover the control-logic of the bypass. By further refinements a
100%
fault coverage for single stuck-at faults, including the
control logic, is finally obtained. Based on these results, an
ATPG-assisted m ethod for the generation of such a diagnostic
test program is described for arbitrary processor components.
This m ethod is finally applied to the m u ltiplexer structures for
which the manually coded test program is available. The test
length and test coverage of the generated test program and of the
hand-coded test program are compared.
I.
INTRODUCTION
Beside power, area, and performance constrains, reliability
becomes a more and more important issue for the design of
embedded systems. Due to a reduced feature size (28 nm and
beyond), hardware is exposed to higher stress conditions dur­
ing operations [ 1 8] and deviations of device- and circuit pa­
rameters in the production process [3 , 25] . Due to these facts,
permanent faults will occur faster and more frequently during
the lifetime of highly integrated devices, which will result in
more early-life failures and wear-out effects. Therefore, future
reliable processors should be able to cope with permanent
faults in the field; e.g. by some kind of self-reconfiguration.
Several approaches for such a self-reconfiguration have been
published. In [ 1 4] permanent faults are handled by executing a
program that does not use the defect components of the proces­
sor. Various versions of the program are computed in advance
and stored on-chip. In [ 1 7] various program transformations
are proposed, in order to adapt the program in-the-field. In [22]
a more regular scheme is presented that allows to adapt the
executed program in-the-field to the current fault state of the
processor. However, in these approaches a diagnostic test
method, which allows for localizing the defect component in
the processor, is not included. A hardware-based reconfigura­
tion scheme together with a software-based self-test is present­
ed in [ 1 5 ] . In [9] a hardware based self-test and reconfiguration
scheme is presented. In both approaches the granularity of the
self-test and self-repair is at the granularity level of functional
units. In [23 ] the granularity of a software-based self-repair is
lowered down to simple 2: I -multiplexer structures. A software-
based self-test for this level of granularity has been presented
in [24] . The paper at hand presents a refinement of the manual­
ly developed diagnostic test program in [24] for the read-ports
and bypasses. By the refinements, faults in the control logic of
the bypass are covered, and the fault coverage for the bypass is
improved to 1 00% . The main contribution of the paper is the
well-structured ATPG-assisted method for generating the diag­
nostic test program, and a comparison between the manually
developed test program and the test program generated with
A TPG support.
II.
RELATED WORK
The diagnostic self-test presented in this paper will work
in-the-field, but off-line. I.e., the processor is able to detect a
permanent fault autonomously, but not during normal opera­
tion. Rather the test is performed during the start-up of the
processor or in idle-times . The diagnostic results of such a test
can be used by a self-repair routine, which is embedded into
the processor for re-configuration purposes. Two maj or strate­
gies exist for such an in-field off-line-test. First, a scan-based
built-in self-test (BIST) may be employed. This type of test
uses the scan-test infrastructure in the processor [2 1 ] . Test
responses are compacted on-chip for reducing the memory
consumption, e.g. by MISR structures. But fault localization
for diagnostic purposes is usually done off-chip, because diag­
nostic BIST is used for the post-production analysis of defects.
I.e., determining the scan chain and the scan cell containing the
faulty test response is usually done off-chip. Potentially a de­
vice with BIST can execute a self-test in the field. Unfortunate­
ly, the localization of a fault, based on a single MISR signature,
is a problem due to the strong compaction of the test responses.
Therefore BIST-approaches that produce more than a single
signature have been developed [8] . Moreover, in [26] the local­
ization of the scan chain containing the faulty test response is
done on-chip by repeating the test several times . In [ 1 0, 12]
also multiple signatures are generated, and faulty signatures
can be saved on-chip. This supports an off-chip diagnosis that
determines faults in the net list based on faulty signatures.
Thus, all of these techniques still rely on powerful off-chip
analysis techniques. Moreover, typically scan-test and diagno­
sis works on flat gate level net lists that do not know processor
components at functional level. Mapping a fault in the net list
on processor components is not in the scope of these works .
A second maj or strategy for detecting permanent faults in­
the-field is a software-based self-test (SB ST). This is basically
978-1-4799-0597-3/13/$31.00 ©2013 IEEE
a functional approach, because the inputs of processor compo­
nents are stimulated by executing a test program, and the cor­
rect functional behavior is observed at their outputs [20, 27] .
According to [20] , the methods to generate this kind of func­
tional test can be divided into functional and structural ones.
Functional generation methods can be purely random or feed­
back based. A pure random based method is described in [ 1 9] .
There the test program i s generated by a kernel on-chip. The
kernel produces executable test programs. In [ 1 1 ] a method
called "IlGP" is presented, which uses feedback information
from fault simulation to reduce the test program size of the
randomly generated instructions in order to improve the effi­
ciency of the SBST. Structural methods for generating test
programs rely on the knowledge of gate-level or RTL descrip­
tions. The benefit of all those methods is the availability of a
structural-fault coverage and the possibility to shift the process
of pattern generation for complex logic functions into an
A TPG tool to receive deterministic test pattern that can be
mapped to a specific instruction sequence [4] . A module-based
test program generation is presented in [7] . Extensions of a
SBST to a diagnostic SBST are presented in [ 1 , 2, 6] . The
diagnostic capability has been developed for production test.
The test programs generate a signature that is analyzed off­
chip, for example with dictionary based-methods. Thus, for in­
field diagnosis, these approaches suffer from the same problem
as diagnostic scan-based approaches. In [ 1 3 ] a SBST for single
stuck-at faults in multiplexer structures of a processor has been
proposed. And in [ 1 6] minimal test sets for single stuck at
faults in multiplexer structures have been proposed. The meth­
od in the paper at hand is for detection of multiple faults in
multiplexer structures. Obviously a SBST is very well suited
for an in-field-test. However, very often this type of test is used
as a low-cost post-production test for improving the fault cov­
erage. Therefore, the goal in almost all publications about
SBST is to achieve high fault coverage with short test pro­
grams. This results in a low diagnostic resolution, because as
much faults as possible should be covered by applying a single
test pattern. In turn, this means that various faults can be the
reason for a failing test pattern, and a location of the fault is not
uniquely possible. This paper moves away from this paradigm,
because the diagnostic software-based self-test is explicitly
developed for in-field-diagnosis. The diagnostic capability
requires distinguishing between various fault situations. At
least this is achieved by an increased number of test patterns.
III.
contains 1 6 -bit registers, then the read port is composed of 1 6
identical instances o f a multiplexer tree (mux-tree). Thereby
data input k of mux-tree i is connected to bit i of register k.
Each mux-tree receives the same control signal r. Therefore all
mux-trees select their data input from the same register r. From
a functional point of view, the read-port in the given example
has 64 1 6-bit data inputs rO, . . . ,r63, a 6-bit select signal r, and a
single 1 6-bit data output. A software-based self-test of the read
port is done by initializing the registers rO, . . . ,r63 with appro­
priate values, applying a value to r and capturing the response
at the data output.
M u ltiplexer
Tree D
Figure 1
Read -Port Structure.
B. Multiplexer Structures in the Bypass
The bypass of a processor core has a very similar structure
to the read port. It is used for forwarding values in pipe lined
processors. For example, suppose a superscalar processor ar­
chitecture with a 4-stage instruction pipeline (fetch, decode,
execute, write-back) and four execution units. I.e., four results
are computed simultaneously in the execution stage, and four
results are present at the same time in the write-back stage.
These eight values are stored in pipeline registers. We will
name these registers as exO, . . . ,ex3 and wbO, . . . ,wb3. The by­
pass is now a multiplexer structure as it is shown in figure 2.
read­
port
exO ex1
ex2 ex3
wbO wb1
wb2 wb3
THE DIAGNOSTIC TEST
The diagnostic test in this paper is a refinement of the soft­
ware-based self-test programs presented in [24] . The test is
used in [24] for diagnostic purposes of a VLIW processor with
4 issue slots. The register file is built up from standard cells, so
the read-ports are multiplxer-based. The test programs apply
test patterns at the inputs of the read-ports of the mUlti-ported
register file and at the inputs of the bypasses. The next section
briefly describes these components.
A. Multiplexer Structures in the Read-Ports
The structure of a multiplexer-based read port of a multi­
ported register file with 64 registers is shown in figure 1 . The
read port is used to read the value of a selected register. The
register is selected by the control signal r. If the register file
L...-�-r- Ds,-wbO
L...-�- Ds'-wb3
Figure 2
Bypass Structure.
It has 9 1 6 -bit data inputs, a single data output, and a 4-bit
control signal. This control signal is used to select either the
input from the read port (no forwarding) or from one of the
pipeline registers (forwarding). The control signal is generated
by an encoder, and the input signals for the encoder are gener­
ated by compare-components (cmp). Each cmp compares the
number of a destination register from the write-back- or exe­
cute-stage with the used source register number in the decode
C.
RPO, . . . ,RP63 : The FRC RPx represents all faults that
will have the effect that register x is not read properly
through the read port.
•
BPF : This FRC represents all faults that will have the
effect that a required forwarding in a bypass does not
work properly. I.e., one of the inputs Dst_exO, . . . ,
Dst_wb3 in figure 2 has the same value as Src_de, but
the forwarding of the corresponding value is not done
correctly.
•
BPNF : This FRC represents all faults that will have the
effect that forwarding takes place in a bypass although
a forward is not needed. I.e., none of the inputs
Dst_exO, . . . , Dst_wb3 in figure 2 has the same value as
Src_de, but nevertheless one of the data inputs
exO, . . . ,wb3 is selected by the bypass.
Please note that the classification of faults into FRCs does
not change the faults covered by the test. But it changes the
granularity of the diagnosis, because all faults belonging to a
single FRC are mapped to the same functional misbehavior.
•
IV.
THE MANUALLY GENERATED TEST PROGRAM
The test programs for the read-port- and bypass-structures
in figure 1 and figure 2 have been developed manually with
respect to the FRCs given above. Based on the functional mis­
behavior specified by the FRC, the faults belonging to a certain
FRC are determined by a manual analysis of the gate list of the
considered component. Then the test patterns are derived for
exercising the faults. In existing approaches for software-based
diagnosis [ 1 , 6] this is done the other way around. First, the test
patterns are determined, and then the faults that cannot be sepa­
rated by these test patterns are grouped together. Table I shows
all test patterns that are used for a read port test. A single test
pattern defmes all inputs of the read-port.
r
No. of Test Pattern
rO
0
1
2
3
4
...
64
65
66
67
ClassifYing Faults/or Diagnsotic Purposes
The quality of a functional diagnostic test depends on two
issues. First, it should achieve high fault coverage. In order to
evaluate fault coverage, a fault model is needed, that deter­
mines all possible faults within a component. Second, detected
faults must be distinguished according to the functional misbe­
havior they produce. The link between the fault model and the
produced functional misbehavior is made by fault-repair­
classes (FRCs). The set of FRCs is defined from a functional
point of view and depends strongly on the capabilities of the
self-repair approach. I.e., a FRC represents a functional misbe­
havior that can be handled by a certain self-repair mechanism.
Therefore it is important to group together all detectable faults
that can produce this misbehavior. A FRC contains all faults
(according to the fault model) that will produce the correspond­
ing functional misbehavior. The following FRCs were defmed
for the read port and bypass structures shown in figure 1 and
figure 2. Thereby we have taken into account the features of
the software-based self-repair routine from [23 ] :
TEST PATTERNS FOR THE READ PORT
TABLE I.
stage. The valid-flag of each pipeline register is neglected in
the figure. Encoder and cmp-components can be considered as
the control logic of the bypass. The bypass is tested by apply­
ing appropriate test patterns at the inputs exO, . . . ,ex3, wbO, . . . ,
wb3, read-port, Src_dex, Dst_exO, . . . ,Dst_wb3. This is done by
filling up the pipeline with appropriate instructions.
0
0
0
0
1
2
3
0
0
0
0
r2
1
2
0
0
-I
0
0
0
0
-I
62
63
0
0
0
0
0
0
0
r62 r63
...
0
0
0
0
0
-I
0
0
63
127
128
rl
0
0
0
0
...
...
0
0
0
0
...
0
0
0
0
0
0
0
0
...
...
...
-1
...
...
0
-I
0
From the table it follows that the full test o f a single read
port requires 128 test patterns. Test patterns 1 to 64 are used for
a stuck-at 1 test. All data inputs are 0 (rO, . . . ,r63) and each
register is selected once by r. If there is a SA 1 that propagates
to the output of the read-port, then it will be detected. Test
patterns 65 to 128 are used for testing for address and stuck-at­
o faults. Each test pattern applies a - 1 at this data input that is
selected by r. If this - 1 is not observed at the data output, then
there is either an address fault or a SAO fault in the data path. A
detailed motivation for these test patterns can be found in [24].
Applying the specified 128 test patterns to the read port re­
quires a test program with 640 instructions.
The organization of the bypass test is very similar to the or­
ganization of the read-port test. In [24] the inputs of the bypass
are set to the test patterns shown in table II by an appropriate
instruction sequence. A "-" in colurrms Dst_exO, . . . ,Dst_wb3
means that the value of the corresponding pipeline register is
not valid. Test patterns 1 to 1 6 check for stuck-at- l faults. The
test patterns are applied in two phases. The fust phase ( 1 -8)
uses register 0 as source register in the decode stage (src_de
0). The second phase (9- 1 6) uses register 63 as source register
in the decode stage. Thereby each test pattern sets all data in­
puts of the bypass to 0, and all inputs of a single cmp­
component either to 0 or 1 . By this it is checked that the for­
warding works and no stuck-at- l fault occurs in the data-path
of the multiplexer. The stuck-at-O test is done in two phases
again ( 1 7-32). But each test pattern holds exactly the selected
data input of the bypass at -1 while all other data inputs are O .
=
TABLE Il.
TEST PATTERNS FOR THE BYPASS
Dst
data inputs
N
o read
ex( exl ex2 ex3 !wbO wb l wb2 wb3�x( exl ex2 ex3 wb( wb l wb wb3 src_de
• port
1 0 0 0 0 0 0 0 0 0 0 - - - - - - 0
0
� 0 0 0 0 0 0 0 0 0 - 0 - - - - - -
0
fi 0
]( 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
- - 63 - - 63 -
H 0
1 0
H 0
0
-I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-I
0
0
0
-1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
��
�5
�('
�2
-1
-
-
-
-
-
-
-
-
-
- - 0 63 - 0 - 63 -
-
-
-
-
-1
-
-
-
-
-
-
0
-1
-
-
-
0
-
63
0
-
63
...
0
63
63
...
63
0
0
...
0
63
63
...
63
From table II it follows that 32 test patterns are needed for
the bypass test. The assembler implementation of the test rou­
tine takes 88 instructions (the assembler code can be found in
[24]). In order to determine the fault coverage results shown in
table III, we have used the gate list of a pipelined VLIW pro­
cessor. Using this gate list, the test programs were simulated on
the processor in multiple runs. The read ports and the bypass
were built up from simple gates and 2: I -multiplexers in the
used gate list. Using the stuck-at fault model, we could there­
fore define all possible faults at gate level. The read port has
566 faults, and the bypass has 140 1 faults. The faults were
related manually to the FRCs. In a fust test cycle a fault simu­
lation was done for each possible single-stuck-at fault in the
bypass and read port. In each test run of the cycle a single fault
was inj ected in the gate list and then the test program was sim­
ulated on the processor model containing the fault. For the read
port a fault coverage of 1 00% was obtained using the test pat­
terns shown in table I. For the bypass a fault-coverage of
9 1 . 0% was obtained. A maj or limitation of the bypass test as it
is presented in [24] is that it only checks for correct forward­
ing. Therefore all detected faults will belong to the FRC BPF
(see row BPF in table III). A manually analysis of the missed
faults in the gate list of the bypass showed up that these faults
are located in the control logic of the bypass. These were exact­
ly the faults that will cause a false-forwarding, thus, belonging
to the FRC BPNF. From a further analysis we could find out
that these faults could be stimulated by reading a register with
number r in the decode stage and writing at the same time a
register in the pipeline with the number r ', where r and r ' differ
in exactly one bit position. This could be checked with six
different register combinations (register number is coded into
six bits). All of these six register combinations must be used
for each of the eight pipeline registers exO, . . . ,wb3, from which
a forwarding is possible. This results fmally in 48 additional
test patterns. The fault coverage for the FRC BPNF is 5 5 . 0% .
Because this test covers all faults that were missed with the
FRC BPF, the fault coverage for the whole bypass could be
improved to 1 00% .
TABLE III.
Component
FAULT COVERAGE OF THE MANUAL APPROACH
FRC
Read Port RPO URP I U . . . URP63
BPF
Bypass
BPNF
Fault Coverage
test patterns
1 00%
9 1 .0%
55.0%
128
32
48
In a second test cycle an exhaustive fault simulation was
done for all possible double stuck-at faults in the read port and
in the bypass. All of these faults could be detected successfully.
V. ATPG ASSISTED TEST PRORAM GENERATION
The presented manual test routine provides excellent test
coverage combined with diagnostic features. However, if im­
plementation details of the multiplexer structure change, then
some of the presented test pattern may no longer be effective.
Then a manual classification of the faults into FRCs is needed
again for the new multiplexer structures. Furthermore, the fault
simulation for determining the fault coverage is a time­
consuming task. For this reason we will present in this section
an ATPG assisted approach for diagnostic test program genera­
tion. The ATPG tool is used for generating test patterns for the
defined FRCs. Figure 3 shows the proposed method. For each
processor component (e.g. the bypass), a set of FRCs is de­
fined. This is done from a functional point of view. Then the
processor component under test is synthesized. As in the man­
ual approach, each FRC represents certain misbehavior of the
corresponding component. In order to force the A TGP tool to
generate only test patterns that will test for the specified mis­
behavior, some constraints on the test patterns must be speci­
fied. For example, if the forwarding of the bypass should be
tested, then the test patterns must fulfill the property that some
destination registers in the write-back or execution stage must
have the same number as the source register in the decode­
stage of the pipeline. This constraint is used by the ATPG toll
for the generation of the test patterns for the FRC BPF. Please
note that structural information about the component is not
taken into account for the definition of the constraints. The
ATPG tool only generates test patterns that fulfill the given
constraint(s) . Thus, if the test patterns will be applied by a test
program, then the behavior is tested under the specified con­
straints. The application of the test patterns is done by mapping
the test patterns into pre-defmed test program-templates, as it is
described for example in [5] . The definition of the templates
must be done manually.
Figure 3
Flow of ATPG-supported test program generation.
Please note that test pattern generation is done for each
FRC separately. This ensures that each of the test programs
checks for the behavior of its corresponding FRC . Therefore,
the fault coverage, which is reported by the ATPG tool for the
test patterns obtained for a single FRC is sometimes low.
Moreover, some faults in the component may be tested multi­
ple times by test patterns from different FRCs. This is always
the case for a fault that will produce misbehavior in various
FRCs. The final fault coverage of the whole component is
obtained by checking the fault coverage of the test patterns
generated for all FRCs of that component. The presented flow
in figure 3 must be repeated for each component of the proces­
sor, for which a diagnostic test is needed.
We have applied this method to the Fault-Repair-Classes
BPF, BPNF, and RPO, . . . ,RP63 . The constraint for the FRC
BPNF specifies that the source register number in the decode
stage is different from all destination register numbers in the
execute- and write-back stage of the pipeline. For each FRC
RPx the constraint specifies that the register number at the
control input of the multiplexer must be x. Given these con­
straints, test patterns were generated for the FRCs shown in the
fust four rows of table IV. The last two rows summarize the
results for the whole bypass and read port.
PROPERTIES OF THE ATPG-GENERATED TEST PROGRAM
TABLE TV.
No. of Constraints Number of TP fault coverage
FRC
RPx (min)
RPx (max)
BPF only
BPNF only
I
1
4224
1 664
10
18
94
66
28.6%
29.0%
94.3%
58 .2%
Read Port
Bypass
64
5888
904
1 60
1 00%
99.3%
Because there are 64 FRCs for the read port, only the min­
imum and maximum of the results obtained for these FRCs are
shown. The number of generated test patterns (TP) ranges
between l O and 1 8 for each FRC RPx. No more than 29% of
the faults can be tested with these test patterns for each FRC
separately. However, in total each fault in the read port is cov­
ered. The bypass is tested by two FRCs. Both of them together
yield a fault-coverage of 99 . 3% . l OO% fault coverage were not
obtained, because 6 faults in the synthesized gate list of the
bypass were classified as untestable by the ATPG tool (even
without using constraints). It can be noticed that the number of
constraints, which are needed to specify the properties of both
FRCs, is very high. This is due to some technical limitations of
the used ATPG tool. But the needed constraints have a very
regular structure. So they were generated by scripts.
The results in table IV were obtained for a non-optimized
synthesis of the read-port and bypass. The proposed method
from figure 3 has been also applied to a different implementa­
tion of the bypass and read port structure. For this purpose the
behavioral VHDL descriptions have been synthesized under
timing constraints, which results in a different gate list. The
synthesis results for the optimized and non-optimized multi­
plexer structures are shown in table V.
SYNTHESIS RESULTS.
TABLE V.
l
I
Component No. of Gates
Read Port
Bypass
Read Port
Bypass
I
I
I
I
Area
28 1 4
748
Delay in ps
I
C ollapsed Faults
I
4 1 62
865
I
I
I
I
4088
1 151
I
793
1 62
I
Non-Optimized
998
909
227
1
1 72
I
I
I
Timing Optimized
558
7472
589
1 695
I
I
I
The method shown in figure 3 has been also applied to the
timing optimized gate list of the bypass and read port. The
results are shown in table VI. The obtained fault coverage is
almost the same, but with other test patterns. This demonstrates
that the method in figure 3 can be applied to arbitrary compo­
nents, as long as FRCs are specified.
TABLE VI.
PROPERTIES OF THE TEST PROGRAM GENERATED WITH
ATPG-As SISTANCE (TrMING OPTIMIZED)
VI.
CONSTRAINT-BASED TEST PATTERN REDUCTION
In tables IV and VI it can be noticed that the number of test
patterns is large, compared to the manual approach. For this
reason we will describe in this section an iterative method that
can be used to reduce the number of test patterns without
changing the fault coverage nor the diagnostic capability. Fig­
ure 4 extends the flow in figure 3 .
Figure 4
For each test set, which has been generated for a certain
FRC according to the method in figure 3 , the covered faults are
determined. After this, the A TPG constraints for the test pat­
terns can be modified. Modifying the constraints is done manu­
ally. The test patterns are generated again with the modified
constraints. If the same faults are covered with the new test set,
then the new test set can be used, if it contains fewer test pat­
terns. This iteration can be repeated until a satisfying result is
obtained. There are two reasons, why the iterative improve­
ment can be helpful. First, the number of test vectors may be
reduced, which will also reduce the length of the test program
generated for this test set. Second, the test patterns become
more homogeneous by the constraints, which will also simplify
the test program. For example, the test patterns generated with
the method in figure 3 define very irregular data for the data
inputs of the mUltiplexer. This will force the test program to
load many different constants as initialization code. With the
iterative improvement from figure 4 it was possible to reduce
the number of test vectors and to obtain more homogenous test
data. By this, the ATPG-produced test patterns became very
similar to the test patterns of the manually developed test pro­
gram. Thereby, our strategy during the iterative improvement
was to obtain more homogeneous test patterns. But this strate­
gy may be not successful in any case. Table VII shows three
different additional constraints that have been used for an im­
provement of the initial constraints of the FRCs BPF and
BPNF.
TABLE VIT.
No. of Constraints
RPx (min)
RPx (max)
BPF only
BPNF only
I
1
4224
1 664
10
17
1 00
52
3 1 .0%
3 1 .2%
94.6%
49. 1 %
Read Port
Bypass
64
5888
837
1 52
1 00%
99.5%
RESULTS FOR IMPROVEMENT BPF AND BPNF
No. of Constraint Additional Constraint Description BPF BPNF
Initial
1
2
Number of TP fault coverage
FRC
Iterative Test Pattern Improvement.
3
1 00
121
All data inputs are either 0 or - 1
All data inputs are 0 (or 1) and at 1 3 6
most one data input is - 1 (or 0)
All data inputs are 0 (- 1 ) and only 90
the sleeted data input is - 1 (or 0)
52
67
70
59
Constraint i has been used in iteration i of the improvement
process. The table also contains the corresponding number of
produced test patterns. The method was applied to the timing­
optimized gate list of the bypass. It can be seen that for the
FRC BPF the number of test patterns could be reduced. For the
FRC BPNF this was not the case. Table VIII summarizes the
results of the improvement method applied to the timing opti­
mized gate list of the read port.
RESULTS FOR IMPROVEMENT RPx
TABLE VIII.
No. of
Additional Constraint Descrip-
RPx
RPx
Constraint
tion
(min)
(max)
10
5
2
17
8
2
Initial
1
2
Each data input is either 0 or - I
All not selected register inputs
must have the same value
With the improvement method the number of test patterns
could be reduced to 2 for each FRC RPx. This is as good as in
the manual approach. Finally table IX compares the results for
the manually developed test program with the results for the
test program generated with A TPG assistance.
TABLE IX.
COMPARISON OF MANUAL AND ATPG APPROACH
Property
Manually
Fault coverage read port
Test patterns read port
Test program length read port
Fault Coverage bypass
Test patterns bypass
Test program length bypass
ATPG
1 00%
1 00%
128
128
640
640
99.5%
1 00%
32+48 = 80 �0+52= 1 42
376
568
The comparison shows that the ATPG generated test pro­
gram for the bypass does not reach the efficiency of the manu­
ally developed test program. It has an overhead of about 50%.
However, the ATPG-assisted approach can be applied to arbi­
trary components of a processor without a detailed analysis of
structural information, and the ATPG tool determines all faults
that belong to a certain FRC based on the given constraints.
VII.
CONCLUSION
This paper presented two versions of a diagnostic software­
based self-test program for multiplexer-based read-ports and
bypasses of a processor. It turned out that the manually devel­
oped version provided excellent fault coverage combined with
diagnostic capabilities. The test program that was generated
with ATPG-support has a slightly lower fault coverage and it is
longer. The advantage of the ATPG-based approach is that it
can be applied to components without knowing their internal
structure.
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