Ultra Fast FET-Input
Operational Amplifier
LLC
LH0032 / LH0032C
FEATURES
GENERAL DESCRIPTION
• 500V/µs Slew Rate
Bandwidth
• 70MHz
12
Ω Input Impedance
• 10
• As Low as 2mV Max Input Offset Voltage
• FET Input
Null with Single Pot
• Offset
• No Compensation for Gains Above 50
• Peak Output Current to 100mA
The LH0032 is a FET input, high slew rate amplifier capable
of driving up to 100mA current.
With wide bandwidth, high slew rate, high input impedance
and high current drive capability, LH0032 is an ideal choice for
many applications that includes high speed integrator, video
amplifier, summing amplifier, high speed D/A converters, etc.
ORDERING INFORMATION
Part
Package
LH0032G
LH0032CG
H12A (TO8-12 Lead)
H12A (TO8-12 Lead)
Temperature Range
-55oC to +125oC
-25oC to +85oC
CONNECTION DIAGRAMS
OUTPUT
COMPENSATION
NC
BALANCE/
COMPENSATION
3
2
4
INV
INPUT
12
+
5
11
OUT
10
6
NON-INV
INPUT
V+
1
7
8
NC
V-
9
NC
NC
Top View
H12A
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . ±30V or± 2VS
Power Dissipation, PD
TA = 25oC. . . . . . . . . . . . . 1.5W, derate 100oC/W to 125oC
TC = 25oC. . . . . . . . . . . . . 2.2W, derate 70oC/W to 125oC
Operating Temperature Range, TA
LH0032G . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
LH0032CG . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC
Operating Junction Temperature, TJ . . . . . . . . . . . . . . 175oC
Storage Temperature Range . . . . . . . . . . . . -65oC to +150oC
Lead Temp. (Soldering, 10 seconds). . . . . . . . . . . . . . 300oC
DC ELECTRICAL CHARACTERISTICS VS = ±15V, TMIN ≤ TA ≤ TMAX unless otherwise noted (Note 1) (TA = T j)
LH0032
SYMBOL
LH0032C
PARAMETER
UNITS
MIN
TYP
MAX
2
15
MIN
TYP
MAX
5
10
2
15
20
mV
50
15
50
µV/ o C
TEST CONDITIONS
TA = TJ = 25oC (Note 3)
VOS
Input Offset Voltage
∆VOS/∆T
Average Offset Voltage Drift
IOS
Input Offset Current
25
250
25
50
500
5
pA
pA
nA
IB
Input Bias Current
100
1
50
500
5
15
pA
nA
nA
VINCM
Input Voltage Range
±10
±12
±10
±12
V
Note 6
CMRR
Common Mode Rejection
Ratio
50
60
50
60
dB
∆VIN = ±10V
60
70
60
70
dB
VO = ±10V,
f = 1kHz
RL = 1kΩ
(Note 7)
±13
V
RL = 1kΩ
AVOL
Open-Loop Voltage Gain
57
VO
Output Voltage Swing
IS
Power Supply Current
PSRR
Power Supply Rejection
Ratio
±10
57
±13.5
18
50
60
±10
20
20
50
60
22
(Note 4)
VIN = 0
TJ = 25oC (Note 2)
TA = 25oC (Note 3)
TJ = 25oC (Note 2)
TA = 25oC (Note 3)
mA
TA = 25oC,
IO = 0 (Note 3)
dB
∆VS = 10V
(±5 to ±15V)
TJ = 25oC
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
AC ELECTRICAL CHARACTERISTICS VS = ±15V, RL = 1kΩ, TJ = 25oC (Note 5)
SYMBOL
PARAMETER
SR
Slew Rate
ts
Settling Time to 1% of Final Value
MIN
TYP
350
500
MAX
UNITS
CONDITIONS
V/µs
AV = +1
∆VIN = 20V
100
AV = -1
ts
Settling Time to 0.1% of Final Value
tR
Small Signal Rise Time
8
20
tD
Small Signal Delay Time
10
25
300
ns
AV = +1, ∆VIN = 1V
Note 1. LH0032G/CG are 100% production tested as specified at 25 oC, Specifications at temperature extremes are verified by testing, periodic
characterization, or correlation.
Note 2. Specification is at 25oC junction temperature due to requirements of high-speed automatic testing. Actual values at operating
temperature will exceed the value at TJ = 25oC. When supply voltages are ±15V, no-load operating junction temperature may rise 40-60oC above
ambient, and more under load conditions. Accordingly, VOS may change one to several mV, and I B and IOS will change significantly during
warm-up. Refer to IB and I OS vs. temperature graph for expected values.
Note 3. Measured in still air 7 minutes after application of power. Guaranteed thru correlated automatic pulse testing.
Note 4. ∆VOS/∆T is the average value calculated from measurements at 25 oC and TMAX, specifications at temperature are verified by testing,
periodic characterization, or correlation.
Note 5. Not 100% production tested; verified by testing, periodic characterization, or correlation.
Note 6. Guaranteed by CMRR test condition.
Note 7. Guaranteed thru correlated pulse testing at T j = 25 oC.
AUXILIARY CIRCUITS
Offset Null
Output Short Circuit Protection
V+
V+
LM113
12
6
10k
+
12
6
LH0032
4
5
+
INPUTS
3
LH0032
5
-
2
11
-
11
62Ω
10
OUTPUT
10
V-
V-
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM POWER
DISSIPATION
24
INFINITE HEAT SINK
TA = -55˚C
22
SUPPLY CURRENT (mA)
POWER DISSIPATION (W)
2.5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.0
θJC = 70˚C/W
1.5
1.0
NO HEAT SINK
θJA = 100˚C/W
0.5
20
TC = 25˚C
18
16
14
TA = +125˚C
12
0
10
0
25
50
75
100
125
150
5
10
15
TEMPERATURE (˚C)
SUPPLY VOLTAGE (±V)
INPUT VOLTAGE RANGE AND OUTPUT
VOLTAGE vs. SUPPLY VOLTAGE
BODE PLOT
(UNCOMPENSATED)
20
80
VS = ±15V
RL = 1k
TC = 25˚C
VOLTAGE GAIN (dB)
0
15
VOUT
10
VIN
5
45
60
PHASE
40
90
135
180
GAIN
20
225
PHASE (DEGREES)
VINCM , VOUT (±V)
20
270
0
10k
0
10
5
20
100k
1M
10M
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
BODE PLOT (UNITY GAIN
COMPENSATED)
LARGE SIGNAL
FREQUENCY RESPONSE
80
24
60
0
PHASE
40
45
90
GAIN
20
100M
26
VS = ±15V
135
PHASE (DEGREES)
VOLTAGE GAIN (dB)
15
VOLTAGE GAIN (dB)
0
A V = +10
22
20
18
A V = +1
16
14
12
10
VS = ±15V
RL = 1k
TC = +25˚C
8
0
10k
100k
1M
10M
FREQUENCY (Hz)
100M
6
10
100
1M
10M
100M
FREQUENCY (Hz)
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
COMMON MODE REJECTION
RATIO vs. FREQUENCY
LARGE SIGNAL
PULSE RESPONSE
90
VS = ±15V
RL = 1k
80
+10
OUTPUT VOLTAGE (V)
COMMON-MODE REJECTION RATIO (dB)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
70
60
50
40
30
20
VS = ±15V
A V = +1
RL = 1k
+5
0
-5
10
-10
0
10k
100k
1M
10M
100M
0
100
200
300
400
500
FREQUENCY (Hz)
TIME (ns)
LARGE SIGNAL
PULSE RESPONSE
NORMALIZED INPUT BIAS AND OFFSET
CURRENT vs. JUNCTION TEMPERATURE
10 4
CURRENT – NORMALIZED
TO CURRENT AT TJ = 25˚C
OUTPUT VOLTAGE (V)
10
VS = ±15V
A V = +10
RL = 1k
5
0
-5
10 3
10 2
101
-10
0
100
200
300
400
10 0
25
500
45
65
85 105 125 145 165
JUNCTION TEMPERATURE (˚C)
TIME (ns)
NORMALIZED INPUT BIAS
CURRENT DURING WARM-UP
CURRENT – NORMALIZED
TO CURRENT AT TIME = 0
100
VS = ±15V
TA = 25˚C
10
1
0
2
4
6
8
10
TIME FROM POWER TURN-ON (MINUTES)
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
TYPICAL APPLICATIONS
Unity Gain Amplifier
10X Buffer Amplifier
5pF
8pF - 10pF
V-
V-
12
12
2k
6
INPUT
2
+
INPUT
2
+
3
3
11
LH0032
5
6
OUTPUT
5
4
10
11
LH0032
-
10
OUTPUT
9k
100pF
VV-
1k
100
100X Buffer Amplifier
Non-Compensated Unity Gain Inverter
V+
V+
10k
INPUT
6
12
+
11
LH0032
5
-
+
10k
10
5
INPUT
V-
-
11
LH0032
270
10k
12
6
0.01
+
OUTPUT
10
100
V+
High Speed Sample and Hold
100Ω
V+
2N2222
2N4391
VOUT
+
VIN
2N3907
10k
V+
LH0032
100Ω
1N914
1k
CS = 1000pF
V-
LOGIC
CONTROL
1/2 DH0034
*Use polystyrene dielectric for minimum drift
V-
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
TYPICAL APPLICATIONS (Continued)
High Speed Current Mode MUX
3.8pF
4
5
V-
R5
6
18µF
12
R1
2
AM9710
A1
5.1k
R2
5
6
3
LH0032
6
1
2
-
G1
A2
3
11
VOUT
+
10
5.1k
R3
11
G2
9
5
V-
7
A3
5.1k
R4
G3
13
10
8
A4
5.1k
G4
12
14
APPLICATION INFORMATION:
Power Supply Decoupling
The LH0032, like most high speed circuits, is sensitive to
layout and stray capacitance. Power supplies should be
bypassed as near to pins 10 and 12 as practicable with low
inductance capacitors such as 0.01µF disc ceramics.
Compensation components should also be located close to
the appropriate pins to minimize stray reactances.
Input Current
Because the input devices are FETs, the input bias current
may be expected to double for each 11oC junction
temperature rise. This characteristic is plotted in the typical
performance characteristics graphs. The device will self-heat
due to internal power dissipation after application of power
thus raising the FET junction temperature 40-60oC above
free-air ambient temperature when supplies are ±15V. The
device temperature will stabilize within 5-10 minutes after
application of power, and the input bias currents measured at
that time will be indicative of normal operating currents. An
additional rise would occur as power is delivered to a load due
to additional internal power dissipation.
There is an additional effect on input bias current as the input
voltage is changed. The effect, common to all FETs, is an
avalanche-like increase in gate current as the FET
gate-to-drain voltage is increased above a critical value
depending on FET geometry and doping levels. This effect
will be noted as the input voltage of the LH0032 is taken
below ground potential when the supplies are ±15V. All of the
effects described here may be minimized by operating the
device with VS ≤ ±15V.
These effects are indicated in the typical performance curves.
Input Capacitance
The input capacitance to the LH0032/LH0032C is typically
5pF and thus may form a significant time constant with high
value resistors.
For optimum performance, the input
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
In the non-inverting configuration, it may be advantageous to
bootstrap the case and/or a guard conductor to the inverting
input. This serves both to divert leakage currents away from
the non-inverting input and to reduce the effective input
capacitance. A unity gain follower so treated will have an
input capacitance under a picofarad.
Figure 1. LH0032 Frequency Compensation Circuit
R2
0.01µF
12
CA
5 _
INPUT
4
11
LH0032
R1
OUTPUT
3
6 +
2
10
CC
0.01µF
-15V
Two compensation schemes may be used, depending on the
designer’s specific needs.
The first technique is shown in Figure 1. It offers the best
0.1% settling time for a ±10V square wave input. The
compensation capacitors CC and CA should be selected from
Figure 2 for various closed-loop gains. Figure 3 shows how
the LH0032 frequency response is modified for different value
compensation capacitors.
Figure 2. Recommended Value of Compensation
Capacitor vs Closed-Loop Gain for Optimum
Settling Time
100
10
75
CC
5
50
CA
25
0
1000
0
1
10
100
COMPENSATION CAPACITANCE CA (pF)
+15V
R3
Compensation
COMPENSATION CAPACITANCE CC (pF)
capacitance to the inverting input should be compensated by
a small capacitor across the feedback resistor. The value is
strongly dependent on layout and closed loop gain, but will
typically be in the neighborhood of several picofarads.
CLOSED LOOP GAIN
Figure 3. The Effect of Various Compensation
Capacitors on LH0032 Open Loop Frequency
Response
A VOL
60
40
C C = 0pF
C C = 1pF
0
C C = 5pF
C C = 10pF
-45
20 C C = 5pF
C C = 10pF
0 VS = ±15V
RL = 1k
TA = 25˚C
-20
10k
100k
-90
PHASE
C C = 1pF
C C = 0pF
1M
10M
-135
-180
100M
10V
PHASE SHIFT (DEGREES)
VOLTAGE GAIN (dB)
80
Figure 4. LH0032 Unity Gain Non-Inverting Large
Signal Pulse Response:
TA = 25oC, CC = 10pF, CA = 100pF
10V
100nS
FREQUENCY (Hz)
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A
LH0032 / LH0032C
LLC
Although this approach offers the shortest settling time, the
falling edge exhibits overshoot up to 30% lasting 200 to
300ns. Figure 4 shows the typical pulse response.
If obtaining minimum ringing at the falling edge is the primary
objective, a slight modification to the above is recommended.
It is based on the same circuit as that of Figure 1.
The values of the unity gain compensation capacitors CC and
CA should be modified to 5pF and 1000pF, respectively.
Figure 5 shows the suitable capacitance to use for various
closed-loop gains. The resulting unity gain pulse response
5
1000
4
3
CC
2
500
CA
1
0
1
10
100
0
1000
COMPENSATION CAPACITANCE CA (pF)
COMPENSATION CAPACITANCE CC (pF)
Figure 5. Recommended Value of Compensation
Capacitor vs Closed-Loop Gain for Optimum Slew Rate
waveform is shown in Figure 6. The settling time to 1% final
value is actually superior to the first method of compensation.
However, the LH0032 suffers slow settling thereafter to 0.1%
accuracy at the falling edge, and nearly four times as much at
the rising edge, compared to the previous scheme. Note,
however, that the falling edge ringing is considerably reduced.
Furthermore, the slew rate is consistently superior using this
compensation because of the smaller value of Miller
capacitance CC required.
The second compensation scheme works well with both
inverting or non-inverting modes. Figure 7 shows the circuit
schematic, in which a 270ohm resistor and a 0.01µF capacitor
are shunted across the inputs of the device. This lag
compensation introduces a zero in the loop modifying the
response such that adequate phase margin is preserved at
unity gain crossover frequency. Note that the circuit requires
no additional compensation.
Heat Sinking
While the LH0032 is specified for operation without any
explicit heat sink, internal power dissipation does cause a
significant temperature rise.
Improved bias current
performance can thus be obtained by limiting this temperature
rise with a small heat sink such as the Thermalloy No. 2241 or
equivalent.
The case of the device has no internal
connection, so it may be electrically connected to the sink if
this is advantageous. However, that this will affect the stray
capacitance to all pins and may thus require adjustment of
circuit compensation values.
CLOSED LOOP GAIN
Figure 6. LH0032 Unity Gain Non-Inverting Large
Signal Pulse Response: CC = 5pF, CA = 1000pF
Figure 7. LH0032 Non-Compensated Unity Gain
Compensation
+15V
10V
1k
1k
INPUT
0.01µF
5 _
LH0032
270
1k
12
11
OUTPUT
6 +
10
0.01µF
0.01µF
10V
50nS
-15V
CALOGIC LLC, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
DS047 REV A