STLVD112
High speed protection switch
Features
■
24mA CMOS output drive current
■
LVTTL input thresholds
■
Controlled skew between data and clock
signals
■
LVDS input-output up to 155 MHz
■
Improved latch-up immunity up to 300mA
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TSSOP
Description
The STLVD112 is a low voltage differential to
LVTTL signal converter with enhanced loop-back
and crosspoint features. The synchronous design
allows a phase alignment between a clock and its
data; this means a better BER (Bit Error Rate)
performance.
The advanced 0.35ìm technology makes the
STLVD112 suitable for data rates up to 200Mbit.
The main application field is SDH/SONET
telecom infrastructure. The STLVD112 flexible
switch architecture makes it easy to implement
multiple protection schemes in STM1 access
systems.
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card. In normal mode the STLVD112 converts the
differential data levels of the LVDS and related
clock signal from (to) the line interface in LVTTL
level signals to (from) the backpanel. In addition
the switch functions prevent the equipment from
line interface faults. In fact, it is possible to switch
the signals coming from a different line interface
to the local line interface or the signals from the
local line interface to a different line interface.
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Thanks to the flexible multiplexing allowed, it
becomes simple to redirect the data/clock signal
coming from the faulty access card to the spare
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Order codes
Part number
Temperature
range
Package
Packaging
STLVD112BTR
-40 to 85 °C
TSSOP48 (Tape & Reel)
1000 parts per reel
May 2007
Rev. 3
1/15
www.st.com
15
STLVD112
Contents
1
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Truth tables
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
.............................................. 5
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STLVD112
Pin configuration
1
Pin configuration
Figure 1.
Pin connections
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Pin configuration
Table 1.
STLVD112
Pin description
Pin n°
Symbol
1, 6, 14, 22
VS1
Main power supply
2
CKsp_in
LVTTL Clock input
3
DATAsp_in
LVTTL Data input
4, 9, 13, 17, 21,
25, 36, 44, 48
GND
5
LOSch
7
CKsp_out
LVTTL clock output
8
DATAsp_out
LVTTL data output
10, 18, 31, 38
VS2
11
CKch_in
LVTTL clock input
12
DATAch_in
LVTTL data input
15
CKprev_in
LVTTL clock input
16
DATAprev_in
LVTTL data input
19
CKch_out
LVTTL clock output
20
DATAch_out
LVTTL data output
23
CKprev_out
LVTTL clock output
24
DATAprev_out
LVTTL data output
26, 30, 37, 43
N.C.
27
Kloop_sp
28
Kloop_I
29
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DATAinB
33
Second power supply
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Not connected
Control input
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Control input
Control input
LVDS data input -
CKinB
LVDS clock input -
CKinA
LVDS clock input +
CKoutB
LVDS clock output -
40
CKoutA
LVDS clock output +
41
DATAoutB
LVDS data output -
42
DATAoutA
LVDS data output +
45
LOSsp
46
LOSi
Control input
47
LOSprev
Control input
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Control output
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LVDS data input +
35
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Control output
DATAinA
34
Ob
Ground
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Ki
32
Name and function
STLVD112
Truth tables
2
Truth tables
Table 2.
Truth tables for the five MUX
Inputs
Output
Ki
Kloop_sp
Kloop_i
DATA_out
LOW
X
X
DATAch_in
HIGH
X
X
DATAsp_in
Inputs
Output
Ki
Kloop_sp
Kloop_i
DATAch_out
X
X
X
X
LOW
HIGH
DATAin
DATAch-in
Inputs
Output
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Ki
Kloop_sp
Kloop_i
DATAsp_out
LOW
HIGH
X
LOW
LOW
HIGH
X
X
X
DATAprev_in
DATA_in
DATAsp_in
Inputs
Ki
Kloop_sp
Kloop_i
X
X
X
X
LOW
HIGH
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Inputs
Ki
Kloop_sp
LOW
HIGH
X
LOW
LOW
HIGH
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Output
LOSch
LOSi
LOW
Output
Kloop_i
LOSsp
X
X
X
LOSprev
LOSi
LOW
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Maximum ratings
STLVD112
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VS1, VS2
Supply voltage
-0.3 to 4.6
V
VS2
Supply voltage
-0.3 to (VS1 + 0.3)
V
VI
DC input voltage
-0.3 to (VS1 + 0.3)
V
VO
DC output voltage
-0.3 to (VS1 + 0.3)
V
Iik
DC input diode clamp current
±20
mA
Iok
DC output diode clamp current
±20
mA
IO
DC output current
±50
mA
TL
lead temperature (10sec)
300
°C
Tstg
storage temperature range
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-65 to 150
°C
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Note:
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied.
Table 4.
Recommended operating conditions
Symbol
Parameter
VS1, VS2
Supply voltage
VS2
Supply voltage
VI
DC input voltage
VO
DC output voltage
Top
Operating temperature
dt/dv
Maximum input rise and fall time
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Value
Unit
3 to 3.6
V
3 to (VS1 + 0.3)
V
0 to VS1
V
0 to VS1
V
-45 to 85
°C
10
ns/V
STLVD112
Electrical characteristics
4
Electrical characteristics
Table 5.
Electrical characteristics (over recommended operating conditions, unless otherwise
noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Parameter
Min.
Typ.
Max.
Unit
0.2
0.4
V
VOL
Low level output voltage
IOUT = 24 mA
VOH
High level output voltage
IOUT = 24 mA
VIL
Low level input thresholds
VOUT = 0.1V or VS1 - 0.1
0
0.8
V
VIH
High level input thresholds
VOUT = 0.1V or VS1 - 0.1
2
VSI
V
IIN
Input leakage current
VIN = GND or VCC
-1
1
µA
ICC
Quiescent supply current
Table 6.
VIN = GND or VCC
15
fCLOCK = 155MHz
110
Parameter
RL = 100 Ω
ΔVOD
Change in differential output voltage
between logic states
VOC(SS)
Steady-state common-mode output
voltage
ΔVOC(SS)
Change in steady-state common- mode
output voltage between logic State
ΔVOC(PP)
Peak-to-peak common-mode output
voltage
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Short circuit output current
IOFF
Power off output current
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Max.
Unit
454
mV
50
mV
1.30
V
50
mV
150
mV
Min.
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Typ.
364
-50
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1.15
-50
100
VO(Y) or VO(Z) = 0
-24
-4
mA
VOD = 0
±12
VCC = 0, VO = 2.4V
-1
1
µA
LVDS receiver electrical characteristics (over recommended operating conditions, unless
otherwise noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Parameter
VITH+
Positive-going differential input
voltage threshold
VITH-
Negative-going differential input
voltage threshold
|VID|
Magnitude of differential input voltage
VIC
mA
Test condition
Differential output voltage
Symbol
V
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VOD
Table 7.
VSI-0.5 VSI-0.3
LVDS driver electrical characteristics (over recommended operating conditions, unless
otherwise noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
O
Test condition
Common-mode input voltage
Test condition
Min.
Typ.
Max.
Unit
100
mV
-100
mV
0.1
0.6
V
0.5 |VID|
2.4-0.5
|VID|
V
VCC-1
7/15
Electrical characteristics
Table 8.
LVDS switching timing characteristics (Over recommended operating conditions, unless
otherwise noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Parameter
Test condition
Table 9.
Propagation delay time, low-to-highlevel output (50% to 50%)
tPHL
Propagation delay time, high-to-lowlevel output (50% to 50%)
tTLH
Transition time, low-to-high-level
output (10% to 90%)
tTHL
Transition time, high-to-low-level
output (90% to 10%)
fopr
Operative frequency
Test condition
Measured with
VIN = 0 to 2.5V,
fCLOCK = 1MHz,
fDATA = 0.5MHz
tr = tf = 0.4ns, +Duty
Cycle = 50%
tPHL, tPLH are referred
to output clock
transitions.
Parameter
tPHL
Propagation delay time, high-to-lowlevel output (50% to 50%)
tTLH
Transition time, low-to-high-level output
(10% to 90%)
Min.
Typ.
Max.
Unit
2.4
3.9
5.6
ns
2.5
4.2
5.3
ns
0.7
1.3
1.6
ns
0.7
1.1
1.3
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tTHL
Transition time, high-to-low-level output
(90% to 10%)
Measured with
VIN = 0 to 2.5V,
fCLOCK = 1MHz,
fDATA = 0.5MHz
tr = tf = 0.4ns, +Duty
Cycle = 50%
tPHL, tPLH are
referred to output
clock transitions.
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Test condition
Propagation delay time, low-to-highlevel output (50% to 50%)
bs
ns
100
tPLH
Symbol
Unit
155
200
ns
MHz
AC control output (LOSsp, LOSch) (Over recommended operating conditions, unless
otherwise noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Table 11.
Max.
<1
Parameter
tPLH
Table 10.
Typ.
AC LVTTL IN LVTTL OUT (Over recommended operating conditions, unless otherwise
noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Min.
Typ.
Max.
Unit
2.4
3.6
4.4
ns
2.4
3.4
4.2
ns
0.9
1.9
2.3
ns
0.7
1.0
1.2
ns
AC LVTTL IN LVDS OUT (Over recommended operating conditions, unless otherwise
noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Parameter
tPLH
Propagation delay time, low-to-highlevel output (50% to 50%)
tPHL
Propagation delay time, high-to-lowlevel output (50% to 50%)
tTLH
Transition time, low-to-high-level output
(20% to 80%)
tTHL
Transition time, high-to-low-level output
(80% to 20%)
fopr
Operative frequency
8/15
Min.
Minimum pulse width
tW
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STLVD112
Test condition
Measured with
VIN = 0 to 2.5V,
fCLOCK = 1MHz,
fDATA = 0.5MHz
tr = tf = 0.4ns, +Duty
Cycle = 50%
tPHL, tPLH are
referred to output
clock transitions.
Min.
Typ.
Max.
Unit
2.8
3.8
4.7
ns
2.6
3.4
4.1
ns
0.4
0.5
0.6
ns
0.4
0.6
0.7
ns
100
155
200
MHz
STLVD112
Table 12.
Electrical characteristics
AC LVDS IN LVTTL OUT (Over recommended operating conditions, unless otherwise
noted. All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Parameter
tPLH
Propagation delay time, low-to-highlevel output (50% to 50%)
tPHL
Propagation delay time, high-to-lowlevel output (50% to 50%)
tTLH
Transition time, low-to-high-level output
(10% to 90%)
tTHL
Transition time, high-to-low-level output
(90% to 10%)
fopr
Operative frequency
Table 13.
Parameter
ts
Setup time
tH-
Hold time
Setup time
tH-
Hold time
ts
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tH-
Max.
Unit
4.3
5.6
6.9
ns
4.1
5.4
6.7
ns
0.7
0.9
1.1
ns
0.8
1.0
1.3
ns
100
155
200
MHz
Min.
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Typ.
Max.
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Unit
ns
ns
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Test condition
f = 10MHz,
VICM = 1.2 V
VDIFF = 400mV,
VINTTL = 0 to 2.5V
Min.
Typ.
Max.
Unit
1
ns
1
ns
LVDS IN LVTTL OUT (Over recommended operating conditions, unless otherwise noted. All
typical values are at TA = 25°C and VS1, VS2 = 3.3V)
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Test condition
f = 10MHz,
VICM = 1.2 V
VDIFF = 400mV,
VINTTL = 0 to 2.5V
Parameter
ts
Symbol
Typ.
LVTTL IN LVDS OUT (Over recommended operating conditions, unless otherwise noted. All
typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Table 15.
VDIFF = 400mV
Measured with
VICM = 1.2 V,
fCLOCK = 1MHz,
fDATA = 0.5MHz
tr = tf = 0.4ns, +Duty
Cycle = 50%
tPHL, tPLH are
referred to output
clock transitions
Min.
LVTTL IN LVTTL OUT (Over recommended operating conditions, unless otherwise noted.
All typical values are at TA = 25°C and VS1, VS2 = 3.3V)
Symbol
Table 14.
Test condition
Setup time
Hold time
Parameter
Test condition
f = 10MHz,
VICM = 1.2 V
VDIFF = 400mV,
VINTTL = 0 to 2.5V
Min.
Typ.
Max.
Unit
1.5
ns
1
ns
9/15
Diagram
STLVD112
5
Diagram
Figure 2.
Logic diagram
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STLVD112
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
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Package mechanical data
STLVD112
TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
1.2
A1
0.05
0.047
0.15
A2
MAX.
0.002
0.006
0.9
0.035
b
0.17
0.27
0.0067
0.011
c
0.09
0.20
0.0035
0.0079
D
12.4
12.6
0.488
0.496
E
8.1 BSC
E1
6.0
6.2
e
0.244
0.0197 BSC
K
0°
8°
0°
L
0.45
0.75
0.018
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0.236
0.5 BSC
A
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0.318 BSC
K
8°
0.030
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PIN 1 IDENTIFICATION
1
7065588D
12/15
STLVD112
Package mechanical data
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
330
13.2
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
MAX.
0.504
30.4
0.519
1.197
Ao
8.7
8.9
0.343
0.350
Bo
13.1
13.3
0.516
0.524
Ko
1.5
1.7
0.059
0.067
Po
3.9
4.1
0.153
P
11.9
12.1
0.468
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0.161
0.476
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Revision history
STLVD112
7
Revision history
Table 16.
Revision history
Date
Revision
28-May-2007
3
Changes
Order codes has been updated and the document has been reformatted.
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STLVD112
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
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All ST products are sold pursuant to ST’s terms and conditions of sale.
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Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
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UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
O
)
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,
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SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
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15/15