UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
E. Alon
P. Nuzzo
Homework #3 Solutions
EECS 240
Use the EECS240 90nm CMOS process in all home works and projects unless noted
otherwise. In this homework you may use just the typical (tt) device parameters.
1.
Pole-Zero Doublets: In this problem we will be looking at the behavior of the pseudo-differential
amplifier shown below to gain some intuition into the origin and response of pole-zero doublets. You
can assume that M1 and M2 form a differential pair (i.e. their small signal model parameters are
identical) with infinite small-signal output impedance (ro). Moreover, you can assume that R1 is larger
than R2, and all capacitors are negligible with the exception of the ones explicitly drawn in the diagram.
VDD
Vi1
M1
Vo2
Vo1
R1
Vi2
M2
C
C
R2
a. Derive an expression for the transfer functions H11(s) = Vo1(s) /Vi1(s) and H22(s) = Vo2(s) /Vi2(s) in
terms of R1, R2, C and the transistors’ gm.
Solution:
This question is really just asking for the gain of a common source (CS) stage. H11(s) = Vo1(s)
/Vi1(s) and H22(s) = Vo2(s) /Vi2(s) can then be derived by inspection as follows:
1  − g m R1

H11 ( s ) =
− g m  R1 ||
=
Cs  1 + R1Cs

1  − g m R2

− g m  R2 ||
H 22 ( s ) =
=
Cs  1 + R2Cs

1
b. Sketch the magnitudes of H11 and H22 versus frequency on the same plot.
Solution:
|H11(ω)|dB
|H22(ω)|dB
gmR1
gmR2
-20dB/dec
1/R1C
1/R2C
gm/C
ω
c. Now derive and sketch the time-domain voltage response of Vo1 to a voltage step on Vi1. Similarly,
derive and sketch the time-domain voltage response of Vo2 to a voltage step on Vi2.
Solution:
Although this problem is obviously solvable with inverse Laplace transforms, let’s take a simple
intuitive approach. We know that initially C looks like a short circuit, and so at t = 0, Vo1=0 as well.
We also know that C will eventually become an open circuit, so at t = ∞, Vo1 = -gmR1. Finally, we
know that the time constant of the settling will be R1C since that is the location of the pole. Now all
we have to do is use this information to plug values into an equation that gives the time domain
response of a single-pole system:
Vo1 (t ) = Vinitial + (V final − Vinitial )(1 − e −t R1C )
Vo1 (t ) =
− g m R1 (1 − e −t R1C )
Similarly, for Vo2 we obtain
− g m R2 (1 − e −t R2C ) .
Vo 2 (t ) =
This answer is indeed correct and requires essentially no math to reach. However, just to show a
more formal method of solving the problem, we can reach the same result using inverse Laplace
transforms to solve for the step response Vo1(s) as follows:
−g R
1
Vi1 ( s ) =⇒ Vo1 ( s ) = m 1 ,
s
s (1 + R1Cs )
and remembering that
1
s ( sτ + 1)
−1
L

→(1 − e − t τ ) .
2
0
Step Response
Amplitude
-gmR2
-gmR1
Time (sec)
d. Using the results from part a. and part b., sketch the magnitude of the transfer function for
differential gain H(s) = (Vo2-Vo1)/(Vi1-Vi2).
Solution:
Since we are just interested in the differential gain, we can assume that the amplifier is driven by a
purely differential signal (no common mode) such that Vd = Vi1-Vi2. Therefore, we have Vi1= Vd/2
and Vi2=-Vd/2. Moreover, we observe that Vo1 will totally be determined by Vi1 and, similarly, Vo2
will totally be determined by Vi2. Therefore, using the results from parts a. and b., we can write:
− Vo1 H 22 ( s )Vi 2 − H11 (=
Vo 2 =
s )Vi1 H 22 ( s )
−Vd
V
− H11 ( s ) d
2
2
Vd
2
( H ( s) + H 22 ( s) ) =
Vo 2 − Vo1
g m  R1
R2 
=
− 11
+
H (s) =


2
2  1 + R1Cs 1 + R2Cs 
Vi1 − Vi 2
RR
1 + 2C 1 2 s
g ( R + R2 )
R1 + R2
= m 1
2
(1 + R1Cs )(1 + R2Cs )
=
− ( H11 ( s ) + H 22 ( s ) )
We can certainly draw the Bode diagram directly starting from the expression of H(s) computed
above. As an alternative, we can still use the Bode diagrams part b. to sketch the one of H(s). In
fact, we found that H(s) is practically the arithmetic mean of H11(s) and H22(s), with a sign
inversion. The magnitude of H(s) can then be inferred from the magnitude of the mean of H11(s) and
H22(s). However, care must be taken to manipulate the plots of H11(s) and H22(s) when they are in
logarithmic scale. The result is shown in the figure below.
We observe that H(s) has a lower frequency pole ωp1=1/(R1C) and a higher frequency pole
ωp2=1/(R2C), which are respectively associated with the left and right side of the pseudo-differential
amplifier. Since ωp1 kicks in at lower frequencies with respect to ωp2, there is a frequency band in
which the contribution of M1 to the differential gain becomes practically negligible with respect to
the contribution given by M2, which creates a zero at the frequency
ωz =
ω p1 + ω p 2
2
=
R + R2
1
1
+
= 1
2 R1C 2 R2C 2CR1 R2
.
3
|H(ω)|dB
gmR1
gm (R1+R2)/2
gmR2
-20dB/dec
1/2(R1||R2)C
1/R1C
1/R2C
gm/C
ω
In this frequency band where the signal on the left side of the circuit is essentially being heavily
filtered out while the signal on the right side of the circuit still has gain, the overall differential gain
is dominated by the right side of the circuit – i.e., the gain is simply equal to gmR2.
e. Now sketch the time-domain voltage response of the differential output Vo2-Vo1 to a differential
voltage step (Vi1-Vi2). While you can certainly derive this response using inverse Laplace
transforms and partial fractions, you may find it significantly easier to use your answers from the
previous sections instead.
Solution:
Without having to solve for the time domain solution mathematically, we know that both capacitors
will initially look like short circuits, which means that the output will start at 0. Eventually the
response settles to gm(R1+R2)/2. Moreover, the system has two poles and one zero as seen in part d.
Since this is a linear system, we expect the step response is a combination of two exponentials such
as:
(
Vdo ( t ) = V f 1 1 − e
Vf 1 +Vf 2
−ω p 1t
) + V (1 − e )
−ω p 2t
f2
(1)
g m ( R1 + R2 )
=
2
All that we need to do is to determine Vf1 and Vf2. However, we have seen in part d. that H(s) can
already be split into the sum of two rational functions, each associated with one of its poles:
=
H (s)
g m R1 / 2 g m R2 / 2
.
+
1 + R1Cs 1 + R2Cs
(2)
We can therefore immediately conclude from (2) that the desired step response is
Vdo ( t ) =
(
)
(
)
g m R1
g R
1 − e −t R1C + m 2 1 − e −t R2C .
2
2
As evident from the above expression, the step response of the differential voltage can also be
obtained by combining the step responses found in part c, adequately scaled. A sketch of this
response, overlapped with the plot of its components is shown below.
4
Step Response
g (R +R )/2
m
1
2
Amplitude
gmR1/2
gmR2/2
0
Time (sec)
As we deduce from the above figure, the dominant pole gets the output voltage most of its way
towards its final value while the fast non-dominant pole gets it the rest of the way. This is basically
always the case for the generic transfer functions with two poles and one zero, when there is a
dominant pole.
To be convinced about this, let us look for an approximate mathematical model for the step
response of a generic transfer function below:
H ′( s ) =
(1 + s ωz )
(1 + s ω )(1 + s ω )
p1
.
(3)
p2
The system described by H’(s) can always be decomposed into two single-order systems using
partial fraction decomposition
=
H ′( s )
A
B
+
(1 + s ω p1 ) (1 + s ω p 2 )
where A and B need to satisfy
1
A + B =

A
+
B ω p1 =
ω
1 ωz
p2

With a little bit of algebra, this comes out to:
=
A
ω p 2 (ω z ω p1 − 1)
ω p1 (ω z ω p 2 − 1)
=
B
ω z (ω p 2 ω p1 − 1)
ω z (ω p1 ω p 2 − 1)
which give us the coefficients of the exact step response. However, if ωp2 >> ωp1, B can very well
approximated by ωp1/ωz since
ω p1 

 ω p1 ω p 2 −

ω z  ω p1
as ω p1 ω p 2 → 0
B=
→
(ω p1 ω p 2 − 1) ωz
5
and therefore A can be approximated as (1 – ωp1/ ωz) . In other words, when the second pole is
truly non-dominant, we can approximate the step response of H’(s) as:
ω p1
 ω p1 
−ω p 1t
−ω t
h ( t ) ≈ 1 −
1− e p2 .
+
 1− e
ω
ω
z 
z

(
(
)
)
From this expression, we can conclude again that the dominant pole gets us most of the way towards
the final value while the fast non-dominant pole gets us the rest of the way. This approximation can
be extremely accurate in many practical cases of interest.
Note that there are other methods you could have used to arrive at an answer for this question. Any
solution that follows a physically correct line of thinking and arrives at a reasonable result will
receive full credit.
2.
Switched-capacitor amplifier: What is the total noise variance at the output of the switched capacitor
amplifier shown below at the end of a complete cycle (i.e., during φ2)? You can assume that the OTA
is simply implemented by an NMOS common-source stage with a given gm and infinite ro.
Cf
φ1
φ1
Vi
φ2
Cs
φ1
φ2
+
φ1
Vo
Solution:
During φ1, all we are really doing is sampling Vi onto Cs. Given that Vi has some finite source
resistance (and hence some thermal noise associated with it), when φ1 goes low, we will sample a noise
variance of kT/Cs. Once φ2 goes high, this noise voltage will appear at the negative input of our OTA,
which will respond to it by transferring that charge onto Cf and restoring the virtual ground. Therefore:
2
=
vo2,Vi
kT  Cs 
kT  Cs  .
=




Cs  C f 
Cf  Cf 
To get the total noise at the output, we just need to look at the noise contribution of the OTA itself
during φ2. First, let’s draw the small signal equivalent circuit (ignoring the noise sampled onto Cs):
vi
Cs
Cf
Vo
gmvi
iM2
If you look at this circuit, you should pretty quickly realize that the transistor is essentially in a diodeconnected configuration – just that there is a capacitive voltage divider between the drain and the gate.
So, the effective resistance of the transistor will just be (Cf+Cs)/(Cfgm). Since the effective load
capacitance is CsCf/(Cs+Cf), the noise at the output due to the OTA will be:
6
( Cf + Cs ) g m Cf kT γ ( Cs + Cf )
vo2, gm 4kT
γ gm
=
=
4Cs Cf ( Cf + Cs ) Cf
Cs C f
kT  Cs   Cf 
v
γ   1 + 
=
C f  C f   Cs 
2
2
2
o , gm
Therefore, the total noise at the output will be:
vo2
=
kT  Cs

Cf  Cf
2

 Cf  

1
1
γ
+
+


 
 Cs  
 
Note that the above calculation assumed that the switches were ideal, and hence did not include any
noise sampled onto Cf during φ1. If the switches were not ideal, there would be an additional kT/Cf of
noise voltage variance at the output.
3.
Gain Boosted Cascode: This problem will focus on the gain-boosted cascode amplifier shown below.
To simplify the analysis, you can ignore the ro of the transistors and all of the capacitors except for
those explicitly drawn in the diagram.
v3
C2
v4
C3
M2
v2
M3
v1
C1
M1
a. What is the frequency response H(s) = v3(s)/v1(s) of this amplifier? Approximately what is the unity
gain frequency of the amplifier?
Solution:
As usual, let’s first draw the small signal model:
v4
C3
gm3v2
gm2(v2-v4)
gm1v1
C2
v3
v2
C1
7
The fastest way to figure out the frequency response of this amplifier is just to look at how much of
the current from M1 will make it to flow into the output load (i.e., C2). If we look at the input
impedance of M2 from node v2, it will be:
Zi,M 2 =
g
v4
= − m3
v2
sC3
1
g m2 (1 − v 4 v 2 )
sC
→ Zi,M 2 = 3
g m2 ( g m3 + sC3 )
Now we can just use the current divider between Zi,M2 and 1/sC1:
I out , M 1 =
I out , M 1 =
I out , M 1 =
1 sC1
IM1
1 sC1 + sC3 g m2 ( g m3 + sC3 )
g m2 ( g m3 + sC3 )
g m2 ( g m3 + sC3 ) + s 2 C1C3
1 + s ( C3 g m3 )
IM1
s ( C1C3 g m2 g m3 ) + s ( C3 g m3 ) + 1
2
IM1
From here, it is easy to see that:

  g m1 
1 + s ( C3 g m3 )
H (s ) = −  2
 s ( C C g g ) + s ( C g ) + 1   sC 
1 3
3
m2 m3
m3

 2 
As long as the amplifier is designed to be stable under unity-gain feedback, the dominant pole of the
circuit should be set by the output load, and so the unity gain frequency is still just gm1/C2.
b. Approximately what conditions are required to guarantee that the gain boosting feedback loop
maintains at least 45º of phase margin? You should provide your answer in terms of gm1, gm2, gm3,
C1, C2, and C3. What conditions would we obtain if at least 60º of phase margin are required
instead?
Solution:
The unity-gain frequency of the gain-boosting CS amplifier is approximately ωu = gm3/C3, and we
know that the pole at the source of the cascode is approximately ωp2= gm2/C1. Therefore, in order to
achieve 45º of phase margin, the non-dominant cascode pole must be greater than the unity-gain
frequency of the gain-boosting amplifier, i.e.:
g m2 g m3 .
≥
C1
C3
(1)
In fact, given the loop gain transfer function for the gain-boosting feedback loop
T (s ) =
g m3
1
,
sC3 s ( C1 g m2 ) + 1
we recall that the phase margin is defined as
ω  π
ω 
− arctan  u =
− arctan  u  .
 ω p2  2
 ω p2 
2




Therefore, to achieve at least 45º of phase margin, we need
φM = π + ∠T ( jωu )= π −
π
8
ω  π
ωu
− arctan  u  ≥
⇒
≤1


ω p2
2
 ω p2  4
π
(2)
as required in (1). If at least 60º of phase margin are required instead, we should modify (2) as
follows
ω  π
ωu
1 ,
− arctan  u  ≥
⇒
≤


ω p2
2
3
 ω p2  3
π
which finally gives
g
g m2
≥ 3 m3 .
C1
C3
c. Assuming this amplifier is used in unity gain feedback, what conditions are required to guarantee
that the gain boosting feedback loop does not introduce any significant pole-zero doublets that
might limit the settling response?
Solution:
What we’re basically trying to ensure is that the gain-boosting loop settles faster than the gainbandwidth of the overall amplifier. Therefore, we can pretty quickly say that:
g m3 g m1
≥
C3
C2
Another (more mathematical) way of arriving at this constraint is realizing that open-loop zeros do
not move under feedback. This means that when if we close the entire amplifier in unity gain
feedback, if we want to ensure that there is no closed-loop pole-zero doublet inside the unity-gain
bandwidth, the zero (which is at gm3/C3) must be outside the closed-loop bandwidth (which is
gm1/C2).
d. Assume now that C1=C3=50 fF, C2=1.5 pF, V*M1 = 180 mV, and V*M2 = 90 mV. In order to achieve
at least 60º phase margin and the criteria from part c), what are the minimum and maximum
gm3/gm1?
Solution:
Combining the solutions from b) and c) we get:
gm2
g
g
≥ m 3 ≥ m1 ⇒
C
C2
3C1
3
gm2
g
g
≥ m 3 ≥ m1
50
1.5
fF
pF
3 ⋅ 50 fF
(3)
We also know that ID1=ID2, and so:
=
g m1
2 I D1
2I D
=
V *M 1 180mV
=
gm2
2I D2
2I D
=
V *M 2 90mV
g m 2 = 2 g m1
9
Plugging back in to the inequality in (3), we finally get:
2 g m1
0.1
≥ g m3 ≥
g m1
3
3
1.15 ≥ g m 3 g m1 ≥ 0.034
10