ELECTRONIC CIRCUITS
QUESTION BANK
UNIT-1& UNIT-2 Syllabus
UNIT-1
SINGLE STAGE AMPLIFIERS DESIGN AND ANALYSIS
Review of CE, CB, CC & CS amplifiers-Classification of Amplifiers, Distortion in amplifiers- Approximate analysis, CE, CB, CC
amplifiers.
UNIT-1I
BJT & FET FREQUENCY RESPONSE
Logarithms-Decibels-General frequency consideration- Low frequency analysis-Low frequency response of BJT amplifiers-Low
frequency response of FET amplifiers-Miller effect capacitance-High frequency response of BJT amplifier-Square wave testing.
Questions
1.(a) Draw the small-signal equivalent circuit for an emitter follower stage at high frequencies and Obtain the voltage gain.
(b) Derive the expressions for fβ and fT..
(May/June 2009,set-1)
2.(a) Discuss the effect of coupling capacitor (Cc) on low frequency response of CE amplifier. [6]
(b) For a CB transistor amplifier driven by a voltage source of internal resistance Rs = 1.2k the load impedance is resistor RL = 1k.
The h-parameters are hib=22., hfb= - 0.98, hob= 0.5 µA/V, hrb= 3 × 10−4 . Calculate AV , AI,and RI .
(June 2009,set-1)
3. (a) Draw the circuit diagram of common source amplifier with unbypassed Rs and derive voltage gain and output resistance.
[2+3+3]
(b) Determine the overall voltage gain of the cascode amplifier shown in figure 6 with RB1=7.5K, RB2=6.8K, RB3=3.3K, RE=1.3K,
RC=2.2K. For the two transistors β1= β2=120 and supply voltage VCC=18V.
(June 2009,set-3)
4. (a) Draw the circuit diagram of common source amplifier and derive expressions for voltage gain and output resistance. [2+3+3]
(b) For the circuit shown in figure 6b, determine AI , AV , RI and R0 using reasonable approximations. The h-parameters for the
transistor are given as hie=2K, hfe=100, hoe= 10−5mhos, hre is negligible.
Figure 6b
(Aug/Sep 2008,set-4)
5. (a) Draw the low frequency small signal model of a transistor in CB and CE configurations and explain significance of each model.
(b) The amplifier circuit shown in figure 6b uses a transistor with hfe=100, hie=3.37K.Calculate AI , AV , RI .
Figure 6b
(Aug/Sep 2008,set-2)
6. (a) Explain the method of evaluating h parameters for a transistor in CC configuration.
(b) A CB amplifier is driven by a voltage source of internal resistance Rs=1k.The load impedance is RL=1K. The transistor
parameters are hib= 22, hfb= -0.98, hrb=2.9×10−4, hob= 0.5µA/V. Compute current gain, voltage gain, input and output impedance
of the amplifier. (June 2009,set-3)
7. (a) Draw the circuit diagram of small signal CE amplifier circuit and give its equivalent hybrid model. What is the role of Cc and
Ce.
(b) Obtain frequency response of CE amplifier circuit and find out its band width. What is the impact of CC and CS on the band
width?
(RR:Apr/May 2006,set-1)
8. (a) Write a short notes on millers theorem.
(b) Analyse a single stage transistor amplifier using h - parameters. ( May/Jun 2008,set-1)
9. (a) Draw the low frequency hybrid equivalent. Circuit for CE & CB amplifier.
(b) Give the approximate h-parameter conversion formulae for CB and CC configuration in terms of CE.
(c) Give the advantages of h-parameter analysis.
( May/Jun 2008,set-2&4)
(d) Give the procedure to form the approximate h – model from exact h – modelof amplifier.
10. (a) Compare AV ,Ai,Ri&R0 of CE, CB and CC configuration.
(b) The h-parameters of a transistor used in a CE circuit are hie = 1.0 K , hre= 10×10−4, hfe = 50, hoe = 100 K. The load resistance
for the transistor is 1 K in the collector circuit. Determine Ri,Ro,AV ,Ai in the amplifier stage (Assume Rs = 1000 )
( May/Jun 2008,set-3)
11. (a) Draw the high frequency small signal model of a transistor in CE configuration and explain significance of each component.
[3+5]
(b) A transistor with hie=1.1K, hfe=50, hre=205X10−4 , hoe=25µA/V is connected in CE configuration as shown in figure 6.
Calculate AI , AV , RI , R0.
Figure 6
( Apr/May ’07,set-4)
12.Sketch the small-signal high-frequency circuit of a CS amplifier and derive the expression for the voltage gain.
(May/June2009 ,set-3)
13. (a) Prove that (i) hfe=gm r b′e for a Hybrid π model of CE amplifier.
(b) How does a Ce and Cc vary with | Ic | and | VCE |.
(c) How does gm vary with | Ic | and | VCE |, T.
(February 2007,set-1)
UNIT-3 Syllabus
FEEDBACK AMPLIFIERS
Concept of feedback, Classification of feedback amplifiers, General characteristics of negative feedback amplifiers, Effect of
feedback on Amplifier characteristics-Voltage series-Voltage shunt, Current series and Current shunt Feedback configurationsSample problems.
Questions
1.(a) State three fundamental assumptions which are made in order that the expression Af =A/(1+Aβ) be satisfied exactly. [8]
(b) An Amplifier has a value of Rin=4.2K, AV =220 and β=0.01. Determine the value of input resistance of the feedback amplifier.
[4]
(c) The amplifier in part (a) had cut-off frequencies f1=1.5KHz and f2=501.5KHz before the feedback path was added. What are the
new cut-off frequencies for the circuit?
(Jun’09,set-1&4 )
2. (a) Define the following terms in connection with feedback [3+3+3]
i. Return difference,fb
ii. Closed loop gain
iii. Open loop gain
(b) Referring to the figure 7 shown below, it has RS=600, RL=2K, hfe=80 and hie=5K, RB=40K Calculate Avf , Av, Rif ,Rof .
Figure 7
(Jun’09,set-2)
3.(a) Explain negative feedback with the help of the emitter follower as an example. Why is the emitter follower so called? [8]
(b) The gain of an amplifier is decreased to 10,000 with negative feedback from its gain of 60,000. Calculate the feedback factor.
Express the amount of negative feedback in dB. (Jun’09,set-3)
4.(a) What do you understand by feedback in amplifiers? Explain the terms feedback factor and open loop gain. [4+2+2]
(b) Calculate the gain, input impedance, output impedance of voltage series feedback amplifier having A=300, Ri=1.5K,RO=50K
and β=1/12.
( Aug/Sep 2008,set-1)
5. (a) Draw the circuit diagram of voltage shunt feedback amplifier and derive expressions for voltage gain and feedback factor.
(b) An amplifier has midband gain of 125 and a bandwidth of 250KHz.
i. If 4% negative feedback is introduced, find the new bandwidth and gain
ii. If bandwidth is restricted to 1MHz, find the feed back ratio.
( Aug/Sep 2008,set-2 )
6.(a) Define Desensitivity
(b) For large values of D, what is Af? What is the significance of this result? [5]
(c) An Amplifier has a mid-frequency gain of 100 and a bandwidth of 200KHz.
i. What will be the new bandwidth and gain if 5% negative feedback is introduced?
ii. What should be the amount of negative feedback if the bandwidth is to be restricted to 1MHz?
(Aug/Sep 2008,set-3)
7. (a) Explain with circuit diagram a negative feedback amplifier and obtain expressions for its closed loop gain. [4+4]
(b) The gain of an amplifier is decreased to 1000 with negative feedback from its gain of 5000. Calculate the feedback factor and the
amount of negative feedback in dB. (Aug/Sep 2008,set-3)
8. (a) Discuss briefly about various characteristics of an amplifier which are modified by negative feedback. [8]
(b) An RC coupled amplifier has a voltage gain of 1000. f1=50Hz, f2=200KHz and a distortion of 5% without feedback. Find the
amplifier voltage gain,f11, f21 and distortion when a negative feedback is applied with feedback ratio of 0.01.
(February 2008,set-1&3)
9. (a) How does negative feedback reduce distortion in an amplifier. [8]
(b) An Amplifier has a voltage gain of 400, f1=50Hz, f2=200KHz and a distortion of 10% without feedback. Determine the voltage
gain, f1f , f2f and Df when a negative feedback is applied with feedback ratio of 0.001.
(February 2008,set-2)
10. (a) Explain the concept of feedback as applied to electronic amplifier circuit. What are the advantages and disadvantages of
positive and negative feed- back? [4+3+3]
(b) An Amplifier has a voltage gain of 1000. With negative feedback, the voltage gain reduces to 10. Calculate the fraction of the
output that is fedback to the input.
(February 2008,set-4)
11. (a) Calculate voltage gain, input impedance and output impedance of a CE amplifier with current-shunt negative feedback.
(b) Explain how negative feedback can increase the bandwidth of an amplifier. (Jun’09,set-1)
12. (a) What is the effect of negative feedback on the output noise level of an amplifier? Does it improve the signal-to-noise ratio?
(b) An amplifier with negative feedback has a gain of -100. It is found that without feedback, an input signal of 50mV is required to
produce a given output, whereas with feedback in the input signal must be 0.6V for the same output. Find the amount of feedback in
decibels and the values of open loop
gain and feedback factor.
(Jun’09,set-2)
13. (a) Explain how the nonlinear distortion can be reduced by using negative feedback in an amplifier.
(b) Calculate voltage gain, input impedance and output impedance of a CE amplifier with Voltage-Series negative feedback.
(Jun’09,set-4)
14. (a) Explain the concept of feedback as applied to electronic amplifier circuits. What are the advantages and disadvantages of
positive and negative feedback?
(b) With the help of general block diagram explain the term feedback.
(c) Define the following terms in connection with feedback. [6+4+6]
i. Closed loop voltage gain.
ii. Open loop voltage gain.
(February 2008,set-1; Aug/Sep 2007,set-2)
15. Show that for voltage shunt feedback amplifier transresistance gain, Ri and Ro are decreased by a factor (1+Aβ) with feedback.
(February 2008,set-2)
UNIT-4 Syllabus
OSCILLATORS
Condition for oscillations. RC and LC type Oscillators, Crystal oscillators, Frequency and amplitude stability of oscillators,
Generalized analysis of LC oscillators, Quartz, Hartley, and Colpitts Oscillators, RC-phase shift and wien-bridge oscillators.
Questions
1. (a) Show that the gain of Wien bridge oscillator using BJT amplifier must be atleast 3 for the oscillations to occur.
(b) In a transistorized Hartley oscillator the two inductances are 2mH and 20µH while the frequency is to be changed from 950KHZ
to 2050KHZ. Calculate the range over which the capacitor is to be vaired.
(RR:June 2009,set-4; Aug/Sep 2008,set-3&4;
RR:Aug/Sep’08 set-1)
2. (a) Discuss and explain the basic circuit of an LC oscillator and derive the condition for the oscillations?
(b) A crystal has L=2H, C=0.01PF and R=2k. Its mounting capacitance is 2PF. Calculate its series and parallel resonating frequency.
(RR:June 2009,set-1; February 2008,set-4)
3. (a) What type of feedback is employed in oscillators? And what are the advantages. Discuss the conditions for sustained
oscillations.
(b) Find the capacitor C and hfe for the transistor to provide a resonating frequency of 10KHZ of a phase-shift oscillator. Assume
R1=25k, R2=60k,Rc=40k, R=7.1k and hie=1.8k. (RRL:June 2009,set-2)
4. (a) Draw the circuit diagram of a RC phases shift oscillator using BJT. Derive the expression for frequency of oscillators.
(b) Classify different type of oscillators based on frequency range.
(c) Why RC oscillators are not suitable for high frequency applications. (Aug/Sep 2008,set-2; February 2008,set-2&3; 5times)
5. (a) Derive the expression for frequency of oscillations in RC-phase shift oscillator using BJT.
(b) A crystal has L=0.1H, C=0.01PF, R=10k and CM=1PF. Find the series resonance and Q-factor.
(February 2008,set-1)
6. (a) Derive an expression for frequency of oscillation of transistorized Colpitts oscillator.
(b) A quartz crystal has the following constants. L=50mH, C1=0.02PF, R=500 and C2=12PF. Find the values of series and parallel
resonant frequencies. If the external capacitance across the crystal changes from 5PF to 6PF, find the change in frequency of
oscillations. (RR:Aug/Sep’08,set-3)
7. (a) Prove that oscillations will not be sustained if, at the oscillator frequency, the magnitude of the product of the transfer gain and
feedback factor are less than unity.
(b) Explain how to stabilize the amplitude against variation due to fluctuations occasioned in wein bridge oscillator?
(June 2009,set-4)
8. For the feedback network shown in figure 8 find the transfer function and the input impedance. If this network is used in a phase
shift oscillator, find the frequency of oscillation and the minimum amplifier voltage gain. Assume that the network does not load
down the amplifier.
(June 2009,set-1)
9.(a) Classify various oscillators based on O/P waveforms, circuit components, operating frequencies and feedback used.
(b) A phase shift oscillator is to be designed with FET having gm = 5000µs, rd=4k while the resistance in the feedback circuit is 9.7k.
Select the proper value of C and RD to have the frequency of oscillations as 5KHZ.
(RR:February 2008,set-1)
UNIT-5 Syllabus
LARGE SIGNAL AMPLIFIERS
Class-A Power Amplifier, Maximum Value Efficiency of Class-A Amplifier, Transformer coupled amplifier- Push Pull AmplifierComplimentary Symmetry Circuits (Transformer Less Class B Power Amplifier) – Phase Inverters, Transistor Power Dissipation,
Thermal Runway, Heat sinks.
Questions
1.(a) Explain about Class-B push pull amplifier and its advantages, with neat diagram.
(May’09,set-1)
(b) Explain the Complementary symmetry power amplifier, with neat diagram.
2. (a) Explain about transformer-coupled class-A power amplifier. (6)
(May’09,set-2)
(b) Derive the expression for efficiency to class-C power amplifier.
3. What is the drawback of class B amplifier. How it is going to overcome using class AB amplifier with neat
diagram.
(May’09,set-3)
4. How even harmonics is eliminated using push-pull circuit, derive the expression.
(May’09,set-4)
5.(a) Explain the classification of power amplifiers based on class of operation and compare them.
(b) A power amplifier supplies 3w to a load of 6K. The zero signal d.c collector current in 55 mA and the collector current with
signal in 60mA. How much is the percentage in second harmonic distortion?
(Nov’08,set-1)
6.(a) Explain with neat circuit diagram, the working of a Transformer coupled class A power amplifier. What are its advantages and
disadvantages?
(Nov’08,set-2)
(b) A class B, push pull amplifier drives a load on 16, connected to the secondary of the ideal transformer. The supply voltage in 25V.
If the turns on the primaryin 200 and the No. of turns the secondary in 50, Calculate maximum power o/p, d.c power input, efficiency
and maximum power dissipation per transistor.
7.(a) Draw a neat circuit diagram of pushpull class B amplifier. Explain its working.
(b) In a class B complementary power amplifier Vcc=+15V, -Vcc=15V and RL=4. Calculate
i. maximum a.c power which can be developed
ii. collector dissipation while developing maximum a.c power
iii. efficiency
iv. maximum power dissipation per transistor.
(Nov’08,set-3)
8. Prove that the maximum efficiency of a class B amplifier in 78.5%. (Nov’08,set-4)
9. (a) Draw the circuit diagram of a push pull amplifier and explain its working.
(b) Derive the equation for efficiency of a class B amplifier.
(Feb’07,set-1&2)
10.(a) Explain about heat sinks. Explain the term Thermal Resistance. Give the sketches of heat sinks.
(b) What is the Junction to ambient Thermal Resistance for a device dissipating 600 mw into an ambient temperature of 500C and
operating at a junction temperature of 1100C?
(Feb’07,set-3)
11. (a) What is thermal resistance? What is the unit of thermal resistance.
(b) Explain the commonly available heat sinks.
(Feb’07,set-4)
(a) Explain why the complimentary symmetry power amplifier has become more popular in modern circuits.
(b) Draw a practical circuit of a complimentary symmetry push pull amplifier circuit? Explain its function.
(Nov’06,set-2)
12.(a) How are amplifiers classified based on the bias conditions.
(b) Derive the equation for power output and conversion efficiency of a class A series fed Amplifier.
(Nov’06,set-3)
13. (a) Distinguish between large signal and small signal amplifiers.
(b) What are the advantages and disadvantages of push pull amplifier.
(Nov’06,set-4)
UNIT-6 Syllabus
LINEAR WAVESHAPING : High pass, low pass RC circuits, their response for sinusoidal, step, pulse, square and ramp inputs.
CLIPPERS AND CLAMPERS: Diode clippers, Transistor clippers, clipping at two independent levels, Comparators, applications
of voltage comparators, clamping operation, Clamping circuit taking source and diode resistances into Account, , Clamping circuit
theorem, practical clamping circuits, effect of diode characteristics on clamping voltage.
Questions
1. (a) The periodic ramp voltage shown is applied to a low pass RC circuit. Find the equations from which to determine the steady
state output waveform.
Supplementary Examinations, May 2005
Figure 1:
(b) If T1=T2=RC, find the maximum and minimum value of the output voltage and plot this waveform.
2.
Draw the RC high pass circuit and explain its working with step voltage input.
Supplementary Examinations, November 2006
3. (a) Three low pass RC circuits are in cascade and isolated from one another by ideal buffer amplifiers. Find the expression for the
output voltage as a function of time if the input is a step voltage. [10]
(b) Find the rise time of the output in terms of RC in the above case. [6]
Supplementary Examinations, November 2005
4. (a) A Current pulse of amplitude I and width Tp is applied to a parallel RC combination, (C input side). Plot to scale the waveforms
of the current iC for
the cases
i. Tp < RC
ii.Tp = RC
iii.Tp > RC
(b) Compare RC low pass circuit with RC high pass circuit. Supplimentary Examinations, May/Jun 2009
5 (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8]
Nov 2008,set4
6. (a) A square wave whose peak-to-peak value is 1V, extends ±0.5V with reference to ground. The half period is 0.1 sec This voltage
impressed upon an R.C. differentiating circuit whose time constant is 0.2 sec. Determine the maximum and minimum values of the
output voltage in the steady state.
(b) Draw the response of high pass circuit for square wave and derive the expression for percentage tilt. [8+8]
Nov 2008,set2
7. (a) Prove that for any periodic input wave form the average level of the steady state output signal form the RC high pass circuits is
always Zero.
(b) Prove the above statement for different periodic input waveforms. [8+8]
May/Jun 2009,set2
8. (a) A symmetrical square wave of peak to peak amplitude V and frequency ‘f ’ is applied to a high pass RC circuit. Find the
percentage tilt. [12]
(b) How can this tilt be reduced?
November 2006,set3
9. (a) A pulse is applied to a lowpass RC circuit. Prove by direct integration that the area under the pulse is same as the area under the
output waveform across the capacitor. Explain the result.
November 2006,set4
10. (a) A square wave whose peak-to-peak value is 1V extends ± 0.5 V with respect to ground. The duration of the positive section is
0.1 Sec and of the negative section is 0.2 sec. If this wave form is impressed up on an RC differentiating circuit whose time constant
is 0.2 sec; what are the steady state maximum and minimum values of the output waveform? [10]
(b) Prove that the area under the positive section is equal to the area under the negative section of the output waveform of a high- pass
RC circuit. [6]
Feb 2008,set3
11.(a) What is synchronized clamping? Explain.
(b) Design a diode clamper circuit to clamp the positive peaks of the input signal at zero level. The frequency of the input signal is
500 Hz.
May 2005
12. (a) State and prove clamping circuit theorem. [6]
(b) A square wave input as shown in figure 2b below is applied to the clamping circuit. Sketch the steadystate output waveform
and derive the necessary expressions. [10]
Figure
Supplementary Examinations, November 2006
13. (a) Design a clipping circuit with ideal components, which can give the waveform
shown in figure 1 below for a sinusoidal input. [8]
Figure 1:
(b) Design a diode clamper to restore a d.c level of +3 Volts to an input signal of peak to peak value of 10 Volts. Assume drop across
diode is 0.6 Volts. As shown in the figure (figure 2)below [8]
Figure 2:
Nov 2005
14. (a) Draw the diode comparator circuit and explain the operation of it when ramp input signal is applied.
(b) Explain the operation of two level slicer.
May/Jun 2009
15. (a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer
characteristic.
(b) Draw the circuit diagram of emitter coupled clipper. Draw its transfer characteristics indicating all intercepts, slopes and voltage
levels derive the necessary equations.
November 2007
16. Give the circuits of series clipper circuits and explain their operation with the help of transfer characteristics.
Feb 2008
17. (a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer
characteristic.
(b) For the circuit shown in figure 1 below:
Figure 1:
If R = 1K, VR2 = 10V, VR1 = 7 V
RF = 0 and Rr =infinite
i. Sketch the transfer characteristic
ii. If Vi = 20 sin wt sketch the input and output waveforms.
18. Explain the principle of clamping. Discuss the effect of source impedance, shunt resistance and cut in voltage.
19. (a) Draw the basic circuit diagram of a DC restorer circuit and explain its operation. Sketch the out put wave form for a sinusoidal
input.
(b) Draw the basic circuit diagram of positive peak clamper circuit and explain its operation. [8+8]
May/Jun 2009,set3
20.(a) Give the circuits of different types of shunt clippers and explain their operation with the help of their transfer characteristics.
(b) Draw the diode differentiator comparator circuit and explain the operation of it when ramp input signal is applied. [8+8]
Nov2007,set3
UNIT-7 Syllabus
SWITCHING CHARACTERISTICS OF DEVICES : Diode as a switch, piecewise linear diode characteristics, Diode Switching
Times,Transistor as a switch, Break down voltage consideration of transistor, saturation parameters of Transistor and their variation
with temperature, transistor-switching times
Questions
1.(a) Explain the phenomenon of “latching” in a transistor switch.
(b) A transistor has fT = 50 MHz, 4FE=40, Cb0c=3PF and operates with Vcc=12V and Rc=500W . The transistor is operating
initially in the neighborhood of the cutin point. What base current must be applied to drive the transistor to saturation in 1µ sec?
November2006,set 2&3 ,May 2005
2. (a) Explain the behaviour of a BJT as a switch in electronic circuits. Give an example.
(b) Write a short note on the switching times of transistor. [8+8]
Nov 2008
3. (a) Explain the behavior of a BJT as a switch. Give Applications. [8]
(b) Write a short note on switching times of a transistor. [8]
Feb 2008 set1.
4. (a) Explain the terms pertaining to transistor switching characteristics.
i. Rise time.
ii. Delay time.
iii. Turn-on time.
iv. Storage time.
v. Fall time.
vi. Turn-off time.
(b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents. [6+10
November 2007 set1
5. Write Short notes on:
(a) Diode switching times
(b) Switching characteristics of transistors
(c) FET as a switch.
May/Jun 2009 set1
6. (a) Explain in detail the junction diode switching times. [8]
(b) Give a brief note on piecewise linear diode characteristics.
November 2005
7. (a) Sketch neatly the waveforms of current & voltages for a transistor switch with capacitance loading circuit.
(b) What are catching diodes? [12+4]
November 2008,set3
8. Write Short notes on:
(a) Diode switching times
(b) Switching characteristics of transistors
(c) FET as a switch. [4+8+4]
November 2008,set4
9. (a) Explain how transistor can be used as a switch in the circuit, under what condition a transistor is said to be ‘OFF’ and ‘ON’
respectively.[6]
(b) A germanium transistor is operated at room temperature in the CE configuration. The supply voltage is 6 V, the collector circuit
resistance is 200 and the base current is 20 percent higher than the minimum value required to drive the transistor into saturation.
Assume the following transistor parameters:
I co =5µA,
I EO =2µA,
h FE =100, and r bb ′=250 . Find V BE (Sat) and V CE (Sat). November 2006,set2
10. (a) Explain the phenomenon of “latching” in a transistor switch. [6]
(b) A transistor has f T = 50 MHz, h FE =40, C bc =3PF and operates with V cc =12V and Rc =500 . The transistor is operating
initially in the neighborhood of the cutin point. What base current must be applied to drive the transistor to saturation in 1µ sec? [10]
November 2006,set 2&3
11. (a) Describe the switching times of BJT by considering the charge distribution across the base region. Explain this for cut off,
active and saturation regions.
(b) Define the following terms:
i. storage time
ii. delay time
iii. rise time
iv. fall time.
November 2006,set4
12. (a) Explain the behavior of a BJT as a switch. Give Applications. [8]
(b) Write a short note on switching times of a transistor. [8]
February 2008,set3
13. (a) Explain how transistor can be used as a switch in the circuit, under what condition a transistor is said to be ‘OFF’ and ‘ON’
respectively. [6]
(b) A germanium transistor is operated at room temperature in the CE configuration. The supply voltage is 6 V, the collector-circuit
resistance is 200 and the base current is 20 percent higher than the minimum value required to drive the transistor into saturation.
Assume the following transistor parameters: Ico=-5µA, IEO=-2µA, hFE=100, and r bb′ =250 . Find V BE(Sat) and V CE(Sat).
February 2008,set4
UNIT-8 Syllabus
MULTIVIBRATORS : Analysis and Design of Bistable, Monostable, Astable Multivibrators and Schmitt trigger using transistors.
Questions
1.Explain how to draw the various waveforms and calculate their voltage levels in an emitter coupled monostable multi.
May 2005
2. (a) Discuss the symmetrical and Asymmetrical triggering in case of Bistable transistor multivibrator.
(b) For the given circuit ,find UTP & LTP. What is this circuit called? Data given
h fe (min)=40, V CE (sat)=0.1 V, U BE (sat)=0.7 V V r =0.5V, V BE (active)=0.6V.
November 2006,set1
3. (a) What is a direct connected binary circuit? Explain the direct connected binary with the help of a circuit diagram. [8]
(b) Mention the advantages and disadvantages of the above. Mention its use., November 2005
4. (a) Explain different triggering methods of binary circuits.
(b) A collector coupled Fixed bias binary uses NPN transistors with hFE = 100.The circuit parameters are VCC = 12v, VBB = -3v,
RC = 1k , R1 = 5k , and R2 = 10 k . Verify that when one transistor is cut-off the other is in saturation. Find the stable state currents
and voltages for the circuit. Assume
for transistors VCE(sat) = 0.3V and VBE(sat) = 0.7V. [8+8]
5. (a) With the help of a diagram explain the working of a fixed Bias transistor binary. [6]
(b) The fixed bias binary uses n-p-n silicon transistors with hfe=20. Assume that Vcc=12volts, Vbb=3volts,Rc=1k, R1=10k R2=20k.
Find the stable state current and voltages if Vce(sat)=0 and Vbe(sat)=0. [10]
February 2008 set1
6. (a) Draw the circuit diagram of selfbias with symmetrical triggering using diodes. Explain the working of the same.
(b) Compare between triggering at base and collectors.
7. What is a monostable multivibrator? Explain with the help of a neat circuit diagram the principle of operation of a monostable
multi, and derive an expression for pulse width. Draw the wave forms at collector and Bases of both transistors. [16]
November 2008,set1&3
8. Design a Schmitt trigger circuit using n-p-n silicon transistors to meet the following specifications:
Vcc=12v, UTP=4v, LTP=2v, hfe=60, Ic2=3mA. Use relevant assumptions and the empirical relationships. [16]
February 2008,set2
10. (a) What is an astable multivibrator? Explain. How does this differ with the
other multivibrators? [6]
(b) Derive an expression for the period of oscillations of astable multivibrator.[6]
(c) Bring out the effect of supply voltage, Junction voltages and temperature on the period of oscillations of the astable multi. [4]
February 2008,set4
11. A transistor Schmitt trigger uses npn silicon transistors with h fe (min)=30 ;V ce (sat)=0.1v,V BE (sat)=0.7v ;V cc =12v,R c1 =2k
R c 2 =1k, R 1 =20kW, R 2 =100kW, R e =500W,R S =2kW.
a) Draw the circuit diagram. Calculate all the steady state currents & voltages.
(b) Determine UTP & LTP. [4]
(c) Find Hystersis voltage. [2]
(d) Sketch the output waveform if a triangular waveform as shown is applied to the circuit. [2]
November 2006,set2
12. (a) Design a collector coupled as table multivibrator to meet the following Specifications:
f =10KHZ,V CC =12V,I C (sat)=4mA and h FE (min)=20.Assume that V CE (sat)=0.3V and V BE (sat)=0.7V. [8]
(b) An a stable multi is used as a voltage to frequency converter. Find the ratio of V V CC ,if the voltage to frequency converter
generates oscillations of frequency thrice that when V=V CC .
November 2006,set3
13. Design a Monostable circuit that produces a pulse width of 10 m sec. Assume h fe =30, V CE (sat)=0.3V, V BE sat=0.7V I c
=5mA, V cc =6V. V BB =1.5V, Q 1 ON and Q 2 OFF. November 2006,set4
14. (a) Draw the circuit of a self-biased binary using NPN transistors and explain its working.
(b) Design an astable multivibrator to generate 5kHz square wave with a duty cycle of 40% and if amplitude 12V. Use NPN transistor
having hFE = 100, VBesat = 0.7V, VCEsat = 0.2, ICmax = 100mA. Show the waveforms seen at both the collector and bases. [8+8]
May/Jun 2009,set2
15. (a) Design a collector coupled transistor monostable multivibrator to produce a time delay of 100 µsec. Use transistors have hFE
of 250. Use ±12V sources, VCE(sat) = 0.3V, VBE(sat) = 0.7V and VBEcutoff = 0V
(b) Show that the astable multivibrator works as voltage controlled oscillator. May/Jun 2009,set3
16. (a) What are the different types of multivibrators? Name them and sketch their circuits.
(b) Design an astable multi for an o/p amplitude of 15V and square wave frequency of 500Hz. Assume hFEmin = 50, ICsat = 5mA and
VCEsat = 0. [8+8]
May/Jun 2009,set4
17. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Derive the Expressions for its UTP and LTP.
(b) Explain how an Schmitt trigger circuit acts as a comparator.
November 2007,set3