Dual/Quad Low Power, High Speed
JFET Operational Amplifiers
OP282/OP482
Active filters
Fast amplifiers
Integrators
Supply current monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current under 250 µA per
amplifier. These unity-gain stable amplifiers have a typical gain
bandwidth of 4 MHz.
The JFET input stage of the OP282/OP482 ensures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 V of each supply, low
power consumption, and high slew rate, the OP282/OP482
are ideal for battery-powered systems or power restricted
applications. An input common-mode range that includes the
positive supply makes the OP282/OP482 an excellent choice for
high-side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead narrow SOIC and MSOP packages. The OP482 is
available in PDIP and narrow SOIC packages.
1
8
V+
–IN A
2
7
OUT B
+IN A
3
6
–IN B
V–
4
5
+IN B
OP282
OP-482
00301-001
OUT A
Figure 1. 8-Lead Narrow-Body SOIC (S-Suffix) [R-8]
OUT A 1
–IN A 2
OP282
+IN A 3
TOP VIEW
(Not to Scale)
V– 4
8
V+
7
OUT B
6
–IN B
5
+IN B
00301-002
APPLICATIONS
PIN CONNECTIONS
Figure 2. 8-Lead MSOP [RM-8]
OUT A
1
–IN A
2
+IN A
3
V+
4
+IN B
5
–IN B
6
OUT B
7
14 OUT D
– +
13 –IN D
+ –
12 +IN D
OP482
11 V–
10 +IN C
– +
+ –
9
–IN C
8
OUT C
00301-003
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier max
Low offset voltage: 3 mV max
Low bias current: 100 pA max
Fast settling time
Common-mode range includes V+
Unity-gain stable
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
OUT A
1
14
OUT D
–IN A
2
13
–IN D
+IN A
3
12
+IN D
OP482
V+
4
11
V–
+IN B
5
10
+IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
00301-004
FEATURES
Figure 4. 14-Lead Narrow-Body SOIC (S-Suffix) [R-14]
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
OP282/OP482
TABLE OF CONTENTS
Specifications..................................................................................... 3
High-Side Signal Conditioning ................................................ 12
Electrical Characteristics ............................................................. 3
Phase Inversion........................................................................... 12
Absolute Maximum Ratings............................................................ 4
Active Filters ............................................................................... 12
ESD Caution.................................................................................. 4
Programmable State-Variable Filter......................................... 13
Typical Performance Characteristics ............................................. 5
Outline Dimensions ....................................................................... 14
Applications Information .............................................................. 12
Ordering Guide .......................................................................... 16
REVISION HISTORY
10/04—Data Sheet Changed from Rev. E to Rev. F
Deleted 8-Lead PDIP .........................................................Universal
Added 8-Lead MSOP .........................................................Universal
Changes to Format and Layout.........................................Universal
Changes to Features.......................................................................... 1
Changes to Pin Configurations....................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications ................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Table 3............................................................................ 4
Added Figure 5 through Figure 20; Renumbered
Successive Figures............................................................................. 5
Updated Figure 21 and Figure 22 ................................................... 7
Updated Figure 23 and Figure 27 ................................................... 8
Updated Figure 29 ............................................................................ 9
Updated Figure 35 and Figure 36 ................................................. 10
Updated Figure 43 .......................................................................... 11
Changes to Applications Information.......................................... 12
Changes to Figure 44...................................................................... 12
Deleted OP282/OP482 Spice Macro Model Section.................... 9
Deleted Figure 4................................................................................ 9
Deleted OP282 Spice Marco Model ............................................. 10
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
10/02—Data Sheet Changed from Rev. D to Rev. E
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin......................................1
Edits to Ordering Guide ...................................................................3
Edits to Outline Dimensions......................................................... 11
9/02—Data Sheet Changed from Rev. C to Rev. D
Edits to 14-Lead SOIC (S-Suffix) Pin .............................................1
Replaced 8-Lead SOIC (S-Suffix)................................................. 11
4/02—Data Sheet changed from Rev. B to Rev. C
Wafer Test Limits Deleted ................................................................2
Edits to Absolute Maximum Ratings ..............................................3
Dice Characteristics Deleted............................................................3
Edits to Ordering Guide ...................................................................3
Edits to Figure 1.................................................................................7
Edits to Figure 3.................................................................................8
20-Position Chip Carrier (RC Suffix) Deleted ........................... 11
Rev. F | Page 2 of 16
OP282/OP482
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grade.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
VOS
OP282
OP282, −40°C ≤ TA ≤ +85°C
OP482
OP482, −40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V1
VCM = 0 V
VCM = 0 V1
VOS
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
CMRR
AVO
Offset Voltage Drift
Bias Current Drift
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
Open-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
−11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C
RL = 10 kΩ
RL = 10 kΩ, −40°C ≤ TA ≤ +85°C
Min
ZOUT
Max
Unit
0.2
3
4.5
4
6
100
500
50
250
+15
mV
mV
mV
mV
pA
pA
pA
pA
V
dB
V/mV
V/mV
µV/°C
pA/°C
0.2
3
1
−11
70
20
15
∆VOS/∆T
∆IB/∆T
VOH
VOL
ISC
Typ
90
10
8
RL = 10 kΩ
RL = 10 kΩ
Source
Sink
f = 1 MHz
PSRR
ISY
VS
VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C
VO = 0 V, −40°C ≤ TA ≤ 85°C
SR
BWP
tS
GBP
ØO
RL = 10 kΩ
1% distortion
To 0.01%
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
+13.5
3
+13.9
−13.9
10
−12
200
25
210
±4.5
7
−8
316
250
±18
V
V
mA
mA
Ω
µV/V
µA
V
9
125
1.6
4
55
V/µs
kHz
µs
MHz
Degrees
1.3
36
0.01
µV p-p
nV/√Hz
pA/√Hz
The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
Rev. F | Page 3 of 16
−13.5
OP282/OP482
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration
Storage Temperature Range
P-Suffix (N), S-Suffix (R), RM Packages
Operating Temperature Range
OP282G, OP282A, OP482G
Junction Temperature Range
P-Suffix (N), S-Suffix (R), RM Packages
Lead Temperature Range (Soldering 60 sec)
1
Ratings
±18 V
±18 V
36 V
Indefinite
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +85°C
−65°C to +150°C
300°C
For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Table 3.
Package Type
8-Lead MSOP [RM]
8-Lead SOIC (S-Suffix) [R]
14-Lead PDIP (P-Suffix) [N]
14-Lead SOIC (S-Suffix) [R]
1
θJA1
206
157
83
104
θJC
44
56
39
36
Unit
°C/W
°C/W
°C/W
°C/W
θJA is specified for the worst-case conditions; i.e., θJA is specified for device in
socket for CERDIP, PDIP; θJA is specified for device soldered in circuit board
for SOIC or MSOP package.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 4 of 16
OP282/OP482
TYPICAL PERFORMANCE CHARACTERISTICS
70
180
90
20
45
0
0
CLOSED-LOOP GAIN (dB)
40
50
PHASE (Degree)
135
40
AVCL = 100
30
AVCL = 10
20
10
AVCL = 1
0
–10
–45
–20
VS = ±15V
TA = 25°C
60
60
–20
100k
FREQUENCY (Hz)
10k
–90
10M
1M
–30
1k
00301-005
–40
1k
Figure 5. OP282 Open-Loop Gain and Phase vs. Frequency
10k
100k
FREQUENCY (Hz)
1M
30
VS = ±15V
RL = 10k
40
VS = ±15V
RL = 10k
CL = 50pF
25
–SR
35
30
SLEW RATE (V/ s)
OPEN-LOOP GAIN (V/mV)
10M
Figure 8. OP282 Closed-Loop Gain vs. Frequency
45
25
20
15
20
15
10
+SR
10
00301-006
0
–75
–50
–25
0
25
50
75
100
0
–75
125
00301-009
5
5
–50
–25
TEMPERATURE (°C)
1000
+OS
50
–OS
30
20
00301-007
10
0
100
200
300
50
75
100
125
400
100
125
VS = ±15V
VCM = 0V
100
10
1
0.1
–75
500
LOAD CAPACITANCE (pF)
00301-010
INPUT BIAS CURRENT (pA)
VS = ±15V
RL = 2k
70 V = 100mV p-p
IN
AVCL = 1
T
= 25°C
A
60
0
25
Figure 9. OP282 Slew Rate vs. Temperature
80
40
0
TEMPERATURE (°C)
Figure 6. OP282 Open-Loop Gain vs. Temperature
OVERSHOOT (%)
OPEN-LOOP GAIN (dB)
VS = ±15V
TA = 25°C
00301-008
80
–50
–25
0
25
50
75
TEMPERATURE (°C)
Figure 7. OP282 Small Signal Overshoot vs. Load Capacitance
Figure 10. OP282 Input Bias Current vs. Temperature
Rev. F | Page 5 of 16
OP282/OP482
20
1000
VOLTAGE NOISE DENSITY (nV/ Hz)
VS = ±15V
TA = 25°C
TA = 25°C
RL = 10k
15
OUTPUT VOLTAGE SWING (V)
VOH
100
10
100
1k
FREQUENCY (Hz)
–5
–10
VOL
00301-014
0
±5
±10
±20
±15
SUPPLY VOLTAGE (V)
Figure 14. OP282 Output Voltage Swing vs. Supply Voltage
1000
VS = ±15V
TA = 25°C
100
VS = ±15V
TA = 25°C
100
OUTPUT IMPEDANCE ( )
INPUT BIAS CURRENT (pA)
0
–20
10k
Figure 11. OP282 Voltage Noise Density vs. Frequency
1000
5
–15
00301-011
1
10
10
10
1
AVCL = 100
10
AVCL = 10
1
–10
–5
0
5
10
00301-015
0.1
–15
00301-012
AVCL = 1
0.1
100
15
1k
10k
FREQUENCY (Hz)
COMMON-MODE VOLTAGE (V)
Figure 12. OP282 Input Bias Current vs. Common-Mode Voltage
480
480
TA = 25°C
SUPPLY CURRENT ( A)
475
470
465
460
455
470
465
460
0
±5
±10
±15
450
–50
±20
SUPPLY VOLTAGE (V)
00301-016
455
00301-013
SUPPLY CURRENT ( A)
1M
Figure 15. OP282 Closed-Loop Output Impedance vs. Frequency
475
450
100k
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 13. OP282 Supply Current vs. Supply Voltage
Figure 16. OP282 Supply Current vs. Temperature
Rev. F | Page 6 of 16
125
OP282/OP482
10
VOH
8
6
4
2
0
100
1k
LOAD RESISTANCE ( )
25
20
15
10
5
0
100
10k
1k
10k
FREQUENCY (Hz)
1M
140
140
VS = ±15V
120 TA = 25°C
VS = ±15V
TA = 25°C
120
100
100
+PSRR
80
80
CMRR (dB)
60
40
20
–PSRR
60
40
20
0
–20
–20
00301-018
0
–40
–60
100
1k
100k
10k
FREQUENCY (Hz)
–40
–60
100
1M
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 21. OP282 CMRR vs. Frequency
Figure 18. OP282 PSRR vs. Frequency
14
200
VS = ±15V
TA = 25°C
300 OP282
(600 OP AMPS)
VS = ±15V
12
160
SINK
10
120
UNITS
8
SOURCE
6
80
4
0
–50
–25
0
25
50
75
100
0
–2000
125
TEMPERATURE (°C)
00301-022
40
2
00301-019
SHORT-CIRCUIT CURRENT (mA)
100k
Figure 20. OP282 Maximum Output Swing vs. Frequency
Figure 17. OP282 Absolute Output Voltage vs. Load Resistance
PSRR (dB)
VS = ±15V
TA = 25°C
RL = 10k
AVCL = 1
00301-020
MAXIMUM OUTPUT SWING (V p-p)
VOL
12
00301-017
ABSOLUTE OUTPUT VOLTAGE (V)
14
30
VS = ±15V
TA = 25°C
00301-021
16
–1200
–400
0
400
1200
VOS ( V)
Figure 19. OP282 Short-Circuit Current vs. Temperature
Figure 22. OP282 VOS Distribution SOIC Package
Rev. F | Page 7 of 16
2000
OP282/OP482
70
400
VS = ±15V
300 OP282
(600 OP AMPS)
360
60
320
50
OVERSHOOT (%)
280
240
UNITS
AVCL = 1
NEGATIVE EDGE
VS = ±15V
RL = 2k
VIN = 100mV p-p
200
160
AVCL = 1
POSITIVE EDGE
40
30
120
20
80
0
0
4
8
12
16
20
24
28
32
00301-026
10
00301-023
40
0
36
0
100
TCVOS ( V/°C)
VS = ±15V
TA = 25°C
0
60
50
AVCL = 100
0
180
10k
100k
1M
FREQUENCY (Hz)
10M
40
30
AVCL = 10
20
10
AVCL = 1
0
–10
00301-027
135
00301-024
20
CLOSED-LOOP GAIN (dB)
PHASE (Degrees)
90
1k
500
VS = ±15V
TA = 25°C
45
40
–20
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 24. OP482 Open-Loop Gain, Phase vs. Frequency
Figure 27. OP482 Closed-Loop Gain vs. Frequency
35
25
VS = ±15V
RL = 10k
30
–SR
20
VS = ±15V
RL = 10k
CL = 50pF
SLEW RATE (V/ s)
25
20
15
10
15
10
+SR
5
5
–50
–25
0
25
50
75
100
0
–75
125
TEMPERATURE (°C)
00301-028
0
–75
00301-025
OPEN-LOOP GAIN (V/mV)
OPEN-LOOP GAIN (dB)
60
400
Figure 26. OP482 Small Signal Overshoot vs. Load Capacitance
Figure 23. OP282 TCVOS Distribution SOIC Package
80
300
200
LOAD CAPACITANCE (pF)
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 25. OP482 Open-Loop Gain (V/mV)
Figure 28. OP482 Slew Rate vs. Temperature
Rev. F | Page 8 of 16
125
OP282/OP482
1000
1000
VS = ±15V
TA = 25°C
100
10
00301-029
1.0
0.1
0
–50
–25
0
25
50
75
100
100
10
1
0.1
–15
125
00301-032
INPUT BIAS CURRENT (pA)
INPUT BIAS CURRENT (pA)
VS = ±15V
VCM = 0V
–10
TEMPERATURE (°C)
Figure 29. OP482 Input Bias Current vs. Temperature
5.0
45
3.5
75
100
3.0
125
20
±5
±10
±15
±20
SUPPLY VOLTAGE (V)
Figure 33. OP482 Relative Supply Current vs. Supply Voltage
OUTPUT VOLTAGE SWING (V)
30
RL = 10k
TA = 25°C
10
5
0
–5
–10
–15
00301-031
VOLTAGE NOISE DENSITY (nV/ Hz)
40
1k
0.90
15
50
100
0.95
20
60
10
1.00
0
VS = ±15V
TA = 25°C
70
1.05
0.85
Figure 30. OP482 Phase Margin and Gain Bandwidth Product vs. Temperature
80
1.10
00301-033
4.0
0
10
15
00301-034
50
RELATIVE SUPPLY CURRENT (ISY)
GAIN BANDWIDTH PRODUCT (MHz)
GBW
00301-030
PHASE MARGIN (Degrees)
4.5
0
25
50
TEMPERATURE (°C)
10
TA = 25°C
55
–25
5
1.15
VS = ±15V
RL = 10k
–50
0
Figure 32. OP482 Input Bias Current vs. Common-Mode Voltage
60
40
–75
–5
COMMON-MODE VOLTAGE (V)
–20
10k
0
FREQUENCY (Hz)
±5
±10
±15
±20
SUPPLY VOLTAGE (V)
Figure 31. OP482 Voltage Noise Density vs. Frequency
Figure 34. OP482 Output Voltage Swing vs. Supply Voltage
Rev. F | Page 9 of 16
OP282/OP482
600
100
500
80
400
60
300
–PSRR
40
20
200
AVCL = 10
0
0
100
1k
10k
00301-035
AVCL = 1
100k
00301-038
AVCL = 100
100
20
100
1M
1k
FREQUENCY (Hz)
100k
1M
Figure 38. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency
20
VS = ±15V
VS = ±15V
SINK
1.10
1.05
1.00
0.95
0.90
0.85
0.80
–75
–50
–25
0
25
50
75
100
15
10
SOURCE
5
00301-039
SHORT-CIRCUIT CURRENT (mA)
1.15
00301-036
RELATIVE SUPPLY CURRENT (ISY)
1.20
0
125
–75
TEMPERATURE (°C)
–50
–25
0
25
50
30
MAXIMUM OUTPUT SWING (V)
25
POSITIVE
SWING
8
NEGATIVE
SWING
6
4
20
15
10
00301-037
1k
0
10k
LOAD RESISTANCE ( )
00301-040
5
2
0
100
125
VS = ±15V
TA = 25°C
AVCL = 1
RL = 10k
VS = ±15V
TA = 25°C
10
100
Figure 39. OP482 Short-Circuit Current vs. Temperature
16
12
75
TEMPERATURE (°C)
Figure 36. OP482 Relative Supply Current vs. Temperature
ABSOLUTE OUTPUT VOLTAGE (V)
10k
FREQUENCY (Hz)
Figure 35. OP482 Closed-Loop Output Impedance vs. Frequency
14
VS = ±15V
V = 100mV
TA = 25°C
+PSRR
PSRR (dB)
IMPEDANCE ( )
VS = ±15V
TA = 25°C
1K
10K
100K
FREQUENCY (Hz)
Figure 40. OP482 Maximum Output Swing vs. Frequency
Figure 37. OP482 Maximum Output Voltage vs. Load Resistance
Rev. F | Page 10 of 16
1M
OP282/OP482
320
100
280
80
240
200
UNITS
CMRR (dB)
60
40
160
120
20
80
–20
100
1k
40
10k
100k
0
1M
0
Figure 41. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency
700
VS = ±15V
TA = 25°C
300 OP482
(1200 OP AMPS)
400
300
200
100
00301-045
UNITS
500
0
0
400
–2000 –1600 –1200 –800 –400
VOS ( V)
4
8
12
16
20
24
28
TCVOS ( V/°C)
FREQUENCY (Hz)
600
00301-043
VS = ±15V
TA = 25°C
VCM = 100mV
00301-041
0
800
1200 1600 2000
Figure 42. OP482 VOS Distribution P Package
Rev. F | Page 11 of 16
Figure 43. OP482 TCVOS Distribution P Package
32
OP282/OP482
APPLICATIONS INFORMATION
The OP282 and OP482 are dual and quad JFET op amps that
are optimized for high speed at low power. This combination
makes these amplifiers excellent choices for battery-powered or
low power applications that require above average performance.
Applications benefiting from this performance combination
include telecommunications, geophysical exploration, portable
medical equipment, and navigational instrumentation.
HIGH-SIDE SIGNAL CONDITIONING
There are many applications that require the sensing of signals
near the positive rail. OP282s and OP482s were tested and are
guaranteed over a common-mode range (−11 V ≤ VCM ≤ +15 V)
that includes the positive supply.
PHASE INVERSION
Most JFET-input amplifiers invert the phase of the input signal
if either input exceeds the input common-mode range. For the
OP282/OP482, negative signals in excess of approximately 14 V
cause phase inversion. The cause of this effect is saturation of
the input stage leading to the forward-biasing of a drain-gate
diode. A simple fix for this in noninverting applications is to
place a resistor in series with the noninverting input. This limits
the amount of current through the forward-biased diode and
prevents the shutting down of the output stage. For the
OP282/OP482, a value of 200 kΩ has been found to work;
however, this adds a significant amount of noise.
15
One application where this is commonly used is in the sensing
of power supply currents. This enables it to be used in current
sensing applications, such as the partial circuit shown in Figure 44.
In this circuit, the voltage drop across a low value resistor, such
as the 0.1 Ω shown here, is amplified and compared to 7.5 V.
The output can then be used for current limiting.
15V
10
VOUT
5
0
0.1
–5
500k
100k
RL
–10
–15
–15
1/2
OP282
00301-046
500k
Figure 44. High-Side Signal Conditioning
–10
–5
0
VIN
5
10
15
00301-047
100k
Figure 45. OP282 Phase Reversal
ACTIVE FILTERS
The wide bandwidth and high slew rates of the OP282/OP482
make either an excellent choice for many filter applications.
There are many active filter configurations, but the four most
popular configurations are Butterworth, Elliptical, Bessel, and
Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table 4.
Table 4.
Type
Butterworth
Chebyshev
Elliptical
Bessel (Thompson)
Selectivity
Moderate
Good
Best
Poor
Overshoot
Good
Moderate
Poor
Best
Phase
Nonlinear
Amplitude (Pass Band)
Maximum Flat
Equal Ripple
Equal Ripple
Linear
Rev. F | Page 12 of 16
Amplitude (Stop Band)
Equal Ripple
OP282/OP482
PROGRAMMABLE STATE-VARIABLE FILTER
The circuit shown in Figure 46 can be used to accurately
program the Q, the cutoff frequency fC, and gain of a 2-pole
state variable filter. OP482s have been used in this design
because of their high bandwidths, low power, and low noise.
This circuit takes only three packages to build because of the
quad configuration of the op amps and DACs.
1
2π
where
256
is the digital code for the DAC.
The gain of this circuit is set by adjusting
The DACs shown are used in the voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not
on the absolute values of the DAC’s resistive ladders. This makes
this circuit unusually accurate for a programmable filter.
. The gain equation is
256
DAC 2 is used to set the Q of the circuit. Adjusting this DAC
controls the amount of feedback from the band-pass node to
the input summing node. Note that the digital value of the
DAC is in the numerator; therefore, zero code is not a valid
operating point.
Adjusting DAC 1 changes the signal amplitude across R1;
therefore, the DAC attenuation times R1 determines the amount
of signal current that charges the integrating capacitor, C1. This
cutoff frequency can now be expressed as
256
R7
2k
R4
2k
VIN
DAC8408
1/4
C1
1000pF
R5
2k
OP482
1/4
OP482
C1
1000pF
R1
2k
1/4
1/4
OP482
DAC8408
1/4
OP482
1/4
DAC8408
1/4
OP482
R1
2k
1/4
OP482
HIGH PASS
LOW
PASS
BAND PASS
R6
2k
R3
2k
R2
2k
1/4
1/4
OP482
1/4
DAC8408
OP482
00301-048
1/4
Figure 46.
Rev. F | Page 13 of 16
OP282/OP482
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
6.20 (0.2440)
5.80 (0.2284)
1.27 (0.0500)
BSC
0.50 (0.0196)
45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 47. 8-Lead Standard Small Outline Package [SOIC]
Narrow-Body S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
3.00
BSC
8
3.00
BSC
1
5
4.90
BSC
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 48. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. F | Page 14 of 16
0.80
0.60
0.40
OP282/OP482
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
14
8
1
7
6.20 (0.2441)
5.80 (0.2283)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 49. 14-Lead Standard Small Outline Package [SOIC]
Narrow-Body S-Suffix (R-14)
Dimensions shown in millimeters and (inches)
0.685 (17.40)
0.665 (16.89)
0.645 (16.38)
14
8
1
7
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
0.015 (0.38)
MIN
0.180 (4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
SEATING
0.022 (0.56) 0.060 (1.52) PLANE
0.018 (0.46) 0.050 (1.27)
0.014 (0.36) 0.045 (1.14)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-095-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 50. 14-Lead Plastic Dual-in-Line Package [PDIP]
P-Suffix (N-14)
Dimension shown in inches and (millimeters)
Rev. F | Page 15 of 16
45°
OP282/OP482
ORDERING GUIDE
Model
OP282ARMZ-R21
OP282ARMZ-REEL1
OP282GS
OP282GS-REEL
OP282GS-REEL7
OP282GSZ1
OP282GSZ-REEL1
OP282GSZ-REEL71
OP482GP
OP482GS
OP482GS-REEL
OP482GS-REEL7
OP482GSZ1
OP482GSZ-REEL1
OP482GSZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
14-Lead PDIP
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00301–0–10/04(F)
Rev. F | Page 16 of 16
Package Option
RM-8
RM-8
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
P-Suffix (N-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
Branding
A0B
A0B