EMC’14/Tokyo 13A-B7 Signal Integrity: Influence of Non-linear Driver, Different Bit Rates, and Estimation by Different Algorithms Sheng-Yun Hsu, Chiu-Chih Chou, and Tzong-Lin Wu Graduate Institute of Communication Engineering National Taiwan University Taipei, Taiwan tlwu@ntu.edu.tw Abstract— Signal integrity issue has become more and more important in recent years. In order to have a good signal quality, many aspects in a digital channel must be carefully considered. In this paper we compare the effects of non-ideal output driver and different power distribution networks (PDNs) on the signal integrity. The channel performance variation under different driving bit rates is also analyzed. In addition, to reduce simulation time, various algorithms for fast and accurate signal integrity estimation have been proposed [1, 4] as alternatives to the conventional time-consuming PRBS simulation. The next part of this paper compares the performances of these algorithms for a circuit with nonideal PDN. From these results, we could get a qualitative understanding of these algorithms. Keywords—bit rate; eye diagrm; power distribution network; non-linear driver; signal integrity I. INTRODUCTION In a modern high-speed digital channel, various effects may influence the signal integrity (SI). For example, transmission line discontinuities such as bent or mismatch might cause multiple reflections of the data signal, thus producing the intersymbol interference (ISI) and degrading the signal quality greatly. Also, the output waveforms of a digital driver might be distorted by a nonideal power distribution network (PDN) [2-3]. Fig. 1 shows a general picture of a digital channel. In addition, as the data rate increases, the allowed charge (discharge) time for the pull up (pull down) circuitry in the output driver becomes shorter. If the driver cannot follow such high-speed transitions, the output signal would be distorted and thus increasing the bit error rate (BER). The increasing data rate will also cause severer voltage ripples on the PDN because of the PDN’s parasitic inductors and capacitors. To put it briefly, everything gets worse as the data rate goes higher. Input Signal Output Driver Fig. 1. A general digital channel. Copyright 2014 IEICE Receiver Signal Channel Receiver Conventionally the digital channel is evaluated by running PRBS simulation. However, for more complex systems, this takes more time. Therefore, several algorithms were proposed [1,4] to predict the channel performance without running PRBS. These algorithms can be categorized into two parts. First, peak distortion algorithm [1] can predict the worstcase inner/outer boundary of the eye diagram based on superposition principle. Since there are many non-linear effects in the channel, the multiple edge response (MER) method [4] was proposed to approximately estimate the performance of a non-linear channel. Second, statistical analysis [5] can provide BER. It is a more general methodology for SI evaluation since the worst-case eye boundary obtained in the previous part might be meaningless if the eye diagram is closed. Both methods, however, rely on the superposition of one or more basis waveforms. As a result, when the nonlinear effects such as the interaction between driver and PDN are included, these algorithms may have errors. In this paper, the above issues are examined. Section II compares the SI degradation of four different of circuits, including ideal/nonideal driver, two different PDNs, and different bit rates. Section III briefly introduces the algorithms and discusses the accuracy issue comparing with PRBS. II. NONIDEAL DRIVER, PDN, AND DIFFERENT BIT RATE In this section, part A shows the circuits that we used to conduct the simulation. Part B shows the simulation results including the eye height, jitter, and bathtub curves of different circuits. The effect of different bit rates is also analyzed. In the end of this section, a short conclusion is given. A. Circuit Setting Fig. 2 shows the basic topology of the circuit used for simulation. Ideal input signal Vin is transmitted through a driver (ideal or CMOS) with or without PDN connected to it, followed by two ideal transmission lines with a series inductor L1 and a shunt capacitor C2 between them representing nonideal effects in the channel. The transmission line is then terminated with a resistor R2. The CMOS driver is a 2-stage inverter as in Fig. 3(a), which is commonly used in practical 121 EMC’14/Tokyo A 13A-B7 Jitter (ps) Eye Height (V) 1.8V B PDN 1 60 0.9 50 0.8 C1 Driver Vin R1 40 0.7 L1 Ideal TL Vout Ideal TL C2 Circuit 1 R2 30 Circuit 2 0.6 Circuit 3 20 Circuit 4 0.5 10 0.4 A PDN 0.3 B 0 2 Fig. 2. The circuit setting for simulation. 4 6 Bit Rate(Gb/s) 8 10 Fig. 4. Eye height and jitter of four kinds of circuits in different bit rates. B log10(BER) 0 L2 OUT IN -1 A Circuit 1 Circuit 2 -2 R3 Circuit 3 Circuit 4 -3 (a) -4 (b) 0 Fig. 3. (a)The output driver consists of two stages of CMOS inverter. (b)The PDN consists of series inductor and resistor. circuits to amplify the input signal. The PDN is built up with L2 and R3 in Fig. 3(b), and node A in Fig. 3(b) is connected to C1 in Fig. 2. In Fig. 2 and 3, R1=50Ω, L1=1nH, C2=1pF, R2=50Ω, transmission line Z0=50Ω, time delay=100ps. Four different kinds of circuits are defined as follows: Circuit1: ideal driver, no PDN. Circuit2: CMOS driver, no PDN. Circuit3: CMOS driver, PDN L2=1nH, C1=1nF, R3=0.2Ω. Circuit4: CMOS driver, PDN L2=5nH, C1=200pF, R3=0.2Ω. We compare the effect of CMOS driver on the eye diagram through Circuit 1 and Circuit 2. Adding PDN effects in Circuit 2 then becomes Circuit 3, from which we can evaluate the effect of PDN on SI by observing the changes of the eye diagrams. In Circuit 4 the PDN is making worse by increasing L2 and decreasing C1. After analyzing these four circuits, we can easily tell which is the major issue that degrades the signal integrity. B. Simulation Results To simulate these 4 circuits, five different bit rates are used: (2, 4, 5, 8, 10) Gbps. After running PRBS, the eye height and jitter of each circuit are recorded in Fig. 4, where the horizontal axis is bit rate, and the left and right axis are eye height and jitter respectively. As can be seen, generally the Copyright 2014 IEICE 0.2 0.4 0.6 0.8 1 1.2 1.4 Time (UI, 1UI=100ps) 1.6 1.8 2 Fig. 5. Bathtub curve of four kinds of circuits. eye heights become smaller as the bit rate goes higher, no matter which circuit it is. Specifically, circuit 1 and circuit 2 show only minor difference as the bit rate increases, although circuit 2 uses a non-ideal CMOS driver. For circuit 3, where a nonideal PDN is presented, the eye height decreases dramatically as bit rate soars, which means that the voltage ripples in the PDN caused by the parasitic resistors and inductors affect the output signal of the driver significantly, and this phenomenon becomes even worse as bit rate climbs up. Increasing the effect of PDN in circuit 4 by decreasing C1 to 200pF and increasing L2 to 5nH, we see that the eye height becomes even smaller for high bit rates, which indicates that a poor designed PDN will result in a considerable SI degradation. Similar results can be found for the jitter in Fig. 4. Fig. 5 shows the bathtub curve of the 4 circuits. The bit rate is 10 Gbps with rise/fall time both 10ps. As can be seen, the results in Fig. 5 are in accordance with Fig. 4, where circuit 3 and 4 show clear difference between Circuit 1 and 2, and circuit 4 possess the smallest eye width. To sum up, the main cause that degrades the signal integrity in this circuit is the PDN, rather than the non-ideal driver. It is clear in Fig. 4 and Fig. 5 that, especially at high bit rates, a poor PDN will result in a poor signal quality. Although limited to this specific circuit setting, this result may be considered a general fact. The PDN design is as much important as the output driver in modern high speed circuits. 122 EMC’14/Tokyo III. 13A-B7 ALGORITHM FOR FAST SIGNAL INTEGRITY ESTIMATION In this section, the very fundamental core of the SI estimation algorithms mentioned in the Introduction section will be introduced. Part A covers the basic equations of the algorithms and explains its meaning, followed by a brief description of the estimation method. Simulation results will be given and discussed in part B, including the estimated worst-case eye boundary and the bathtub curve. the approximate received signal, the eye diagram and bathtub curve can be directly calculated. B. Simulation Results We use circuit C described in section II with bit rate 10 Gbps. Fig. 6 shows the estimated inner boundaries of the eye diagram as well as the PRBS result for reference. As can be seen, order 2 is much more accurate than order 1. Another Voltage(V) 1.3 A. Basic Principles of the Estimation Algorithm Any input signal x(t) can first be expressed as the linear superposition of the step function u(t) as 1.2 1.1 ∞ x(t ) = ∑ ( s[n] − s[n − 1])u (t − nUI ) 1 n =0 ∞ = ∑ s[n](u (t − nUI ) − u (t − (n − 1)UI )) MER order 2 (1) 0.8 n =0 0.6 0.5 0 y (t ) = ∑ | s[n] − s[n − 1] | R s[ n − m ]....s[ n −1] (t − nUI ) (2) 60 80 100 log10(BER) 0 -0.5 -1 MER order 1 -1.5 MER order 2 -2 -2.5 PRBS -3 -3.5 -4 (3) 0 n=0 0.5 1 1.5 2 Time (UI, 1UI=100ps) where R(t) is the specific rising or falling response with m preceding bits being s[n-m] to s[n-1], i.e., the waveform used for superposition is dynamically selected based on the preceding bit patterns. Thus, if m is large enough, presumably all the nonlinear effects in the circuit can be captured in these R(t)’s, at the cost of 2m many basis waveforms. The m is called the order of MER. Conceptually, selecting a larger m results in a more accurate estimation, but also makes the preparation work more tedious. Practically using order 2~4 would give reasonably accurate estimation results, and the time required would still be much less than running PRBS. The whole process of the MER method is as follows. First, use SPICE simulator to get the rising and falling responses of the circuit. For order 1, there are only one rising response (‘01’) and one falling response (‘10’). For order 2, there will be two rising responses (‘001’, ‘101’) and two falling responses (‘110’, ‘010’). Second, randomly build a binary sequence (say, 1000 or 10000 bits) to represent the PRBS input. Third, instead of directly running SPICE to get the PRBS output, use the waveforms obtained in the first step and equation (3) to construct the output waveform. After obtaining Copyright 2014 IEICE 40 Time(ps) where SBR(t) is the single bit response. Once we have SBR, the channel performance can be estimated using (2) without running the lengthy PRBS simulation. However, when the nonlinear effects in the circuit is pronounced, (2) produces great error. The multiple edge response (MER) method is then proposed [4] to overcome this problem. In MER method, the received signal is written as, following the first equality in (1) and with controllable error, ∞ 20 Fig. 6. Inner boundary of the eye diagram estimated by MER algorithm. ∞ n=0 PRBS 0.7 where s[n] is the input binary signal (either 1 or 0) and UI the unit interval. If n<0, s[n]=0. When the input signal transmits through output driver, channel, and receiver, the received signal y(t) can be approximately written as, following the second equality [1], y (t ) = ∑ s[n]SBR (t − nUI ) MER order 1 0.9 Fig. 7. Bathtub curve estimated by MER method. thing worth noting is that, contrary to intuition, order 1 MER overestimates the inner boundary. This means that although it is true a larger m gives better accuracy, a smaller m does not necessarily give an underestimation. Fig. 7 shows the bathtub curves of the same circuit. Similar results can be seen. The difference between MER and PRBS may be caused by the order of the MER. The larger the order is, the smaller the difference between MER and PRBS will be, but which also costs more time. In addition, rising or falling waveforms may have small ripples not due to the circuit itself but the SPICE convergence error. Such seemingly insignificant tiny ripples might be added up in the algorithm to produce an unrealistically poor eye diagram. To some extent this problem can be solved by choosing an appropriate length of the rising or falling waveforms. Despite the various causes of error discussed above, it should be mentioned, however, that the MER algorithm itself has nothing to do with any particular kind of circuits. It is a very general method and can be used in any digital channel, linear or nonlinear. 123 EMC’14/Tokyo 13A-B7 As a brief conclusion of this paper, The performance of PDN in modern high speed systems is becoming increasingly important because of its significant influence on SI. The MER method provides an efficient way to quickly estimate SI; but the accuracy of estimated results must be carefully examined. [3] [4] REFERENCES [1] [2] B. K. Casper , M. Haycock and R. Mooney "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes", Proc. Symp.VLSI Circuits Dig. Tech. Papers, pp.54 -57, 2002 T.L. Wu, F. Buesink, and F. Canavero, “Overview of Signal Integrity and EMC Design Technologies on PCB: Fundamentals and Latest Copyright 2014 IEICE [5] 124 Progress” in Electromag. Compat., IEEE Trans. on, vol 55, pp. 624-638, Aug , 2013 C.C. Chou, H.H. Chuang, T.L. Wu, S.H. Weng, C.K. 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