Design of Self-Biased Fully Differential Receiver and
Crosstalk Cancellation for Capacitive Coupled
Vertical Interconnects in 3DICs
Myat Thu Linn Aung1, Eric Lim2, Takefumi Yoshikawa3, Tony T. Kim1
1
VIRTUS, School of EEE, Nanyang Technological University, Singapore (aung0038@e.ntu.edu.sg; thkim@ntu.edu.sg).
Panasonic Semiconductor, Singapore. 3Mixed-signal Technology Development Division, Panasonic Corporation, Japan.
2
Abstract—Interconnect density in traditional capacitive coupling
electrodes array is limited by capacitive crosstalk between
electrodes. In this work, we propose an array structure where
single-ended and differential pair electrodes (designed in the
common-centroid
structure)
are
alternatively
placed
horizontally and vertically. The proposed structure not only
cancels out the crosstalk noise but also reduces the spacing
requirement between electrodes. A novel self-biased fully
differential receiver suppresses the common-mode coupled
crosstalk in the differential electrodes. The receiver provides
CMRR of 25dB and can recover wide band (10 kHz ~ 1 GHz)
signals with 32dB gain. It consumes 25 µW at 1 GHz. It is
designed and simulated in a 1.5V 0.13µm CMOS technology.
I.
INTRODUCTION
Three dimensional (3D) integration technology has been
considered as a solution to complex system integration making
heterogeneous integration viable. With the 3D integration,
vertical interconnects become possible, which improve the
interconnect density, communication distance, propagation
delay, dynamic power consumption, and form factor. Microbump technologies provide face-to-face connections between
two dies while through-silicon-via (TSV) technologies
facilitate the stacking of multiple dies. Nonetheless, these
benefits come with huge cost due to additional post processing
and fabrication process steps. Moreover, the TSV technologies
are not mature yet and have various issues related to
mechanical and thermal stresses. Additional constraints such
as dummy TSVs and large guard spaces have to be considered
to relieve the mechanical stress in TSVs during manufacturing
resulting in substantial silicon area overheads [1].
Alternative low cost options have been studied in literature
such as inductive coupling [2] and capacitive coupling
interconnects [3]. The use of coupling effect eliminates
physical connections where ESD protection is essential,
improving the overall performance of the coupling electrodes.
The performance of the inductive coupling interconnect is
comparable to TSVs in term of silicon usage, data rate, power
consumption and ability to integrate multiple dies. Additional
benefits are low cost, relaxed overlay alignment, high yield,
and higher reliability compared to the physical counterparts
Figure 1. An example of capacitive coupling interface with face-to-face
die stacking
[4]. Compared with the above interconnect technologies,
capacitive coupling based interconnects allow better
performance except it is only limited to the face-to-face
configuration. In this interconnect, digital signal can be
directly transferred to the receiving die through the coupling
node [5]. Moreover, [6] demonstrated the signal recovery
circuit using Non-Return-To-Zero (NRZ) coding achieving
1.27Gb/s/pin. [7] pushed the data rate even further to
10Gb/s/pin by implementing UWB impulse-shaping and RF
modulation scheme into capacitive coupling interconnect.
Several approaches have been reported to better utilize the
capacitive electrode area by introducing bi-directional [8] and
simultaneous bi-directional signaling [9]. Despite the above
advancements, [10] pointed out that the density of capacitive
coupling interconnects is limited by capacitive crosstalk. Due
to this, interconnects are spaced by a distance, which
contributed to area overhead, in order to minimize the
crosstalk as well as to improve Bit-Error-Rate (BER) [7].
In this work, we propose a design solution to solve the
crosstalk issue by careful planning in electrodes array layout
and receiver design for the direct digital signal transmission. A
novel self-biased fully differential receiver is incorporated to
reject any common-mode noise occurred at the differential
pair electrodes. With the proposed solution, the capacitive
coupling interconnects can be placed closer improving overall
interconnect density.
II.
As demonstrated in Fig. 1, coupling capacitors are formed
when the TX electrodes and RX electrodes meet face-to-face.
Panasonic Semiconductor, Singapore sponsors this work under Join
Industrial Postgraduate Scholarship.
978-1-4673-5762-3/13/$31.00 ©2013 IEEE
PREVIOUS SINGLE-ENDED RECEIVER AND LAYOUT
966
To form reasonable amount of capacitance, the distance
between two electrodes is maintained in a few µm range. Due
to vertical integration, overall interconnect distance is short
leading the signal flight time across interconnect to be shorter
than the signal rise or fall time. Therefore, it can be modelled
as lumped capacitive load and the coupled voltage at RX can
be approximated as:
∆V=
CC
CC +CPRX
×VDD
(1)
where CC is coupling capacitance and CPRX is the parasitic
capacitance associated with RX electrode. Equation 1
suggests that parasitic capacitance should be minimized to
improve the coupling voltage. However, when implementing
high-density capacitive coupling electrodes, one of the most
challenging issues is the crosstalk between neighbouring
electrodes. Two types of crosstalk (inductive and capacitive
crosstalk) have been discussed in the literatures but in this
voltage mode interconnect, capacitive crosstalk is dominant.
Fig. 2(a) illustrates parasitic coupling components between
two interconnects including the crosstalk components such as
CRX, CTR, and CTX. CTX is less significant among the three
crosstalk components because both TX<0> and TX<1> are
low impedance nodes driven by two transmitters. Although
the value of CTR is small compared to that of CRX, its
crosstalk effect is also significant as it is direct coupling from
a low impedance node to a high impedance node.
Figure 2. (a) Illustration of capacitive components between two
interconnects. (b) Simple demonstration of capacitive crosstalk
components in 3 × 3 array.
Figure 3. Single-ended receiver with gain stage and a latch.
A 3 × 3 RX array is demonstrated in Fig. 2(b) where all
the crosstalk components associated with RX are lumped into
CLUMP where
(2)
Obviously, the central electrode, RX<4> undergoes the
largest amount of crosstalk noise, possibly leading to a failure
in data recovery. This is especially for the single ended
receiver whose input is adaptively biased at a voltage level
with high sensitivity (Fig. 3) [11]. Fig. 4 shows the transient
response of the receiver output (RX_OUT) when the
emulated crosstalk noise at 2GHz with 70mVp-p is added to
the RX node. The receiver output (RX_OUT) demonstrates
its vulnerability to ac noise that is also amplified together
with the input signal. Failure in data recover happens when
the output noise exceeds the noise margin of the latch.
III.
Figure 4. Transient response of the single-ended receiver in the present
of crosstalk noise.
RX<6>
RX<6>
In this section, a novel electrode array (extendable to n ×
n array) structure is proposed to tackle the crosstalk effect
together with the newly developed self-biased fully
differential amplifier.
A. Electrode Array Layout
As explained in the previous section, single-ended
capacitive interconnects have limitation in placement due to
the multiple crosstalk factors. They require sufficient spacing
between electrodes to minimize crosstalk. The impact of
crosstalk in electrode spacing is presented in [10] where the
single-ended capacitive electrodes require more than 3µm
967
RX<8>
RX<7>
Differential
crosstalk currents
are cancelled
PROPOSED SELF-BIASED FULLY-DIFFERENTIAL
RECEIVER AND ELECTRODE ARRAY LAYOUT
RX<8>
Crosstalk
component
RX<3>
RX<4>
RX<4>
ICM
IDF
ICM
RX<0>
ICM ICM
IDF
IDF
RX<0>
Mutual Coupling
RX<1>
Single‐ended electrode
CC CPRX
CC+CPRX
RX<5>
IDF
Common‐mode
crosstalk currents are
added equally
RX<2>
RX<2>
Common‐centroid differential pair electrode
CLUMP =CTR +
Figure 5. Proposed distributed array structure in 3 × 3 array
configuration.
spacing so that the receiver can properly recover the data.
However, this spacing is also subject to the electrode size and
the type of data transmission whether it is direct transmission,
coded transmission or RF modulation [7].
Shielding and twisted differential line structures can be a
solution to suppress crosstalk between long transmission
lines. However, it is not feasible in capacitive electrodes since
they are only implemented in a top metal plane. This provides
no room to cancel the capacitive crosstalk from neighbouring
multiple electrodes. To address this issue, we propose a
distributed single-ended and differential electrodes structure
(Fig. 5). In the distributed structure, the single-ended and
differential pair electrodes are placed in an alternate fashion
in the horizontal and vertical directions in a top metal plane.
The common-centroid differential pair electrodes not only
achieve good matching between the electrodes pair but also
cancel out the capacitive crosstalk. For example, when
electrodes are perfectly aligned, signal transitions in
differential electrode (RX<4>) does not cause crosstalk to the
facing single-ended electrodes (RX<1, 3, 5, 7>) as the
crosstalk currents (IDF) are always cancelling each other. This
help to improve the performance of the neighbouring singleended electrodes. In addition, signal transitions in the singleended electrode (RX<5>) only affect the common-modevoltage of the differential electrodes (RX<2, 4, 8>) as the
same amount of crosstalk current (ICM) is flowing to each of
the neighbouring differential pair. Such common-mode shift
is effectively suppressed by the proposed receiver addressed
in section III (B). With the aid of the proposed crosstalk
cancellation technique, the achievable minimum spacing
between electrodes is only limited by the fabrication
capability and alignment precision between two dies.
Figure 6. Proposed self-biased fully differential receiver.
Figure 7. Input and output waveforms of the proposed receiver.
B. Receiver Design
Followings are the key features of the proposed receiver
for recovering the capacitively coupled differential signal.
•
Transistors count has to be small so that it can be
placed just underneath its electrodes.
•
High common-mode-rejection-ratio (CMRR) is
necessary to reject any common-mode noise caused
by the neighbouring single-ended electrodes.
•
Self-biasing at the input would be advantages
especially to detect small voltage change.
•
Native mutual coupling in the common-centroid
differential pair electrodes (Fig. 5) results in
attenuation of coupled signal. Moreover, when the
electrodes in the array are placed close to one
another, stray capacitance increases and the signal is
further attenuated. Therefore, a high gain receiver is
required to provide enough voltage swing at the
output.
To meet the above requirements, we propose a receiver
(Fig. 6) with two differential amplifiers where two inputs
(RX and RX ) are connected to either positive or negative
input of each differential pairs. The current mirror load at
each amplifier is essential to achieve high CMRR. In
addition, the diode connected transmission gates (T1 and T2)
968
Figure 8. (a) Simulation results of receiver gain and its output phase
shift. (b) Common-mode-rejection-ratio of the receiver.
provide self-biasing capability to each amplifier's input. The
impedance of the diodes are dynamically varied depending on
the amplifier output voltage bringing the voltage level of both
coupled signals (RX and RX) to a DC level (VDD ⁄2) after an
output transition occurs (Fig. 7). This leaves the input
impedance high after that and ready to sense the next signal
transition. The threshold voltage drop across the diode
connected transmission gates limits the peak-to-peak output
swing (OUT and OUT ). The output swing can be
approximated as:
VDD ⁄2
VTHP < VOUT < VDD ⁄2
IV.
VTHN
(3)
SIMULATION RESULTS
This section analyses voltage gain, phase shift, commonmode-rejection-ratio and transient waveforms of the proposed
receiver. The receiver is designed and simulated using a
commercial 0.13µm CMOS technology. The simulation
includes the coupling capacitance (CC) of 1fF, the stray
capacitance of 500aF, and 1fF for the mutual coupling
between RX and RX respectively. Two transistors inverter is
used as a load at the output of each differential receiver.
Simulation result (Fig. 8(a)) shows that the maximum
voltage gain of receiver is 32dB and its cut-off frequency is
around 1GHz. At the frequency of higher than 1GHz, total
biasing time (tSB) which is limited by the RC of T1 or T2,
becomes larger than the period of the signal resulting in next
signal transition to happen before completing the biasing. As
a result, the receiver becomes less sensitive to coupled signal
and the voltage gain drastically rolls off beyond 1GHz.
Despite the bandwidth of 1GHz, the receiver still provides a
reasonable voltage gain up to a few GHz. Positive phase at
the lower frequency is due to the leakage injected into the
input nodes mainly through the transmission gate. Therefore,
the lowest and safest operating frequency of the receiver is
concluded as 10 kHz. Based on Fig. 8(b), the CMRR of the
receiver is as large as 25dB within the pass-band where the
maximum CMRR of 28dB is located at 5MHz.
Figure 9. Transient waveforms demonstrating the common-mode
suppression.
Transient analysis is also conducted to see the effect of
CMRR in time domain. In this analysis, a 500Mbps
differential signal is applied to the input node (IN and IN). In
addition, a 2GHz common-mode noise signal having 200mV
peak-to-peak voltage (more than two times the magnitude of
the injected noise to RX in Fig. 4) is also applied to RX and
RX . The recovered signals from two differential outputs
clearly show that the inserted common-mode noise is
effectively suppressed as shown in Fig. 9. The proposed
receiver consumes 25µW at 1GHz.
V.
CONCLUSION
We have presented both the electrode array layout and
circuit approaches to achieve highest interconnects density by
eliminating capacitive crosstalk. Parting from the conventional
electrodes array structure, we introduce the distributed array
wherein single-ended and differential pair electrodes are
placed in alternative fashion. The common-centroid structure
of the differential electrodes suppresses its crosstalk to the
neighboring single ended electrodes while crosstalk by the
single ended electrodes, which affects the common-mode
voltage of the differential electrodes, is eliminated by the
circuit mean. The proposed self-biased fully differential
receiver provides CMRR of up to 28dB with 32dB voltage
gain to reject any common-mode noise. Its operation
frequency extends from 10 kHz to 1 GHz. The receiver power
consumption is 25µW at 1GHz signal. It is designed in 1.5V
0.13µm CMOS technology.
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