Product is End of Life 3/2014
Si9750
Vishay Siliconix
In-Rush Current Limit MOSFET Driver
DESCRIPTION
FEATURES
The Si9750 current limit MOSFET interface IC is designed to
operate between a power source and a load using a low onresistance power MOSFET with a sense terminal or in conjunction with a low ohmic sense resistor. The Si9750 current
limiter prevents source and load transients during hot swap
and power-on with programmable dv/dt and di/dt. Both turnon and steady-state current limits can be individually programmed, providing protection against short circuits. Power
on RESET and logic controls allow complete microprocessor
interfacing. The RESET function of the Si9750 is industrystandard with full programmability.
•
•
•
•
2.9 to 13 V Input Operating Range
Microprocessor RESET
Integrated High-Side Driver for N-Channel MOSFET
Programmable di/dt Current
The Si9750 is available in a 16-pin SOIC package and is
rated over the commercial temperature range (0 to 70 °C).
The Si9750 is available in both standard and lead (Pb)-free
packages.
FUNCTIONAL BLOCK DIAGRAM
VDD
VDD
LBOOST
COIL
RBIAS
Bias
Ref
Boost
BOOST
CBOOST
POR
HI/LO
ENABLE
Low RDS
N-Channel FET
GATE
Gate
Drive
Control
STATUS
CGATE
IBIAS
SENSE
Overcurrent
CRETRY
Retry
Delay
+
LIMSET
-
LOAD
POR
CRST
VLOAD
VRST
Reset
Load
+
Ref
GND
Document Number: 70028
S-40754-Rev. D, 19-Apr-04
RSENSE
(mW)
POR
Reset
Delay
Bandgap
RLIMSET
Ref
RESET
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Product is End of Life 3/2014
Si9750
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltages Referenced to Ground
Limit
VDD
Unit
15
Boost Voltage
29
Inputs/Outputs (except Gate, Boost and VRST)
V
- 0.3 to VDD + 0.3
VRST Input Current (0 < VRST < 15 V)
20
Inputs/Outputs Current
20
RESET Current
3
STATUS Current
mA
3
Storage Temperature
- 65 to 125
Junction Temperature
150
Power Dissipation (package)a
16-Pin SOICb
Thermal Impedance (ΘJA)
°C
900
mW
140
°C/W
Notes:
a. Device Mounted with all leads soldered or welded to PC board.
b. Derate 7.2 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
2.9 V ≤ VDD ≤ 13.2 V
HI/LO = GND, RBIAS = 12.5 kΩ
LBOOST = 100 µH, CBOOST = 100 nF
Limits
0 to 70 °C
Mina
Unit
Typb
Maxa
4
8
Supply
Quiescent Current
IQ
ENABLE = Logic Low
mA
Logic
Enable Turn-On Voltage
VEN(on)
Enable Turn-Off Voltage
VEN(off)
Enable Source Current
IENSRC
0.3 x VDD
0.7 x VDD
VENABLE = 0 V
40
120
V
µA
Turn-On Time
tON
Turn-Off Time
tOFF
Turn-On Boost
tON(BST)
See Figure 4
600
tOFF Initial Short Circuit
tOFF(ISC)
CGATE = 33 nF, See Figure 6
10
tOFF Short Circuit
tOFF(SC)
CGATE = 33 nF, See Figure 7
2
VSTAT
ISINK = 200 µA
0.4
V
tSTDLY
See Figure 8
25
µs
Status Output Voltage
Status Output Delay Time
5
See Figure 3
5
Status Threshold
VSTATTHR
0.85 x VDD
HI/LO Turn-On Voltage
VHILO(on)
0.7 x VDD
HI/LO Turn-Off Voltage
VHILO(off)
µs
0.95 x VDD
V
0.3 x VDD
Gate Drive
Enhancement Voltage
(VGATE - VSENSE)
Source Current
Sink Current
VGS
ISOURCE
ISINK
VCBOOST = 9 V
8.5
10.5
15
1.06
1.30
1.54
1.6
2.6
3.7
V
mA
Current Sense Circuit
Current Sense Amplifier Common Mode Range
Current Sense Amplifier Voltage Offset
Current Sense Amplifier Bias Current
RLIMSET Reference Current
VCMR
0
VDD + 0.3
V
VOS
-3
3
mV
ISOS
Current Sense Amplifier Hysteresis
VHYST
Current Sense Amplifier Series Offset
VSOS
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2
Normal Operation
IRLIMSET
- 0.2
18
19.5
12
HI/LO = VDD, VCMR > 0.5 V
20
21
µA
mV
Document Number: 70028
S-40754-Rev. D, 19-Apr-04
Product is End of Life 3/2014
Si9750
Vishay Siliconix
SPECIFICATIONS
Parameter
Symbol
Test Conditions Unless Specified
2.9 V ≤ VDD ≤ 13.2 V
HI/LO = GND, RBIAS = 12.5 kΩ
LBOOST = 100 µH, CBOOST = 100 nF
Limits
0 to 70 °C
Mina
Typb
Unit
Maxa
Power On Reset
RESET Output Voltage
RESET Output
Hysteresisc
VOP(rst)
IOUT = 1 mA, VDD > 2 V
VHYST
See Note c
VRST
RESET Comparator Input Threshold
Voltaged
0.4
2
1.223
1.250
V
mV
1.277
V
VRBIAS
0.5
RESET Comparator Input Bias Current
IBIAS
- 0.2
RESET Timer Delay
tRSTD
CRST = 15 nF, See Figure 8
110
150
190
µs
RETRY
tRETRY
CRETRY = 100 nF
70
130
200
ms
RESET Comparator Offset
mV
µA
Notes:
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test.
c. In a practical situation, VHYST is multiplied by ratio of a resistor divider chain. For VDD = 13.2 V, VHYST = 20 mV.
d. The RESET comparator input threshold specification (VRST) includes the RESET comparator offset voltage.
PIN CONFIGURATION AND ORDERING INFORMATION
SOIC-16
BOOST
1
16
COIL
VDD
2
15
GND
GATE
3
14
CRST
LOAD
4
13
CRETRY
SENSE
5
12
RESET
LIMSET
6
11
STATUS
HI/LO
7
10
VRST
ENABLE
8
9
RBIAS
ORDERING INFORMATION
Part Number
Temperature Range
Package
0 to 70 °C
SOIC-16
Si9750CY
Si9750CY-T1
Si9750CY-T1-E3
Top View
PIN DESCRIPTION
Pin Number
Function
Description
1
2
3
4
BOOST
VDD
GATE
LOAD
5
SENSE
6
LIMSET
7
HI/LO
8
ENABLE
9
RBIAS
10
VRST
11
STATUS
12
RESET
13
14
15
16
CRETRY
CRST
GND
COIL
Output of on-chip Boost converter. A 100 nF capacitor should be connected between BOOST and GND
Positive supply pin.
Connection to external power MOSFET gate.
Connection to positive supply side of LOAD.
Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A
standard MOSFET may also be used in conjunction with a low ohmic value shunt resistor.
Connects overcurrent limit set resistor RLIMSET to the reference input of overcurrent trip comparator.
CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to
GND for low Capacitive loads and to VDD for high capacitive loads.
CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high.
A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator
resistor RLIMSET and the GATE(on) charge current. See Functional Description for equations.
Input to voltage monitor comparator.
Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is
greater than 90 % of VDD.
Open drain NMOS output. This pin is driven low during power on reset or when VRST is lower than the internal
1.25 V reference.
A capacitor connected from this pin to GND programs the retry timer.
A capacitor connected from this pin to GND programs the reset timer.
Negative supply pin.
Connection to Boost converter inductor.
Document Number: 70028
S-40754-Rev. D, 19-Apr-04
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Product is End of Life 3/2014
Si9750
Vishay Siliconix
FUNCTIONAL DESCRIPTION
The Si9750 together with an N-Channel MOSFET provides
the following functions:
• limits di/dt current for hot insertion applications
• provides complete short circuit protection
• high-side drive allows N-Channel MOSFET to be used,
for lower power dissipation
• industry-standard microprocessor reset function
• logic control input and outputs
If the HI/LO pin is tied low the current limit is 20 % higher
during turn-on than the steady state current limit point.
ILOAD x R SENSE > 1.2 x I BIAS x RLIMSET
(2)
(with pin HI/LO = Low)
If a higher current limit is needed at start-up, the HI/LO pin
can be tied high. The equation becomes:
ILOAD x R SENSE > 1.2 x I BIAS x RLIMSET
+ I BIAS (1 kΩ + RHI )
(HI/LO = High)
Setting the Current Limit
(SENSE, HI/LO pins, RLIMSET, RSENSE)
(3)
The current limit point is determined by the voltage across
RSENSE, the value of RLIMSET, and the bias current. The current limit circuit is shown in Figure 1
Notice that any current limit can be set at turn-on using an
optional resistor, RHI.
The steady state current is set by the equation:
Relaxation Mode Current Limit
(CRETRY pin)
(1)
ILOAD x R SENSE > IBIAS x RLIMSET
Due to the highly capacitive nature of some loads, the Si9750
has an option to increase the current limit point to a much
higher level at turn-on. In this case, turn-on is defined as
VGATE < VDD + 7.8 V. This function is implemented with the
HI/LO pin.
In an overload condition, the Si9750 will go into a relaxation
mode current limit operation that not only protects the source
and load, but also reduces the power dissipated in the MOSFET. When an overload is detected, the circuit quickly turns
off, then goes into a retry mode whereby the current is
ramped up slowly. If the fault still exists, the current will ramp
down again. This sequence will repeat indefinitely at a period
defined by 106 x CRETRY until the fault is removed. Typically,
capacitors in the range of 1 nF to 1 µF can be used
on CRETRY, but the period should be > 50 ms.
IBIAS
Si9750
Overcurrent
−
+
HI/LO
1 kΩ, ± 20 %
SENSE
GATE
LIMSET
RHI
(Optional)
RSENSE
VDD
HI/LO
RLIMSET
ILOAD
VLOAD
330 Ω
330 Ω
33 nF
Figure 1.
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Document Number: 70028
S-40754-Rev. D, 19-Apr-04
Product is End of Life 3/2014
Si9750
Vishay Siliconix
FUNCTIONAL DESCRIPTION (CONT’D)
di/dt Limiting On Hot and Cold Insertion (GATE pin)
Boost Converter
(COIL, BOOST pins)
The GATE pin provides a constant current source that is
used to control the rate of rise of the gate of the MOSFET,
and hence to control the di/dt of the load and source current.
The equation that governs the gate current is:
12
ISOURCE = 1.25 V x
R BIAS
1.2 mA
The boost converter generates the gate drive for the external
N-Channel MOSFET. This is limited to typically VDD + 11 V.
The boost inductor should typically be 100 µH, < 3.5 Ω,
> 180 mA dc, and the boost capacitor should be 100 nF.
(4)
Logic Control
(STATUS, ENABLE, RESET, VRST and CRST pins)
(for R BIAS = 12.5 kΩ)
Typically, a 33 nF capacitor should be connected from the
GATE pin to ground. If a large ISOURCE is needed for high di/
dt, a 330 Ω resistor in series with CGATE may be necessary
to prevent oscillation. In the case that VDD > 6 V, a resistor of
approximately 330 Ω is also recommended in series with the
gate. (Figure 1).
STATUS. The status monitor detects when the load voltage
is 90 % of input voltage, VLOAD > 0.9 x VDD. This pin is an
open-drain NMOS output, capable of sinking 200 µA at VOL
= 0.4 V. If this pin is used in conjunction with the ENABLE of
another unit, power supply sequencing (or daisy-chaining) is
easily implemented.
Reference Bias Current
(RBIAS pin)
ENABLE. This CMOS logic compatible input serves as the
on/off control pin. This pin has 40 µA minimum pull-up to
VDD.
This pin sets the internal current used by RLIMSET to determine all the current limit points. Typically RBIAS = 12.5 kΩ
which sets a 20 µA bias current. The equation which relates
RBIAS to IBIAS is:
I BIAS = 1.25 V
5 x RBIAS
20 µA
(5)
(for R BIAS = 12.5 kΩ)
RESET (VRST, CRST, RESET pins). This is a standard implementation of the microprocessor reset function. A comparator looks at the voltage on VRST pin and compares it with
1.25 V. This function is programmable by using an external
voltage divider. When VRST is higher than 1.25 V, the reset
signal is delayed by the CRST pin, defined by Equation (6)
and then goes high. (Figure 2):
Reset delay t RSTD
Power on Reset (POR)
(VDD pin)
(6)
10 4 x C RST
HI/LO Pin
RLIMSET
CRETRY
This function monitors the voltage on the VDD pin and signals
the system if all input voltage requirements have been met.
At turn-on when VDD > 2.7 V ± 200 mV, a POR signal is generated for a duration of 100 µs. After this point the system is
released into operation. If VDD falls below 2.7 V ± 200 mV, a
second POR signal will be generated. If two POR signals are
detected, this indicates that the source for VDD is not capable
of supplying the load current. The IC then turns off the MOSFET and initiates its retry period, hence fully protecting the
MOSFET from an over-power condition.
Current
Short Circuit
Applied to Output
Turn-On
VGATE > VDD + 7.8 V
Current Limit Point
ILOAD
Figure 2. Typical Operation Under Start-up Condition With
An Overcurrent Fault Applied to the Output
Document Number: 70028
S-40754-Rev. D, 19-Apr-04
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Product is End of Life 3/2014
Si9750
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C unless noted
3.0
3.0
I SINK - Gate-Sink Current (mA)
I SOURCE - Gate-Source Current (mA)
3.5
2.5
2.0
1.5
1.0
0.5
4
8
12
16
2.8
2.6
2.4
2.2
2.0
2.80
20
4.88
RBIAS (kΩ)
9.04
11.12
13.20
40
50
VDD (V)
Gate-Source Drive Current vs. RBIAS
Gate-Sink vs. VDD
50
400
t RESET − RESET Timer Delay (µS)
I R(LIMSET) - R LIMSET Current (µA)
6.96
40
30
20
10
0
300
200
100
0
0
4
8
12
16
20
0
10
RBIAS (kΩ)
20
30
CRST (nF)
RLIMSET Current vs. RBIAS
RESET Timer Delay vs. CRESET
600
t RETRY - RETRY Delay (mS)
500
400
300
200
100
0
0
50
100
150
200
250
300
350
400
CRETRY (nF)
RETRY Delay vs. CRETRY
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Document Number: 70028
S-40754-Rev. D, 19-Apr-04
Product is End of Life 3/2014
Si9750
Vishay Siliconix
SWITCHING TIME TEST CIRCUITS
VDD
0
ENABLE
0.7 VDD
0.3 VDD
tON
tOFF
ISOURCE
50 %
0
50 %
ISINK
Figure 3. Normal-Mode Operation
ENABLE
1
0
1
1
VDD
VDD
0
tBOOST
0
1
90 %
VBOOST−VDD
tON(bst)
1
ISOURCE
0
1
50 %
0
Figure 4. Timing Definition with ENABLE Already On
Figure 5. Start of Boost Converter
tRETRY
ILOAD
ILOAD
VSENSE
Threshold
Threshold
VSENSE
tOFF(isc)
tOFF(sc)
ISOURCE
VG
1V
0
50 %
ISINK
Figure 6. First Short Circuit
Figure 7. Relaxation-Mode Current Limit
1
VG
0
1
Status Threshold
VLOAD
0
1
tSTDLY
STATUS
tSTDLY
0
0.3 x VDD
1
tRSTD
RESET(2)
0
(2) With reset input divider correctly set, monitoring VLOAD
Figure 8. STATUS and RESET
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70028.
Document Number: 70028
S-40754-Rev. D, 19-Apr-04
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7
Package Information
Vishay Siliconix
SOIC (NARROW):
16-LEAD (POWER IC ONLY)
JEDEC Part Number: MS-012
MILLIMETERS
16
15
14
13
12
11
10
Dim
A
A1
B
C
D
E
e
H
L
Ĭ
9
E
1
2
3
4
5
6
7
8
INCHES
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.20
0.004
0.008
0.38
0.51
0.015
0.020
0.18
0.23
0.007
0.009
9.80
10.00
0.385
0.393
3.80
4.00
0.149
0.157
1.27 BSC
0.050 BSC
5.80
6.20
0.228
0.244
0.50
0.93
0.020
0.037
0_
8_
0_
8_
ECN: S-40080—Rev. A, 02-Feb-04
DWG: 5912
H
D
C
All Leads
e
Document Number: 72807
28-Jan-04
B
A1
L
Ĭ
0.101 mm
0.004 IN
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1
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Revision: 02-Oct-12
1
Document Number: 91000