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MODULE 6
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SEQUENTIAL ELEMENTS
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.5.1
7.5.2
7.6
7.6.1
7.6.2
7.6.3
7.7
7.8
Introduction
Timing Metrics for Sequential Circuits
Classification of Memory Elements
Static Latches and Registers
The Bistability Principle
Multiplexer-Based Latches
Master-Slave Edge-Triggered Register
Timing Properties of Multiplexer-Based Master ….
Low-Voltage Static Latches
Static SR Flip-Flops — Writing Data by Pure Force
Dynamic Latches and Registers
Dynamic Transmission-Gate Edge-Triggered Registers
C2MOS — A Clock-Skew Insensitive Approach
True Single-Phase Clocked Register (TSPCR)
Alternative Register Styles
Pipelining: An Approach to Optimize Sequential Circuits
Latch versus register based pipelines
NORA-CMOS A logic style for pipelined circuits
Nonbistable Sequential Circuits
The Schmitt Trigger
Monostable Sequential Circuits
Astable Circuits
Perspective: Choosing a Clocking Strategy
Summary
326 – 327
327 – 328
328 – 330
330
330 – 332
332 – 333
333 – 335
335 – 339
339 – 341
341 – 344
344
344 – 346
346 – 350
350 – 354
354 – 358
358 – 360
360
361 – 363
364 – 367
367 – 368
368 – 370
370 – 371
371 – 372
§ 7.5 Will be discussed with module 08 timing design
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Sequential Elements - Outline
„ Background
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FSM with Positive Edge Triggered
Registers
„ Timing, terminology, classification
„ Static Flipflops
„ Latches
„ Registers
„ Dynamic Flipflops
„ Latches
„ Much of this material has
already been covered in CS1
(v Genderen), Lecture 4(?),
Katz Section 6.1
„ Here we will add transistorlevel implementation,
dynamic flipflops
„ Registers
„ Non-bistable elements
„ Schmitt Trigger
Ch. 7
§ 7.1
Ch. 6
[Sorin Cotofana]
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Memory elements
„
„
„
„
„ Flip-flops provide memory/state
„ VLSI uses predominantly D-type
flip-flops
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Variations in memory elements
„ Form of required clock signal.
„ How behavior of data input around clock affects
the stored value.
„ When the stored value is presented to the output.
„ Whether there is ever a combinational path from
input to output.
Store a temporary value, remember a state
Typically controlled by clock.
May have load signal, etc.
In CMOS, memory is created by:
„ capacitance (dynamic);
„ feedback (static).
„ Also see http://en.wikipedia.org/wiki/Flip-flop_(electronics)
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1
Timing Metrics Reminder
Nomenclature
Beware for confusion
tc-q
tsu
thold
tplogic
tcd
T
: delay from clock (edge) to Q
: setup time
: hold time
: worst case propagation delay of logic
: best case propagation delay
(contamination delay)
T ≥ tc-q + tplogic + tsu
: clock period
t
+t
≥t
cdregister
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cdlogic
hold
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Latches vs. Registers
Katz (CS1)
Rabaey
Latch
Level sensitive
storage element
Level sensitive
storage element
Register
Group of
storage elements
Edge triggered
storage element
Flip Flop
Edge triggered
storage element
Bistable element
using feedback
CLK = CK=φ
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Static vs. Dynamic Memory Elements
Latch
Register
Static
Dynamic
Level-sensitive
Edge-triggered
Transparent when clock
is active
Input and output isolated
Operate through positive
feedback
Store charge on
(parasitic) capacitor
Sampling on 0 → 1 clock:
positive edge triggered
Preserve state as long as
power is on
Charge leaks away (in
milliseconds)
Sampling on 1 → 0 clock:
negative edge triggered
Can work when clock is
off
Safer
More robust
Clock must be kept
running (for periodic
refresh)
Clock active high:
positive latch
Clock active low:
negative latch
Faster, smaller
Faster, smaller
Rabaey: bistable elements are called Flip Flops
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Positive Feedback: Bi-Stability
Static Latches and Registers
Vi1
Vo1 =V i2
Vo2
V
o1
Vi2 = Vo1
„Latches Î can be gated or not
„Registers
Vi2 = Vo1
Vi1
Vo2
A
C
„ Loop-gain in A,B <<1
„ A,B: stable points
„ Loop-gain in C >> 1
„ C: meta-stable point
§ 7.2.1
B
Vi1 = Vo2
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2
SR-Latch
S
QQ
>1
S
R
QQ
>1
R
S
Q
R
Q
Clocked SR-Latch
S
R
Q
Q
0
1
0
1
0
0
1
1
Q
1
0
0
Q
0
1
0
S
forbidden
&
Q
&
S
Q
&
R
S
Q
R
Q
QQ
R
S
R
Q
Q
1
0
1
0
1
1
0
0
Q
1
0
1
Q
0
1
1
Q
&
Q
CK
&
R
S
&
S
forbidden
D
R
„
„
„
„
„
„
Katz: gated latch
Positive latch (active on CK high)
Naïve implementation
16 transistors
D latch requires 9xN, 9xP
Larger area, cost, power
„ Construction of D-latch
„ D-latch, D-register most common in
VLSI
§ 7.2.5
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Multiplexer-Based Latches
CMOS Clocked SR-Latch
VDD
S
&
Q
&
M2
Q
CK
R
&
Q
&
φ
M6
M1
S
M5
M4
Q
M8
M3
φ
M7
R
CLK
φ = CK
„ Save 6 (incl. 4 large) PMOS transistors and 2 NMOS
„ D-latch requires 7 x N, 3 x P (instead of 9xN, 9xP)
Q: Is this a ratioed design or not?
Does it consume static power?
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YES
NO
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Recirculating latch
Restoration
IN
Recirculating latch
§ 7.2.2
CLK
Multiplexer
Mux-based latches much more common in modern dig. IC’s
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Insensitive for Charge Sharing
φ1
φ1
φ1
φ2
φ1
φ2
φ2
„ Quasi-static, static on one phase
„ Feedback restores value
„ Requires 4 x N, 4 x P, minimum size
(compare 7 x N, 3 x P, non-minimum size)
„ φ1 and φ2 inverse but should be non-overlapping
„ Can suffer from charge sharing (when φ not non-overlapping)
Cin and Cload form communicating vessels when Output connected
directly to input
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φ2
„ Non ratioed
Uni-directionality of this inverter
prevents coupling between Q and D
„ High load to CLK
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3
Latch Designs can Suffer from
Race Problems
Recirculating NMOS Latch.
X
t
loop
t
φ
1
„ Degraded 1 at X
„ Lower noise margin, higher delay, power
D
Q
φ
Q
t
Signal can race around during φ = 1
§ 7.2.3
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Registers
„ Not transparent—use multiple storage elements
to isolate output from input.
„ Master-slave, edge triggered principle
master
§ 7.2.3
D
master
slave
D
Q
Q
§ 6.1.4-5
φ
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Master-slave operation
φ
slave
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φ = 0:
„ master latch is disabled;
„ slave latch is enabled,
„ but master latch output is
stable,
„ so output does not change.
φ = 1:
„ master latch is enabled,
„ loading value from input;
„ slave latch is disabled,
„ maintaining old output value.
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Transistor Level Master Slave
Positive Edge Triggered Register
www.play-hookey.com
clickable
„ Robust Design
„ Can eliminate I1 and I4, however, they make design
more robust (avoid charge sharing, robust input)
„ link
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„ High Clock Load (8 x)
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4
Ratioed Reduced Clock Load
Register
Set-up Time Simulation
„
„
„
„
Slightly smaller delay
between D and CLK
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I2 and I4 are small, even long
Lower clock load
Increased design complexity
Reduced robustness (reverse conduction)
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Schmitt Trigger
Non-bistable Elements
„Schmitt Trigger
V OH
Vou t
In
Out
with hysteresis
„ •VTC
VTC with
hysteresis
V OL
slopes
„ •Restores
Restoressignal
signal
slopes
Was discussed in P-lab
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VM–
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Noise Suppression using
Schmitt Trigger
VM+
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Vi n
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CMOS Schmitt Trigger
V DD
Vin
Vout
M2
V
VM+
M4
X
in
M
1
V out
M
3
VM–
t0
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t
t0 + tp
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Moves switching threshold
of first inverter
t
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5
Schmitt Trigger Simulated VTC
CMOS Schmitt Trigger (2)
VDD
M4
5.0
6.0
M6
M3
4.0
In
Out
4.0
Vout (V)
V X (V)
3.0
2.0
VM+
M2
X
2.0
VM-
1.0
0.0
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
0.0
0.0
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1.0
2.0
M5
V DD
M1
3.0
Vin (V)
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4.0
5.0
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Summary
„ Background
„ Timing, terminology, classification
„ Static Flipflops
„ Latches
„ Registers
„ Dynamic Flipflops
„ Latches
„ Registers
„ Non-bistable elements
„ Schmitt Trigger
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6