Proceedings of IPACK’01
The Pacific Rim/ASME International Electronic Packaging
Technical Conference and Exhibition
July 8-13, 2001, Kauai, Hawaii, USA
Paper # 44592
FATIGUE AND INTERMETALLIC FORMATION IN LEAD FREE SOLDER DIE ATTACH
Patrick McCluskey
CALCE Electronic Products and Systems Center
University of Maryland, College Park 20742
ABSTRACT
With the advent of lead-free soldering, it is
important to understand the effects of this new assembly
process on the reliability of electronic packaging structures.
The new materials and higher reflow temperatures used in
lead-free soldering raise issues of materials and process
compatibility with existing package materials.
New
materials may be required to be selected as die attaches,
component encapsulants, lead finishes, board materials,
and board platings to be compatible with lead-free
soldering. In particular, new high temperature lead-free
and lead-containing die attach materials may be needed in
power electronic devices to withstand the higher soldering
temperatures. However, little information is available in
the literature on the fatigue properties of thin films of these
materials. Such information is critically needed to evaluate
the lifetime of power electronic modules. In this paper, we
will discuss analytical, semi-analytical, and numerical
methods for assessing the fatigue behavior of large area
solder die attaches of these new materials, and the
experimental validation of these methods against thermal
cycle testing.
Keywords: Physics-of-failure, die attach, power
electronics, lead-free solder, fatigue.
INTRODUCTION
Worldwide environmental protection regulations and
market forces are driving the elimination of lead from
electronic products. Research to find an alternative to the
dominant Sn37Pb eutectic solder alloy, widely used for
permanent electronic interconnects, has culminated with
the selection by the National Electronics Manufacturing
Initiative (NEMI) of a suite of three preferred replacement
solder alloys. These are Sn3.5Ag for wave soldering,
Sn0.7Cu for rework, and Sn3.8Ag0.7Cu for reflow. These
solders were chosen for their superior wetting and strength
characteristics and their acceptable fatigue behavior with
respect to Sn37Pb. However, the switch to lead-free
solder raises issues of material and process compatibility
with the new alloy compositions and the needed assembly
temperatures. For example, the solders selected have
melting points above 217°C. This means that in order to
reflow these materials, the components and boards must be
heated to 240°C -260°C, which is 20°C -40°C above the
temperature at which Sn37Pb reflow is conducted. Thus,
new die attach materials, component lead finishes, plastic
encapsulants, board resins, and board platings may be
required that are compatible with the lead-free solder alloys
and the higher processing temperatures. In this article, we
will discuss one of the most critical of these issues, the
need for new, reliable, high temperature die attach
materials.
The effect on die attach of switching to lead-free
solder is greatest for power electronic devices. Die attach
fatigue is usually not a concern in small-signal computing
applications where the thermal and power cycle magnitudes
are relatively small. Furthermore, these applications use a
silver-filled adhesive die attach which should be compatible
with the higher soldering temperatures.
High power
devices require solder alloys as die attaches to provide the
necessary thermal and electrical conductivity, since the die
attach serves a critical element in both the heat dissipation
path and the electrical path. New alloys are required to
withstand the higher reflow temperatures without melting.
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Furthermore, the cyclic operation of power devices
places severe thermal and mechanical stresses on the die
attach. Significant amounts of heat are generated by the
devices during operation, which result in large thermal
cycle magnitudes as the power is switched on and off. In
spite of having good thermal and thermomechanical
properties, significant amounts of creep and thermal fatigue
in the solder die attach layer may be seen during thermal
cycling due to the viscoplastic nature of the solder. In this
study, we have used a systematic approach to study the
stress/strain behavior and the thermal cycling damage
induced in two potential solder attach materials for die
attach of components which will be interconnected using
lead-free solder. Understanding the mechanical behavior of
the solder by this systematic “physics-of-failure (PoF)
based” stress and damage modeling approach enables a
shortening of the design cycle for replacing the current die
attach with one that can withstand lead-free solder reflow,
while enhancing the reliability of the final device.
Fatigue at high homologous temperatures is one of the
most complex topics of materials research due to
interactions between creep damage and plastic cycling
damage at these high operating temperatures [1].
Significant research has been carried out in studying the
effects of creep fatigue on the reliability of attach materials
for high temperature and high power applications. The
thermal instability of a TO-220 package due to soft solder
fatigue has been analyzed by Lin and Patmon [2]. Voids
and crack growth in soft solder die attach layers due to
thermal cycling have been experimentally studied by
Carlson et al. [3]. Electrical failures in silicon power
transistors due to crack growth in the solder joints have
been presented by Sung et al. [4]. Research in the area of
reliability of soft solders during thermal cycling has
revealed the susceptibility of the material to creep and
fatigue. An experimental thermal cycling study can provide
a clear idea of the failure site, failure mode and the number
of cycles to failure, but testing is not a cost-effective or
time-effective method for assessing reliability. Hence in
order to achieve time compression, but still be able to
predict the failure mechanisms accurately, a physics-offailure based modeling technique is essential.
In the paper, a physics-of-failure based reliability
assessment is conducted on a high lead solder and a lead
free solder, considered for use as attach materials in a
Super-220TM package. The Super-220TM package is a
power MOSFET used in the body electronics of an
automobile. The package experiences extreme thermal
cycles in the field, which may cause degradation in the
solder attach leading to fatigue and device failure. The first
step in the PoF approach involves characterizing the
package design, material behavior and the environmental
and operational loads acting on the package. Stress-strain
response is obtained by performing a 2D finite element
analysis. The stress analysis details are then used in a
analytical damage model to determine the life of the attach
material. A thermal cycling test is performed to calibrate
and validate the model, with electrical testing being
conducted to observe shifts in electrical parameters and a
delamination study performed to observe de-adhesion and
degradation across the die attach interface. The failure
observations are then compared with predictions based on
the PoF approach.
NOMENCLATURE
Eeff = effective elastic modulus of the material
E1 = elastic modulus of the material,
E2 = elastic modulus of the plastic
αeff = effective CTE of the material
α1 = CTE of the material
α2 = CTE of the plastic
k1 = stiffness of the material
k2 = stiffness of the plastic
A1 = cross sectional area of the material
A2 = cross sectional area of the plastic
N50 = mean cycles to failure
∆ε c = creep strain per cycle
K = high lead solder creep constant
β = high lead solder creep exponent
RELIABILITY ASSESSMENT OF THE SUPER-220TM
POF BASED SIMULATION
The first step in the PoF approach involves a detailed
characterization of the geometry and materials of the
package and of the environmental and operational loads
acting on the package. In this case, the analysis was
conducted on a Super-220TM package in which either high
lead solder or lead-free solder were used to attach the chip
to the copper leadframe. A 2D finite element model of the
package was conducted to model the stresses and strains in
the die attach layer. PATRAN was used for the geometric
modeling. The package was fixed at nodes where the leads
were attached to the plastic, as a displacement boundary
condition. Since this is a plastic encapsulated microcircuit,
effective material properties were used for the die, die
attach and copper leadframe, that accounted for the
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constraining effect of the plastic. The governing equations
are given by
E eff = ( E 1 A1 + E 2 A 2 ) /(A 1 + A 2 )
αeff = (α1k1 + α2 k 2 ) /(k1 + k 2 )
k1 = A 1E1 / L1
k 2 = A 2E 2 / L 2
The effective elastic properties of the material are
provided in Table 1
Table 1 : Effective elastic properties
Material
Chip
Solder (S1)
Copper
Plastic
Elastic Modulus
(MPa)
9.65*104
0.639*104
9.13*104
1.087*104
CTE
(ppm/K)
3.77
30.3
17.3
32
Poisson’s
ratio
0.28
0.419
0.3
0.33
three temperature cycles in order to make sure that the
energy densities in the attach layer converged. The
ABAQUS solver was used to predict the stress strain
distribution and the hysteresis energy in the attach layer. In
general, soft solders exhibit more damage due to creep
dissipation than fatigue and so failure in the solder is a
function of the creep strain, which causes the maximum
damage.
Based on the analysis, the relevant parameters
affecting the life of the attach layer were identified to be
the creep strain and the inelastic energy density. Both the
creep strain and the inelastic energy densities were found to
be high near the edges of the attach, since the edges reflect
a high stress concentration region. Figure 1 shows the
creep strain distribution to be higher closer to the edge of
the solder attach. Figure 2, a plot of the Von-Mises stress
variation between the center and one of the edges of the
attach layer, shows higher stress concentration at the edges
of the attach layer which could cause crack initiation.
Two relationships, one for the plastic deformation as a
function of stress and temperature and another for the
creep deformation rate as a function of stress and
temperature are required to completely describe the
viscoplastic nature of the solder. The plastic strain
hardening behavior is modeled by the Ramberg - Osgood
relation given by
ε plastic = Kp (T) σ np(T)
where ε plastic is the plastic strain, σ is the stress, Kp (T) is
the strain hardening coefficient and np(T) is the strain
hardening exponent. The creep law used for the solder is
given by the Weertman equation
Figure 1: Equivalent creep strain near the edges of the
solder attach layer
dε creep /dt = Kcσnc e-∆ H / R T
The constitutive equations are incorporated in the
ABAQUS [5] program in the form of a simple FORTRAN
code. Once the geometry is modeled and the effective
properties are assigned to the various materials, the next
step is to simulate the environmental load acting on the
package.
A thermal cycle profile of –55°C to 150°C was used to
model the stress and the strain distribution in the solder die
attach layer. In the model, the package was subjected to
Figure 2: Von Mises stress variation between the center
and one of the edges of the solder attach layer
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Failure predictions were made based on the
accumulated creep strain in the cycle. A literature search
was conducted on various strain-based models [6], [7], [8],
[9] [10]. For the current study, the strain-based model
developed by Darveaux and Banerji [9] was used to predict
the fatigue life because it was developed for material
systems similar in behavior to the alloys used here. The
failure equation is of the form shown below:
N50 = K(∆ε c)-β
where N50 is the mean cycles to failure, ∆ε c is the creep
strain per cycle, and K and β are constants specific to high
lead solders. Using this model, a time-to-failure of 900
cycles was identified.
to-failure for the lead-free solder in the 100,000 cycle
range for the same stress level.
In the current modeling approach, the temperature was
cycled between -55°C and 150°C. Since the upper and the
lower bound on the temperatures are expected to affect the
package reliability during a temperature cycling operation, a
series of simulations were run to plot the variation of life
with respect to the peak temperature as shown in Figure 3.
As expected, the cycles to failure tend to decrease with
increase in the temperature cycle magnitude created either
by an increase in the maximum cycling temperature or a
decrease in the minimum cycling temperature, or both.
S1 Cycles to failure
100000
Cycles to failure
FAILURE PREDICTION
RELIABILITY PREDICTION BY CADMP-II SIMULATION
The previous section on PoF-based simulation
highlighted the approach used in predicting reliability. A
non-linear finite element analysis was used to calculate the
stress/strain distribution in the solder layer. Due to the
viscoplastic nature of the solder, the finite element
simulations took significant time to converge to the
accurate solution. In order to perform reasonably accurate
simulations with greater time efficiency, a physics of failure
software tool (CADMP-II) was used.
10000
1000
-55°C
0°C
100
100
25°C
120
140
160
180
Peak Temp
Figure 3: Plot of Cycles to Failure vs Temperature for S1
EXPERIMENTAL VALIDATION
The software tool has built-in analytical models
that are used to assess the life of the package. The package
architecture is first modeled using a graphical user
interface. The material properties for the various layers in
the package are provided by a materials database resident
in the software. This information on the package
architecture and the material properties along with the
environmental loads is then used by the software to
identify the failure mechanisms precipitated due to the
applied load, and to determine the time to failure of the
package as calculated by each failure model for each
relevant failure mechanism.
Based on the CADMP-II simulation, solder fatigue
was identified to be the dominant failure mechanism. The
software predicted failure of the attach after 1200 cycles
using an Englemaier approach with a modified CoffinManson damage model. The total time spent in running a
simulation using the tool was less than an hour. The time to
failure results were reasonably close to that predicted by
finite element simulations. Similar analysis showed a time-
In the case of power devices used in automotive
electronic systems, repetitive thermal cycles lead to stresses
in the die and the die attach layers. These stresses increase
at high temperatures and result in failures in the die attach
assembly. Failure mechanisms include die fracture, fatigue
crack propagation in the die, de-adhesion, and die attach
fatigue [11]. Failure by these is often accelerated by
subjecting the package to environments that are more harsh
than the field application to obtain the product life
characterization data in a shorter time. In order to
precipitate the above failures, an accelerated temperature
cycling test was conducted.
Two batches of Super-220TM packages, one
containing a high lead (S1) solder, and the other containing
a lead free solder (S0) were temperature cycled between 55°C and 150°C. During the course of the testing,
packages were removed from the temperature cycling
chamber at periodic intervals of 60-100 cycles in order to
conduct electrical testing and delamination analysis. This is
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Copyright © 2001 by ASME
essential to capture changes in both electrical and
mechanical parameters within the component during the
testing. The failure criterion was decided based on
electrical testing of the components.
Frequenc
y
ELECTRICAL TESTING
Electrical testing of the components was done to
find the parametric shifts over the range of thermal cycles.
The critical parameter measured was RDS-ON (On
resistance). During thermal cycling, degradation in the
package will result in a shift in RDS-ON and failure is
typically defined as a 20% increase. It is unusual to see
changes in parameters such as Breakdown voltage (BVDSS)
or Threshold voltage (VGS(th)) unless the die has completely
delaminated from the header.
3.4
3.6
3.8
Rds(on) [mOhms]
4
S0 Rds(on) Shifts
4.2
0 Cycles
1000 Cycles
Frequency
25
20
15
10
5
0
3.3
3.4
3.5
3.6
Rds(on) [mOhms]
3.7
Figure 4: RDS-ON shifts due to thermal cycling for older
Super-220TM devices studied here.
S1
1000 cycles
RDSON Shifts
30 cycles
12
10
8
6
4
2
0
0.185
0.19
0.195
0.2
0.205
0.21
0.215
RDSON (Ohms)
S0
1000 cyles
RDSON Shifts
30 cycles
12
Frequency
For the Super-220TM , electrical testing revealed a
maximum percentage shift of 2.5% in the RDS-ON value for
the devices containing the high lead solder as the attach
material. Using a 20% shift in the RDS-ON as the failure
criterion, none of the devices tested exhibited failure after
1000 temperature cycles. However, the magnitude of the
change is package dependent. For newer devices, the
contribution of the other package elements to RDS-ON is
reduced and therefore the effect of changes in the die
attach layer is greater. This is evident from the plots
shown in Figure 5. The plots show a larger percentage shift
in RDS-ON for newer low RDS-ON devices. For these
devices, a 20% shift in RDS-ON is a more efficient indicator
of device mechanical failure.
1000 Cycles
10
8
6
4
2
0
3.2
Frequency
RDS-ON is the sum of the resistances of the bond wires,
metallization and silicon, die attach, lead frame and the
contact resistance of the leads. Typically, degradation and
voids in the attach layer and any degradation in the wire
bond/die interface can lead to an increase in the on-state
resistance of the devices. The RDS-ON shifts due to thermal
cycling for the two package types are shown in Figure 4. It
is clearly evident that a considerable shift is seen for the
package type containing the high lead solder and a very
negligible shift is observed for the package type with the
lead free solder. Basically, the high lead solder is a soft
solder which undergoes thermal fatigue due to material
softening resulting in an increase in the resistance. The lead
free solder is a hard solder, which has sufficient strength to
avoid any thermal fatigue problems during temperature
cycling.
0 Cycles
S1 Rds(on) Shifts
10
8
6
4
2
0
0.174
0.184
0.194
0.204
0.214
RDSON (Ohms)
Figure 5: RDS-ON shifts due to thermal cycling for Super220 devices with Rds(on)<5mOhms
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DELAMINATION ANALYSIS
Because of their package dependence, measurements
based on electrical parameters do not clearly indicate the
level of mechanical damage that has occurred in the solder
layer due to creep or strain hardening. For these reasons, a
delamination analysis was conducted to monitor the
changes in the die and the die attach to reveal, in more
detail, the extent of this damage.
Delamination analysis was conducted using a C-SAM
(Scanning Acoustic Microscopy). Delamination was
observed in the high lead solder attach as seen in Figure 6.
Cracks in the solder layer are due to the thermal fatigue
and creep interactions that occur during thermal cycling.
The high lead solder being a soft solder accumulated
damage more quickly, resulting in the initiation of cracks
around the edges of the attach layer which propagate
through the bulk of the solder. On the other hand, no
thermal degradation was seen in the lead free solder.
finite element analysis and 1200 cycles to failure with
CADMP-II analysis. From the C-SAM analysis,
considerable delamination was observed after 614 cycles in
the high lead solder. The testing and the predictions
therefore correlated to within a factor of two. One of the
important observations is that the lead free solder showed
better electrical and mechanical performance compared to
the high lead solder. Hence the lead free solder is
recommended for attachment in the Super-220TM . Failure
measurements based on electrical testing did not give a
conservative estimate of failure since the percentage shifts
in the electrical parameters were much less than the
specified 20% failure criterion. However, this was an
artifact of the high initial RDS-ON of the package selected.
The study proves that the modeling approaches can be
used as an efficient tool for the upfront prediction of
reliability and the guiding of materials selection and design
decisions.
ACKNOWLEDGMENTS
The authors would like to thank the over 50 corporate and
government members of the CALCE Electronics Products
and Systems Center for their support of this work.
Particular thanks are due to International Rectifier for its
technical direction and financial contributions to this effort.
Thanks also go to Dr. George Campisi and Mr. Terry
Ericson of the Power Electronic Building Blocks Program
for their sponsorship of this work via ONR Grant
#N000149810842.
REFERENCES
Figure 6: C-SAM delamination analysis
SUMMARY AND CONCLUSIONS
Destructive physical analyses conducted after the
temperature cycling test reveal that maximum thermal
fatigue damage occurs in the attach layer of the package.
The physics-of-failure based modeling approach was able
to capture the mechanical degradation in the form of creep
strain accumulation and predicted 900 cycles to failure with
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