14th International Conference
Reliability and Stress–Related Phenomena in
Nanoelectronics – Experiment and Simulation
Bad Schandau, Germany, May 30 – June 1, 2016
Andreas Aal1, Gottfried Kurz2, André Clausner3
1Electronic
Analysis / Robustness (EEIP/1), Volkswagen AG, Berliner-Ring 2, 38436 Wolfsburg, Germany
2GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
3Fraunhofer Institute for Ceramic Technologies and Systems, Maria-Reiche-Strasse 2, 01109 Dresden, Germany
Phone: +49-(0)5361-9-38277; Fax: +49-(0)5361-9-57-38277; e-mail: andreas.aal@volkswagen.de
Intermittent Functional Loss of Non-Degraded Advanced
Semiconductor Technology based Products
in Harsh Environments – Causes, Reproducibility, Mitigation
Content
1
Background
2
Motivation
3
Experimental Approach
4
SRAM read disturb sensitivity under mechanical load
5
Primitive device electrical aging behavior under mechanical load
6
Discussion
7
Summary
Page 2
1. Background
Future Mobility: Zero Emission, intuitiv, online
The future is a 4wheel computer with client & server functionality
– the ultimate mobile device
Page 3
1. Background
Semiconductor Technology – Enabler for Functions that matter
Key-Technologies (i.e. Smartphone)
Automotive: New digital Products & Services
 Application CPU:
14/16 nm FinFET
(Samsung/TSMC)
 Baseband CPU:
20 nm SOC
 Power Amplifier Modul:
100 nm GaN
 LTE-Modul:
28 nm CMOS
Big Data
Connected
Car
Autonomous
Driving
CloudComputing
 NAND Flash:
15-20 nm MLC
Automotive needs leading-edge technologies from a functional
perspective, but ...
Page 4
2. Motivation
The challenge – AST* in automotive environments
 … function is bound to technology, but technology is bound to initial
key-product design
 Reliability & performance of those technologies @ risk under
automotive loads
Risks:
 Stress exceeds strength
EOL reached too early (mission profile)
General mech. construction insufficience (cracks, delamination etc.)
 Parametric deviations
Permanent w/o aging effect
Reversible / intermittent
Partially permanent / reversible with aging effect
This work: focuses on mech. induced parametric deviations …
*AST = Advanced Semiconductor Technologies
Page 5
2. Motivation
The challenge – AST in automotive environments
Application
Parametric drifts outside specified values after 1st
operation
Similar effect observed
for 3 IC vendors /
technologies in 2014
 so not a single case
Lucero, IRPS 2015
Gaps
 Awareness of technology sensitivity to thermomechanical stress insufficient
 AEC-Q100 qualification in sockets insufficient to mimic
board-level effects under real reflow conditions
 Wafer technology qualification did not sufficiently
consider CPI / CPBI*
Leatherman, IRPS 2012
* CPI / CPBI– chip package-board interaction
Task: Mimic automotive loads and follow failure RCA*
*RCA = Root Cause Analysis
Page 6
3. Experimental Approach
Quantitative mech. loads & typ. environmental loads
Approach I
 Analysis of SRAM read disturb sensitivity under mechanical load
Nano-indentation
VdipR – Tests
FEM Simulation of mechanical induced stress @ transistor level
caused by external forces
Calibration of simulation & electrical measurements
Approach II
 Analysis of primitive device electrical aging behavior under
mechanical load
Effect of uHAST, TC, wafer thinning on HCI behavior
Quantify stress, watch effects – conclude knowledge based
Page 7
4. Experimental – SRAM read disturb
Approach I - mechanical setup for n-indentation
 28 nm HKMG 64 Mbit SRAM, full process flow
 Wafer thinning to 250 µm / Flipchip assembly to 948µPGA package
 ATE test at 85°C / 25°C of assembled SRAMs
 Remove of package lid and further down thinning of remaining Sithickness (min. 35 µm)
Application of mech. stress by n-indentation @ chip back side
Page 8
4. Experimental – SRAM read disturb
Approach I - VdipR Test
RD – Procedure (RDP)
 Write step @ Vnom (checkerboard pattern)
 Voltage dip down to VdipR
 Read (disturb) step
 Voltage rise to Vnom & read with pass/fail assessment
 Repeat @ different mech. load conditions
Calibration I
 VdipR chosen at threshold to bit flip (high sensitivity to mech. load)
 Drawback – background noise  solution: statistical averaging by
repeating RDP (fail assessment when > 10 fails in 20 repetitions or #
fails per 50 VdipR repetitions )
Fail calibration to mech. load
Page 9
4. Results – SRAM read disturb
Approach I - Simulation of mechanical induced stress @ transistor
level caused by external forces
Image overlay of VdipR and von-Mises stress simulation @ 1.3 N
Page 12
4. Results – SRAM read disturb
Approach I - Simulation of mechanical induced stress @ transistor
level caused by external forces
Image overlay of VdipR and hydrostatic stress simulation @ 1.3 N
Page 13
4. Results – SRAM read disturb
Approach I - Simulation of mechanical induced stress @ transistor
level caused by external forces
Image overlay of VdipR and normal stress in x direction simulation @
1.3 N
Page 14
4. Results – SRAM read disturb
Approach I - Simulation of mechanical induced stress @ transistor
level caused by external forces
Image overlay of VdipR and normal stress in y direction simulation @
1.3 N
Page 15
4. Results – SRAM read disturb
Approach I - Simulation of mechanical induced stress @ transistor
level caused by external forces
Image overlay of VdipR and normal stress in z (indentation) direction
simulation @ 1.3 N
Page 16
4. Results – SRAM read disturb
Approach I - Calibration of simulation & electrical measurements
 Correlation of the SRAM functionality & simulation stresses through chip operation
voltage shift with/without indenter load
 Determination of voltage shift required to hold cell stable (increase under
indentation load)
Shift in minimum required SRAM operation voltage with
simulation stresses  reliability criteria can be derived
Page 17
5. Results – TQV test structure chip
Approach II – pure HCI aging, higher stress
Watch these curves on the next slide
HCI effect per channel length with distinct L - separation
Page 20
5. Results – TQV test structure chip
Approach II – HCI aging after uHAST, higher stress
These curves have shifted upwards
This form of graphical illustration is
insufficient to show the important things
TC/uHAST cause a ~const. shift of pMOS Id,sat degradation
Page 21
5. Results – TQV test structure chip
Approach II – pure HCI aging
Effect of HCI stress on pMOS Id,sat degradation
Page 22
5. Results – TQV test structure chip
Approach II – HCI aging after uHAST / TC + uHAST
σ
Partially reversible shifts and variance increase
Page 23
5. Results – TQV test structure chip
Approach II – HCI aging after uHAST / TC + uHAST
σ=
Shift & variation are voltage dependent
Page 24
5. Results – TQV test structure chip
Approach II – HCI aging & uHAST, TC, wafer thinning
Secondary stress effect is L and V dependent
Page 25
6. Discussion
Approach II
 Usually package form-factor related tests are applied after tech-qual rather
than investigating the effect already during technology qualification
 This approach then considers mechanical effects as linear, reversible and
without effect on aging
 In addition the meaning of variability increase / decrease my be
underestimated
 TC after wafer processing before wafer thinning & further assembly may
reduce variability
Results from Intel (IRPS 2012) show that nMOS Idsat shift is stronger affected as
pMOS – we see pMOS sufficiently enough affected
 Shift is 37-50 % higher when going down from 25 °C to -10 °C
 Shift is 20 % higher when die thickness is reduced from 200 um to 120 um
Page 26
7. Summary
Approach I
 Based on the combination of a smart n-indentation setup, optimized
SRAM sensitivity, FEM simulations and corresponding calibration via
cell operation voltage adjustment, …
 … it is now possible to quantify the transfer ratio of externally applied
stress to local stress on Si device level, which …
 … can positively extend current DfR methodologies
Approach II
 For the 1st time the effect of mechanical-stress related tests on
primitive device aging has been investigated
 The results & literature shows, how to further improve corresponding
test scenarios (test @ lower temp, decrease die thickness etc.)
 The effect of mechanical-stress has the potential to significantly
change primitive device aging and therefore modelling
Page 27
ACKNOWLEDGEMENTS
The authors thank the team from GLOBALFOUNDRIES and Fraunhofer
IKTS for their support.
Especially to mention are:
Christoph Sander – IKTS
Martin Gall – IKTS
Ardechir Pakfar - GLOBALFOUNDRIES
Michael Otto – GLOBALFOUNDRIES
5
Sebastian Dej – GLOBALFOUNDRIES
Page 28
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