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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 6, DECEMBER 2003
Time-to-Voltage Converter for On-Chip
Jitter Measurement
Tian Xia, Member, IEEE, and Jien-Chung Lo, Senior Member, IEEE
Abstract—In this paper, we present the concept and design of a
time-to-voltage converter (TVC), and demonstrate its application
to on-chip phase-locked loop (PLL) jitter measurement. The TVC
operates in an analog, continuous mode without using a sampling
clock. It compares the signal under measurement with a reference
signal by charging and discharging a capacitor. First, the low-frequency reference signal charges the capacitor in one cycle. Then,
the jitter signal discharges the same capacitor repeatedly until the
voltage on the capacitor falls below a threshold. The number of
times the jitter signal needs to discharge the capacitor is recorded
on a binary counter. We demonstrated that a 160-ps injected jitter
is successfully measured by the proposed TVC with a 2-MHz reference signal. We also demonstrated the successful measurement
of a 14-ps average PLL jitter, without jitter injection. An 8% measurement error is found in both experiments, using four-bit counters. Finally, we analyze the relations between design parameters
and show trade-offs between measurement resolution and measurement time.
Index Terms—Charge pump, on-chip measurement, phaselocked loop (PLL), signal jitter, time-to-voltage conversion (TVC).
I. INTRODUCTION
I
N THE 2001 edition of the International Technology
Roadmap for Semiconductor [1], timing jitter measurement
in high-speed VLSI is stated as one of the top most difficult
challenges. The jitter measurement in phase locked loops
(PLLs) and in gigabit-rate serializer and deserializer (SerDes)
are two most notable examples. These are the challenges
with urgent need for solutions. In this paper, we propose the
concept of time-to-voltage converter (TVC) circuit. Such a
circuit measures timing information directly and continuously.
Specifically, the TVC operates directly with the analog voltage
level that represents the timing values. The measurement
circuit is thus compact enough to be implemented on the chip.
This, in turn, reduces the possibility of environmental noise
interference.
Timing measurement is an important part of many applications such as laser radar, phase meter, PM or FM demodulators,
etc. [2]–[4]. In particular, a class of time-to-digital converter
(TDC) has been developed for these applications. Similar idea
has never been considered for testing deep sub-micron VLSI
to our best knowledge. The proposed TVC is a modified form
of TDC such that the timing information is transformed to
voltage level directly without digitization [5]. Most importantly,
Manuscript received November 30, 2002; revised July 28, 2003.
T. Xia is with the Electrical and Computer Engineering Department, University of Vermont, Burlington, VT 05405 USA.
J.-C. Lo is with the Department of Electrical and Computer Engineering, University of Rhode Island, Kingston, RI 02881 USA.
Digital Object Identifier 10.1109/TIM.2003.818731
this proposed technique differs significantly from the existing
methods, TDC included, in its operating mode such that the
timing measurement is performed in an analog manner without
a sampling clock. This unique feature will enable the timing
measurement of high-speed gigabit-rate circuits possible. Note
that the major obstacle today for such measurement is that the
sampling frequency must be order of magnitude faster than
the circuit under test. Many “difficult challenges” for testing
described in [1] can be solved or alleviated with this new
technique.
To demonstrate the effectiveness of the TVC concept,
we choose to tackle the problem of measuring jitter in PLLs.
PLL-based frequency synthesizers are commonly used to create
accurate reference clock signals in computer and communication systems [6]–[10]. As microprocessor and communication
system clock speed increases, jitter specification becomes a
crucial circuit design parameter. For example, in a synchronous
digital system with a clock frequency of 10 MHz, jitter of
1 ns duration may bring 1% data uncertainty. If the system
clock frequency increases to 100 MHz, the same 1-ns jitter
will cause 10% data uncertainty. As gigahertz digital systems
become common, jitter needs to be identified to avoid degradation of system performance and potentially other serious
consequences.
The proposed circuit is implemented in the 0.5- m CMOS
VLSI technology available from MOSIS. We perform HSPICE
simulations to confirm that the proposed TVC circuit can properly measure PLL jitter in the hundred ps range with a reference
signal of 2 MHz (or 250 ns duty cycle). The reference signal
is order of magnitude slower than the jittery signal to be measured. The measurement error in this experiment is about 8%
when using the minimum configuration, in favor of a smaller
circuitry. We then present the analysis results to further clarify
the relationship between the design parameters and the measurement resolution. Designers can select the appropriate design parameters to fit many other timing measurement applications.
In the next section, we shall present the concept and the designs of TVC. Section III will describe the specific TVC design for on-chip PLL jitter measurement. The simulations will
be presented in Section IV. The analysis results for the design
parameters will be shown in Section V. Conclusions are given
in Section VI.
II. TIME-TO-VOLTAGE CONVERTER
The TDC is mainly used to measure the time interval or pulse
width. One of the important methods to implement the TDC is
shown in Fig. 1, which consists of a TVC followed by an A/D
0018-9456/03$17.00 © 2003 IEEE
XIA AND LO: TIME-TO-VOLTAGE CONVERTER FOR ON-CHIP JITTER MEASUREMENT
1739
converter [11], [12]. In this method, the time interval T between
and
is first converted into a voltage offset
(1)
is digitized into a final digital number N using an A/D
Then,
converter. Generally, the TDC is implemented with a constant
current and a capacitor C. From (1), we can see that the accuis determined by the accuracies of and capacitor
racy of
C. However, due to process variations, it is difficult to control
the accuracy of these components. Thus measurement error will
be inevitably introduced. Additionally, the resolution of the A/D
converter will also affect the measurement accuracy.
Here, we proposed a new method to directly measure time interval without A/D converter, which takes advantage of the repetition of the signal under measurement, and can minimize the
effects of process variations. We called this new method TVC
to N as in the presince it does not require the translation of
vious method. This method is especially suitable for measuring
very short time interval. Its circuit diagram is shown in Fig. 2.
In this circuit, there are one charging current source and one
discharging current sink . is controlled by a low frequency
to charge the capacitor C. is controlled
reference signal
by the signal under measurement, , to discharge the same capacitor. In the application to be shown in a later section, this
signal under measurement is PLLs timing jitter, whose pulse
s. We conwidth is much shorter than the reference signal
’s
trol to charge the capacitor C with voltage offset V in
one positive half cycle, then use to discharge the same capaccycles. For the signal
itor by the same voltage offset in N
should be much larger than
with very narrow pulse width,
. Larger can expedite the discharging process. A counter is
used to record the number N for discharging process, such that
(2)
Consequently
(3)
where T is the pulse width of signal under measurement. Note
that C has been cancelled in the above equation. Here, we can
see the measurement result depends on the current ratio of
, instead of on the absolute value of the current
and
the capacitor C. Therefore the effects of process variations are
minimized. Further, in the proposed TVC, the voltage level
on the capacitor is not converted to a digital number. Instead,
this voltage level is compared against a threshold to enable
or disable the counter.
III. JITTER MEASUREMENT IN CHARGE-PUMP PLL
Although PLL is typically a small circuit, testing a PLL is extremely time consuming and complex. Among the PLL specifications, jitter is the single most important and the most difficult
to measure parameter. Jitter is the deviation of frequency and
phase in the clock signal generated by the PLL. In typical cases,
the jitter is in the range of picosecond (ps). For example, the
jitter specification of the PLL in [9] is within 100 ps at 300 MHz
Fig. 1.
Time-to-digital converter.
Fig. 2.
Proposed TVC circuit.
output frequency. To accurately measure signal in such a short
duration, off-chip measurement is used in practice [13]–[16].
Needless to say that such technique is expansive and is not adequate for embedded PLLs.
An on-chip method is proposed in [17], [18], which uses
sigma-delta principle to obtain the jitter transfer function,
and does not measure the timing jitter value. Another on-chip
method is proposed in [19], [20], which uses a set of delay
units to measure the timing jitter, and does not affect the
PLL’s normal operation, but because the exact delay time of
each delay unit is difficult to know, it makes the measurement
procedure complicate. In [21], Intel also employed on-chip
circuit to test PLL jitter in their Pentium 4 CPU.
A. Charge-Pump Based PLL Frequency Synthesizer
Charge-pump based PLL is widely used due to its extended
operation frequency range and low cost [22], [23]. The general
structure of a charge pump based PLL is shown in Fig. 3. It
is composed of a phase/frequency detector (PFD), which detects phase error between a reference signal and PLL’s feedback
signal to generate digital pulses. The digital pulses are then used
to control the subsequent charge pump to charge or discharge a
loop filter. Depending on the requirement of specific application, the loop filter could be different types: passive filter or active filter; second order filter or higher order filter. The filter’s
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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 6, DECEMBER 2003
Fig. 3. Block diagram of a charge pump based PLL frequency.
output signal controls a voltage-controlled oscillator (VCO).
When the phase error between reference signal and PLL’s feedback signal becomes zero or nearly zero, the VCO will oscillate
is
at a stable frequency. The frequency divider with ratio
used to force the PLL to generate a frequency N times that of
the reference signal.
For frequency synthesizer, the jitter in the generated high frequency clock signal is one of the most important parameter,
[23]–[27]. According to ITU-T G-810 Recommendation, clock
jitter is defined as the “short term deviation in significant instants of digital signals referred to their equidistant normal instants.” Fig. 4 shows the jitter in a clock signal.
Following the jitter definition, if we have a jitter-free clock
signal with the same frequency as the signal under measurement, by comparing their phase, we can easily find the jitter.
However, for on-chip jitter measurement, to generate such a
high frequency golden signal is very difficult if not impossible.
In PLL, the only golden signal that we may safely assume is the
. Generally, we use a crystal oscilinput reference signal,
could be
lator to generate this reference signal. The jitter in
is order of magniassumed zero or nearly zero. However,
tude slower than the signal under measurement. The challenge
to measure the jitter in
.
is how to utilize this golden
B. Jitter in PLL Frequency Synthesizer
is produced by
From Fig. 3, we see the feedback signal
of
s. This
frequency divider, whose frequency is only
signal is transmitted to the phase/frequency detector to be com. By comparing it with the
pared with the reference signal
, we can obtain the jitter in .
jitter free reference signal
’s jitter? If
Is there any relationship between ’s jitter and
yes, what is that relationship? Before taking measurement, we
need to answer these questions first.
Suppose, we have a jitter free golden signal , which has the
. At time instant
’s
same frequency as PLL’s output
and ’s phase is
. The phase difference
phase is
and
is
between
(4)
The timing jitter
is
corresponding to this phase difference
(5)
Fig. 4.
Jitter in clock signal.
where
is the period of . Signal
goes into the frequency
divider and generates the feedback signal . If there is no jitter
’s frequency
should equal
’s frequency
,
in
of ’s frequency . Such that
which is
(6)
and
(7)
, the jitter will cause a phase error
If there is jitter in
between and
. At the output of the frequency divider, this
phase error will be divided by N, so
(8)
is the phase deviation of signal
where
is
sponding timing jitter
. The corre-
(9)
equals
.
Comparing (5) and (9), we find that jitter
However, this does not mean that we can measure any instanfrom signal . The phase frequency detaneous jitter
tector (PFD) detects phase errors by comparing the rising edge
and . Only when
(or falling edge) of the input signals
these signals’ rising edges arrive, the corresponding phase error
can be detected and converted to pulse sequence. Due to the frecan generate only one rising or
quency divider, N cycles
XIA AND LO: TIME-TO-VOLTAGE CONVERTER FOR ON-CHIP JITTER MEASUREMENT
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Fig. 5. Proposed on-chip jitter measurement circuit for the PLL frequency synthesizer.
falling edge in . Thus, the measured jitter of
is actually
. Since the time interval beN cycles accumulated jitter of
tween ’s one rising edge and the next is , we have
(10)
is the period of the jitter free signal , and
where
. Thus, the jitter obtained in
the jitter in ith cycle of
is
is
(11)
is actuFrom the above equation, we can clearly see that
ally an accumulated jitter, which equals the sum of N cycles
. This jitter is also called the long-term jitter. So, by
jitter in
’s long term jitter. From this
measuring signal , we know
’s average period jitter:
long-term jitter, we can calculate
dividing long-term jitter by N.
C. Proposed On-Chip Jitter Measurement Circuit
Fig. 5 shows the proposed on-chip jitter measurement circuit
for a PLL based frequency synthesizer. The jitter measurement
circuit is composed of a charge pump, an XOR gate, an analog
comparator with hysteresis, a capacitor, and a digital counter.
From Fig. 5, we can see that the test circuit does not directly
measure signal
, it uses the input jitter free signal
to
measure the feedback signal . For a PLL, its PFD compares
and , and generates two output signals
two input signals
’s phase is ahead of ’s, there will be a pulse in
U and D. If
’s phase falls behind of ’s, the pulse will
U. Similarly, if
appear in D. The pulse width is proportional to the phase error.
Therefore if we can measure the pulse width of U and/or D, we
will be able to calculate the timing jitter in .
1) Comparator With Hysteresis: In the proposed TVC
circuit, the comparator with hysteresis holds a very important
role. This comparator is designed as a clockwise bi-stable
comparator. The schematic of the comparator is shown in
and
Fig. 6. Fig. 7 illustrates its bi-stable characteristic.
are two threshold voltages.
is the central voltage between
these two thresholds. In the measurement circuit, the central
connects with comparator’s noninverse
voltage source
, which decides the central location of the characterispin
connects with comparator’s inverse
tics. The input signal
is much lower
pin. Initially, when the input voltage
and
, the voltage level on comparator’s output
than
, due to hysteresis, the
terminal is logic-1. If we increase
is higher than
.
output will not turn to logic-0 until
gradually, comparator’s output will not
Then we decrease
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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 6, DECEMBER 2003
Fig. 6. Analog comparator.
Fig. 7. Characteristics of the analog comparator with hysteresis.
flip back to logic high until
is lower than
. The voltage
and
is hysteresis.
difference between
2) Charge Pump: Fig. 8 shows the charge pump circuit
[9]. This charge pump consists of one current source , one
and four switches. M4, M5, M9, and M2
current sink
form the charging current source . M1, M13, M15, and
M12 form the discharging current sink . M6 and M11 are
to effectively switch
used to discharge/charge node
off charging/discharging process when M7, M10, or M3 are
inactive. They will also reduce the charge sharing between
charging current source and discharging current sink. The
charging current source and discharging current sink are
switched on/off by signals
, and
. When
is high,
is low, the discharging current sink
is cut off, the charging current source
is under the control
. During
’s positive half cycle, the current
of signal
XIA AND LO: TIME-TO-VOLTAGE CONVERTER FOR ON-CHIP JITTER MEASUREMENT
1743
Fig. 8. Charge pump structure.
Fig. 9.
Phase/frequency detector.
source is activated. When
is low, the charging current
is
source is cut off, while the discharging current t sink
. The
’s positive cycle is used to
controlled by signal
conduct the discharging current sink . By setting the P and N
respectively, the transistors of M5 and
nodes to GND and
M12 operate at saturation region, which can eliminate a large
instantaneous current during the transition. Hence, the output
can be more stably generated.
voltage of
3) Phase/Frequency Detector (PFD): As shown in Fig. 5,
the measurement circuit connects only to the U and D of the
. As we
PLL under measurement, and share the input,
can see below, U and D nodes are for digital signals. Thus,
the connections of the measurement circuit will not affect
PLL’s analog features. Fig. 9 shows the detailed schematic of
phase/frequency detector (PFD) inside the PLL. PFD is used
to detect the phase error between input reference signal
and PLL’s feedback signal . It serves as an error amplifier.
When the jitter in
is negative (the phase of
lags behind
the phase of ), a pulse will be generated in PFD’s output
is positive (the phase
terminal U. Similarly, if the jitter in
is ahead of the phase of ), the pulse will appear
of
in output terminal D. In the measurement circuit, we use an
XOR gate to get the voltage pulse whose width corresponds
to the jitter magnitude.
For the phase/frequency detector design, the main criterion
is to minimize the dead zone. The dead zone is the phase error
that cannot be detected. With dead zone, the PFD will not be
able to generate pulse in D or U properly. To reduce the dead
zone, a delay element is designed for RST signal. In addition,
an XNOR and two AND gates are used to eliminate the output
signals U and D being logic-1 at same time, which can help to
avoid the charge sharing between the charging current source
and discharging current sink in the followed charge pump subcircuit.
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Fig. 10.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 6, DECEMBER 2003
Injected jitter measurement.
D. Operation Principles
and
control switches S1 and
In the charge pump,
and and D flip-flop’s
S2, respectively, while the jitter pulse
control S3 and S4 separately. Capacitor
conoutput
nects to analog comparator’s negative input pin. The voltage
decides the central voltage of the comparator’s
source
sets the base voltage for the capacitor
hysteresis, while
. Their values are set to be
v, and
v. Actually,
equals comparator’s threshold voltage
. Thus, during measurement, the charging or discharging
process will start from or stop at this voltage point.
is less than
When the measurement process starts, since
initially, comparator’s output
is high, and D flipis high too. So, switch
is on. In
’s
flop’s output
is conducted. Thus the capacitor
positive half cycle, switch
is charged with current source . When the voltage on comparator’s inverse input pin reaches or becomes higher than the
will be toggled to logic-0. When a
threshold voltage
comes, the D flip-flop’s output
new rising edge of
flips to low and
flips to high. Thus switch
is cut off,
and the charging process stops. By setting the amplitude and
size, we can control the charging process to finish in one
cycle.
is high, is conAt the end of the charging process,
ducted, so the discharging process is enabled. Simultaneously,
a digital counter is activated to count the number of clock cycle
of
during discharging process. When there are jitter pulses
coming from the output of phase/frequency detector, switch
is conducted and the capacitor
is discharged by current sink
, the voltage over the capacitor is then decreased. When the
will flip to
voltage over the capacitor drops back to
logic-1, S4 is then cut off. The discharging process is thus ended.
at the binary counter’s output is
At this moment, the datum
locked and read out. Using this number , we can calculate the
jitter value in .
’s duty cycle is 50%, its positive pulse width is
Since the
. The charging voltage offset is
(12)
The discharging voltage offset is
(13)
Because these two voltage offsets are controlled to be equal
,
during the measurement process, we have
so
(14)
XIA AND LO: TIME-TO-VOLTAGE CONVERTER FOR ON-CHIP JITTER MEASUREMENT
Fig. 11.
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TVC measured PLL jitter.
Thus
(15)
The average jitter amplitude
is
the output frequency is 160 MHz. We perform the circuit simulations using HSPICE in two steps. First, we assume a golden
PLL is to be measured. This golden PLL can generate clock
signal without timing jitter. We then intentionally inject jitter to
this golden PLL to test the proposed TVC measurement circuit.
Next, we connect the TVC circuit with a jittery PLL without
jitter injection.
A. Fault Injection Experiment
(16)
From the above equations, we can see that the jitter amplitude could be calculated by the discharging and charging cur, the period of the reference clock signal
,
rent ratio
ratio is known before
and the counter’s output value .
the measurement, which is decided by the sizes of transistors
is also a pre-known parameter.
in the current mirror, and
Therefore, the only number we need to measure is .
IV. CIRCUIT SIMULATIONS
This section shows the PLL jitter measurement. In this PLL,
’s frequency is 2 MHz, and the frethe reference signal
quency divider’s ratio ranges from 71 to 80. Hence, this PLL
can generate frequency ranging from 142 to 160 MHz. In the following simulations, PLL’s frequency divider ratio N is 80, and
Here, a 160-ps jitter signal has been injected into the PFD’s
output for the simulations. In Fig. 10, we show the HSPICE simulation results. The first signal shown at the top is the input reference signal
with 2-MHz frequency. The second waveform
is the injected jitter signal with a pulse width of 160 ps. The
. We
third one is the voltage fluctuations over the capacitor
cycle to finish the charging process. The
can see, it takes 1
and
,
fourth and the fifth waveforms are signals
which are the outputs of the D-flip flop. The last four signals
, and
, respectively.
represent counter’s outputs
Their values represent the number of cycles of the discharging
A and
A.
process. In this case,
, we obtain
At the end of the simulation, when
. According to (16), we find
ns
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Fig. 12.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 52, NO. 6, DECEMBER 2003
Directly measured jitter without using TVC.
So, the measured jitter is 147 ps while the injected jitter is
160 ps. The measurement error is about 8%.
The 160-ps jitter is the long-term accumulated jitter. As explained earlier, the 160-ps at the PFD’s output may represent
a 160 ps/N average jitter at the output of the frequency syn.
thesizer. In this PLL, the frequency dividing ratio is
Hence, the proposed TVC measurement circuit is capable of
detecting a 2-ps average jitter at the output of the PLL-based
frequency synthesizer.
B. PLL Jitter Measurements
In Fig. 11, we show the PLL measurement without jitter injection. The signal depicted on the top is the input reference
. The second one is the feedback signal , which is
clock
represents the phase
the output of PLL’s frequency divider.
and . We also give out the waveform of
error between
, which is the control voltage of the PLL’s VCO. The amis stable, which means that the PLL is in locking
plitude of
, which is the voltage over
status. The fifth waveform is for
in the jitter measurement circuit. By analyzing
the capacitor
, we are assured that the charging process
the amplitude of
. The last four signals represent
is finished in one cycle of
and
, respectively. At the end
counter’s outputs
, which means
of the discharging process,
cycles.
the charging process takes 15
In this circuit, the charging and discharging currents and
are set to be 3.3 uA and 48 uA, separately. By using (16), we
can calculate
ns
(17)
This value is the calculated average long-term timing jitter. We
can convert it to get the corresponding phase error (unit: radian)
(18)
, and
. From this figure, we meaFig. 12 contains
and
directly. As labeled,
sure the phase error between
the directly measured phase error is around 1.25 ns. We can use
this value as reference to check our calculated jitter. The measurement error ratio
%
%
(19)
Since PLL’s frequency dividing ratio N is 80, we can deduce that
is about
the approximate jitter magnitude in PLL’s output
ns
ps.
V. DESIGN PARAMETERS ANALYSIS
To design an on-chip measurement circuit, several factors
need to be considered, measurement time, measurement resolution, the effect of process variations in fabrication, and
resource overhead. According to the above analysis, we know
the measurement time length is
is the time length of the discharging process,
is the
time length of the discharging process. Thus, to shorten the
smaller. From
measurement time, we should try to make
Fig. 13, we can see, when the jitter is within some certain
is inversely proportional to the current
range, the value of
, which means by increasing the current ratio of
ratio of
, we can make
small, and expedite the measurement
ratio cannot be increased limitlessly,
process. However,
because its value also decides the measurement resolution.
As depicted in Fig. 14, the smaller current ratio can bring
,
relatively better resolution. If we use larger ratio of
XIA AND LO: TIME-TO-VOLTAGE CONVERTER FOR ON-CHIP JITTER MEASUREMENT
Fig. 15.
Fig. 13.
Relationship between N and I =I .
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Layout of PLL and jitter measurement circuit.
In this proposed jitter measurement circuit, the potential effects of the fabrication process variations are minimized. From
is one of the
previous descriptions, we see that capacitor
crucial components, which is shared by the charging process
and discharging process. In fabrication, due to the process variations, it is nearly impossible to manufacture a capacitor with
%
absolutely precise value. The general variation is around
%. Fortunately, our proposed method does not require
to
building a precise capacitor, which is clearly shown in the (16).
is cancelled out. Therefore,
In the calculation, the capacitor
a not so accurate capacitor does not affect the measurement
accuracy.
In Fig. 15, we show the layout of the PLL and the proposed
built-in jitter measurement circuit. The large area in the lower
right hand corner of the proposed measurement circuit is the capacitor . Based on this layout, the area overhead of the proposed design is about 21%. We remark here that the overhead
ratio sounds high because of the small size of PLL. The proposed design is quite compact.
VI. CONCLUSION
Fig. 14.
Relationship between measurement resolution and I =I .
the resolution will be worsen. Therefore, there is a trade off
between the measurement time and resolution, for different
applications, we should find a balance point between them.
is about 1 ns, we can set the
For example, if the jitter in
around 15, with this ratio, the measurement
current ratio
jitter,
resolution is about 55 ps, which is about 5.5% of the
and the measurement time is about 16 cycles of reference signal
or nearly 8 ms.
was set
In the above experiments, the reference signal
at 2 MHz. If a faster PLL with a faster reference clock signal
will decrease. Consequently, the
is used, the cycle time
cycle will be reduced, which
charging voltage offset in one
can be inferred from (12). Hence, the discharging process will
take less time to discharge the same voltage offset. Essentially, a
faster reference clock signal will result in a faster measurement
process. Of course, this voltage offset should be larger than comparator’s hysteresis.
We have presented a design of TVC and demonstrated its application to the on-chip jitter measurement in the PLL-based frequency synthesizer. By charging and discharging on the same
capacitor, we cancel out the need to have a precise capacitor
be fabricated (which is almost impossible). This is crucial for
on-chip measurement as it eliminates the tedious tuning process.
Further, the TVC takes timing measurement without a sampling
clock. Note that the sampling clock in the conventional approach
must be an order of magnitude faster than the signal to be meais an order of magsured. In the demonstrations above, the
nitude slower than the jitter under measurement.
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Tian Xia (M’01) received the B.E. degree in
electrical engineering from Huazhong University of
Science and Technology, Wuhan, China, in 1994,
the M.S. degree from Nanjing University of Posts
and Telecommunications, Nanjing, China, in 2000,
and the Ph.D. degree in electrical and computer
engineering from the University of Rhode Island,
Kingston, in 2003.
He is currently an Assistant Professor at the University of Vermont, Burlington. From 1994 to 1997,
he was with Panda Electronics Company, Nanjing,
China, working on microprocessors and FPGA. During the summers of 2002
and 2003, he worked in the PICA group at IBM T. J. Watson Research Center,
Yorktown Heights, NY. His main research interests are in mixed-signal VLSI
design and testing.
Jien-Chung Lo (SM’97) received the Ph.D. degree
in computer engineering from the University of
Southwestern Louisiana, Lafayette, in 1989.
He is currently a Professor with the Department of
Electrical and Computer Engineering, University of
Rhode Island, Kingston. He served as Guest Editor
for the Journal of System Architecture in 2002. His
current research interests include fault-tolerant computing, distributed computing, reliable logic circuit
designs, and mixed-signal VLSI testing.
Dr. Lo was the General Chair of the IEEE 8th
North Atlantic Test Workshop, West Greenwich, RI, May 1999, Program
Co-Chair of the IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, October 2000, and the General Co-Chair of the IEEE
Symposium on Defect and Fault Tolerance in VLSI Systems, October 2001.
He is currently an Associate Editor of IEEE TRANSACTIONS ON COMPUTERS.