152
IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 4, APRIL 1999
On the Correlation Between Drain-Gate Breakdown
Voltage and Hot-Electron Reliability in InP HEMT’s
R. Menozzi, M. Borgarino, K. van der Zanden, and D. Schreurs
Abstract—By comparing devices with different recess widths,
we show that the off-state drain-gate breakdown voltage (BVDG )
may give totally misleading indications on the reliability of
lattice-matched InP HEMT’s under hot-electron (HE) and impact
ionization conditions, from both standpoints of gradual and catastrophic degradation. Since the hot-electron degradation effects
observed in our HEMT’s are quite common, we believe that
our results should be considered as a general caveat whenever
indications on HE HEMT robustness are inferred from BVDG
measurements.
Index Terms— FET’s, high-speed circuits/devices, microwave
FET’s, millimeter-wave FET’s, MODFET’s, reliability.
under practical load conditions,
is the actual reliability
bottleneck [11], [12].
Consistent with these findings, by comparing the
values and the HE degradation of 0.2- m InAlAs/InGaAs/InP
HEMT’s with different gate recess widths, in this letter we
show for the first time that the indications provided by
and those coming from openthe measurement of
channel HE stress experiments go in opposite directions, thus
can be a
confirming that the sole determination of
totally misleading indicator of HE robustness.
I. INTRODUCTION
R
ELIABILITY issues due to hot-electron (HE) and impact
ionization conditions in HEMT’s are given increasing attention in the literature and in industrial reliability assessment.
Very large fields are indeed present in sub-0.25- m channels
when, for the HEMT’s to deliver satisfactory output power,
) is pushed as high as reliability
the drain-source voltage (
considerations allow; recent reports have revealed significant
degradation hazards in both GaAs PHEMT’s [1]–[3] and InP
HEMT’s [4]–[6]. The situation is particularly critical in InP
HEMT’s due to the very small channel bandgap, which favors
impact ionization.
The information on the HEMT capability to withstand
large drain-gate electric fields is typically compounded in
the two-terminal (i.e., off-state) drain-gate breakdown voltage
). The efforts of device designers are therefore aimed at
(
enhancement
devising clever gate recess geometries for
[2]. Generally speaking, the farther apart the drain and gate
, but the power performance is then
contacts, the larger
degraded [7].
or the on-state
It has been recently debated whether
) should be taken as an indicator for
breakdown voltage (
HE reliability. While off-state breakdown is better understood
and modeled [8], [9] than on-state breakdown [10], experimental and theoretical investigations indicate that for InP HEMT’s
Manuscript received October 30, 1998; revised December 7, 1998. This
work was supported in part by ESA, the Fund for Scientific ResearchVlaanderen, the Flemish Institute for Applied Scientific Research (IWT), and
NATO.
R. Menozzi and M. Borgarino are with the Dipartimento di Ingegneria
dell’Informazione, University of Parma, Parma 43100, Italy.
K. van der Zanden is with IMEC MAP-CSE, Leuven B-3001, Belgium.
D. Schreurs is with Katholieke Universiteit Leuven, ESAT-TELEMIC,
Leuven B-3001, Belgium.
Publisher Item Identifier S 0741-3106(99)02832-3.
II. DEVICES
AND
EXPERIMENTS
The HEMT’s were designed and fabricated at IMEC for
millimeter-wave low-noise applications. A schematic cross
section is given in Fig. 1. The channel is a 20-nm undoped In Ga As layer, on top of which sits the -doped
In Al As donor layer; a 7-nm n In Ga As cap
for the ohmics completes the epitaxial structure. After wet
mesa etching and Ni/Au/Ge/Ni/Au ohmic contact formation
(with a source-drain spacing of 1.5 m), the In Ga As
cap is selectively wet-etched for gate recess using a succinic
acid solution; the etch selectivity allows to vary the recess
) with limited vertical etch of the InAlAs. We
width (
) varying from
fabricated samples with recess etch time (
approximately increases
1 to 10 min. Correspondingly,
from 0.2 to 1.2 m. A threshold voltage ( ) increase of 50
mV/min ensues due to noninfinite etch selectivity. Using a
two-level resist e-beam process, a 0.2- m Pt/Ti/Pt/Au T-gate
(slightly offset toward the source) is then deposited. A 200-nm
PECVD SiN layer passivates the surface. Typical values of
peak transconductance ( ) and unity current gain frequency
( ) range from 700 to 800 mS/mm and from 80 to 90 GHz,
and
slightly
respectively. Due to larger drain resistance,
decrease as the recess widens.
The DC and RF characterization, as well as the HE stress,
were carried out on-wafer, at room temperature, using an
was
HP-8510 and a Cascade coplanar probe station.
producing a gate
measured, with source floating, as the
leakage current density of 1 mA/mm, consistent with most
published data. The HEMT’s were HE-stressed by biasing
) corresponding to the
them at the gate-source voltage (
(the most significant operating point for linear applipeak
cations); we applied 15-min stress steps at increasing values
, until reaching catastrophic failure (at a
value
of
).
that we call
0741–3106/99$10.00  1999 IEEE
MENOZZI et al.: CORRELATION BETWEEN DRAIN-GATE BREAKDOWN VOLTAGE AND HOT-ELECTRON RELIABILITY
Fig. 1. Schematic cross section of the HEMT’s under test. Different values
of the recess width WR have been obtained by varying the selective wet-etch
recess time tRE .
Fig. 2. Off-state drain-gate breakdown voltage (BVDG , ) and drain-gate
voltage for catastrophic failure (F VDG , 3) versus recess etch time (tRE ).
BVDG is defined as the drain-gate reverse bias giving a gate leakage current
density of 1 mA/mm with source floating. F VDG is determined biasing the
HEMT at the VGS value that gives the peak gm , and applying 15-min stress
steps at increasing VDG , until catastrophic failure is observed.
III. RESULTS
AND
DISCUSSION
Fig. 2 ( ) shows that
grows dramatically from about
3 to 18 V as the recess gets wider, in agreement with
published results [13] obtained on GaAs MESFET’s. The
farther apart the gate edge and the high-doping InGaAs cap,
. Therefore,
the smaller the peak electric field, at a fixed
for longer
. However,
breakdown is reached at larger
believing wide-recess devices to be more HE-resistant would
be erroneous.
at which the devices under
Fig. 2 also shows ( ) the
, see Section II), due to a
test failed catastrophically (
gate-drain resistive short (a typical product of HE-induced
burnout). There is some spread in the data, but it is clear
with
, hence with
,
that the correlation of
is quite weak, if at all existent, and by no means wide-recess
) devices may be considered more robust than
(i.e., high) ones.
narrow-recess (i.e., lowIn all of the HEMT’s, the HE stress produces, before
catastrophic failure, a gradual reduction of the drain current
153
Fig. 3. Relative change of the peak gm (measured at VDS = 1:8 V) after
HE stress, versus recess etch time (tRE ). The HEMT’s are stressed biasing
them at the VGS value that gives the peak gm , and applying 15-min stress
steps at increasing VDG up to 4 V. The solid line connects the mean values
calculated at each tRE . ’s correspond to HEMT’s with low prestress gm
compared with the other devices with the same tRE = 10 min.
( ) and
. In Fig. 3 we plot, as a function of
, the
(
) of HEMT’s stressed
relative decrease of the peak
V ( ), together with the average
up to the same
values (solid line) (as illustrated by the catastrophic
failure data in Fig. 2, not all of the samples outlived the stress
V; the picture in Fig. 3 therefore neglects
up to
V). The enhancement of the
the HEMT’s with
, as well as the contrast with
degradation with increasing
trend in Fig. 2, is remarkable. It should also be
the
min
noted that the two low-degradation points at
( ) were obtained from devices which had a relatively low
right from the start (10%–14% less than the other
peak
10-min devices); therefore, they should not be considered as
representative as the others. A trend similar to that of Fig. 3
has been observed for the reduction of , which amounts to
about 20% in the 10-min samples.
The data of Fig. 3 is consistent with results obtained on
InP HEMT’s [4]–[6], GaAs MESFET’s [14], and HEMT’s
and
is attributed to electron
[1]. The decrease of
capture at interface states between the semiconductor surface
and the SiN, or in the SiN itself, over the gate-drain region,
leading to reduced surface potential, hence increased depletion:
and
are degraded. This theory is
consequently, both
supported by the observation of breakdown walkout [15] in our
stressed devices, a notorious by-product of increased surface
depletion between gate and drain. It also explains why widerecess devices degrade more than narrow-recess ones. The
trapping of electrons at the surface, and the depletion that
ensues, are clearly more influential in wide-recess devices,
where much of the n InGaAs cap has been etched away,
because the semiconductor–SiN interface is closer to the
channel, and the screening provided by the high-doping cap
is reduced.
IV. CONCLUSIONS
(
We showed that the off-state drain-gate breakdown voltage
) may give misleading indications as to the reliability
154
IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 4, APRIL 1999
of InP HEMT’s under (HE) conditions, from both standpoints
is practically
of gradual and catastrophic degradation.
uncorrelated with the drain-gate voltage that prompts catastrophic failure, and shows a clear inverse correlation with
degradation. Since the HE effects degradation
the gradual
observed in our HEMT’s were observed in GaAs MESFET’s
and GaAs PHEMT’s as well, we believe that our results have
a general validity. They should be considered as a caveat
whenever indications on HE robustness are inferred from
measurements.
ACKNOWLEDGMENT
R. Menozzi and M. Borgarino are grateful to G. Vannini
and A. Santarelli (Univ. of Bologna, Italy) for the use of the
RF characterization equipment.
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