96 GHz Static Frequency Divider in
SiGe bipolar technology
Alexander Rylyakov and Thomas Zwick
IBM T.J. Watson Research Center
November 12, 2003
Outline
• Review of previous 0.13 um SiGe results:
– 4.2 ps Ring Oscillators
– 100 GHz Dynamic Divider
– 62 GHz ECL Static Divider
• Design of the 96 GHz E2CL Static Divider
• Test Setup and Measurement Results
• 0.13 um and 0.18 um SiGe Dividers
Performance Summary and Conclusion
SiGe8HP Technology Overview and
Ring Oscillators
Cutoff frequency +75% from prior generation: > 200 GHz fT
Power gain cutoff frequency +80% from prior generation:
fMAX(MAG) > 180GHz and fMAX(U) > 250 GHz
Record RO delays: < 50% of prior generation
■ Experimental SiGe9HP development wafer achieves 3.9 ps
RO delay vs. tail current
fT, fMAX vs. IC
300
Vcb=1V, 25C
5.2
U fMAX
VEE = -3.6V
5.1
250
Delay per stage, ps
5
200
Next generation
BiCMOS 8HP
fT
150
MAG fMAX
100
Production
BiCMOS 7HP
50
RNOM, WEMIT
4.9
R130, E12
R130, E16
R160, E12
R105, E12
4.8
4.7
4.6
4.5
InP best reported *
55% higher power
15+% lower swing
4.4
4.3
0
1.E-04
1.E-03
Collecto r current (A)
1.E-02
1.E-01
4.2
0.5
1
1.5
2
2.5
3
Tail current, mA
3.5
4
* (2002 data)
SiGe8HP Dynamic Frequency Divider
■ Record Performance:
► 100 GHz, 285mW at -3.8V
► outputs 260 mVpp single-ended at 50 GHz
► packaged and tested by SHF (Electronics Letters, Jan 2003)
■ Competition (published results):
► Hitachi: SiGe, 82 GHz, 396mW at -5.2V,
used divide by 4 (ISSCC 2000)
► NTT: InP/InGaAs HBTs, 90 GHz, 1.4W total at -5.5V,
used divide by 8, claim 110mW per flip-flop (IPRM 2002)
100 mV/div
GND
fIN
fOUT
VEE
Dynamic divider circuit diagram
10 ps/div
Output 50 GHz signal at 100 GHz input
SiGe8HP ECL Static Frequency Divider
■ Maximum input frequency: 62 GHz, at -3.8V
■ Close to 2x increase in performance (compared
to same design in SiGe7HP)
■ Power dissipation can be traded off
for performance
Die micrograph
Vee = - 3V, Pin = 0 dBm
tail current
( mA )
max frequency
( GHz )
2.8
60
1.0
49
0.8
45
0.4
30
Power-speed tradeoff
Design of the 96 GHz E2CL Static Divider
• Motivation:
– explore performance limits of 0.13 um SiGe
(“SiGe8HP”)
– compare design approaches
(ECL vs E2CL)
– develop test equipment
(dividers are useful for synchronization)
• Design Overview:
– fully static, double emitter follower design
– no inductive peaking
– input clock signal is not amplified, only down-shifted
using emitter followers
– output clock buffer is a Cherry-Hooper amplifier
Block Diagram of the Design
CLOCK/2
Q
D
DB
LATCH
C
CB
Q
D
DB
QB
LATCH
C
CB
QB
Cherry-Hooper
Emitter Followers
CLOCK
Latch Schematic
GND
R1
R2
DATA IN
CLOCK
VEE
DATA OUT
Die Micrograph
CLOCK/2
CLOCK
Test Setup Block Diagram
~
1.85 mm Coax
Trigger
SMA Coax
/2
Oscilloscope
Probe:
GPPGSGSGPPG
Spectrum
Analyzer
CW Source
(12-18 GHz)
Probe
Needles
DUT
SMA Coax
Probe
Needles
Phase Shifters
x6
WR10
Variable Attenuator
α
WR10
WR10
Amplifier
( 14 dB at 85 GHz)
all on one positioner
ϕ
Magic T WR10
Term
as
Balun
WR10
WR10
ϕ
WR10
1 mm Coax
Probe:
GPPGSGSGPPG
Frequency Multiplier
( 75 – 110 GHz )
WR10
WR10 to 1 mm adapters
Test Setup
1.0 mm Cable
Magic-T
Multiplier
Amplifier
Attenuator
Phase Shifter
WR-10 to 1.0 mm Adapter
50 mV/div
48.3 GHz Output Signal
10 ps/div
Divider Output Spectrum
Divider Output Spectrum
( 20 MHz span)
Input Sensitivity of the Divider
10
5
Input Power, dBm
0
-5
-10
-5.5V, differential clock
-15
-20
-5.5V, single-ended clock
-25
-5.0V, single-ended clock
-30
-35
0
10
20
30
40
50
60
Input Frequency, GHz
70
80
90
100
SiGe8HP and 7HP Frequency Dividers
Performance Summary
0.13µm SiGe (8HP)
* Dynamic
ECL
VEE (V)
-3.8
* Static
ECL
† Static
E2CL
0.18µm SiGe (7HP)
* Static
ECL
* Static
ECLi
* Static
E2CL
-3.8
-5.5
-3.6
-3.6
-5.2
IEE (mA)
75 1
68 1
140 1
32 2
80 1
662
fSO (GHz)
none
24
35
9
18
19
fCLK(GHz)
100
62
96
33
41
49
fSO is the frequency of self-oscillation
fCLK is the maximum input frequency
Dividers marked with ‘1’: total current for the whole chip
Dividers marked with ‘2’: estimate for divider core only
■ Static ECL shows ~ 2x speed up (8HP vs 7HP, same design and power dissipation)
■ Within same technology, E2CL is faster than plain ECL, but burns more power
■ Inductive peaking (ECLi) also improves performance, trading off area
( * Electronics Letters, Jan. 2003; † This work )
Conclusion
A 96 GHz Static Frequency Divider was
designed and tested in a 210 GHz fT
0.13 µm SiGe bipolar technology
To our knowledge, this is the fastest static
divider in any Si-based technology