3rd International Conference on Electrical & Computer Engineering
ICECE 2004, 28-30 December 2004, Dhaka, Bangladesh
AN AT89C51 MICROCONTROLLER BASED CONTROL CIRCUIT
FOR DUAL THREE PHASE CONTROLLED RECTIFIER
K. M. Rahman1, M. A. Choudhury2 and Tofayel Ahmed Zulfikar3
1
Department of Mechatronics, International Islamic University Malaysia
Jalan Gombak, 53100 Kuala Lumpur Malaysia, Email:kazi@iiu.edu.my
2
Department of Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh
Email: mac@eee.buet.ac.bd
3
Subdivisional Engineer Ghorashal Power Plant BPDB, Ghorashal, Bangladesh
ABSTRACT
A new concept of building the controller of a
thyristor based three-phase dual converter is
presented in this paper. The controller is
implemented using mixed mode digital-analog
circuitry to achieve optimized performance. The realtime six state pulse patterns needed for the converter
are generated by a specially designed ROM based
circuit synchronized to the power frequency by a
phase-locked-loop. The phase angle and other
necessary commands for the converter are managed
by an AT89C51 microcontroller. The proposed
architecture offers 128-steps in the phase angle
control, a resolution sufficient for most converter
applications. Because of the hybrid nature of the
implementation, the controller can change phase
angles online smoothly. The computation burden on
the microcontroller is nominal and hence it can easily
undertake the tasks of monitoring diagnostic data like
overload, loss of excitation and phase sequence. Thus
a full fledged system is realizable with only one
microcontroller chip, making the control system
economic, reliable and efficient.
1. INTRODUCTION
Thyristor based three-phase controlled rectifiers are
widely used in the industry for controlling dc motor
drives. Controlled rectifiers offering power
conversion from ac to dc are reliable and have higher
lifetime compared to other converters. DC motors
have higher torque than ac motors and hence are
suitable for variable speed and speed reversing
applications requiring high torques [1]-[2]. Although
the operation of controlled rectifiers is simple, the
realization of the converter control circuit is complex
in nature [3]-[5]. The control circuit needs the basic
functionalities like (i) Six state pulse generation and
gate drive isolation, (ii) Synchronization of the
control pulses to the power frequency, (iii) Smooth
ISBN 984-32-1804-4
transition in phase angle control, (iv) Startup control,
(v) Phase sequence check, field excitation check and
over-current protection. If the pulse pattern
generation and other control tasks are to be
undertaken by a single processor, an ultra high speed
processor is needed because of the real-time nature of
the system [6]. Moreover, special design interfaces
are required for sensing excitation loss and phase
sequence checks. This makes the system
implementation costly.
In this paper, a new approach is proposed where a
hybrid type circuit generates the real time pulses for
the converter and a processor supervises the
controller functionality. The processor sets the phase
angle, monitors the current, phase sequence,
excitation condition and external control inputs for
start, stop, speed change and speed reversal
operations. For compact and cost effective design,
instead of using a general purpose microprocessor
along with peripheral interfaces, a single
microcontroller chip may be used for the
implementation. All the necessary controls of a
vertical lathe machine driven from a 55kW dc shunt
motor are incorporated in the proposed design using
AT89C51 microcontroller. It is observed that the
AT89C51 driven from a 20MHz clock along with the
hybrid controller can efficiently accommodate all the
control functions in the full operating range of the
converter.
2. THE CONTROLLED RECTIFIER
The dual-converter is designed with SKKT92
silicon-controlled-rectifier (SCR) modules. Because
of application specific design, only one converter
(either the forward converter, P or reverse converter,
N) operate at a time. The P converter gives positive
output voltage Vs, whereas, the N converter gives
negative output voltage. The structure of the dual
converter is shown in Fig. 1.
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Reverse (N) converter
Forward (P) converter
va = Vm sin ωt
+
T3
T1
A
~
B
T4
~
C
T6
T3*
T1*
T5
~
Vs
~
A
T4*
T2
~
T5*
B
T6*
~
C
T2*
-
Fig. 1 Thyristor based dual converter structure.
Three phase mains are connected to the ac inputs A,
B and C for phase-A, phase-B and phase-C
respectively. Considering a phase sequence of ABC,
the phase angle control range is π/6 ≤ α ≤ 2π/3.
Within the operating control range (π/6 ≤ α ≤ 2π/3),
two thyristors (one from the top row and the other
from the bottom row) of the converter conducts the
dc output load current. The overlapping of
conduction of two thyristors are π/6. For three phase
ac input voltages given in (1), the firing angle α is
calculated considering the positive zero crossing of
phase A voltage va as the reference.
v a = Vm sin(ωt )
vb = Vm sin(ωt − 2π / 3)
vc = Vm sin(ωt − 4π / 3)
(1)
Considering inductive load, the output voltage is
given by,
3 α+π / 3
Va =
vab d (ωt )
π α
3 α+π / 3
=
Vm sin(ωt − 5π / 6)d (ωt )
π α
0 π/6 2π/6 π/2 2π/3 5π/6 π 7π/6 8π/6 3π/2 5π/3 11π/6 2π
g1
g2
g3
g4
g5
g6
Fig. 2 Six state pulses for the ac/dc converter.
3. PROPOSED CONTROLLER
3.1 Hybrid Circuit for Six-State Pulse Generation
The proposed scheme is shown in Fig. 3. A total of
128 different shifted patterns are stored in EPROMs.
To have exactly π/3 radians shifting in the six-state
real time pulses, the stored pattern are chosen to be a
multiple of 6. In the proposed design each pattern has
6x64=384 bits.
~
∫
∫
ZCD
Phase
Detector
LPF
Divide
by 384
VCO
3 Phase Supply
Vs
~ ~ ~
+ -
Vcc
(2)
Simplification of (2) yields,
V 3 3
cos(α − π / 6)
Va = m
π
~
Phase A
Increase
Decrease
Overload
Excitation
Phase A
Phase B
Direction
Position
Mode
(CC/CS)
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P3.3
P3.4
P3.5
RUN P0.0
PSEQ P3.0
Fopen P3.1
O/L P3.2
P2.0-P2.6
P0.1
A9-A15
CE
A0-A8
D0-D5
Stored PWM
Pattern
6
Forward
Amplifier
Reverse
Amplifier
Isolation
AT89C51
From (3), it is evident that the converter gives
maximum dc output of Vm 3 3 / π at α = π / 6 and
zero dc output at α = 2π / 3 , giving a control range of
π/2 radians. Six state pulses, each spaced at π/3
radians are required for the converter. For the P
converter, the pulse sequences are g1, g2, g3, g4, g5
and g6 for the thyristors T1,, T2, T3, T4, T5 and T6. For
inductive load, each thyristor may conduct for π
radians. Hence the gate pulse of a thyristor should be
extended for duration of π radians once fired. Typical
firing pulses for the converter are shown in Fig. 2.
For the reverse converter, the pulse sequences are
same as the forward converter, however, the gating
signals g1, g2, g3, g4, g5 and g6 are applied to the
thyristors T*1, T*2, T*3, T*4, T*5 and T*6.
P1.0-P1.7
Reverse
Converter
9
7
F/R P3.6
(3)
Forward
Converter
8
DB0-DB7
+Vcc
ADC0804
Position
Potentiometer
Fig. 3 Proposed control scheme using hybrid circuit
for generating synchronized six-state pulses for the
ac/dc converter.
The centre frequency of the PLL-VCO is set to
384*50=19.2 kHz considering the nominal supply
frequency to be 50Hz. The PLL takes few cycles to
synchronize with the supply frequency. Hence the
converter should not be turned ON during the capture
period; otherwise, there will be unwanted high
voltage output from the converter. To ensure error
free operation, the AT89C51 sends a disable signal at
P0:1 line connected to the PWM EPROM and the
associate firing circuitry during the first few cycles.
The AT89C51 microcontroller supervises the
operation of the controller and makes necessary
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diagnostics. The AT89C51 is programmed according
to the following algorithm:
Controller Algorithm
1) Initialize the reference voltage output Vref. Set
Vout = 0; Vδ = 0. Disable EPROM output.
2) Check the field circuit at P0.5. If field circuit is
open goto step 17, else goto step 3.
3) Check the phase sequence from the signals at
pins P0.6 and P0.7. If phase sequence is not
correct, disable the EPROM then goto step 16.
4) Delay for some time so that the PLL can lock the
input supply frequency.
5) Check the mode of operation at pin P3.5. If
constant motor speed is needed (mode=0), then
set Vchange = 0, otherwise read the ADC data
connected at port P1 and set Vchange = ADC data.
6) Check the direction of rotation at pin P3.3. If
direction changes while motor runs, reset speed
to zero first and wait some time. Choose the
appropriate converter (Forward or Reverse) at
pin P3.6.
7) Check the field circuit. If field circuit is open,
disable the EPROM and goto step 17, otherwise,
goto step 8.
8) Check for inching motion request at P3.4. If
inching motion is requested, disable the EPROM
output and set Vout = 0, otherwise keep Vout as
before.
9) Keep track of the number of cycles counter, K. If
K = Kmax, goto step 10, otherwise, goto step 13.
10) Set K = 1. Check the speed requests at pins P0.2
(increase) and P0.3 (decrease). If speed increase
is requested, increase Vref. If speed decrease is
requested, decrease Vref.
11) If Vref > Vout, increase Vout. If Vref < Vout, decrease
Vout.
12) If Vchange > Vδ, increase Vδ. If Vchange < Vδ,
decrease Vδ.
13) Set the phase angle α corresponding to Vout + Vδ
and send the phase angle data to the EPROM
connected at port P2. Enable the EPROM.
14) Check the overload status pin P0.4. If overload
detected, disable the EPROM and then goto step
18, otherwise, goto step 15.
15) Check for the start of a new cycle. If a new cycle
is detected, increment K, otherwise, keep K as
before. goto step 5.
16) Send blink signal at P3.0. Loop at this step.
17) Send blink signal at P3.1. Loop at this step.
18) Send blink signal at P3.2. Loop at this step.
scan pulses in a fundamental period in synchronism
with the phase-A voltage reference. The phase
detector PD2 of CD4046 is used that produces inphase pulses at Cin with the reference at Sin when the
PLL is in locked condition. The Q9 and Q10 lines of
the 14-bit binary counter (CD4040) are connected to
an AND gate. The output of the AND gate is
connected to the asynchronous RESET input of
CD4040. Thus the CD4040 is reset after a count
value of 384. The inverted Q9 signal is connected to
the phase detector input (Cin pin of CD4046). The
waveform at Cin pin of CD4046 has a duty cycle of
66% in locked condition.
4049
Cin
Phase A
reference
VCO OUT
Clock
Q9
Q10
Sin
CD4046
CD4040
P2
Rx
VCO IN
Rz
R1
Cx
Reset
Ry
Q1-Q9
C2
Cx
9
A0-A8
C1
Fig. 4 Phase locked loop (PLL) circuit and the scan
counter for the control circuitry.
3.3 Protection Circuits
3.3.1
Overload Protection
To protect the converter thyristors and the dc load
from over-current, two phase current from the ac side
is monitored. Since the converter operate in fullbridge mode, during fault in any phase of the
converter, the fault current returns through the other
two phases. Hence, the current monitored on any two
phases can sense the overload if any. In the proposed
scheme, the overload protection circuit monitors the
phase currents of A and B. Two current transformers
isolate the live lines and the secondary sides are fed
to a bridge rectifier. The output of the bridge rectifier
is connected to a low resistance R1. A pulsating
voltage is generated across R1 proportional to the
maximum current of the A or B phases that is filtered
with a large capacitor C. After filtering, the output
becomes a dc voltage that is applied to an optoisolator (4N35) through a potentiometer. The
potentiometer sets the overload limit.
Vcc
D1
D3
D5
A
B
R1 C
D4
D6
R3
R2
P0.4
D2
74LS14
3.2 The Phase Locked Loop (PLL) Circuit
4N35
The PLL circuit is shown in Fig. 4 and is the crucial
part of the controller. It is designed to generate 384
Fig. 5 Overload protection incorporated from two
phases of the ac side.
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Rectifier Output Voltage
600
Voltage (V)
The output of 4N35 is buffered with inverters to
generate TTL logic level voltage that feds the P0.4
pin of AT89C51. Figure 5 shows the over-current
protection circuit used in the proposed scheme.
400
200
Phase A
Phase B
Phase C
0
Vcc
D1
D3
D5
Phase C
Neutral
D4
R1
0
R2
D6
D2
P0.5
74LS14
4N35
Field (-)
Field (+)
2
3
Angle (Rad)
4
5
6
Fig. 7 Three phase voltages and controlled rectifier
output voltage for a phase angle of 600, the rms
phase voltage is 240V.
5. CONCLUSION
Fig. 6 Loss of excitation (field) protection taking
feedback from the field circuit current.
3.3.2
1
Loss of Excitation Protection
For shunt type dc motor drives, the field current is
different from the armature current. The field circuit
should be checked before supplying current to the
armature; otherwise, short circuit current may flow
damaging the armature commutators and the
converter thyristors. The output of the field circuit
bridge-rectifier (D1-D4) as shown in Fig. 6 is
connected to two series diodes (D5-D6) before
applying to the motor field. During steady state, dc
current flows in the motor field if the field circuit is
in good condition and its mains have proper supply
voltage. The dc voltage across D5-D6 will be VE =
2Vth, where Vth is the threshold voltage of the series
diodes D5 and D6. The diodes D5 and D6 are silicon
power diodes, hence, during conduction VE will be
about 1.4V. The output VE is connected to an optoisolator 4N35 and the isolated output of 4N35 is
buffered and fed to pin P0.5 of AT89C51. Thus with
presence of field excitation, the opto-isolator
produces a logic 0 level voltage at P0.5 of AT89C51.
4. RESULTS
The proposed converter and the controller are built
and tested in the laboratory. The converter is also
tested as part of the 55kW dc shunt motor drive of a
vertical lathe machine of Ghorashal Power Plant
Workshop. The controller functions properly as per
theoretical expectations and offer smooth operation
during steady state and dynamic conditions. The
protection features are also tested during the running
conditions and found to work well. Reversal of
speed, increase or decrease of speed, constant cutting
and constant motor speed operations are also tested
and verified at both full load and no load conditions.
Simulation output of a typical three phase ac input
voltages and the rectifier output voltage are shown in
Fig. 7 for a firing angle of 600.
A new technique for designing the controller of a
converter is reported in this paper. The controller is
implemented using mixed analog digital and memory
circuitry centered on a single chip microcontroller.
Because of the hybrid type of implementation, the
controller offers high performance at low cost, and
hence is suitable for commercial and industrial
applications.
ACKNOWLEDGEMENT
This work was supported by Bangladesh Power
Development Board (BPDB).
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