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py g © 2004 byy Oxford Universityy Press, Inc.
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ISBN 0–19–517267–1
Printing number: 9 8 7 6 5 4 3 2 1
Printed in the United States of America
2
Introduction to Electronics
3
υ s ( t ) = Rs is ( t )
υ s (t ) = Rs is (t )
Figure 1.1 Two alternative representations of a signal source: (a) the Thévenin form, and (b) the Norton form.
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Figure 1.2 An arbitrary voltage signal vs(t).
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υ ( t ) = Va sin ω t
a
(1.1)
Figure 1.3 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency V = 2Pf rad/s.
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4V
1
1
(sin ω 0 t + sin 3ω 0 t + sin 5ω 0 t + ⋅ ⋅ ⋅)
υ(t) =
3
5
π
(1.2)
Figure 1.4 A symmetrical square-wave signal of amplitude V.
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Figure 1.5 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.4.
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Figure 1.6 The frequency spectrum of an arbitrary waveform such as that in Fig. 1.2.
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Figure 1.7 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).
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Figure 1.8 Variation of a particular binary digital signal with time.
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D = b0 2 + b1 2 + b2 2 + ⋅ ⋅ ⋅ + bN −1 2
0
1
2
N −1
(1.3)
Figure 1.9 Block-diagram representation of the analog-to-digital converter (ADC).
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υ 0 ( t ) = Aυ i ( t )
(1.4)
Figure 1.10 (a) Circuit symbol for amplifier. (b) An amplifier with a common terminal (ground) between the input and output ports.
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υ0
Voltage gain (Aυ ) ≡
υI
(1.5)
Figure 1.11 (a) A voltage amplifier fed with a signal vI(t) and connected to a load resistance RL. (b) Transfer characteristic of a linear voltage amplifier
with
ith voltage
oltage gain Av.
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load power (PL )
Power gain (A p ) ≡
input power (PL )
υ 0 i0
=
υ I iI
i0
Current gain (A i ) ≡
iI
A p = Aυ A i
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(1.6)
((1.7))
(1.8)
(1.9)
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15
Voltage
g ggain in decibels = 20 log
g Aυ
dB
Current gain in decibels = 20 log Aυ
dB
Power gain in decibels = 20 log Aυ
dB
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Pdc = V1 I1 + V2 I 2
η ≡
Pdc + PI = PL + Pdissipated
PL
× 100
Pd c
(1 .1 0 )
Figure 1.12 An amplifier that requires two dc supplies (shown as batteries) for operation.
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EXAMPLE 1.1
Input
9
= 9V/V
1
Aυ = 20 log9 ≅ 19.1 dB
Aυ =
Vi: 1V
Ii: 00.11 mA
Output
Vo: 9V
1 kΩ
Power Supply
±10V, 9.5 mA
∧
I0 =
9V
= 9mA
1kΩ
∧
Ai =
I0
∧
I0
=
9
= 90 A/A
01
0.1
A i = 20 log90 = 39.1 dB
PL = V0rms I 0rms =
PI = Virms I irms =
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9
2
9
2
1 0.1
2
2
= 40.5 mW
= 0.05 mW
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18
Ap =
PL
40 5
40.5
=
= 810 W/W
0.05
PI
A p = 10 llog810
810 = 29
29.1
1 dB
Pdc = 10 × 9.5 + 10 × 9.5 = 190 mW
Pdissipated = Pdc + Pi - PL
= 190 + 0.05
0 05 - 40.5
40 5 = 149.6
149 6 mW
η =
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PL
× 100 = 21.3 %
Pdc
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19
L−
Aυ
≤ υI
≤
L+
Aυ
Figure 1.13 An amplifier transfer characteristic that is linear except for output saturation.
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υ I ( t ) = VI + υ i ( t )
υ 0 ( t ) = V0 + υ 0 ( t )
υ I ( t ) = Aυυ i ( t )
dυ 0
Aυ =
dυ Ι
at Q
Figure 1.14 (a) An amplifier transfer characteristic that shows considerable nonlinearity. (b) To obtain linear operation the amplifier is biased as shown,
and the signal amplit
amplitude
de is kept small
small. Observe
Obser e that this amplifier is operated from a single power
po er supply,
s ppl VDD.
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EXAMPLE 1.2
-11 40υ Ι
υ 0 = 10 - 10 e
(1
(1.11)
11)
υ Ι = 0.690 V
L+ = 10 - 10-11 10 V
VI = 0.673 V
Aυ = -200 V
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Figure 1.15 A sketch of the transfer characteristic of the amplifier of Example 1.2. Note that this amplifier is inverting (i.e., with a gain that is negative).
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Figure 1.16 Symbol convention employed throughout the book.
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RL
υ 0 = Aυ oυ i
RL + Rυ
υ0
RL
Aυ ≡
= Aυ o
υi
RL + R0
Ri
υ i = υs
Ri + Rs
(1.13)
(1
(1.12)
12)
υ0
Ri
RL
= Aυ o
υs
Ri + Rs RL + R0
Figure 1.17 (a) Circuit model for the voltage amplifier. (b) The voltage amplifier with input signal source and load.
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Figure 1.18 Three-stage amplifier for Example 1.3.
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EXAMPLE 1.3
υι 1
1 MΩ
=
= 0.909 V/V
υ s 1 MΩ + 100 kΩ
Aυ 1 ≡
υi 2
100 kΩ
= 10
= 9.9 V/V
υi1
100 kΩ + 1 kΩ
Aυ 2 ≡
υi 3
10 kΩ
= 100
= 90.9 V/V
υi 2
10 kΩ + 1 kΩ
Aυ 3 ≡
υL
100 Ω
=1
= 0.909 V/V
100 Ω + 10 Ω
υi 3
Aυ ≡
υL
= Aυ 1Aυ 2 Aυ 3 = 818 V/V
υi1
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υ L υ L υ i1
υ
=
= Aυ i 1
υ s υ i1 υ s
υs
= 818 × 0.909
0 909 = 743.6
743 6 V/V
Ai ≡
i 0 υ L 100Ω
=
i i υ i 1 1 MΩ
= 104 × A υ = 8.18 × 106 A/A
Ap ≡
PL υ L i 0
=
PI υ i 1 i i
= A υ A i = 818 × 8.18 × 106 =66.9 × 108 W/W
A p (dB) =
1
⎡ A (dB) + A i (dB)⎤⎦
2⎣ υ
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Aυο
⎛ Ro ⎞
= A is ⎜
⎟
R
⎝ i⎠
Aυο = Gis Ro
Aυο
Rm
=
Ri
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(1.14)
(1.15)
(1.16)
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Figure 1.19 (a) Small-signal circuit model for a bipolar junction transistor (BJT). (b) The BJT connected as an amplifier with the emitter as a common
terminal bet
between
een input
inp t and ooutput
tp t (called a common-emitter
common emitter amplifier).
amplifier) (c) An alternative
alternati e small
small-signal
signal circuit
circ it model for the BJT
BJT.
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EXAMPLE 1.4
rπ
υ be = υ s
rπ + Rs
(1 17)
(1.17)
υ o = − gmυ be (RL ro )
(1
(1.18)
18)
υo
rπ
=−
gm (RL ro )
υs
rπ + Rs
(1
(1.19)
19)
υo
25
2.5
=−
× 40 × ( 5 100 )
υs
2.5 + 5
= − 63.5
63 5 V/V
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υo
2.5
−
× 40 × 5
υs
2.5 + 5
= − 66.7 V/V
β i = gmυ be
b
β = gm rπ
β = 40 mA/V × 2.5 kΩ
= 100 A/A
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Figure E1.20
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Vo
T (ω ) =
Vi
∠T (ω ) = φ
Figure 1.20 Measuring the frequency response of a linear amplifier. At the test frequency V, the amplifier gain is characterized by its magnitude (Vo/Vi)
and phase F.
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To (ω )
T (ω ) =
Ti (ω )
To ( s )
T ( s) =
Ti ( s )
Figure 1.21 Typical magnitude response of an amplifier. |T(V)| is the magnitude of the amplifier transfer function—that is, the ratio of the output
Vo(V) to the input Vi(V).
)
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Figure 1.22 Two examples of STC networks: (a) a low-pass network and (b) a high-pass network.
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Figure 1.23 (a) Magnitude and (b) phase response of STC networks of the low-pass type.
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Figure 1.24 (a) Magnitude and (b) phase response of STC networks of the high-pass type.
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Figure 1.25 Circuit for Example 1.5.
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EXAMPLE 1.5
Zi
Vi = Vs
Z i + Rs
Vi = Vs
1
1 + RsYi
1
= Vs
1 + Rs ⎡⎣(1 / Ri ) + sC i ⎤⎦
Vi
1
=
Vs 1 + ⎡⎣( Rs / Ri ) + sC i Rs ⎤⎦
Vi
1
1
=
Vs 1+( Rs / Ri ) 1 + sC i ⎡⎣( Rs Ri ) /( Rs + Ri )⎤⎦
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(1.20)
41
Vo = µ Vi
RL
RL + Ro
Vo
1
1
1
=µ
Vs
1+( Rs / Ri ) 1+( Ro / RL ) 1 + sC i ⎡⎣( Rs Ri ) /( Rs + Ri )⎤⎦
Rs Ri
τ = Ci
= C i ( Rs // Ri )
Rs + Ri
(1.22)
Vo
1
1
( s = 0) = µ
K≡
Vs
1 + ( Rs / Ri ) 1 + ( Ro / RL )
ω0 =
1
τ
=
1
C i ( Rs // Ri )
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(1.21)
(1.23)
((1.24))
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1
1
K = 144
= 100 V/V
1 + (20 / 100) 1 + (200 / 100)
ω0 =
1
60pF × (20kΩ//100kΩ )
1
6
=
=
10
rad/s
-12
3
60 × 10 × (20 × 100 /(20 + 100)) × 10
106
= 159.2kHz
f0 =
2π
Vo
100
( jω ) =
T ( jω ) ≡
Vi
1 + j (ω / 106 )
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υ 0 ( t ) = 10sin10
10 i 102 t , V
υ 0 ( t ) = 9.95sin(105 t − 5.7° ), V
υ 0 ( t ) = 7.07 sin(106 t − 45° ), V
T 1 and φ = − tan -1 100 = −89.4°
υ 0 ( t ) = 0.1sin(108 t − 89.4° ), V
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Figure 1.26 Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.
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Figure 1.27 Use of a capacitor to couple amplifier stages.
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Figure E1.23
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Figure 1.28 A logic inverter operating from a dc supply VDD.
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NH H = VOH − VIH
(1.25)
NM L = VIL − VOL
(1.26)
Figure 1.29 Voltage transfer characteristic of an inverter. The VTC is approximated by three straightline segments. Note the four parameters of the VTC
(VOH, VOL, VIL, and VIH) and their use
se in determining the noise margins (NMH and NML).
)
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NH H = NM L = VDD /2
(1.27)
Figure 1.30 The VTC of an ideal inverter.
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Figure 1.31 (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b) equivalent circuit when vI is low; and (c)
eq i alent circuit
equivalent
circ it when
hen vI is high
high. Note that the sswitch
itch is ass
assumed
med to close when
hen vI is high.
high
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Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied
in Section 4.10.
4 10
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Figure 1.33 Another inverter implementation utilizing a double-throw switch to steer the constant current IEE to RC1 (when vI is high) or RC2 (when vI is
lo ) This is the basis of the emitter
low).
emitter-coupled
co pled logic (ECL) st
studied
died in Chapters 7 and 11.
11
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Pdynamic = ffCV
2
DD
((1.28))
y( t ) = Y∞ − (Y∞ − Y0+ )e
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− t /τ
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(1.29)
54
Figure 1.34 Example 1.6: (a) The inverter circuit after the switch opens (i.e., for t ≥ 0+). (b) Waveforms of vI and vO. Observe that the switch is assumed
to operate instantaneously.
instantaneo sl vO rises exponentially,
e ponentiall starting at VOL and heading toward
to ard VOH .
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EXAMPLE 1.6
VOL = Voffset +
= 0.1+
VDD − Voffset
Ron
R+R on
5 − 0.1
× 0.1 = 0.55 V
1.1
.
υ 0 ( t ) = 5 − (5 − 0.55)e − t / τ
1
2
1
= (5 − 0.55)
0 55)
2
= 0.69τ = 0.69 RC
υ 0 ( t PLH ) = (VOH + VOL )
t PLH
= 0.69
0 69 × 103 × 10−11
= 6.9 ns
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Figure 1.35 Definitions of propagation delays and transition times of the logic inverter.
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Figure P1.6
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Figure P1.10
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Figure P1.14
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Figure P1.15
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Figure P1.16
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Figure P1.17
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Figure P1.18
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Figure P1.37
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Figure P1.58
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Figure P1.63
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Figure P1.65
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Figure P1.67
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Figure P1.68
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Figure P1.72
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Figure P1.77
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Figure P1.79
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Table 1.1 The Four Amplifier Types
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