Resonant Micro-Inverters for Single-Phase
Grid-connected Photovoltaic Systems
by
Sayed Ali Khajehoddin
A thesis submitted to the
Department of Electrical and Computer Engineering
in conformity with the requirements for
the degree of Doctor of Philosophy
Queen’s University
Kingston, Ontario, Canada
April 2010
c Sayed Ali Khajehoddin, 2010
Copyright Abstract
This thesis addresses the design and implementation of micro-inverters for gridconnected single-phase photovoltaic (PV) systems. Despite the existing research
issues concerning Micro-inverters, they have recently become very attractive due
to their modularity and capability of independent maximum power point tracking
(MPPT). The complexity in the design of micro-inverters stems from strict grid connection standards and high expectations of compactness, large amplification gain,
high efficiency over a wide range of operating conditions and excellent output power
quality. Moreover, since micro-inverters are exposed to a wide temperature range,
the reliability and life-time of this technology are major problems. The main limiting
factor in the life-time of micro-inverters is the use of large electrolytic capacitors for
power decoupling.
New circuit configuration and control structures to design a compact and efficient
micro-inverter with high quality and robust output power injection capabilities are
introduced in this thesis. In the proposed topology electrolytic capacitors are eliminated, removing the obstacles in achieving a durable and reliable design. To achieve
a compact design, the proposed micro-inverter consists of a soft-switching high frequency resonant converter at the input and a hard-switching lower frequency inverter
with a high order filter at the output.
i
Small and large signal models of the resonant converter are obtained to design
controllers. A new optimal controller and a design method are also proposed for the
inverter that yield robust performance with a high quality output in the presence
of grid voltage harmonics, impedance uncertainties and frequency changes. Furthermore, using a new nonlinear control strategy, a direct instantaneous power control
method is proposed to achieve fast active and reactive power injections into the grid
without using the measurement or calculation of active and reactive powers.
A comprehensive steady state analysis is carried out to arrive at a final design that
ensures optimum responses for all operating conditions. Moreover, for all proposed
controllers, stability analysis is performed to guarantee sufficient stability margins accounting for uncertainties and nonlinearities. Analytical, simulation and experimental
results are presented to verify the effectiveness of the proposed methods.
ii
Acknowledgments
I would like to express my deepest appreciation for the feedback, advice, and guidance
of my thesis supervisors Prof Praveen K. Jain and Dr. Alireza Bakhshai. I would also
like to thank them not only for their insight and intuition but also for their friendship
and encouragement that helped make several years of research enjoyable.
I would also like to acknowledge Prof. Hirofumi Akagi, Prof. Yan-Fei Liu and
other members of my committee for their constructive comments and feedbacks.
My greatest appreciation is extended to Dr. Shangzhi Pan and Dr. Masoud
Karimi-Ghartemani. I am indebted to Pan for the collaborative effort in the experimental phase of the project, and to Masoud for discussions on theoretical aspects.
I would like to offer my thanks to all graduate students in the ePEARL lab,
especially Darryl Tschirhart, Alireza Safaee and Majid Pahlevaninezhad for many
productive discussions over the past few years.
I acknowledge the financial support provided by NSERC, ORF and OGS during
the course of this project.
The last but certainly not the least, I would like to express my gratitude and
thanks to my wife and my parents whose encouragement and support were always
invaluable to me, and in fact the love and support offered by them kept me going
throughout the process of researching and writing this thesis.
iii
To my parents
and my lovely wife
Table of Contents
Abstract
i
Acknowledgments
iii
Table of Contents
iv
List of Figures
vii
List of Symbols
xiii
List of Acronyms
xv
Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . .
1.1 PV Converter Specifications . . . . . . . . . . . . . . . . . .
1.1.1 Maximum Power Point Tracking . . . . . . . . . . . .
1.1.2 Partial Shading and Nonidentical PV Cells . . . . . .
1.1.3 Power Decoupling . . . . . . . . . . . . . . . . . . . .
1.1.4 Other PV Converter Specifications and Standards . .
1.2 PV System Topologies . . . . . . . . . . . . . . . . . . . . .
1.2.1 Centralized Topology . . . . . . . . . . . . . . . . . .
1.2.2 String and Multi-String Topologies . . . . . . . . . .
1.2.3 Micro-inverters . . . . . . . . . . . . . . . . . . . . .
1.3 Review of Existing Micro-Inverter Topologies . . . . . . . . .
1.3.1 Non-isolated Topologies . . . . . . . . . . . . . . . .
1.3.2 Isolated Topologies . . . . . . . . . . . . . . . . . . .
1.4 Existing Power Decoupling Methods . . . . . . . . . . . . .
1.4.1 Power Decoupling Using Energy Storage Components
1.4.2 Power Decoupling Using Auxiliary Circuits . . . . . .
1.5 Description of the Proposed Structure . . . . . . . . . . . . .
1.6 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . .
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1
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Chapter 2: Micro-Inverter Topology . . . . . . . . . . . . . . . . .
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Series Resonant Converter Circuit Topology . . . . . . . . . . . .
2.3 Series Resonant Converter Principle Of Operation . . . . . . . . .
2.4 Series Resonant Converter Steady-State Analysis and Design . . .
2.4.1 Calculation of the Instantaneous Value of the Bus Voltage
2.4.2 Calculation of the Equivalent Resistance Rac . . . . . . . .
2.4.3 Converter Gain Calculation . . . . . . . . . . . . . . . . .
2.4.4 Design of Transformer Turn Ratio . . . . . . . . . . . . . .
2.4.5 Calculations of Turn-Off Currents . . . . . . . . . . . . . .
2.4.6 The RMS Resonant Tank Current . . . . . . . . . . . . . .
2.4.7 Voltage Stress on the Resonant Tank Capacitor . . . . . .
2.4.8 Design Approach for Ls ωr . . . . . . . . . . . . . . . . . .
2.4.9 Design Approach for ω . . . . . . . . . . . . . . . . . . . .
2.4.10 Variable Frequency Control Method . . . . . . . . . . . . .
2.4.11 Variable Bus Voltage Control . . . . . . . . . . . . . . . .
2.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 3: Power Decoupling and PV Side Control . . . . . .
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Power Decoupling Issue . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Implementation of the Power Decoupling Method . . .
3.3 Series Resonant Converter Control Method . . . . . . . . . . .
3.4 Large Signal Model of the APWM Series Resonant Converter .
3.5 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Elimination of the Internal Decoupled Dynamics . . . .
3.6 Controller Design and Stability Analysis . . . . . . . . . . . .
3.7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . .
3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 4: Synchronization and Bus Voltage Control .
4.1 General Block Diagram . . . . . . . . . . . . . . . . . .
4.2 Synchronization With the Grid Voltage . . . . . . . . .
4.3 Control Loop Based on Instantaneous Power Control .
4.3.1 Instantaneous Power Control . . . . . . . . . . .
4.3.2 Stability Analysis of the Proposed System . . .
4.4 Design Guidelines . . . . . . . . . . . . . . . . . . . . .
4.4.1 Simulation Results . . . . . . . . . . . . . . . .
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4.5
4.6
4.7
Bus Voltage Control . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 System Equations and Control Objectives . . . . . . . .
4.5.2 System Modeling and the Proposed Design Method . . .
4.5.3 Design of the Modified Voltage Control Loop . . . . . . .
4.5.4 Stability Analysis of the Modified Voltage Control Loop
Modified Pulse Width Modulation for Output Inverter . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5: Output Inverter Control . . . . . . . . . . . . . . .
5.1 First-order Inductive Filter . . . . . . . . . . . . . . . . . . . .
5.2 Third-order Inductive-Capacitive-Inductive Filter . . . . . . .
5.3 Output Current Control Loop Design . . . . . . . . . . . . . .
5.3.1 Controller Objectives and Requirements . . . . . . . .
5.3.2 Control Approach . . . . . . . . . . . . . . . . . . . . .
5.4 Concept of Linear Quadratic Regulator (LQR) . . . . . . . . .
5.5 Extension of the Regulating Problem to the Tracking Problem
5.6 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . .
5.7 Proposed Solution . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 Selecting Matrix Q . . . . . . . . . . . . . . . . . . . .
5.8 Damping the LCL-filter Resonance Frequency . . . . . . . . .
5.9 Robustness Against Grid Impedance . . . . . . . . . . . . . .
5.10 Output Current Harmonic Cancelation . . . . . . . . . . . . .
5.11 Controlling the Start-up Transient . . . . . . . . . . . . . . . .
5.12 Digitization of the Controllers Using Delta Operator . . . . . .
5.13 Experimental Results . . . . . . . . . . . . . . . . . . . . . . .
5.14 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 6: Summary and Future Work . . . . . . . . . . . . . . . . . 191
6.1 Summary of Contributions . . . . . . . . . . . . . . . . . . . . . . . . 191
6.2 Suggested Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Appendix A: PV Cell Characteristic . . . . . . . . . . . . . . . . . . . 207
A.0.1 PV Cell Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 209
Appendix B: Micro-inverter PSIM Simulation Schematics . . . . . . 211
Appendix C: VHDL Code . . . . . . . . . . . . . . . . . . . . . . . . . 218
vi
List of Figures
1.1
1.2
1.3
(a) Centralized, (b) String and (c) multi-string topologies. . . . . . .
Micro-inverter topology . . . . . . . . . . . . . . . . . . . . . . . . . .
(a) Voltage source inverter switching at high frequency to form the grid
current, (b) Current source inverter unfolding the rectified sinusoidal
current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Isolated topologies using a (a) low frequency transformer and (b) high
frequency transformer . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 General block diagram for the conventional approach for power decoupling in multi-stage micro-inverters with a voltage source inverter at
the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 General block diagram for the conventional approach for power decoupling in multi-stage micro-inverters with an unfolding stage at the
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Flyback inverter with active power decoupling . . . . . . . . . . . . .
1.8 Modified flyback converter with decoupling capability . . . . . . . . .
1.9 Modified high efficiency flyback converter with active decoupling . . .
1.10 Current source inverter and associated decoupling circuit . . . . . . .
1.11 Forward converter with active decoupling . . . . . . . . . . . . . . . .
1.12 General block diagram for the proposed approach . . . . . . . . . . .
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Asymmetric PWM series resonant converter power circuit topology .
Typical steady-state operating waveforms. . . . . . . . . . . . . . . .
Equivalent circuits for operating intervals labeled in Fig. 2.2 for the
converter shown in Fig. 2.1 . . . . . . . . . . . . . . . . . . . . . . .
Three equivalent circuits for the resonant tank: (a) no simplification,
(b) fundamental approximation for vp , and (c) fundamental approximation for vin and vp . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus voltage at minimum and maximum points for (a) Cbus = 20µF (b)
Cbus = 40µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rac as a function of time for (a) Cbus = 20µF (b) Cbus = 40µF . . . .
Rac at minimum and maximum points for (a) Cbus = 20µF (b) Cbus =
40µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
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2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
3.1
3.2
Normalized quality factor at minimum and maximum points for all
possible operating condition . . . . . . . . . . . . . . . . . . . . . . .
Evaluation of inequality (2.18) for (a) N=21 (b) N=23 . . . . . . . .
The duty cycles of S1 at extremum points of the bus voltage (a) at the
maximum points (b) at the minimum points . . . . . . . . . . . . . .
Turn-off currents for S2 at (a) minimum points of the bus voltage, (b)
maximum points of the bus voltage . . . . . . . . . . . . . . . . . . .
(a) Turn-off currents for S1 , (b) the RMS of the currents of the resonant
tank at the extremum points of the bus voltage . . . . . . . . . . . .
The RMS value of the voltage of the series capacitor at the extremum
points of the bus voltage for different Ls ωr . . . . . . . . . . . . . . .
Turn-off currents for S2 for different Ls ωr at (a) minimum points of
the bus voltage, (b) maximum points of the bus voltage . . . . . . . .
(a) Turn-off currents of S2 and (b)Duty cycle, for different ω at maximum and minimum points of the bus voltage at minimum VP V . . .
Turn-off currents of S2 at maximum and minimum points of the bus
voltage for different ω at maximum VP V . . . . . . . . . . . . . . . .
(a) Turn-off currents of S2 and (b) Duty cycle at maximum and minimum points of the bus voltage with variable ω control . . . . . . . . .
The RMS value of ires at maximum and minimum points of the bus
voltage with the variable bus voltage and variable frequency control
method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSIM simulation results for bus voltage and input power at VP V =45V.
PSIM simulation results for switching actions to achieve ZVS at turnon and turn-off of S1 and S2 for (a) VP V =25V and (b) VP V =45V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulation results for tank waveforms at Pin =200W and VP V =45V .
Micro-inverter board . . . . . . . . . . . . . . . . . . . . . . . . . . .
Experimental results for switching actions to verify ZVS of S1 and S2
for VP V =30V and (a) IP V =2A and (b) IP V =6A . . . . . . . . . .
Experimental results for switching actions to verify ZVS of S1 and S2
for VP V =45V and (a) IP V =1.2A and (b) IP V =5A . . . . . . . . .
Experimental results for resonant tank current, resonant tank capacitor
voltage and transformer primary voltage at VP V =45V and (a) Pin
=200W , (b) Pin =50W . . . . . . . . . . . . . . . . . . . . . . . . .
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(a) A general block diagram for single-phase grid connected PV converter, (b) Output current, voltage and instantaneous power waveforms 74
Conventional Approach Inverter Block Diagram . . . . . . . . . . . . 75
viii
3.3
(a) First implementation of the decoupling control circuit, (b) PSIM
simulation of the converter waveforms during one grid cycle . . . . . .
3.4 Series resonant converter controller block diagrams . . . . . . . . . .
3.5 Large signal model of the first stage of the micro-inverter . . . . . . .
3.6 Stability regions of controllers’ gains for (a) constant PV voltage and
variable input power (b) constant input power and variable PV voltage
3.7 Closed loop poles for different gains of controller 0.1 ≤ kp ≤ 1 (a)
ki = 1000 (b) ki = 20000, and (c) duty cycle to output open loop poles
and (d) closed loop poles, for different Pin values shown by the same
color and different VP V . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 (a) Open loop Bode diagram of the converter in blue and the compensator in green (b) Closed loop Bode of the first stage . . . . . . . . .
3.9 Experimental results for resonant tank current, tank capacitor voltage,
PV voltage and bus voltage at VP V =45V and IP V =5A . . . . . . . .
3.10 Experimental results for (a) PV voltage and bus voltage and (b) PV
voltage and current high frequency ripples, at VP V =45V and IP V =5A
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Inverter side control and synchronization block diagram . . . . . . . .
(a) Standard Phase Locked Loop (PLL) (b) Enhance Phased Locked
Loop (EPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard PLL (in green) and EPLL (in blue) (a) outputs versus input
signals and (b) output phase errors in the presence of input with noise
and the absence of input . . . . . . . . . . . . . . . . . . . . . . . . .
Experimental waveform showing the transients of EPLL at the startup
Block diagram of the proposed controller within the entire loop connecting the PV to the grid through the converter . . . . . . . . . . .
Root-locus of (4.10) when: (a) µ4 = 4000 and µ5 varies from 0.01 to
0.07 (b) µ5 = 0.04 and µ4 varies from 1000 to 7000 (c) µ4 varies from
1000 to 4000 and µ5 = 0.00001µ4 (d) µ4 varies from 1000 to 4000 and
µ5 = 0.08 − 0.00001µ4 . . . . . . . . . . . . . . . . . . . . . . . . . .
Root-locus of (4.11) when: (a) µ1 varies from 0 to 1000 and µ2 = 500
(b) µ2 varies from 0 to 1000 and µ1 = 500 (c) µ1 varies from 0 to 1000
and µ2 = µ1 (d) µ1 varies from 0 to 1000 and µ2 = 1000 − µ1 . . . . .
Performance of the proposed system in tracking active and reactive
power commands: (a) active and reactive commands in pu (b) grid
voltage and current in pu (c) instantaneous power error in pu . . . .
Performance of the proposed system against the grid voltage variations:
(a) grid voltage and current in pu (b) instantaneous power error in pu
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4.10 Performance of the system against grid frequency variations: (a) grid
voltage and current in pu (b) instantaneous power error in pu (c) estimated frequency in Hz . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Performance of the proposed system against grid voltage harmonics
and noise: (a) grid voltage in pu (b) grid current in pu . . . . . . . .
4.12 Block diagram of a single-phase grid-connected inverter system using
LCL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Bus voltage control loop . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 (a) Block diagram of the modified voltage control loop (b) Simplified
time variant model of the voltage control loop, (c) Transfer function
diagram of the notch filter . . . . . . . . . . . . . . . . . . . . . . . .
4.15 (a) Range of kp and ki that maintain stability, (b) Root locus of closedloop poles of the bus voltage control loop when −4 < kp < 0 and
ki = 100kp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Step responses of the equivalent LTI system to the input pin changing
from 0W to 200W for damping ratios from 0.5 to 2 . . . . . . . . . .
4.17 Eigenvalues of Q as a function of time over a period of grid frequency
4.18 Magnitude of the current when the input power jumps from 100W to
200W at t=0.1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Modified PWM to remove harmonics from the output current caused
by oscillations at the bus voltage . . . . . . . . . . . . . . . . . . . .
4.20 Modified PWM to remove harmonics from the output current caused
by oscillations at the bus voltage for two cases (i) the bus voltage is dc
(denoted by xVdc in green) and when the bus voltage has oscillations
using the modified PWM (denoted by xmod in blue) . . . . . . . . . .
4.21 Harmonics spectrum of the output of inverter with oscillatory bus voltage, modulated using modified PWM at 1200Hz showing (a) whole
spectrum (b) higher frequency components (c) zoomed at low frequency
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Harmonics spectrum of the output of inverter with constant bus voltage, modulated using conventional PWM at 1200Hz showing (a) whole
spectrum (b) higher frequency components (c) zoomed at low frequency
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Experimental result showing the bus voltage, output current and grid
voltage at full power . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Experimental result showing the output of the inverter voltage and
current at full power . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
5.2
118
118
119
122
124
127
128
130
131
133
134
136
136
137
137
First-order L filter interfacing an inverter to the utility grid . . . . . . 140
Third-order LCL filter interfacing an inverter to the utility grid . . . 141
x
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
Filtering diagram of an L filter and an LCL filter (L=10mH, L1 =L2 =220µH,
C=2.2µF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
(a) L12 versus C and (b) k versus C for various values of L changing
from 10mH to 50mH . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
The proposed closed-loop structure . . . . . . . . . . . . . . . . . . . 148
The proposed control Loop . . . . . . . . . . . . . . . . . . . . . . . . 154
Block diagrams showing the process of states transformation . . . . . 158
Monitoring the closed-loop characteristics when qi s are increased one
by one: (a) Bandwidth of the closed loop system (b) overshoot in
percentage (c) settling time in ms (d) damping of LCL-filter resonance
mode (e) time-constant of the system’s fastest mode (f) system’s zero 162
(a)The loci of poles of the closed-loop system when qi s are increased
one by one (b) zoomed to show the loci close to the origin . . . . . . 163
Plot of the state feedback gains while increasing qi s one after another 164
Simulation of a step response to the input power . . . . . . . . . . . . 165
Deviation of the closed loop poles when vc is fed back and is not fed
back. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Closed loop Bode diagram of the inverter (a) from the output current
to the reference input (b) from the output current to the disturbance
input, when the LCL resonance is not well damped . . . . . . . . . . 167
Closed loop Bode diagram of the inverter (a) from the output current
to the reference input (b) from the output current to the disturbance
input, when the LCL resonance is well damped . . . . . . . . . . . . 168
Simulation of the output grid current for minimum input power when
(a) the LCL resonance is not well damped (b) the LCL resonance is
damped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
The result of the method proposed in Section 5.7.1 for the loci of the
closed loop poles when the grid side inductor L2 is increased from its
nominal value to 20mH . . . . . . . . . . . . . . . . . . . . . . . . . . 171
The impact of uncertainties on the grid-side inductor L2 (a change from
0.5 mH to 1 mH) on the closed loop root locus when the standard poleassignment is used for designing the controller . . . . . . . . . . . . . 171
The controller structure to remove the effect of the grid voltage harmonics from the output grid current. . . . . . . . . . . . . . . . . . . 174
Open loop bode diagram of the system shown in Fig. 5.18. . . . . . . 175
Simulation of a step response to the input power when the grid voltage
has harmonics and no harmonic cancelation is used . . . . . . . . . . 176
Simulation of a step response to the input power when the grid voltage
has harmonics and the harmonic cancelation structure is used . . . . 176
The proposed control Loop to control start-up transients . . . . . . . 178
xi
5.23 Simulation of the start-up transients at full power, (a) without the kF F
branch (b) with thekF F branch . . . . . . . . . . . . . . . . . . . . . 180
5.24 Simulation of the start-up transients at minimum input power, (a)
without the kF F branch (b) with the kF F branch . . . . . . . . . . . . 180
5.25 Direct form II (DFII) implementation of the digital controller CP R (z) 183
5.26 Implementation of γ −1 in terms of z −1 . . . . . . . . . . . . . . . . . 183
5.27 Direct form II (DFII) delta domain implementation of the digital controller CP R (γ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.28 Simulation of the micro-inverter with digitized controller. . . . . . . . 187
5.29 Experimental results of the micro-inverter output for full power injection.188
5.30 Experimental results for a step change in the input power from full
power to half power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
5.31 The effect of the controller introduced in Section 5.11 on the transient
of the output current in the startup . . . . . . . . . . . . . . . . . . . 189
A.1 Typical Voltage-current characteristics of PV cells for (a) different irradiation levels, (c) different temperatures and typical Voltage-Power
characteristics of PV cells for (b) different irradiation levels, (d) different temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
A.2 Equivalent circuit for a PV cell. . . . . . . . . . . . . . . . . . . . . . 209
B.1
B.2
B.3
B.4
B.5
B.6
First stage of the power circuit and the associated control systems .
second stage of the power circuit and the associated control systems
Digital implementation of the enhanced phase lock loop . . . . . . .
First stage of the power circuit and the associated circuits . . . . .
Inverter and the associated circuits . . . . . . . . . . . . . . . . . .
Output filter and the associated circuits . . . . . . . . . . . . . . .
xii
.
.
.
.
.
.
212
213
214
215
216
217
List of Symbols
Vg
IP V
VP V
VOC
ISC
ns
Irs
ires
vCs
vin
vp
io
igrid
ωg
∆vP V
N
vbus
o
PSRC
o
Pinv
Pin
∆Vbus
DC
Vbus
min
Vbus
max
Vbus
min
IS2
max
IS2
min
IS1
max
IS1
ωs
Ts
ωr
Grid Voltage
Photovoltaic output curent
Photovoltaic output voltage
Open circuit voltage of a PV module
Short circuit current of a PV module
Number of cells in series
Cell reverse saturation current
Resonant tank current
Resonant tank capacitor voltage
Resonant tank input voltage
Transformer pirmary voltage
Output current of the rectifier of the resonant converter
Injected current into the grid
Angular frequency of the grid voltage
Photovoltaic output voltage ripple
Transformer turns ratio
Middle stage capacitor bus voltage
Series resonant converter output power
Average inverter output power
Photovoltaic module output power
Peak to peak bus voltage oscillation
Average bus voltage
Bus voltage at the minimum points
Bus voltage at the maximum points
min
Turn off current of S2 when the bus voltage is Vbus
max
Turn off current of S2 when the bus voltage is Vbus
min
Turn off current of S1 when the bus voltage is Vbus
max
Turn off current of S1 when the bus voltage is Vbus
Angular switching frequency of the resonant converter
Switching period of the resonant converter
Angular resonant frequency of the resonant converter
xiii
ψn
θn
φn
Rac
D̂
i∗ref
iref
v̂grid
V̂grid
ω̂g
ϕ̂v
Iˆgrid
ϕ̂i
pref
out
ref
Pout
Qref
out
iinv
vinv
pin
pout
pinv
pgrid
pLCL
ωsi
Phase shift of the n’th harmonic of vp
Phase shift of the n’th harmonic of ires
Phase shift of the n’th harmonic of vin
Equivalent resistance seen from the primary of the transformer
Duty cycle of switch S1 as a function of time
Normalized output current reference
Output current reference
Estimation of the grid voltage
Estimation of the amplitude of the grid voltage
Estimation of the grid angular frequency
Estimation of the grid voltage total phase angle
Estimation of the amplitude of the grid current
Estimation of the grid current total phase angle
Instantaneous output power reference value
Average output active power reference value
Average output reactive power reference value
Inverter output current
Inverter output voltage
Instantaneous input power to the bus capacitor
Instantaneous input power to the inverter
Instantaneous output power of the inverter
Instantaneous injected power to the grid
Instantaneous power of the LCL filter
Angular switching frequency of the output inverter
xiv
Acronyms
Distributed Generation
DG
PWM
Pulse Width Modulated
THD
Total Harmonic Distortion
APWM
PV
Asymmetrical Pulse Width Modulated
photovoltaic
MPPT
Maximum Power Point Tracking
FPGA
Field Programmable Array
Power SIMulator
PSIM
ZVS
Zero Voltage Switching
PLL
Phase Locked Loop
Enhanced Phase Locked Loop
EPLL
Low Pass Filter
LPF
VCO
Voltage-Controlled Oscillator
LTI
Linear Time Invariant
LTV
Linear Time Varying
LQR
Linear Quadratic Regulator
ARE
Algebraic Riccati Equation
FPGA
Field Programmable Gate Array
xv
Chapter 1
Introduction
The ever-increasing demand for energy along with escalating pollution levels have
made renewable energy resources a key research area. Among the renewable energy
options, solar power—and particularly photovoltaic (PV) technology—has attracted
a lot of attention due to advantages such as exceptional availability, low maintenance
cost, noiseless operation and ease of scalability. The exponential growth in the number
of PV system installations over the past decade is a testament to these benefits [1].
Existing PV converter systems can be classified into three main groups: (i) largescale power generation using grid-connected systems with output powers ranging from
tens of kilowatts to megawatts, (ii) remote area applications using stand-alone systems
with a smaller PV plant to supply local loads and (iii) residential and commercial
applications using grid-connected systems with output power capabilities less than a
few kilowatts. At the present time, a small percentage (10.2%) of PV installations are
stand-alone systems, while the majority (89.8%) are grid-connected systems [2].
This thesis focuses on single-phase residential and commercial applications. In
1
CHAPTER 1. INTRODUCTION
2
these applications there are two inevitable characteristics of the system that substantially impact the system efficiency, performance, design life and maintenance cost:
partial shading and double grid frequency output power oscillations. Each application exhibits unique requirement that demands careful selection of the PV system
configuration to optimize performance, efficiency and cost.
A grid-connected PV system consists of two parts: PV modules for converting
solar energy into dc power, and a PV inverter for extracting the maximum available
dc power and injecting the equivalent ac power into the grid. In this chapter a brief
description of PV converter specifications and different possible PV system topologies
are provided to justify micro-inverter based topologies as the most suitable and efficient configuration for residential applications. Existing micro-inverter topologies
along with their associated problems are reviewed and subsequently a topology and
system structure to enhance system specifications are introduced.
1.1
PV Converter Specifications
For grid-connected PV applications, regardless of the topology of the inverter, a number of general properties have always been desired and certain industry specifications
must be met. In this section, the most important requirements are briefly discussed.
1.1.1
Maximum Power Point Tracking
The changing irradiation level and operating temperature of a PV module results
in a varying nonlinear power source for the PV system (see appendix A for a more
detailed explanation of PV module characteristics and models). The output voltage
CHAPTER 1. INTRODUCTION
3
and current of the PV module determine its operating point and thus stipulate its
output power. As a result, to keep overall output power per unit cost low, gridconnected converters should be able to adjust the input resistance so as to extract
maximum available power from the PV under all operating conditions. This task
is achieved by employing a Maximum Power Point Tracking (MPPT) algorithm [3]
within the PV system.
1.1.2
Partial Shading and Nonidentical PV Cells
The output voltage level of a single PV cell is low and thus not enough for an efficient
power conversion using existing topologies. Therefore, PV cells are usually connected
in series to form PV arrays/strings with a higher output voltage.
An array consisting of several series-connected modules has a number of problems such as mismatch losses and partial shading. These problems are particularly
prominent in residential applications, where the PV arrays are usually close to many
buildings and/or trees causing shadows. Moreover, in this application, the PV arrays are installed on a roof and/or a facade with different orientations and layouts,
thus creating mismatch losses. When partial shading occurs the resulting I-V characteristic has two local maxima that will adversely affect the MPPT algorithm. More
importantly, the output power from the array will be less than the sum of the power
outputs corresponding to the constituent modules and thus, the peak power is not
optimal. The extent of these problems depends on the selected PV system topology
and is minimized in the extreme case when an inverter with MPPT is designated for
each cell.
CHAPTER 1. INTRODUCTION
1.1.3
4
Power Decoupling
The instantaneous output power oscillates at twice the grid frequency in single-phase
grid-connected systems. In PV systems, the input power generation is dc and thus
the oscillation of the instantaneous power at the output, if reflected in the input,
deviates the input operating point from dc values. If there is any power oscillation on
the PV side, the maximum power is only achievable at the peak of oscillation, which
translates into less average power extraction than the available maximum power [4,5].
This is a power loss that reduces the efficiency of the PV system. Therefore, power
pulsation is a key problem in these systems and the PV converter should decouple the
output power pulsation from the input dc power generation to maximize the efficiency.
Power decoupling is conventionally performed by using large electrolytic capacitors
in the design to minimize the output power pulsations’ effects on the input operating
point.
1.1.4
Other PV Converter Specifications and Standards
The grid poses uncertainties to the PV system such as voltage variations, frequency
fluctuations and grid impedance. The efficiency and performance of inverters vary
as the input and output voltage/current levels change. Therefore, grid-connected PV
inverters should be able to efficiently inject high quality current into the grid for all
conditions and despite all uncertainties in the system.
Codes and standards [6–9] impose guidelines and limits for output power quality
in terms of output current Total Harmonic Distortion (THD) and allowed amount
of dc level, proper grounding systems, safety and protection. In North America,
the standards require grounding for both system (a current-carrying conductor) and
CHAPTER 1. INTRODUCTION
5
equipment (the frame and chassis) and they stipulate the use of isolation for systems
operating at voltages higher than 50V [4, 6]. The result is that only transformer
isolated converter topologies can be used in the design of PV electricity generation
systems in North America.
1.2
PV System Topologies
Over the last two or three decades, a number of different PV system topologies have
been proposed for grid-connected PV applications [4, 10–23]. In most cases there is
a trade off between total efficiency in partial shading (independent MPPT) and cost
(complexity of the circuit). Four of the most important and commonly used topologies
are discussed here.
1.2.1
Centralized Topology
In a centralized topology [4, 10–12] (also called plant-oriented topology), in order to
build a sufficiently high dc voltage, PV cells are connected in series to form strings and
then similar strings are connected in parallel to increase the power level, as shown in
Fig. 1.1(a). Although the centralized topology is very simple and useful for several
tens of kilowatts or more, it suffers from severe limitations. First, the system design
demands expensive dc switches, reinforced isolations, and careful consideration of
safety and protection circuits because there are significant amounts of high voltage
dc wiring between the PV modules and the inverter [10]. Second, partial shading or
any mismatch between the PV modules can cause a significant drop in the output
power generation, since the parallel connection of the strings with diodes forces their
CHAPTER 1. INTRODUCTION
6
voltages to be equal, and in case of partial shading an entire string may no longer
deliver power to the inverter. In other words, a centralized MPPT seems to be the most
serious drawback of this topology. Third, during central inverter outage there is no
power generation. These limitations make it a suitable topology for only large-scale
and industrial applications where partial shading does not exist.
1.2.2
String and Multi-String Topologies
To overcome the aforementioned problems, string and multi-string (also called module oriented) topologies have been proposed [4, 10–12, 17]. These two topologies are
specifically advantageous in medium power applications [10] where partial shadings
are expected and PV strings are installed in different orientations, layout and rated
powers.
In a string topology, as shown in Fig. 1.1(b), the PV panels are installed in series
to generate a high enough voltage that amplification is not necessary, and each string
is attached to a grid-connected inverter. Unlike the centralized topology, there are
no losses associated with string diodes and since separate MPPTs are performed on
each string a partial shading on one of the panels does not eliminate the whole string
from power generation.
In multi-string topology, as shown in Fig. 1.1(c), each string is connected to a
dc-dc converter and all converters are connected to a central dc-ac inverter through
a common dc-link. Therefore, each string can be still controlled individually but
the approach is cheaper than a string topology because the inverter is not repeated
for every string. System extension is simply performed by adding strings and the
associated dc/dc converters as long as the central inverter is over-designed to handle
7
CHAPTER 1. INTRODUCTION
D1
Dn
PV
PV
PV
PV
PV
PV
PV
PV
PV
PV
PV
PV
PV
DC
DC
DC
DC
PV
AC
AC
DC
DC
DC
DC
AC
Vgrid
(a)
AC
Vgrid
Vgrid
(b)
(c)
Figure 1.1: (a) Centralized, (b) String and (c) multi-string topologies.
the higher peak power.
Despite these advantages, a lot of dc wiring is still present in both string and
multi-string topologies. Moreover, MPPT is not performed on each module and the
least efficient panel constrains the maximum available power of the string.
1.2.3
Micro-inverters
The effect of partial shading or mismatches among PV modules can be minimized by
using a separate inverter for each PV panel, as shown in Fig. 1.2. This approach is
called a micro-inverter or module-integrated topology [4, 13–16, 18, 24]. Compared to
other topologies, micro-inverters have the advantage of easy scalability in other words
they are “plug and play”. The low system installation cost and high performance of
8
CHAPTER 1. INTRODUCTION
PV
Module
Inverter
PV
Module
Inverter
PV
Module
Inverter
Vgrid
Figure 1.2: Micro-inverter topology
this topology make it a perfect candidate for future PV systems. These advantages,
however, come at the expense of some complications:
• Micro-inverter designs should be compact enough to be attached to the back of
one PV panel and thus one of the major challenges in the design is the number
and size of components. Particularly in micro-inverters, the bulky decoupling
electrolytic capacitor and the large inductor at the inverter output are serious
design bottlenecks.
• PV modules along with their micro-inverters are usually located on the roof of
buildings and are not easily accessible. Also, the number of inverters per kW
output power is higher than in other topologies. Therefore, in case of a failure
or technical problems, repair and maintenance costs are higher than for other
topologies.
• These inverters are exposed to a wide range of temperature and humidity, which
adversely affects the life-time and performance of the converter. It has been
CHAPTER 1. INTRODUCTION
9
reported that for micro-inverters the mean time to first failure (MTFF) is only
five years [24]. Electrolytic capacitors are the most vulnerable components in
micro-inverters and they considerably degrade the reliability of the system.
These complications demand more complex design and more expensive components and this has led to a high manufacturing cost. Nevertheless, with the massproduction of such systems the total cost is expected to decrease, making microinverters a competitive topology.
1.3
Review of Existing Micro-Inverter Topologies
A grid-connected micro-inverter performs three tasks: (i) dc power extraction, (ii)
MPPT, (iii) voltage amplification and (iv) ac power injection. Depending on the
number of stages in the converter topology, these tasks are assigned to different stages
in the converter.
In a single-stage topology, all tasks are handled by one converter. However, since
the output power oscillates at twice the grid frequency, the peak power is twice
the average injected power to the grid and so the single stage must be designed for
toleration of twice the average power. As a result, single stage topology has limited
power capacity, compromised output quality and limited operation range.
In multi-stage topologies, the first stage usually handles the first three tasks, while
the second stage performs the ac power injection. There are two different approaches
for multi-stage topologies as shown in Fig. 1.3. In one approach (shown in Fig.
1.3(a)) the first stage is a dc-dc converter generating a pure dc output and the second
stage is an inverter switching at high frequency to control the current fed into the
10
CHAPTER 1. INTRODUCTION
grid. In the other approach (shown in Fig. 1.3(b)) the first stage is a dc-dc converter
that generates a rectified sinusoidal waveform at its output and the second stage is
an inverter switching at the line frequency to unfold the current and inject ac power
to the grid. The inductor shown in Fig. 1.3(b) can also represent a high frequency
transformer with an energy storage configuration similar to flyback converters. It is
worth mentioning that in the former approach the dc-dc converter provides constant
power and is only designed for average output power, while in the latter approach
both stages must be capable of handling double output peak power.
Generally a micro-inverter can be implemented with or without a transformer.
Isolated inverter topologies may use a transformer embedded in a high-frequency dcdc converter or dc-ac inverter, or a line-frequency (low-frequency) transformer toward
the grid (see Fig. 1.4). The line-frequency transformer is not desirable because of its
high size, weight and price.
DC
DC
PV
DC
Vgrid
PV
DC
AC
(a)
|igrid|
Unfolding
Stage
Vgrid
DC
(b)
Figure 1.3: (a) Voltage source inverter switching at high frequency to form the grid
current, (b) Current source inverter unfolding the rectified sinusoidal current
11
CHAPTER 1. INTRODUCTION
Lowfreq.
freq.
Low
DC
HighHigh
freq.freq.
DC
Vgrid
DC
Vgrid
PV
PV
AC
(a)
DC
AC
(b)
Figure 1.4: Isolated topologies using a (a) low frequency transformer and (b) high
frequency transformer
1.3.1
Non-isolated Topologies
Since in Europe and Japan the use of isolated topologies is not obligatory, there are
many non-isolated converters proposed in the literature. Since a sinusoidal waveform
can be generated from the difference of the output of two dc-dc positive converters,
a number of topologies are proposed based on two converters with differential outputs, inspired by the full bridge converter that is basically two bidirectional buck
converters. A few examples are boost inverter [25], buck-boost inverter [26], Cuk,
Zeta and D2 based converters [27]. Other types of inverter topologies consist of two
dc-dc converters with parallel outputs. Each dc-dc converter only operates during the
positive or negative half cycles of the grid voltage [27–29]. The focus of this thesis is
on isolated topologies and transformer-less designs are not further discussed.
CHAPTER 1. INTRODUCTION
1.3.2
12
Isolated Topologies
The isolated topologies can be divided into four major groups.
No Energy Storage in the Transformer
In this category converters usually consist of two or more stages and the first stage
is basically isolated dc to dc converters such as full-bridge, half-bridge, push pull
or forward converters. A dual-stage topology based on push pull is proposed in
reference [4]. A dual version of a voltage-fed half bridge converter is introduced in
reference [30] which is a double inductor push pull converter. The configuration is
basically two interleaved boost converters to achieve lower ripple at the input. Based
on this topology, a three-stage inverter is also developed in reference [13], however,
the converter has a high number of switching components with three stages and thus
cost and size are adversely affected.
Transformer as an Energy Buffer
There are a number of PV converters which are based on boost derived isolated topologies such as flyback-based converters. In this approach the magnetization inductance
of the transformer is charged from the input stage and is discharged to form the
output grid current. These converters are mostly designed for discontinuous modes
of operation to reduce the magnetizing inductance. An example is the converter
proposed in reference [31] where two sets of buck-boost choppers are combined in
a bridge form and the peak current is controlled to generate the output sinusoidal
waveform. A two-stage PV converter based on flyback topology followed by a voltage
source inverter is introduced in reference [32] and the same flyback converter followed
CHAPTER 1. INTRODUCTION
13
by an unfolding current source inverter is proposed in references [33, 34]. The former
operates in continuous mode as opposed to the latter which operates in discontinuous mode. In continuous mode conduction losses are lower because the RMS value
of the current is reduced. However, the discontinuous topology has smaller passive
components and lower switching losses for the unfolding inverter.
Reference [35] proposes another version of a flyback-based converter with a centertapped transformer. Two outputs from the transformer are connected to the grid,
one at a time, through two MOSFETs, two diodes, and a common filter circuit, enabling the flyback converter to produce both a positive and a negative output current.
Another flyback-based inverter is proposed in reference [36] where two bidirectional
flyback converters have parallel input and cascaded output.
Topologies Based on Matrix Converters
Some topologies have used matrix converters or cycloconverters at the output [37–39].
In these topologies the first stage generates and changes the sign of sine PWM current
pulses at high frequency to allow the use of a transformer and the second stage unfolds the high frequency pulses to generate unipolar sine PWM output current. These
approaches open the possibility of a more compact design and lower part count. However, they require bi-directional switches capable of blocking voltage and conducting
current in both directions that are not commercially available. These topologies do
not have any passive elements except at the PV side, causing two issues: (i) sophisticated and high bandwidth controllers are required to avoid any spike during the
transients of switches, (ii) the power decoupling is done at a low voltage level using
a large electrolytic capacitor.
CHAPTER 1. INTRODUCTION
14
Topologies Based on Resonant Converters
Resonant converters have been widely used in high frequency dc-dc converters [40–
43]. MOSFETs in resonant converters turn-on and off under zero current and/or
zero voltage switching which minimizes the switching losses and makes them suitable
for high frequency operation. The application of resonant converters for PV system
applications has received very little attention in the literature. Reference [44] proposes
four possible types of grid-connected PV inverters based on resonant converters. In
the first topology the PV array output is connected to a high-frequency voltage source
resonant inverter whose output is modulated using a cycloconverter to form the output
grid current. The second topology is based on a resonant converter followed by a
voltage source inverter. A slightly modified version of this topology is discussed
in references [45, 46], where by adding two extra diodes in the full bridge voltage
source inverter, the operation in rectifier mode is prevented. The third topology,
considered in reference [44], consists of a resonant converter feeding a current source
line commutated inverter. The operating frequency of the resonant inverter controls
the voltage and current at the output of the high frequency rectifier. Therefore, power
injection into the grid can be controlled by the operating frequency of the resonant
converter. The fourth topology controls the dc link current with a hysteresis controller
and the output line frequency inverter unfolds this rectified sinusoidal current and
injects it into the grid. Reference [44] attempts to propose different options for the
application of resonant converters in PV systems but it does not provide enough
analysis, simulation or experimental results to verify the performance of topologies
for all operating conditions.
CHAPTER 1. INTRODUCTION
1.4
15
Existing Power Decoupling Methods
It is possible, as adopted in reference [47], to use a balanced three-phase grid system to
resolve the instantaneous power oscillation. This method, although it seems practical
for three phase applications, has the disadvantage of power pulsation when the grid
becomes unbalanced. Also, the approach in reference [47] has very limited application
because the majority of residential customers only have access to single phase systems.
The focus of the rest of the section is on power decoupling in single phase systems.
1.4.1
Power Decoupling Using Energy Storage Components
As mentioned in Section 1.1.3, if there is no power decoupling in single-phase inverters,
the power generation at the PV terminal will contain oscillations that result in a
deviation from the optimum point. Therefore, there should be energy storage in
the circuit to supply oscillatory power and to reduce the power pulsation at the
PV
terminal. The decoupling problem is normally resolved by a large electrolytic
capacitor in the range of milli-Farads. This is highly undesirable because it decreases
the life-time and increases the volume, weight and cost of the inverter.
Depending on the topology, different locations of the energy storage are possible.
For single-stage topologies it is located at the PV terminals. For multi-stage microinverters, when a voltage source inverter is employed at the output as shown in Fig.
1.5, the power decoupling capacitor can be placed at the input terminals or at the
dc bus. It is beneficial to have most of the decoupling capacitance on the dc bus
because the voltage level is higher and the same amount of energy storage can be
achieved with a smaller capacitor. This has encouraged designers to increase the
dc bus voltage to a very high level as proposed in reference [48]. The generation
16
CHAPTER 1. INTRODUCTION
Large Electrolytic
Capacitor Bank
IPV
VPV
PV
High DC voltage
Voltage fed
igrid
DC
CPV2 CPV1
DC
VDC DC
CDC2 CDC1
LAC
Vgrid
AC
Figure 1.5: General block diagram for the conventional approach for power decoupling
in multi-stage micro-inverters with a voltage source inverter at the output
of a high dc voltage is not efficient and it poses an excessive voltage stress on the
inverter and on the output of the first stage. Moreover, the high voltage on the bus
enlarges high frequency ripples on the current, which requires large passive filters for
compensations. This approach is mostly used for topologies where the transformer is
not an energy buffer as proposed in references [4, 30].
Since the voltage source inverter at the output requires a bulky inductor for connection to the grid, in micro-inverters it is usually preferred to use an unfolding power
circuit in the last stage as discussed and shown in Fig. 1.6. In this structure, a very
large electrolytic capacitor bank should be installed at the PV terminals because the
voltage level is very low and the amount of capacitance required becomes large. For
example in the micro-inverter proposed in reference [49], the electrolytic capacitor is
10mF. In general all topologies that use the transformer as an energy buffer, employ
this configuration for power decoupling.
17
CHAPTER 1. INTRODUCTION
Very Large Electrolytic
Capacitor Bank
IPV
VPV
PV
Current shaping
|igrid|
igrid
DC
Unfolding
Stage
CPV4 CPV3 CPV2 CPV1
Vgrid
DC
Figure 1.6: General block diagram for the conventional approach for power decoupling
in multi-stage micro-inverters with an unfolding stage at the output
1.4.2
Power Decoupling Using Auxiliary Circuits
To avoid the electrolytic capacitor, some topologies use auxiliary circuit for decoupling. Fig. 1.7 shows a grid-connected flyback converter with an extra capacitor and
switch to perform the decoupling task [50]. This circuit is controlled so as to keep the
input current drawn from the PV cell constant and thus the extra or lack of current
which produces the power pulsation is redirected to or drawn from the decoupling
capacitor. The peak of the input current i1 is constant and the current ix tolerates
the pulsations. The smaller the cap selected, the larger the voltage variation induced.
Because of the leakage inductance of the transformer, during turn-off, a voltage spike
appears across the auxiliary transistor SX [51].
To solve this problem, a modified version of this circuit is proposed in reference
[51] as shown in Fig. 1.8. First, the main switches Sbuck−boost are switched on to
energize the transformer and when the input current reaches a certain value, the
output switches turn-on to discharge the transformer. After this period, the leakage
current of the transformer will be sent to the input capacitor through Df b1 and Df b2 ;
the energy in the leakage current which would be wasted in the original topology.
18
CHAPTER 1. INTRODUCTION
Power decoupling circuit
DX
Cx Sx
Dac1 Sac1
Lf
i2
iac
L2
it
Cr
L1
Cdc
L2
Vgrid
DM
PV
Dac2 Sac2
SM
Figure 1.7: Flyback inverter with active power decoupling
A common problem with the previous two topologies is that the output current is
supplied only on one stage out of 4 or 5 stages and the other time intervals are used
for the power decoupling process. This makes the output current waveform pulse
shape have a very high peak and narrow pulse width which leads to high conduction
and switching losses [52].
SBuck-boost
Sflyback1
Dfb1
Sac1
1:N:N
Dac1
DX
Cs
PV
Cf
iL
Cn
Lf
Dac2
Dfb2
Sflyback2
Sac2
Figure 1.8: Modified flyback converter with decoupling capability
The flyback converter shown in Fig. 1.9 is proposed to realize an active power
decoupling [52]. In this configuration the pulse width of the output current is widened
compared to the original topology shown in Fig. 1.7; therefore, the efficiency is
improved. The original topology shows a 63% efficiency for 100W input power as
19
CHAPTER 1. INTRODUCTION
opposed to this topology which has 73% efficiency for 55W input power [52]. However,
the distortion of the output current is increased because of the switching delays and
a compensation delay is introduced [52]. Although improved in many aspects, this
topology still suffers from a very low efficiency and low output power level.
Power Decoupling Circuit
Cx
Sx
DAC1
SAC1
idc
PV
it
L1
L2
L1
L2
DM
Cdc
Lf
i2
DX
Cr
DAC2
Vgrid
SAC2
SM
Figure 1.9: Modified high efficiency flyback converter with active decoupling
Reference [53] proposes yet another decoupling topology shown in Fig. 1.10. The
input consists of a filter and a buck-boost converter, which is realized by S1 , D1 and
the transformer primary inductance. If the main switch S1 is on, the energy is stored
in the transformer, otherwise either the energy is transferred to the grid by means of
the inverter (while S2 is on) or the energy is transferred to the capacitor Cdc (while S2
is off). Switch S2 is controlled such that the output power pulsation is drawn from the
capacitor and PV modules only provide constant average output power. Since a series
connection is used, the required capacitor is smaller than the parallel capacitor at the
PV terminal. This topology suffers from a high number of switches in series which
can cause high losses. The inverter is a current source type and most of the switches
are implemented by a MOSFET in series with a diode that deteriorates the efficiency,
especially for applications where the PV voltage is low and thus the current in the
20
CHAPTER 1. INTRODUCTION
circuit is high. More important is that this topology is basically non-isolated: for
isolation, it uses a low frequency transformer that is not practical in a micro-inverter
topology.
Filter
D1
n:1
Ci
PV
Li
LP
S1
io
Output Filter
S2H
L3
LS
S2
S1H
D2
C1
S1L
S2L
L4
Vgrid
C2
L2
C3
Cdc
Figure 1.10: Current source inverter and associated decoupling circuit
Fig. 1.11 shows another topology based on a forward converter with extra circuitry for power decoupling functionality [54]. The main switches are denoted by M
and the auxiliary circuit components are labeled as X. The concept of the operation
is that whenever the input power is more than the instantaneous power, the auxiliary circuitry stores the excessive energy in capacitor Cx , and once the output power
becomes more than the PV power generation, the stored energy is supplied to the
output to compensate for the lack of energy. It can be observed that using a transformer, passive and active components, the proposed auxiliary circuit can displace
the double frequency oscillation. However, this topology is proposed for input voltage
around 200 volts: for that voltage the capacitors at the PV is 44µF but for 25 volts
input the required capacitor may be in the range of electrolytic capacitors again. The
efficiency has also not fully reported: it is only mentioned that this topology shows
improvement when compared to the 73% efficiency of the topology shown in Fig. 1.9.
21
CHAPTER 1. INTRODUCTION
SX2
Lf
SM2
SAC1
SX0
Cf
SX1
CX
iAC
SAC3
LS
Vgrid
CDC
PV
LX
SM1
SAC2
SAC4
Figure 1.11: Forward converter with active decoupling
1.5
Description of the Proposed Structure
The review of the existing topologies reveals that for power decoupling either electrolytic capacitors or auxiliary circuits are used. The former has serious life-time,
size and maintenance problems and the latter approaches mainly exhibit low efficiency and/or high voltage stress with compromised results.
In this thesis micro-inverter topology and control systems are introduced to minimize the aforementioned problems. Fig. 1.12 shows the proposed power circuit block
diagram. In this structure, as explained in Chapter 3, owing to the new decoupling
method and high switching frequency of the first stage, the power pulsations are
IPV
Small
cap
Resonant
converter
Small
cap
DC
Voltage fed
modified PWM
Small size filter
igrid
DC+AC
Cbus
CPV
Vgrid
PV
DC+AC
AC
Figure 1.12: General block diagram for the proposed approach
CHAPTER 1. INTRODUCTION
22
only drawn from the bus capacitor and the input power extraction is kept constant
with a minimum capacitor at the PV terminal. The proposed decoupling method
creates a dc plus ac voltage at the middle stage and then uses a modified Pulse
Width Modulated (PWM) technique, as discussed in Section 4.6, to remove all double
frequency harmonics from the output current. Therefore the power pulsations have
minimum impact on the input power extraction or output power injection. By accepting a large ac oscillation on the bus and controlling the average bus voltage, as
explained in Chapter 4, it is possible to optimize both the value of the bus capacitor
and the voltage stress on the inverter. In the proposed micro-inverter, the input and
bus capacitors can be reduced to less than 20µF, an improvement of two or three order of magnitude. To achieve an even more compact design, the inverter is connected
to the grid using a 3rd order LCL filter rather than a single bulky inductor. A new
control design method and robust controller structure are proposed in Chapter 5 to
handle the harsh behavior of this LCL filter. As a result, the proposed structure and
control systems yield a compact design suitable for micro-inverter application.
1.6
Thesis Objectives
The main objective of this thesis is to design and implement a compact, durable
and efficient micro-inverter that complies with North American codes and standards.
To achieve this goal, new structure and control methods are proposed. For each
controller, an appropriate model, systematic control design methods and a detailed
stability analysis are developed. Briefly, the dissertation’s objectives are:
CHAPTER 1. INTRODUCTION
23
1. To develop and optimize a resonant converter topology to provide Zero Voltage Switching (ZVS) while minimizing conduction losses for maximum power
extraction from the PV source under varying conditions;
2. To derive a small signal and large signal model for a system including the
resonant converter and the nonlinear PV module in order to develop a control
strategy that provides power decoupling between the PV and the grid;
3. To propose new nonlinear controller and reference generation systems for (i)
injecting high quality instantaneous power without measuring active or reactive
powers and (ii) controlling the average bus voltage;
4. To propose design procedures and control structures for the output inverter to
achieve optimum and robust responses for startup, dynamic, and steady state
operations and also to obtain high quality grid synchronized output current
with damped resonance oscillations despite all uncertainties and variations of
the grid;
5. To digitize control algorithms suitable for fixed-point Field Programmable Gate
Array (FPGA) implementation; and
6. To verify the system design and analysis using simulation and experimental
results.
1.7
Thesis Outline
In Chapter 2 an overall description of the proposed micro-inverter is presented. For
the first stage of the converter, an Asymmetrical Pulse Width Modulated (APWM)
CHAPTER 1. INTRODUCTION
24
series resonant converter is used, which has the following desired specifications: amplification, isolation, high power density and soft switching. The basic principle of
operation is explained in detail. It is shown how the instantaneous power oscillation
of the second stage and variations in irradiation level (input power) and ambient temperature (input voltage) affect the operating points of the converter. The limitations
posed by these variations on the design procedure are analytically and graphically
presented. Switching frequency and average value of the bus voltage are two degrees
of freedom that are used to propose a controller to widen the range of operation
with zero voltage switching. Both theoretical and experimental verifications are also
provided.
Chapter 3 introduces a new power decoupling method and describes the PV side
controller design method. The method decouples output power oscillations from the
input dc power generation without using large electrolytic capacitors. This method
increases the life-time and reduces the volume, weight, and cost of the inverter, all
desired specifications in micro-inverter applications. The nonlinear large signal model
of the system is then obtained and a linear small signal model is also derived using
the extended describing function method and linearization technique . After the
elimination of internal dynamics, the small signal model is used to design a stable
and wide-band closed loop system to achieve the desired performance. Simulation
and experimental results demonstrate good dynamic responses of the method.
Chapter 4 presents a detailed analysis of synchronization methods, active power,
reactive power and dc bus voltage control loops. The selected Phase Locked Loop
(PLL) structure for grid synchronization eliminates the harmful double frequency oscillations from the control loop in a manner that is simple and suitable for grid-connected
CHAPTER 1. INTRODUCTION
25
single-phase applications. A new method is proposed based on direct nonlinear control of the instantaneous power rather than controlling active and reactive powers
independently. The design procedure and stability analysis are also elaborated. It
is shown that the proposed method (i) is not sensitive to grid frequency variations,
(ii) is robust against grid harmonics and (iii) is suitable for digital implementation.
This chapter also presents bus voltage control based on energy state variables. The
proposed control loop makes the system equations linear and removes high order harmonics from the bus voltage. Since the dc bus system model is time varying, the
Lyapunov method is used to prove the stability. At the end of the chapter, the PWM
method is modified to removes excessive harmonics from the output of the converter.
In Chapter 5, a further reduction in the size of the micro-inverter is obtained by
using a higher order filter at the output of the inverter. The method to design the filter and associated control systems are discussed. A new design of an optimal control
scheme is proposed to stabilize the output current injection and to actively damp the
harmful oscillating mode of this filter. It is shown that the standard Linear Quadratic
Regulator (LQR) problem can be extended to the tracking sinusoidal reference problem and the optimality and robustness of the method against uncertainties in the grid
impedance are verified by example. The controller structure is further developed so
as to minimize the effect of grid harmonics on the output current and coefficients of
this controller were optimally obtained using the improved LQR technique in a systematic method to arrive at a desirable response. Conventionally, the inrush current
at the startup of the system is suppressed by protection systems. In this chapter,
however, the inrush current is minimized by the modification of the proposed controller. Moreover, a new design method is developed to find the coefficient of this
CHAPTER 1. INTRODUCTION
26
controller. Resonant type controllers are useful to achieve zero steady state error for
tracking sinusoidal references, however, a digital implementation of such controllers
is error-prone. The delta operator overcomes this drawback of resonant controllers
and when implemented in delta domain (instead of z domain), the sensitivity can
be highly reduced by an appropriate adjustment of the parameters. Simulations and
experimental results are provided to approve the proposed concepts.
Finally, Chapter 6 summarizes the contributions of the thesis and proposes a few
other possibilities for future research.
Chapter 2
Micro-Inverter Topology
2.1
Introduction
A micro-inverter topology is the integration of the PV modules/cells and the inverter
into one electrical device so that one electrical product can convert light into electrical
ac power. As explained in Section 1.1, any PV inverter should be able to perform
MPPT, power decoupling and high quality ac power injection into the grid at maximum
efficiency for all input voltage and power levels. Moreover, a micro-inverter has to be
designed as compactly as possible using a minimum number of reliable and inexpensive
components to be integrated into a PV module. To achieve these objectives, this thesis
proposes the structure that was shown in Fig. 1.12. In the first stage, an APWM
resonant converter topology [40, 42, 55] is selected because it provides the following
features:
• the high switching frequency needed by the proposed decoupling method discussed in Chapter 3 to reduce the size of the PV capacitor;
27
CHAPTER 2. MICRO-INVERTER TOPOLOGY
28
• the isolated topology required by North American standards for grid-connected
PV
inverters;
• the voltage amplification required to cennect a low-voltage PV module to a
high-voltage grid;
• the high efficiency obtained by operating above the resonant frequency to achieve
ZVS;
and
• the high power density and compact design obtained by the high switching
frequency of resonant converters.
The APWM series resonant converter offers near zero switching losses while operating at constant and very high frequencies [55]. The aforementioned special characteristics and the low number of components make APWM series resonant converters
an ideal candidate for photovoltaic micro-inverters.
In the proposed structure shown in Fig. 1.12, the average of the resonant converter
output voltage (i.e. the bus voltage) is controlled by the output inverter while the
first stage controls only the input voltage. As will be shown, the bus voltage contains
large double grid frequency oscillations that affects the current and voltage of the
resonant tank. As a result, the steady state operation of the resonant converter is
different from conventional applications.
To take into account the bus voltage oscillation and special operation of the resonant converter, a new complete steady state analysis of the system is performed. The
result of the analysis is used to design the converter so that (i) ZVS is guaranteed for
all PV operating conditions and (ii) conduction losses are minimized. Simulation and
experimental results are provided to verify design and analysis methods.
29
CHAPTER 2. MICRO-INVERTER TOPOLOGY
is1
iPV
CPV
PV
iPV
+
vPV
_
S2
vPV
New
MPPT
Hardware
is2
S1
APWM
Modulator
ref
vPV
+
vCs _ ires
+ Cs
vin
_
io
T
Ls +
vp
_
igrid
DC+AC
D1 Cbus
Output
filter
vgrid
AC
1:N D2
Inverter
PV
voltage
control
Figure 2.1: Asymmetric PWM series resonant converter power circuit topology
2.2
Series Resonant Converter Circuit Topology
Fig. 2.1 shows the circuit diagram of APWM series resonant converter that is proposed for the micro-inverter in PV applications. The power circuit consists of a
chopper with two switches S1 and S2 , a series resonant tank made by capacitor Cs
and inductor Ls , a high-frequency transformer T, a rectifying circuit with two diodes
D1 and D2 and the output bus capacitor Cbus . The chopper controls the output PV
voltage by controlling the amount of current drawn from the PV capacitor CP V . The
output voltage of the chopper is a high frequency unidirectional waveform with an
amplitude equal to VP V . The series resonant tank converts this unidirectional voltage
into oscillatory current ires and the dc component of the output of the chopper is
blocked by the resonant tank capacitor Cs . Since the output voltage of the resonant
converter is controlled by the inverter in the next stage, the resonant converter should
be able to inject the dc input power to the next stage for under all variations of input
power, output voltage and input voltage reference. The high frequency transformer
provides the voltage amplification and the isolation. The rectifying circuit rectifies
CHAPTER 2. MICRO-INVERTER TOPOLOGY
30
the high frequency resonant current and supplies dc power to the middle stage bus.
2.3
Series Resonant Converter Principle Of Operation
As shown in Fig. 2.1, the output of a PV module is directly connected to the input of the APWM series resonant converter. A major challenge in using a PV and
controlling its output voltage is the nonlinear current-voltage (I-V) characteristics
described in Appendix A that result in a variable maximum power point (MPP) on
the power-voltage (P-V) curve, as shown in Fig. A.1. Therefore, to achieve maximum
power point tracking ability, the MPP reference is generated for the converter and the
APWM series resonant converter must be able to follow this voltage reference for all
conditions. The average output voltage of the resonant converter is regulated by the
grid-connected inverter while the ripple of the bus voltage is stipulated by the circuit
parameters and input power level. The control scheme for the input stage is shown
in Fig. 2.1. The maximum power point tracking block receives the input current and
voltage information, and generates the desired voltage reference VPref
V . The PV voltage controller, which is a PI controller in this case, forces the input voltage to follow
the voltage reference generated by the MPPT block. It is worth mentioning that a
PI controller is ideal for the regulation control problems and if used in the tracking
of a variable signal it will generate a nonzero steady state error. In this application,
however, the input irradiation level changes very slowly compared to the switching
frequency, and a simple PI controller results in a negligible steady state error even
for relatively rapidly changing conditions.
31
CHAPTER 2. MICRO-INVERTER TOPOLOGY
s1
Vgs
s2
Vgs
vin
vPV
ires
1
vp
vbus /N
io
Io
is1
IPV
A1
A2
∆vPV
I
t0 t1
II III
t2 t3 t4 t5
IV
V VI
t6 t7 t0
Figure 2.2: Typical steady-state operating waveforms.
32
CHAPTER 2. MICRO-INVERTER TOPOLOGY
PV
CPV
Cs ires
is1
iPV
+
vPV
_
+
S1
vin = vPV
S2
_
io
Ls +
vp
_
1:N D2
(a) Interval I
Cs1
iPV
PV
CPV
+
vPV
_
Cs
is1
is2
S1
ires
+
io
Ls +
vp
_
Cs2
vin
S2
_
PV
CPV
Cs
+
vPV
_
is2
S1
ires
+
vin = 0
S2
_
io
Ls +
vp
_
Cs ires
iPV
PV
+
vPV
_
is2
S1
+
vin = 0
S2
_
io
Ls +
vp
_
Cs1
iPV
CPV
+
vPV
_
Cs
is1
S1
is2
ires
+
vin
_
is1
PV
CPV
+
vPV
_
S1
is2
S2
Cs
ires
Ls +
vp
vin = vPV
_
_
+
(f) Interval VI
D1 Cbus
+
vbus
_
1:N D
2
(e) Interval V
iPV
+
vbus
_
io
Ls +
vp
_
Cs2
S2
D1 Cbus
1:N D2
(d) Interval IV
PV
D1 Cbus +
vbus
_
1:N D
2
(c) Interval III
CPV
D1 Cbus +
vbus
_
1:N D2
(b) Interval II
iPV
D1 Cbus +
vbus
_
io
D1 Cbus
+
vbus
_
1:N D2
Figure 2.3: Equivalent circuits for operating intervals labeled in Fig. 2.2 for the
converter shown in Fig. 2.1
CHAPTER 2. MICRO-INVERTER TOPOLOGY
33
For a typical operating condition, the steady-state waveforms for the APWM
series resonant converter in different stages of operation are shown in Fig. 2.2 and
the equivalent circuits for each stage are shown in Fig. 2.3.
These stages of operation are given as follows:
• Interval I: At t0 the resonant current ires becomes positive and remains positive
for the rest of the time in this interval. During this interval, S1 is on and S2
is off. This interval is divided to two parts: (i) (t0 -t1 ) when the PV output
current is higher than the current drawn by the converter and as a result the
input capacitor CP V is being charged (ii) (t1 -t2 ) when the opposite happens and
CP V is being discharged. During Interval I the output voltage vin of the chopper
is equal to the PV voltage VP V . The rectifier output current goes through the
diode D1. Therefore, the voltage on the primary side of transformer vp equals
vbus /N if neglecting voltage drop across the diode. At t2 , S1 is turned off for
input voltage regulation.
• Interval II: Like the previous interval, this interval is also divided into two
parts: (t2 -t3 ) when CP V is discharged and (t3 -t4 ) when CP V is charged. At the
beginning of this interval, at time t2 , S1 is turned off. The positive current flow
through the resonant branch charges the output capacitance of S1 and at the
same time discharges the output capacitance of S2 . At t4 the output capacitor
of S1 is fully charged and that of S2 is fully discharged. During this interval
switch S2 is kept off to achieve ZVS in the next interval.
• Interval III: At the beginning of this interval the resonant current forces the
conduction of the body diode in S2 . As a result if at any moment during this
interval switch S2 is turned on ZVS is achieved. During this interval, S1 is kept
CHAPTER 2. MICRO-INVERTER TOPOLOGY
34
off. Thus, the chopper output voltage vin is zero. Because ires is still positive,
D1 is on and D2 is still off, so the voltage on the primary side of transformer is
still vbus /N.
• Interval IV: At t5 , the sign of the resonant current changes and becomes
negative. This forces the rectifier diode D2 to conduct and thus the voltage on
the primary side of the transformer also changes to a negative value, −vbus /N.
During this interval, S2 and D2 are on and S1 and D1 are off. Thus, the chopper
output voltage vin is also zero.
• Interval V: At the beginning of this interval, S2 is turned off. The negative
current flow through the resonant branch discharges the output capacitance of
S1 and at the same time charges the output capacitance of S2 . At t7 the output
capacitor of S2 is fully charged and that of S1 is fully discharged. During this
interval S1 should be kept off to achieve ZVS in the next interval.
• Interval VI: At the beginning of this interval the negative resonant current
forces the conduction of the body diode in S1 . As a result, if at any moment
during this interval switch S1 is turned on ZVS is achieved. During this interval,
S2 is kept off. Thus, the chopper output voltage vin is equal to VP V . Because
ires is still negative D2 is on and D1 is still off and the voltage on the primary
side of the transformer is still −vbus /N. At t0 , the resonant current ires changes
to a positive value, which is the start of another operating cycle.
In steady state operation, if the controller is assumed to be fast enough to reject
all disturbances from the input voltage, the average voltage of the input capacitor
CP V will become constant. Figure 2.2 shows is1 and the PV output current waveforms
CHAPTER 2. MICRO-INVERTER TOPOLOGY
35
on one graph. The difference between these two currents goes to the input capacitor
and this difference can be positive or negative. The shaded area A1 and A2 show the
amount of charge respectively discharging and charging the capacitor. As a result, to
achieve steady state operation the area of the two shaded regions in the graph should
be equal.
2.4
Series Resonant Converter Steady-State Analysis and Design
Fig. 2.1 shows that the series resonant converter is connected to an inverter. The
bus voltage at the output of the converter has various harmonic components: (i) a dc
component that is regulated by the inverter using a dc bus controller introduced in
Chapter 4, and (ii) higher order harmonics with a dominant second order harmonic
whose values are determined by circuit parameters, the dc component of the bus
voltage and the input power. Therefore, the output impedance of the converter is
variable and more importantly, it is not a linear function of the circuit operating
point.
Fig. 2.4 shows the equivalent circuit diagram of the resonant tank of the converter
at three levels of approximation. Since the resonant tank current controls the rectifier
diodes (D1 and D2 ), the primary voltage of the transformer becomes in-phase with the
current. The amplitude of vp is stipulated by the instantaneous amplitude of the bus
voltage. Due to the fact that fundamental component of vp is in-phase with ires , the
equivalent circuit in Fig. 2.4(b) can be derived where the primary side voltage source
is replaced by a resistor. More simplification can be achieved by considering only the
36
CHAPTER 2. MICRO-INVERTER TOPOLOGY
+
+
vin
_
vCs _ ires
+
Ls +
vp
_
Cs
(a)
+
vin
_
vCs _ ires
+
Ls +
vp
_
Cs
(b)
Rac
+
vin
_
vCs _ ires
Ls +
vp
_
Cs
Rac
(c)
Figure 2.4: Three equivalent circuits for the resonant tank: (a) no simplification, (b)
fundamental approximation for vp , and (c) fundamental approximation
for vin and vp
fundamental component of vin as shown in Fig. 2.4 (c), however, since the topology
is using the APWM method, vin will have dominant harmonics and the fundamental
approximation does not seem accurate enough. For the rest of the discussion the
equivalent circuit (b) is used and the value of Rac is required. Since Rac depends on
the bus voltage, the instantaneous value of the bus voltage should be known before
any further calculation.
2.4.1
Calculation of the Instantaneous Value of the Bus Voltage
For the sake of simplicity it is assumed that the converter is lossless and the output
filter energy storage is negligible. For a more accurate analysis please refer to Section
4.5.1. The inverter of Fig. 2.1 controls the current injected into the grid, igrid , such
o
o
o
that PSRC
= Pinv
, where PSRC
is the series resonant converter output power and
o
Pinv
is the average inverter output power over one grid frequency. Since the passive
elements of the resonant converter are small, it is reasonable to further assume that
o
o
PSRC
= Pin , i.e., PSRC
is dc power. Therefore, the only energy storage component is
37
CHAPTER 2. MICRO-INVERTER TOPOLOGY
Cbus . Assuming that the inverter generates a current in phase with the grid voltage,
the output power can be derived as follows:
igrid (t) = Igrid sin(ωg t), Vg (t) = Vgrid sin(ωg t)
o
⇒ PSRC
1
⇒ poinv (t) = Vgrid Igrid (1 − cos(2ωg t))
2
Z π
1
2ωg 2ωg o
o
= Pinv =
pinv (t)dt = Vgrid Igrid = Pin .
π 0
2
(2.1)
(2.2)
o
From equations (2.1) and (2.2) it is concluded that poinv (t± ) = PSRC
where t± =
± 4ωπg , and for the time range t ∈ (− 4ωπg , 4ωπg ), the resonant converter output power
will be greater than the injected output power into the grid. Therefore, over this
min
max
range of time the bus capacitor, Cbus , will be charged from Vbus
to Vbus
, as shown
below:
1
1
max 2
min 2
Cbus (Vbus
) − Cbus (Vbus
) =
2
2
∆Vbus =
Z
π
4ωg
−π
4ωg
o
(PSRC
− poinv (t))dt =
Pin
,
DC
ωg Cbus Vbus
Pin
⇒
ωg
(2.3)
DC
min
max
where ∆Vbus is the peak to peak bus voltage oscillation and Vbus
= (Vbus
+ Vbus
)/2.
Using the same procedure over t ∈ (0, t), one can derive the following equations:
Z t
1
1
2
DC 2
o
Cbus (vbus (t)) − Cbus (Vbus ) =
(PSRC
− poinv (t))dt
(2.4)
2
2
0
Vgrid Igrid
=
sin(2ωg t)
(2.5)
4ωg
s
Vgrid Igrid
DC 2
⇒ vbus (t) =
(Vbus
) +
sin(2ωg t)
(2.6)
2ωg Cbus
s
Pin
DC 2
=
(Vbus
) +
sin(2ωg t).
(2.7)
ωg Cbus
It is worth mentioning that since the capacitor voltage changes from a minimum to
CHAPTER 2. MICRO-INVERTER TOPOLOGY
38
DC
a maximum over t ∈ (− 4ωπg , 4ωπg ), at t = 0 the voltage is equal to Vbus
.
Using (2.3), equation (2.6) can be rewritten as follows:
r
DC 2
DC ∆Vbus
⇒ vbus (t) = (Vbus
) + Vbus
sin(2ωg t).
2
(2.8)
Equations (2.6) and (2.8) show that the bus voltage contains all harmonics, however, the dominant parts are the dc and second order harmonics. Figures 2.5(a) and
2.5(b) show the minimum and maximum peaks of the bus voltage for different operating conditions. It can be seen that the smaller the capacitor the larger the bus
variation that appears at the output of the converter.
From the figures it can be seen that for a given capacitor value, if the average
DC
min
bus voltage (Vbus
) is not large enough, the minimum bus voltage (Vbus
) can reach
low values. Since the output of the inverter is connected to the grid, for all operating
min
conditions Vbus
should be larger than the peak of Vg otherwise the inversion and
current injection is not feasible for the second stage. Therefore, for Cbus = 20µF the
minimum acceptable average bus voltage is around 250V and for Cbus = 40µF it is
around 230V.
It is important to note that the low frequency component of the bus voltage
affects the primary voltage of the transformer and also the resonant tank current
and voltage. This low frequency component appears as an amplitude modulation
for the currents and voltages. As a result, the frequency components are all at high
frequency and there is no low frequency harmonics at the transformer. In other
words, since the current and voltage of the transformer change their sign at high
frequency, the transformer is reset at high frequency and it does not see any low
frequency component. Therefore, it is only designed based on the high frequency
characteristics.
CHAPTER 2. MICRO-INVERTER TOPOLOGY
39
(a)
(b)
Figure 2.5: Bus voltage at minimum and maximum points for (a) Cbus = 20µF (b)
Cbus = 40µF
CHAPTER 2. MICRO-INVERTER TOPOLOGY
2.4.2
40
Calculation of the Equivalent Resistance Rac
Figures 2.1 and 2.4 (a) show that the voltage of the primary side of the transformer
(vp ) is the instantaneous bus voltage that is modulated at the resonant converter
switching frequency. Since the variation in the bus voltage occurs much more slowly
than the switching frequency, it is assumed that the amplitude of vp is constant over
one switching period. Therefore, vp can be derived as follows:
∞
vbus (t) X 4
vp (t) =
sin(nωs t + ψn ),
N n=0 nπ
(2.9)
where N is the transformer turn ratio, ωs is the resonant converter switching frequency
vbus
sgn(ires ), the phase of
and ψn is the phase shift of the nth harmonic. Since vp =
N
the first harmonic of vp is equal to that of ires ; in other words, for n=1, ψn =θn , where
θn is the phase shift of the nth harmonic of the resonant tank current. Equation (2.9)
shows that the primary voltage of the transformer and subsequently Rac are changing
continuously. By neglecting the series resonant power losses and noting that the
resonant converter has very fast dynamics it is reasonable to assume that the output
o
power of the converter is equal to its input power, PSRC
= Pin . Using (2.6) , (2.9)
and considering only fundamental components, one can determine Rac (t) as follows:
(t) 2
(Vp1 (t))2
( 4vbus
)
8
Pin
DC 2
πN
Rac (t) =
=
= 2 2
(Vbus ) +
sin(2ωg t)
(2.10)
o
2PSRC
2Pin
π N Pin
ωg Cbus
Figures 2.6(a) and 2.6(b) show graphs of Rac for different Pin as a function of
time. For moment, the value of the transformer turn ratio is selected to be 23; it
will be shown that this is the minimum acceptable value. It can be observed that for
higher input power levels, the percentage of variation of Rac increases significantly.
DC
Equation (2.10) shows that Rac depends also on Vbus
and this dependency is shown
in Figures 2.7(a) and 2.7(b).
CHAPTER 2. MICRO-INVERTER TOPOLOGY
(a)
(b)
Figure 2.6: Rac as a function of time for (a) Cbus = 20µF (b) Cbus = 40µF
41
CHAPTER 2. MICRO-INVERTER TOPOLOGY
42
(a)
(b)
Figure 2.7: Rac at minimum and maximum points for (a) Cbus = 20µF (b) Cbus =
40µF
43
CHAPTER 2. MICRO-INVERTER TOPOLOGY
2.4.3
Converter Gain Calculation
To derive the gain formula analytically, the equivalent circuit shown in Fig. 2.4 (b) is
used. Since the input voltage (vin ) is pulse width modulated, the resonant converter
generates output vin as shown in Fig. 2.2. If it is assumed that duty cycle of switch
S1 is D, the time variation of vin can be represented by the following Fourier series:
∞ √
X
2VP V p
vin (t) = DVP V +
1 − cos(2nπD) sin(nωs t + φn ),
(2.11)
nπ
n=1
where
φn = arctan
sin(2nπD)
.
1 − cos(2nπD)
This equation can be futhur simplified to yield
∞
X
2VP V
vin (t) = DVP V +
sin(nπD) cos(nωs t − nπD).
nπ
n=1
(2.12)
Now, using the equivalent circuit shown in Fig. 2.4 (b), it is straightforward to derive
the resonant current ires :
∞
X
2VP V sin(nπD) cos nωs t − nπD − arctan Q(nω −
q
ires (t) =
nπRac
1 2
1 + Q2 (nω − nω
)
n=1
1
)
nω
,
(2.13)
where Q = (Ls ωr )/Rac and ω = ωs /ωr . Since there is a series capacitor in the tank,
the current does not have any dc component. As shown in Fig. 2.5(a), for Pin in the
range of 10 to 200 watts and a bus capacitor of 20µF, the bus voltage can drop within
an unacceptably low range and henceforth the bus capacitor is selected as 40µF. Fig.
2.8 shows the quality factor (Q) calculated for all operating conditions. It can be
seen that the highest Q variation appears for the lowest average bus voltage and
highest Pin . The quality factor should not be too high because the circuit becomes
too sensitive to frequency variation. If Ls ωr is chosen in the range of 1 to 2 ohms the
quality factor will remain within a reasonable range. The reasonable range of quality
CHAPTER 2. MICRO-INVERTER TOPOLOGY
44
Figure 2.8: Normalized quality factor at minimum and maximum points for all possible operating condition
factor for series resonant converter is in the range of 1-4.
For the sake of simplicity only the first harmonic component of ires is considered
for the following gain calculations:
i(1)
res = Ires sin(ωs t + θn ),
(2.14)
where



I =


 res
2VP V sin(πD)
q
πRac 1 + Q2 (ω − ω1 )2


π
Q


.
 θn = − πD − arctan Qω −
2
ω
As shown in Fig. 2.1, the current of switch S1 (iS1 ) is equal to the resonant
tank current whenever the switch is on, or in other words, iS1 = Dires . For constant
45
CHAPTER 2. MICRO-INVERTER TOPOLOGY
irradiation and temperature conditions, IP V is constant and thus, to maintain the
input voltage (VP V ) at a constant level, the average of IP V and iS1 should be equal
in one switching cycle. In other words:
Z
Z
Z
1 Ts
1 Ts
1 DTs
IP V =
iS1 dt =
Dires dt =
Ires sin(ωs t + θn )dt
Ts 0
Ts 0
Ts 0
⇒ IP V =
(2.15)
Ires
sin(πD) sin(πD + θn ).
π
Using this equation and (2.14) one can obtain:
IP V
2VP V sin2 (πD)
Q
q
=
cos arctan(Qω − )
ω
2
π Rac 1 + Q2 (ω − ω1 )2
⇒ IP V Rac =
2VP V sin2 (πD)
.
π 2 (1 + Q2 (ω − ω1 )2 )
Using (2.10) and Pin = IP V VP V , the equation IP V Rac =
(2.16)
(Vp1 (t))2
2VP V
can be derived.
Therefore, the right hand side of this equation and (2.16) will be equal and that
yields:
(1)
Vp
2 sin(πD)
= q
.
VP V
π 1 + Q2 (ω − ω1 )2
(1)
Using (2.9) it is clear that Vp
= 4vbus /(Nπ). As a result, the gain of the converter
from the PV to the bus at the output of the converter is:
vbus (t)
N sin(πD(t))
= q
.
VP V
2 1 + Q2 (ω − ω1 )2
(2.17)
CHAPTER 2. MICRO-INVERTER TOPOLOGY
2.4.4
46
Design of Transformer Turn Ratio
Equation 2.17 shows that to be able to control the input voltage for all conditions,
the turn ratio of the transformer should be designed such that:

2f (t)
2f (t)


→
≤ 1, where
 sin(πD) = NV
NVP V
PV
r
(2.18)

1 2

2

f (t) = vbus (t) 1 + Q(t) (ω − ) .
ω
In this equation Q is replaced by Q(t) to emphasize the dependency of Q on time.
Extremum points of f (t) should be calculated to prove that condition (2.18) holds
for all conditions. Since Q(t) = (Ls ωr )/Rac (t), using (2.10), Q′ (t) can be calculated
as follows:
Q(t) =
′
−2Ls ωr vbus
(t)
Ls ωr
′
→
Q
(t)
=
.
8
8
2
3
v
(t)
v
(t)
2
2
2
2
bus
bus
π N Pin
π N Pin
As a result the time derivative of f (t) can be obtained as:
!
1 2
2 2
L
ω
(ω
−
)
s r
′
′
ω
f ′ (t) = vbus
(t) 1 −
(t)g(t).
= vbus
4
( π2 N82 Pin )2 vbus
(t)
(2.19)
′
The equation f ′ (t) = 0 results in vbus
(t) = 0 or g(t) = 0. The real and positive
solution of g(t) = 0 is:
vbus =
r
π 2 N 2 Pin
1
Ls ωr (ω − ).
8
ω
(2.20)
For micro-inverter applications where Pin is less than 250W, and for normal choices
of parameters, the right hand side of this equation is less than 150V. As a result, the
extremum points of f (t) are located at the extremum points of bus voltage.
To design the converter such that for all conditions inequality (2.18) holds, the
function f (t) should be evaluated only at the extremum points of the bus voltage and
then for the worst condition (minimum VP V ), N is selected to satisfy the inequality.
According to (2.6), the bus voltage is a function of the input power and for any
CHAPTER 2. MICRO-INVERTER TOPOLOGY
47
selected operating point, the maximum input power should be known.
max
As an example, PV module parameters can be selected as VPmin
V = 25, VP V = 45
and PPmax
= 200. Figure 2.9(a) and 2.9(b) show an evaluation of inequality (2.18)
V
for this case. It can be seen that the worst condition occurs at full power. It can
be observed that with any turn ratio above N=22, there is a range of Ls ωr that
can maintain the value of sin(πD) under 1 for the whole range of Pin and thus the
inequality holds. In a similar manner graphs can depict duty cycles of the switches
for different conditions. Fig. 2.10 shows the duty cycles at minimum and maximum
points of the bus voltage. From (2.18) it can be seen that the highest level of duty
cycle is 0.5 where sin(πD) reaches its maximum.
2.4.5
Calculations of Turn-Off Currents
As mentioned in detail in Section 2.3, by using APWM resonant converters it is
possible to achieve ZVS at turn-on of the switches if certain conditions are satisfied.
From Fig. 2.2 it can be seen that to guarantee ZVS for S1 at turn-on, it is sufficient
to have negative resonant current when S2 is turned off. Similarly, to achieve ZVS
at turn-on for S2 , resonant current at turn-off of S1 should be a positive value. To
eliminate/reduce turn-off losses, additional capacitors are employed in parallel to the
main switches where they maintain the voltage across the switches at near-zero levels
until the current reaches zero. It is worth mentioning that the parallel capacitors
do not cause any additional losses at turn-on and their energies are fed back to the
circuit provided that ZVS is guaranteed at turn-on. By referring to Fig. 2.2 it can be
seen that the turn-off current of S2 can be found analytically by setting t=0 in the
cosine function in (2.13). It is worth noting that the result is still a function of time
CHAPTER 2. MICRO-INVERTER TOPOLOGY
(a)
(b)
Figure 2.9: Evaluation of inequality (2.18) for (a) N=21 (b) N=23
48
CHAPTER 2. MICRO-INVERTER TOPOLOGY
49
(a)
(b)
Figure 2.10: The duty cycles of S1 at extremum points of the bus voltage (a) at the
maximum points (b) at the minimum points
50
CHAPTER 2. MICRO-INVERTER TOPOLOGY
because the duty cycle, Rac and Q are changing continuously. The turn-off current
of S2 is thus
of f
IS2
(t)
∞
X
2VP V sin(nπD(t)) cos nπD(t) + arctan Q(t)(nω −
q
=
nπRac (t)
1 2
1 + Q2 (t)(nω − nω
)
n=1
1
)
nω
.
(2.21)
Similarly by setting t = DTs in (2.13) the turn-off current of S1 is calculated as
∞
1
X
)
cos
nπD(t)
−
arctan
Q(t)(nω
−
2V
sin(nπD(t))
PV
of f
nω
q
. (2.22)
IS1
(t) =
nπR
(t)
1
2
2
ac
1
+
Q
(t)(nω
−
)
n=1
nω
Fig. 2.11(a) and 2.11(b) show the graph of (2.21) for all possible values of Pin and
VP V . As mentioned before, to achieve ZVS, these graphs should be under the zero
plane and it can be seen that with the current design parameters, ZVS is lost for some
operating conditions. The worst condition in general is where the input voltage is
min
near full power. In particular it can be observed that IS2
(t) is rarely below the zero
plane when the bus voltage is at a minimum. The min or max notations used here
means the value of the parameters calculated at the minimum or maximum points
of the bus voltage. The reason is that at a lower bus voltage the resonant current
becomes larger.
Figure 2.12(a) shows the turn-off current of S1 . It can be observed that for all
conditions ZVS is obtained because the graphs are always positive. When the bus
min
max
voltage is at its minimum, the resonant tank current IS1
is higher than IS1
, because
min
the input power is constant and thus the upper plane relates to IS1
.
The turn-off current of the switches can be used to calculate the value of the
capacitors in parallel with the switches to minimize the turn-off losses. When the
range of turn-off currents for different conditions is wide, the selection of the parallel
capacitors becomes troublesome. For example, the capacitor of switch S1 should be
CHAPTER 2. MICRO-INVERTER TOPOLOGY
51
(a)
(b)
Figure 2.11: Turn-off currents for S2 at (a) minimum points of the bus voltage, (b)
maximum points of the bus voltage
52
CHAPTER 2. MICRO-INVERTER TOPOLOGY
small enough to become discharged for the small turn-off conditions of S2 within the
specific dead-time to achieve ZVS at turn-on for S1 . However, if the parallel capacitor
for S1 is too small it cannot hold the voltage across S1 near zero during turn-off time
and thus it may not be possible to eliminate turn-off losses for all conditions.
2.4.6
The RMS Resonant Tank Current
The summation of the squared amplitudes of harmonics in (2.13) divided by 2 yields
the RMS of the resonant current, given by

∞
X
VP V sin(nπD(t))
RM S

q
Ires
(t) =
nπRac (t) 1 + Q2 (t)(nω −
n=1
1 2
)
nω
2
 .
(2.23)
Fig. 2.12(b) shows the resonant tank RMS current at the minimum and the
maximum bus voltage. It can be seen that the RMS current is directly proportional
to the input power and it does not depend on the input voltage. The RMS current
is at its minimum when the bus voltage is at its maximum and vice versa. These
observations can be justified as follows: at the primary side of the transformer, the
voltage is stipulated by the second stage bus voltage; thus for a constant Pin , the
current and its RMS value only depend on the bus voltage and do not depend on the
input voltage. Similarly, the RMS current does not depend on the value of Ls ωr and
is only a function of input power and bus voltage. Fig. 2.12(b) can be used to select
the current ratings for series resonant tank components.
2.4.7
Voltage Stress on the Resonant Tank Capacitor
The selection of components and operating points affect the stress on the components.
The resonant tank current is derived in (2.13). Since the resonant current is the only
CHAPTER 2. MICRO-INVERTER TOPOLOGY
53
(a)
(b)
Figure 2.12: (a) Turn-off currents for S1 , (b) the RMS of the currents of the resonant
tank at the extremum points of the bus voltage
54
CHAPTER 2. MICRO-INVERTER TOPOLOGY
Figure 2.13: The RMS value of the voltage of the series capacitor at the extremum
points of the bus voltage for different Ls ωr
current passing through the capacitor, the voltage of the capacitor can be found by
integrating the current and dividing it by Cs as follows:
∞
X
2VP V sin(nπD) sin nωs t − nπD − arctan Q(nω −
q
vCs (t) =
n2 Cs ωs πRac
1 2
1 + Q2 (nω − nω
)
n=1
1
)
nω
The RMS of the series capacitor voltage can be found as follows:

2
∞
X
QVP V sin(nπD)
RM S
 .

q
VCs
=
1 2
2
2
n ωπ 1 + Q (nω − nω )
n=1
.
(2.24)
(2.25)
As was previously discussed, the RMS current of the tank does not depend on
VP V and consequently vCs is also independent of the input voltage. Unlike the RMS
current of the resonant tank, vCs varies for different values of Ls ωr . For a constant
resonant frequency, when Ls ωr increases, Cs has to decrease, which in turn increases
vCs . Fig. 2.13 shows the dependency of vCs on Pin and Ls ωr . These graphs can be
used to select the series capacitor ratings.
CHAPTER 2. MICRO-INVERTER TOPOLOGY
2.4.8
55
Design Approach for Ls ωr
Fig. 2.11(a) and 2.11(b) show that ZVS for S1 is lost at turn-on and it is worthwhile
to investigate whether it is possible to change the tank parameters to achieve desirable
performance. Figures 2.14(a) and 2.14(a) show the graphs of turn-off currents of S2
in the worst case (VPmin
V ) when Ls ωr is changed. It can be seen that at the minimum
bus voltage, ZVS is lost within a small range of Pin for all possible Ls ωr . From Fig.
2.14(a), it may seem that by increasing Ls ωr beyond 1.4 Ω, it is possible to achieve
ZVS, however, beyond 1.4 Ω at low input voltage and high power the inequality
(2.18) does not hold and the turn ratio has to be increased. However, if the turn ratio
increases, the resonant current increases and conduction loss increases. Thus there
is no benefit in increasing Ls ωr beyond 1.4 Ω. To increase the gain of the converter,
Ls ωr and subsequently Q can be reduced. The shortcoming of this method is that
with low Q, the harmonics of ires will be high and the assumption of the fundamental
approximation is not true anymore. As a result, when the circuit is implemented, it
can be sensitive to parameters and the analytical values may not be accurate enough.
Thus, Ls ωr should not be reduced excessively and it is recommended to keep it above
0.5 Ω.
2.4.9
Design Approach for ω
The parameter ω is another degree of freedom in the system that can be determined
to satisfy desired performance. Fig. 2.15(a) shows turn-off currents of S2 for different
ω at maximum and minimum points of the bus voltage. It can be observed that for
high enough values of ω, the turn-off current becomes negative. However, Fig. 2.15(b)
shows that increasing ω can increase the duty cycle, and it will become saturated for
CHAPTER 2. MICRO-INVERTER TOPOLOGY
56
(a)
(b)
Figure 2.14: Turn-off currents for S2 for different Ls ωr at (a) minimum points of the
bus voltage, (b) maximum points of the bus voltage
CHAPTER 2. MICRO-INVERTER TOPOLOGY
57
(a)
(b)
Figure 2.15: (a) Turn-off currents of S2 and (b)Duty cycle, for different ω at maximum
and minimum points of the bus voltage at minimum VP V
CHAPTER 2. MICRO-INVERTER TOPOLOGY
58
ω > 1.2. The reason is that at a higher frequency the gain of the resonant tank is
lower and a higher duty cycle is required to compensate. On the other hand, Fig. 2.16
DC
shows if the design parameters are selected to be Ls ωr = 0.7, N = 23, Vbus
= 230V, at
maximum VP V , the turn-off current of S2 is not negative anymore for all conditions.
In this design Ls ωr is reduced to increase the gain at higher frequency and gives more
room to increase ω to solve the turn-off current problem. If the proposed design
procedure is continued, it can be found that for Ls ωr = 0.4 there will exist a range of
1.23 < ω < 1.37 where all desired performance criteria are satisfied except for a very
small range of Pin < 15W at VPmax
where ZVS is lost. However, since at this power
V
level conduction losses are at a minimum, the switches can be designed to tolerate
only the switching losses. If higher Q is desired, a variable frequency control method
can be used.
2.4.10
Variable Frequency Control Method
Fig. 2.16 and 2.15(a) show that by increasing ω it is possible to achieve ZVS. The
figures show that to have ZVS at high input power it is better to have higher ω,
however a high value for ω saturates the duty cycle at low input voltage because of
the insufficient gain. As a result to satisfy both extreme conditions, ω can be changed
as a function of VP V . For example, for Ls ωr = 1 one possible solution is:
ω ref = 1.13 + (1.3 − 1.13)
VP V − VPmin
V
.
min
VPmax
−
V
V
PV
(2.26)
Fig. 2.17(a) shows turn-off current of S2 , which is negative for all conditions as
desired. Fig. 2.17(b) demonstrates duty cycle of S1 at the maximum point of the bus
voltage and it shows that with variable frequency control, the duty cycle is always less
than 0.5 and does not become saturated and thus ZVS is achieved for all conditions.
CHAPTER 2. MICRO-INVERTER TOPOLOGY
59
Figure 2.16: Turn-off currents of S2 at maximum and minimum points of the bus
voltage for different ω at maximum VP V
2.4.11
Variable Bus Voltage Control
The worst condition for the gain inequality in (2.18) is at minimum input voltage
and thus if VP V increases there is more room to increase the bus voltage without
violating (2.18). If the bus voltage increases, ires reduces, which in turn minimizes
the conduction losses in the resonant tank as well as in S1 and S2 . The minimum
min
bus voltage should always satisfies Vbus
> Vgmax . With the aforementioned variable
bus voltage strategy, the worst condition for this inequality happens at the minimum
input voltage and the maximum input power. This operating point determines the
o
minimum bus voltage (vbus
) in a variable bus control strategy. Using variable bus
CHAPTER 2. MICRO-INVERTER TOPOLOGY
60
(a)
(b)
Figure 2.17: (a) Turn-off currents of S2 and (b) Duty cycle at maximum and minimum
points of the bus voltage with variable ω control
CHAPTER 2. MICRO-INVERTER TOPOLOGY
61
Figure 2.18: The RMS value of ires at maximum and minimum points of the bus voltage with the variable bus voltage and variable frequency control method
voltage and variable frequency control strategies together we have:
ω ref = ωmin + ∆ω
VP V − VPmin
V
, and
min
VPmax
−
V
V
PV
ref
o
vbus
= vbus
+ Kvbus (VP V − VPmin
V ).
(2.27)
(2.28)
Fig. 2.18 shows the RMS value of ires at maximum and minimum points of the bus
voltage with the variable bus voltage and variable frequency control method. In this
o
design, parameters of ωmin = 1.13, ∆ω = 1.5 − 1.13, vbus
= 230V and Kvbus = 5 are
selected. Comparing Fig. 2.18 with Fig. 2.12(b) shows that unlike previous methods,
the RMS resonant current is no longer independent of VP V and it reduces at higher
input voltages.
CHAPTER 2. MICRO-INVERTER TOPOLOGY
62
Table 2.1: Simulation Parameters
Parameters
CP V
Cbus
Ls
Cs
fs
DC
Vbus
Grid voltage
Grid frequency
Turns ratio
PV MPP current
PV MPP voltage
2.5
Values
20 µF
40 µF
0.707 µH
4.42 µF
117 KHz
230 V
110 V
60 Hz
23
5 Amp
25 to 45 V
Simulation Results
Using the proposed design method described in the previous section, a 200W resonant
converter is designed for the PV application and is simulated using Power SIMulator
(PSIM) software. The schematics of the digitized system are presented in Figures B.1,
B.2 and B.3. The specification and parameters of the simulation circuits are shown
in Table 2.1.
Fig. 2.19 shows the bus voltage and input power at VP V =45V. It shows that the
bus voltage changes at twice the grid frequency while the input power extraction is
constant. The ripple on the input power is at resonant switching frequency and is at
most 3%.
Fig. 2.20(a) and 2.20(b) show the simulation results for gate-source and drainsource voltages of S1 and S2 for VP V =25V and 45V. It can be observed that ZVS
is achieved at both turn-on and turn-off instants. Simulation results for ires , vin ,vp
63
CHAPTER 2. MICRO-INVERTER TOPOLOGY
Figure 2.19: PSIM simulation results for bus voltage and input power at VP V =45V.
(a)
(b)
Figure 2.20: PSIM simulation results for switching actions to achieve ZVS at turn-on
and turn-off of S1 and S2 for (a) VP V =25V and (b) VP V =45V .
CHAPTER 2. MICRO-INVERTER TOPOLOGY
64
and vbus waveforms are shown in Fig. 2.21 at Pin =200W and VP V =45V. These
waveforms are captured at the maximum bus voltage. It can be observed that since
Q is not high the harmonic components of the resonant tank current are not small
and the current wave form is not sinusoidal. It is worth mentioning that the waveform
of vp also depends on characteristics of the transformer and also the snubber circuit
chosen for the rectifier circuit. Therefore, vp can be even more distorted than what is
shown in the graph and also from the ideal case used in the proposed design approach.
Thus, to achieve the best result it is recommended to fine-tune the result of the design
method in simulation and also in practice.
Figure 2.21: Simulation results for tank waveforms at Pin =200W and VP V =45V
CHAPTER 2. MICRO-INVERTER TOPOLOGY
2.6
65
Experimental Results
An experimental verification of the micro-inverter was carried out using an FPGA.
All controllers and timing circuits for signal conditioning and protection systems were
implemented in the VHDL programming language for FPGA. Figure 2.22 shows the
photovoltaic micro-inverter board for experimental verification. The board includes
all of the power circuit and the necessary hardware to implement the controllers
described in the thesis. The board has two ports; one port is for connection to PV
panel and the other port is for connection to the grid. Due to the complexity of
the controller structures proposed in the thesis it is more convenient to implement all
controller using digital approach. Details regarding problems in digitization procedure
is explained in section 5.12. Since the micro-inverter is connected to two active sources
of energy, i.e., PV and grid, any bug in the code would most probably make the whole
system unstable. This in turn might cause an over-voltage or over-current in the
system and could damage the power and driver circuits. To minimize this problem,
before the actual test of the system the VHDL code is tested on the power circuit
using simulation. The VHDL code can be simulated in ModelSim software, however
all the input signals to the system must be constructed with exact timings, which is
not straightforward. In this thesis the power circuit, signal conditioning circuitries
and data acquisitions are all simulated with very good accuracy in PSIM software,
as shown in Figures B.4, B.5 and B.6. The actual code is simulated accurately in
ModelSim software. The VHDL code for controllers is given in appendix C. Then
MATLAB can be used to interface the code and the rest of the circuit because both
programs can communicate with MATLAB. After debugging the code, the logic of the
program has been verified, however the actual time delays due to the implementation
CHAPTER 2. MICRO-INVERTER TOPOLOGY
66
Figure 2.22: Micro-inverter board
of the code or circuitries may not be accurate, specially when the controller structure
is complicated. For final verification all circuitries and codes are implemented in
practice and experimental results are provided.
The efficiency of the micro-inverter is measured at different input voltages and
power levels as shown in Table 2.2. It can be seen that the maximum efficiency
occurs around VP V =30V and half of the full power (100W).
Figure 2.23 shows the experimental results for switching actions of S1 and S2 at
VP V =30V for low and high power levels. It can be seen that when switch S2 is turned
off, VDS2 reaches 30V and then S1 is turned on, which translates to ZVS for S1 at
67
CHAPTER 2. MICRO-INVERTER TOPOLOGY
Table 2.2: Micro-inverter Efficiency
VP V (V)
41.4
41.0
40.8
41.8
31.1
31.3
31.6
31.5
Pin (W)
162
107
46
189
45
80
140
165
Pout (W)
135
91
38
155
38
69
120
141
η(%)
83
85
83
82
85
88
86
85
turn-on. Similarly it can be seen that ZVS is obtained at turn-on for low and high
power levels for both switches. Figure 2.24 shows the switching actions for VP V =45V
and it confirms obtaining ZVS for both low and high power levels.
For full power (200W) and highest input voltage (VP V =45V), the resonant tank
current, resonant tank capacitor voltage and transformer primary voltage are shown
in Fig. 2.25(a). Considering the 2A negative dc offset in the measurements for the
resonant tank current in the graph, it can be seen that when the resonant tank current
becomes positive, the primary voltage also becomes positive and they are in phase.
The graph only shows the ac part of the capacitor voltage. It can be observed in
Fig. 2.25(b) that the capacitor voltage has negative dc value that is blocking the dc
component of the input voltage to the resonant tank. The graph of ires for low power
exhibits more harmonics as discussed in the theoretical analysis.
CHAPTER 2. MICRO-INVERTER TOPOLOGY
68
(a)
(b)
Figure 2.23: Experimental results for switching actions to verify ZVS of S1 and S2
for VP V =30V and (a) IP V =2A and (b) IP V =6A
CHAPTER 2. MICRO-INVERTER TOPOLOGY
69
(a)
(b)
Figure 2.24: Experimental results for switching actions to verify ZVS of S1 and S2
for VP V =45V and (a) IP V =1.2A and (b) IP V =5A
CHAPTER 2. MICRO-INVERTER TOPOLOGY
70
(a)
(b)
Figure 2.25: Experimental results for resonant tank current, resonant tank capacitor voltage and transformer primary voltage at VP V =45V and (a) Pin
=200W , (b) Pin =50W
CHAPTER 2. MICRO-INVERTER TOPOLOGY
2.7
71
Summary
In this chapter a micro-inverter topology is proposed for PV systems. For the first
stage of the micro-inverter, an APWM series resonant converter is used, which provides isolation (obligated by North American codes and standards), voltage amplification, high power density and high efficiency. The principle of operation of an APWM
series resonant converter is explained and a steady state analysis of the converter is
also presented. It is shown that due to the special decoupling control method the
bus voltage at the output of the converter becomes oscillatory. It is demonstrated
that this oscillation, along with the variation of the irradiation levels (input power),
and ambient temperature (input voltage) affect converter currents and voltages and
design parameters. The constraints posed by these variations are analytically and
graphically presented. Variable frequency and variable bus voltage control methods
are proposed to extend the operating range of the converter to maintain zero voltage
switching at turn-on and to minimize the conduction losses for all conditions. Simulation and experimental results are provided to verify the proposed design method.
Chapter 3
Power Decoupling and PV Side
Control
3.1
Introduction
The instantaneous power in single-phase as well as unbalanced three-phase systems
contains double frequency oscillations. In applications where the input power generation is dc, the oscillation of the instantaneous power at the output may deviate the
input operating point from dc values, resulting in power losses. In such applications,
it is important to decouple power generation from power injection. The first section of
this chapter describes the power decoupling issue and proposes a new method to solve
this problem without introducing excessive passive components in micro-inverters.
In the second part of the chapter a large signal model of the resonant converter
is obtained by considering the nonlinear I-V characteristics of the PV and the nonlinear switching action of the resonant converter, . Furthermore, extended describing
functions and linearization methods are applied to derive the small signal model of
72
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
73
the resonant converter. Then this model is used to design a controller to stabilize the
system while obtaining perfect power decoupling.
3.2
Power Decoupling Issue
Fig. 3.1(a) shows a single phase converter connecting a PV module to a grid. The
output voltage is assumed to be sinusoidal, so that v(t) = Vm sin(ωt), and the output
current is assumed to be controlled and in-phase with the grid voltage, i.e., i(t) =
Im sin(ωt). As a result the output instantaneous power can be calculated as follows:
p(t) = i(t)v(t) = Vm sin(ωt)Im sin(ωt) = Vm Im sin2 (ωt) ⇒
(3.1)
V m Im
(1 − cos(2ωt)).
=
2
Equation (3.1) shows that instantaneous power in single phase systems consists
of two components, a dc part ( Vm2Im ) and an oscillatory part ( Vm2Im cos(2ωt)). Fig.
3.1(b) shows the output instantaneous power, voltage and current waveforms. If
the converter extracts exactly the maximum PV power, the input power Pin will be
only a dc component. Assuming a lossless conversion, to have a stable system the
input average power should be equal to the output average power or in other words,
Pin =
Vm Im
.
2
Since the maximum instantaneous power at the output is twice the input
average power, the extra power has to be provided by passive energy storage. When
such oscillations are transferred to the PV side, the system deviates from its optimum
operating point and power losses occurs.
The decoupling problem is conventionally resolved passively by utilizing large
electrolytic capacitors as shown in Fig. 3.2. Such a solution decreases the lifetime
and increases the volume, weight, and cost of the inverter [4, 5, 50]. Bulky capacitors
also result in the high maintenance expenses to replace the hardware after 7-8 years.
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
74
i
PV
Converter
Pin=DC
v
p(t)=Oscillatory
(a)
(b)
Figure 3.1: (a) A general block diagram for single-phase grid connected PV converter,
(b) Output current, voltage and instantaneous power waveforms
Another solution which avoids the electrolytic capacitor is to use an auxiliary circuit
that draws constant current from the input and generates a high dc voltage at the
middle stage to supply the pulsation required at the output [18, 50, 56]. However,
such solutions exhibit low efficiency and need complex hardware and control systems
for low power applications, which make the overall system inefficient and expensive.
The conventional approaches, as shown in Fig. 3.2, use a control system to regulate the “average” of the input voltage or current to achieve MPPT and to reach
sufficient amplification gain. Therefore, the decoupling is accomplished by either
passive elements or auxiliary power circuits. However, in the new proposed control
system the control objective is to force the input voltage or current to track the reference signal very tightly. As a result, the double frequency oscillations are displaced
and the input power generation can become very close to the optimum dc level.
It is important to note that the choice of control output plays an important role in
this method. For example, assume that the amplitude of the current of the resonant
tank is selected as the output of the controller. In this case any oscillation on the
75
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
IPV
Includes passive
components
Large Electrolytic
Capacitor Bank
VPV
PV
Voltage fed
DC
VDC
CPV4 CPV3 CPV2 CPV1
DC
Output
filter
CDC2 CDC1
DC
MPPT
Algorithm
Implemented by
Microprocessor
IPV
DSP
ref
VPV
Vgrid
AC
Gate
signals
Gate signal
VPV
igrid
Voltage
source
current mode
controller
Average
Duty cycle
Control
VDC
igrid
Vgrid
Figure 3.2: Conventional Approach Inverter Block Diagram
bus voltage will be reflected to the primary of the transformer and therefore the
transformer should provide the oscillations. As a result, the power oscillation has
to be supplied by the resonant capacitor or input capacitor because the resonant
inductor provides only constant power due to the controlled peak current. Hence,
the oscillations are reflected to the PV side if the bus capacitor is not large enough
to make the oscillations of the bus very small. By contrast, in the proposed method,
the oscillations on the bus create oscillations on the tank without affecting the input
operating point.
The power decoupling controller can be implemented using a hysteresis control
or PI controller with high bandwidth. The important key to reject the oscillations
from the input is the high bandwidth of the closed loop system. The bandwidth the
better the responses however, too high bandwidth creates noise problems. Although
the operating point of the converter changes at twice the grid frequency, the converter
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
76
should respond fast enough to reject the effect of this distortion from the PV side.
In this way, the high bandwidth of the system will eventually cause very low or zero
steady state error with fast tracking of the input reference point. As a result, the
input power decoupling is accomplished only by means of the control strategy and
the high switching frequency of the resonant converter as opposed to the methods
that use bulky passive elements or auxiliary circuits.
3.2.1
Implementation of the Power Decoupling Method
Fig. 3.3(a) illustrates the schematic diagram of a sample power circuit to implement
the decoupling strategy. Although the power circuit resembles the topology of a buck
converter, it can be a part of the series resonant converter if the diode is replaced
with a power switch or a buck type converter with a voltage source at the output. In
this topology a hysteresis controller utilizes the main switch to regulate the capacitor
voltage between upper and lower levels. The upper level, Vpvref , is obtained from the
MPPT algorithm. The lower level is calculated in such a way that under worst conditions (i.e., maximum input power) the switching frequency and the voltage ripple do
not exceed certain values, which are determined by the limits considered by designer
on the power loss due to these variations. When the input capacitor voltage exceeds
the upper level, the main switch is turned on, and the capacitor is discharged. The
switch remains on until the capacitor voltage hits the lower limit. Because of the I-V
characteristic of the PV, the level of the input voltage is proportional to the power
generation and thus, by controlling the input voltage the power fed to the circuit is
controlled. To limit the switching frequency, the lower limit is not taken as a constant
value. Instead it is a function of the desired frequency f d and the PV current level.
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
L
S
iPV
+
Vpv
77
iL
Vo
ref
1V
D
C1
ton toff
--
Vpv
MPPT
Algorithm
Vpvref
S
R
iPV
i pv
2 f d C1
SET
CLR
Q
Q
+
(a)
(b)
Figure 3.3: (a) First implementation of the decoupling control circuit, (b) PSIM simulation of the converter waveforms during one grid cycle
The lower limit can be found as follows:
∆Q = C1 ∆Vpv = ipv tof f ⇒ ∆Vpv =
ipv
2C1 f d
(3.2)
For parameters values C1 = 20µF, f d = 100KHz, and imax
= 8A , the PV voltage
pv
variation is ∆Vpv = 2V . It is clear from (3.2) that in obtaining a desired PV voltage
variation, there is a trade off between the switching frequency and the capacitor
value. Utilization factor is a parameter that indicates the loss due to the deviation
from the MPP, [4]. For example, calculations show that to reach 98% utilization ratio,
the voltage ripple should be less than ∆Vpv = 8.5%VpvM P P . Therefore, in the design
procedure the optimum voltage of the PV cell at the highest operating temperature
is selected for VpvM P P , which is the lowest possible PV output voltage. Based on this
value the ∆Vpv is calculated. If the parameters are chosen for the highest irradiation
level and temperature, the proposed control scheme satisfies ∆Vpv < 8.5%VpvM P P for all
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
78
conditions. In fact, according to (3.2), when the irradiation level decreases (decrease
of ipv ), the ∆Vpv also decreases which will guarantee the aforementioned condition for
all irradiation and temperature levels and thus, the circuit always operates below the
selected frequency f d .
With the help of any MPP tracking algorithm, this topology with its control strategy can always absorb the maximum power available from the PV cells independent
of the output voltage and current. The output voltage of this stage are controlled
and stipulated by the next stage. The extracted power from this stage is delivered
to the next stage as long as the output voltage and currents of the converter fall into
a stable operating point. For example, the power circuit shown in Fig. 3.3(a) has a
stable operating point as long as the output voltage of the converter is less than the
input voltage.
Fig. 3.3(b) illustrates the output power and current of the converter when a
voltage source (Vo = k + A sin ωt) is connected to the output. It can be observed
that when the output voltage increases the output current tends to decrease to feed
the constant input power to the output. As a result, the output voltage determines
the output current such that the average output power equals the extracted power
from the PV. Moreover, it can be seen that even with a relatively large variation of
the output voltage, the input power oscillation is within 5% of its dc value. This
topology can also be used with dc load. For instance, if a resistive load is connected
√
to the output, as long as the induced output voltage Vo = Pin Rload is less than the
input voltage, the output power will be constant for all loads. As a result, as opposed
to voltage source or current source concepts, using this simple control method the
converter becomes a controllable “power” source independent of the load.
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
3.3
79
Series Resonant Converter Control Method
The hysteresis control method described in Section 3.2.1 accomplishes the decoupling
task, however, it does have some disadvantages: (i) the uncontrollable switching
frequency of the converter can cause EMI problems, (ii) it is not possible to optimize
the magnetic design when the frequency changes widely. Although this problem
was addressed in Section 3.2.1, in practice with the presence of uncertainties and
disturbances, the theoretical calculations may not be accurate and the frequency
shift can be even larger than the prediction.
Another possible control method for decoupling is to use a conventional PWM
control with feedback of VP V or IP V that exhibits a fixed switching frequency. For
perfect decoupling the system should have high bandwidth. In this way any change
of the irradiation level or temperature or output power generation is compensated by
the controller without any effect on the input operating point. On the other hand,
the controller should not have any steady state error for tracking the input reference
point to be able to extract maximum available power from the PV panel. A proposed
control scheme based on this PWM strategy and which can satisfy these requirements
is shown in Fig. 3.4. The maximum power point tracking block receives the input
current and voltage information and generates the desired voltage reference (VPref
V ).
Two coefficients, ki and kp , are gains of PI controller and designed so that the system
is stable and has high bandwidth. The PI controller forces the input voltage to follow
the voltage reference generated by the MPPT block with zero steady state error.
To guarantee the stability and the desired performance of the system, the resonant
converter is modeled and small signal ac analysis is used to design the PI controller
coefficients.
80
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
is1
iPV
PV
CPV
+
vPV
_
is2
S1
S2
+
vCs _ ires
Ls +
vp
_
+ Cs
vin
_
igrid
io
T
DC+AC
D1 Cbus +
vbus
_
ref
vPV
+_
kp
+
+
APWM
Modulator
vbus
ki
iPV
vPV
vPV
vgrid
AC
Inverter
1:N D2
MPPT
Output
filter
Bus
Voltage
Controller
ref
igrid
ref
vbus
Frequency
Reference
Equation
ω sref
Carrier
Generator
Variable Frequency
Control Method
vPV
Bus voltage
Reference
Equation
Variable bus voltage
Control Method
Figure 3.4: Series resonant converter controller block diagrams
3.4
Large Signal Model of the APWM Series Resonant Converter
As it can be seen from Fig. 3.4 when switch S1 is on, the current of the resonant
tank flows through the switch. As a result, if the duty cycle of S1 as a function of
time is called D̂, the current of S1 will be equal to D̂ ires . This can be modeled as
a dependant current source as shown in Fig. 3.5. The input voltage of the tank, the
transformer primary voltage, the rectifier output current and the inverter current are
also modeled in a similar manner as shown in the large signal model shown in Fig.
3.5.
81
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
Cs
iPV
+
Ls
ires
vpv
+
Cin
vin= D vpv
iS1= D ires
vp=
io=
+
vbus
N
ires
+
N
vbus
sgn(ires)
iinv
Cbus
Figure 3.5: Large signal model of the first stage of the micro-inverter
The governing differential equations of the large signal model are:

dires


Ls
= vin − vCs − vp


dt




dvCs


= ires
 Cs
dt
dvpv


Cin
= ipv − D̂ires



dt



ires dv

bus

− iinv ,
=  Cbus
dt
N (3.3)
where D̂ is the switching function of S1 and iP V and vpv are related by the PV I-V
characteristic according to (A.1) that is rewritten here for ease of reference. It is
assumed that VT = Ans kT
, and thus
q
ipv
v pv
VT
= Iph − Irs e
−1 .
(3.4)
In (3.3) iinv is controlled by the next stage to control the average of the bus voltage.
As a result, if the dynamic equations of the bus voltage are to be derived, the whole
system dynamic for the next stage should be included in the analysis. However, for
the sake of simplicity it is assumed that Cbus is large enough so that the bus voltage
constant over a high frequency switching period. Therefore, the last equation in (3.3)
is eliminated from the ac analysis.
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
3.5
82
Small Signal Model
The set of equations in (3.3) are highly nonlinear. To derive a small signal model
(3.3) should be linearized. The simple State Space Averaging method is not applicable here, because the state variables of the resonant tank contain large and high
frequency variations. Extended describing functions are proposed in [57] for small signal modeling of resonant converters. In this method, first the nonlinear large signal
equations are derived, then the signals with large variations are approximated by fundamental harmonic components, i.e. dc, sine and cosine terms. Then, the harmonic
balance is applied to derive the state equations for the amplitude of the harmonic
components. These are slow varying states for which the standard analysis methods
are applicable. In the end, the nonlinear parts are linearized and small signal state
space equations are derived.
Fig. 2.2 shows the typical waveforms of the resonant converter. The resonant tank
variables can be approximated by fundamental and dc components with respect to
the time axis origin as shown in Fig. 2.2. However, due to unsymmetrical waveforms
the choice of origin at t=0 causes all equations to have both sine and cosine terms.
This makes the calculations extremely complicated. By referring to (2.12) it can be
observed that defining a new variable τ such that ωs τ = ωs t − πD0 , where D0 is the
steady state solution, leaves only cosine terms for vin and makes the equations much
easier to solve.
As discussed in Chapter 2, the steady state equations vary at double grid frequency, however the variations of 120Hz for small signal analysis can be assumed
to be dc. In other words, the operating point of the system varies at double grid
83
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
frequency, however the small signal analysis is performed with the assumption of perturbation of a constant operating point. With the new time origin the resonant tank
variables and vpv are:


cos

ires (τ ) = isin

res sin(ωs τ ) + ires cos(ωs τ )



sin
cos
vCs (τ ) = VCs + vCs
sin(ωs τ ) + vCs
cos(ωs τ )





sin
cos
 vpv (τ ) = VP V + vpv
sin(ωs τ ) + vpv
cos(ωs τ ).
Their time

dires





dt


dvCs

dt





 dvpv
dt
the dc and
(3.5)
derivatives are:
disin
dicos
res
= ( res − ωs icos
)
sin(ω
τ
)
+
(
+ ωs isin
s
res
res ) cos(ωs τ )
dt
dt
dv sin
dv cos
cos
sin
(3.6)
= ( Cs − ωs vCs
) sin(ωs τ ) + ( Cs + ωs vCs
) cos(ωs τ )
dt
dt
sin
cos
dvpv
dvpv
dVP V
cos
sin
=
+(
− ωs vpv
) sin(ωs τ ) + (
+ ωs vpv
) cos(ωs τ ).
dt
dt
dt
first harmonic components of the tank input voltage can be derived as:
vin = DVP V +
2VP V
sin(πD) cos(ωs τ ).
π
(3.7)
In a similar manner the fundamental approximation for D̂ires is derived as follows:
D̂ires =
icos
res
sin(πD)
π
sin
+ ires
(πD −
π
cos
+ ires
(πD +
π
sin(2πD)
) sin(ωs τ )
2
sin(2πD)
) cos(ωs τ ).
2
(3.8)
Using (2.9) and the large signal model, the fundamental approximation for the transformer primary voltage is derived:
vp =
vbus 4
N π
isin
res
p
sin
2
(ires ) +
2
(icos
res )
sin(ωs τ ) +
icos
res
p
sin
2
(ires ) +
2
(icos
res )
!
cos(ωs τ ) .
(3.9)
To find the fundamental approximation for ipv , first (3.4) has to be approximated by
Taylor’s series and then the last equation of (3.5) is used:
ipv = Iph −
Irs
Irs sin
Irs cos
VP V −
vpv sin(ωs τ ) −
v cos(ωs τ ).
VT
VT
VT pv
(3.10)
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
84
After the substitution of (3.5),(3.11),(3.7),(3.8), (3.9) and (3.10) into (3.3), the harmonic balance method yields:
 sin
sin
vCs
vbus 4
isin
dires

res
cos

p
=
ω
i
−
−

s res

sin
2
2

dt
L
N
πL
(ires ) + (icos
s
s

res )


cos


vCs
vbus 4
icos
dicos
2VP V

res
 res = −ωs isin
p
−
−
+
sin(πD)

res

sin
2
cos
2
dt
Ls
N πLs (ires ) + (ires )
πLs




sin
sin


 dvCs = ires + ω v cos

s Cs


Cs

 dtcos
dvCs
icos
res
sin
(3.11)
=
− ωs vCs


dt
C
s



sin

dvpv
isin
sin(2πD)
Irs sin

cos

= ωs vpv − res (πD −
)−
v



dt
πCin
2
VT Cin pv


cos


dvpv
icos
sin(2πD)
Irs cos

res
sin

=
−ω
v
−
(πD
+
)
−
v

s
pv

dt
πCin
2
VT Cin pv





dV
I
I
icos

 P V = ph − rs VP V − res sin(πD).
dt
Cin VT Cin
πCin
If the time derivatives are set to zero, steady state solutions are found. These solutions
match with the results of Chapter 2. In terms of new variables the steady state
solutions are:
sin
Ires
=
cos
Ires
=
sin
VCs
=
cos
VCs
=
Vpvsin =
Vpvcos =
VPref
=
V
VP sin β
Rac
VP cos β
Rac
VP sin β
Rac Cs ωs
VP cos β
−
Rac Cs ωs
VP sin β sin(2πD0 )
+ D0
Rac Cin ωs
2π
VP cos β sin(2πD0 )
− D0
Rac Cin ωs
2π
πVP
,
2 cos β sin(πD0 )
(3.12)
(3.13)
(3.14)
(3.15)
(3.16)
(3.17)
(3.18)
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
85
p
−1
2
2 + Z2
where cos β = Rac / Rac
tank , Ztank = (Ls ωs − (Cs ωs ) ), Rac = VP /(2Pin ) and
VP = 4vbus /(Nπ).
To derive linearized state space equations from (3.11), the state variable vector x
is defined as:
x = isin
res
icos
res
sin
vCs
cos
vCs
sin
vpv
cos
vpv
VP V
T
.
(3.19)
Assuming that D is the input of the nonlinear system defined by (3.11), the nonlinear
state space presentation is:
dx
= F(x, D),
dt
(3.20)
where F(x) = [y1 (x1 , · · · , x7 , D), · · · , y7 (x1 , · · · , x7 , D)]T . The linearization of such a
system is the first order term of its Taylor expansion around the steady state operating
point. Therefore, the linearized system can be written as:
!
x̃
dx̃
= JF (x0 , D0 ) ·
,
dt
D̃
(3.21)
where x̃ = x − x0 and D̃ are small signal variables, x0 and D0 are steady state
operating points and JF (x0 , D0 ) is the Jacobian of F(x, D) evaluated at x0 and D0 :




JF = 



∂y1
∂y1 ∂y1
···
∂x1
∂x7 ∂D 

..
..
.. 
..
.
.
.
.
. 

∂y7
∂y7 ∂y7 
···
∂x1
∂x7 ∂D
in the conventional form are:
The system state space equations

dx̃


= Ax̃ + B1 D̃ + B2 I˜ph
dt

 ỹ = Cx̃.
(3.22)
(3.23)
where A and B1 can be obtained from the Jacobian matrix JF = [A(7×7) |B1(7×1) ].
Two inputs are defined for the system, the duty cycle, D, and the PV current caused
86
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
by irradiation, Iph . The former is the input that regulates the output of the system,
y = VP V , and the latter is the disturbance to the system.
Applying this method to the nonlinear differential equations in (3.11) yields the
following matrix for A:
Rac cos2 β
Ztank cos2 β
−1
−
+ ωs
0

Ls
Ls
Ls

 Ztank cos2 β
Rac sin2 β
−1

−
ω
−
0
s

Ls
Ls
Ls


1

0
0
ωs

Cs


1

0
−ωs 0

C
s
 sin 2πD
D0
0

−
0
0
0

Cin
 2Cin π

sin 2πD0
D0

0
−
+
0
0

2Cin π
Cin


VP
0
−
0
0
2Cin VPref
cos
β
V

the vector for B1 is
"
2VPref
V cos πD0
0
Ls
0
0
0
0

0


VP cos β 


Ls VPref

V


0



,
0



0




0


Irs 
−
Cin VT
(3.24)
−1
0
0
0
0
0
0
−Irs
Cin VT
ωs
−ωs
−Irs
Cin VT
0
0
−2VP sin β
sin2 πD0
Cin Rac
−2VP cos β
···
cos2 πD0
Cin Rac
···
−VP cos β
cos πD0
Cin Rac
T
,(3.25)
−1 T
and finally B2 = [0 0 0 0 0 0 Cin
] and C = [0 0 0 0 0 0 1]T .
3.5.1
Elimination of the Internal Decoupled Dynamics
The state space equations derived in (3.23) have seven variables. As a result, with a
PI controller we have a system of eighth degree. Stability analysis of such a system is
complicated. By examining the matrix A, it can be observed that columns five and
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
87
six are zero except for the fifth and sixth variables. In other words, these two variables
do not affect the other variables and they present an internal decoupled dynamic of
the system. Since the internal decoupled dynamic is stable if the rest of the system
is stable, for the stability and performance analysis they can be eliminated from the
equations. Therefore, the new reduced order system equations are
 r
dx̃


= Ar x̃r + Br1 D̃ + Br2 I˜ph
dt

 ỹ = Cr x̃r ,
with the following new state vector:
h
x̃r = ĩsin
ĩcos
res
res
sin
ṽCs
cos
ṽCs
where
ṼP V
iT
,

Rac cos2 β
Ztank cos2 β
−1
+ ωs
0
0

 −
Ls
Ls
Ls


2
−1 
 Ztank cos2 β
R
sin
β
−1
V
cos
β
ac
P


− ωs
−
0


Ls
Ls
Ls
Ls VPref


V


1
,
Ar = 
0
0
ω
0
s


C

s



1


0
−ω
0
0
s


C
s


VP
Irs 

0
−
0
0
−
Cin VT
2Cin VPref
V cos β
"
#T
ref
2VP V cos πD0
−VP cos β
Br1 = 0
0 0
cos πD0 ,
Ls
Cin Rac
(3.26)
(3.27)

(3.28)
(3.29)
−1 T
Br2 = [ 0 0 0 0 Cin
] , and
(3.30)
Cr = [ 0 0 0 0 1]T .
(3.31)
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
3.6
88
Controller Design and Stability Analysis
As previously mentioned and shown in Fig. 3.4, a PI controller is used for the series
resonant converter. The state space presentation of the PI controller is:


 x̃˙ i = e
(3.32)

 D̃ = ki x̃i + kp e,
where e = y − VPref
V is the input to PI controller and D̃ is the output of the controller
that is also the input of the system (3.26). The closed loop augmented state equations
become
" # "
#" # "
#
" #
r
˙

0
C
x̃
1
0 ˜
x̃

i
i

=
−
ṼPref
+
Iph

V

 x̃˙ r
ki Br1 Ar + kp Br1 Cr x̃r
kp Br1
Br2
" #


x̃i


ỹ = [ 0 Cr ]
.


x̃r
(3.33)
Using (3.33) or (3.28) the closed loop characteristic equation is obtained. Then
the well known Routh’s stability criterion is applied and the stability region for two
unknown gains (kp and ki ) of the controller is obtained. Figures (3.6(a)) and (3.6(b))
show the stability regions for two cases where the PV voltage is kept constant and
the input power is varied from minimum to maximum and vice versa. For each graph
the region above the line is the stable region. It can be seen that the minimum power
and minimum voltage are the worst cases in Figures (3.6(a)) and (3.6(b)) respectively.
Closed loop poles of the system for different gains kp and ki at the worst case condition
are drawn in Figures 3.7(a) and 3.7(b). It can be seen that for low values of kp the
system can become unstable and for large value of kp when ki = 1000 the pole with
only real values gets very close to the imaginary axis making the system step response
too oscillatory. The root loci graphs also show that kp has a substantial effect on the
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
(a)
89
(b)
Figure 3.6: Stability regions of controllers’ gains for (a) constant PV voltage and
variable input power (b) constant input power and variable PV voltage
system response time.
The error feedback signal that is fed to the PI controller contains two ripples: the
high frequency ripple and the double grid frequency ripple (120Hz). Since this signal
is compared with triangular waveforms to generate PWM signals, the ripples on the
error signal should not saturate the comparator. As shown in Fig. 2.10, the 120Hz
ripple of the duty cycles (Dmax − Dmin ) is at a maximum at (vp =25V) and thus
the worst case from vbus ripple rejection occurs at minimum VP V where duty cycle is
large. By increasing kp the 120Hz ripple on VP V can be reduced to a desired value.
On the other hand, large kp creates large high frequency ripples that will add to the
low frequency ripple. Therefore, kp should be designed such that for minimum VP V
the controller signal does not become saturated because of the summation of ripples.
Although for a smaller kp a lower high frequency ripple are generated, Fig. 3.6(a)
shows that to keep the system stable the gain ki must also be small. As mentioned
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
(a)
(c)
90
(b)
(d)
Figure 3.7: Closed loop poles for different gains of controller 0.1 ≤ kp ≤ 1 (a) ki =
1000 (b) ki = 20000, and (c) duty cycle to output open loop poles and
(d) closed loop poles, for different Pin values shown by the same color and
different VP V
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
91
before, overly low ki and kp values can make the system step response too slow and
thus the decoupling may not be perfect. As a result there is a trade off between the
level of decoupling and the high switching ripple (the value of the input capacitor).
For 0.1 ≤ kp ≤ 1 Figures 3.7(a) and 3.7(b) show closed loop poles for ki = 1000 and
ki = 20000 respectively. It can be observed that for small values of kp the poles are
moving faster. In addition, it can be seen that for the larger value of ki shown in
Fig. 3.7(b), the system becomes stable for a larger kp . For the case that ki = 1000
and kp = 1 the system has a dominant real pole which determines the response of the
system and is much slower than the case with ki = 20000 and kp = 1.
The closed and open loop poles and consequently the system response change
with the operating point. For different Pin and VP V values, Fig. 3.7(c) and 3.7(d)
show the converter open loop poles and also closed loop poles. Graphs with the same
colour correspond to constant PV voltages and it can be seen that for all conditions
the system is stable. For the worst case, which is lowest PV voltage and lowest input
power the controller coefficients are designed as discussed and shown in Figures 3.7(a)
and 3.7(b).
The open loop bode diagram of the converter and the compensator are shown in
Fig. 3.8(a). Using this diagram it can be seen that the system is locally stable. By
generating similar bode plots for all operating points it is quite straightforward to
check that for all conditions the system is stable and has large bandwidth to perfomr
power decoupling. The resulting closed loop bode diagram of the first stage is shown
in Fig. 3.8(b). It can be seen that at lower frequencies the gain of the closed loop
is unity, which translates to perfect tracking with zero steady state error. Moreover,
the bandwidth of the closed loop is high enough that it provides fast disturbance
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
92
(a)
(b)
Figure 3.8: (a) Open loop Bode diagram of the converter in blue and the compensator
in green (b) Closed loop Bode of the first stage
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
93
rejection and also perfect power decoupling. Using simulations it can be found that
any values of kp between 0.5 and 0.8 and ki between 15000 and 20000 gives reasonable
responses.
3.7
Experimental Results
The oscillation on the bus voltage causes some double frequency harmonics on the
resonant tank current and capacitor voltage. This is due to the fact that the oscillation on the bus voltage is reflected on the primary voltage and by changing vin , the
proposed control technique tries only to keep the input voltage constant. As a result,
the double grid frequency oscillations are not removed from the tank as shown in Fig.
3.9. It can be observed that the input voltage does not contain any double frequency
harmonic component and perfect decoupling is achieved. Fig. 3.10(a) shows the ac
part of the PV voltage and bus voltage to confirm the perfect power decoupling. In
this graph the ripple on the PV voltage seems to be around 4-5 volt on 5ms time
scale which is a little bit more than 10% of the PV voltage. However, Fig. 3.10(b)
shows that the real ripple is only 2 volt peak to peak on 5µs time scale and in fact
the high frequency spikes are shown in Fig. 3.10(a).
3.8
Summary
This chapter first shows why power oscillations exist in single phase applications and
then presents a method to decouple output power oscillations from the input power
generation without using large electrolytic capacitors. This method increases the
lifetime and reduces the volume, weight, and cost of the inverter, making it suitable
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
94
Figure 3.9: Experimental results for resonant tank current, tank capacitor voltage,
PV voltage and bus voltage at VP V =45V and IP V =5A
for micro-inverter applications where the inverter is exposed to harsh conditions. It is
explained that the power oscillations are removed from the PV side and is displaced
on the bus capacitor. The idea of the proposed method is first developed by a simple
buck type converter and then applied to the APWM resonant converter.
To be able to use linear control tools, a model of the system is required. Therefore, by considering a nonlinear model of the PV and resonant converter a nonlinear
large signal model of the system is obtained. Then, the extended describing function
method and linearization technique are used to derive a small signal model of the
system. By the elimination of internal dynamics, the small signal model is simplified
and the controller parameters are designed such that the overall system becomes fast
and stable for the whole range of operating points.
CHAPTER 3. POWER DECOUPLING AND PV SIDE CONTROL
95
(a)
(b)
Figure 3.10: Experimental results for (a) PV voltage and bus voltage and (b) PV
voltage and current high frequency ripples, at VP V =45V and IP V =5A
Chapter 4
Synchronization and Bus Voltage
Control
The injection of active power is the main objective of PV systems. However, using a
grid-connected inverter and suitable control strategy, it is also possible to compensate
for the reactive power of a load connected to both the grid and inverter. The active
and reactive powers are controlled by shaping the magnitude and phase angle of the
output reference current. Moreover, to control the active power injected to the grid,
the output current must be synchronized with the grid voltage. A PLL acts as a filter
and generates a synchronizing signal that is in phase with the grid voltage regardless of
the presence of noise, disturbances or harmonics. In this chapter different approaches
for grid synchronization, bus voltage control and current reference generation are
introduced.
Since the proposed decoupling control method in Chapter 3 displaces the oscillations from the input to the bus voltage, the bus voltage is no longer a pure dc source.
As a result, using a simple modulation strategy, an inverter with an oscillatory bus
96
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
97
voltage generates non-sinusoidal output current. In the last section of this chapter,
a modified PWM strategy is introduced to prevent these oscillations from generating
harmonics at the output current.
4.1
General Block Diagram
Micro-inverters consist of two stages: the first stage extracts power from the PV
modules and the second stage injects the power into the grid. These stages are
connected to each other by the bus capacitor. The bus capacitor is charged by the
first stage and discharged by the second stage. If the rates of charge and discharge
are not controlled the bus voltage becomes unstable. Fig. 4.1 shows a block diagram
of the bus voltage control system. The design of the output current control loop is
explained in detail in Chapter 5.
If only active power injection is desired, the output current reference (iref ) should
be in phase with the grid voltage, where i∗ref is obtained by feeding the grid voltage
to a PLL. Since the grid voltage is uncontrollable, the amplitude of igrid controls both
the amount of active power injected into the grid and the discharge of the capacitor
vgrid
Synchronization
and output current
reference generator
*
iref
iref
∏
ref
Vbus
+
PI
Output
current
controller
+
To PWM
modulator and
power circuit
igrid
vbus
Figure 4.1: Inverter side control and synchronization block diagram
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
98
bus voltage. In other words, if the amplitude of iref is controlled such that the bus
voltage is kept constant, the power injection into the grid becomes equal to the power
extraction from the PV module. This is simply done by the PI controller shown in
Fig. 4.1.
Different possibilities for synchronization techniques and bus voltage control are
discussed in the next sections.
4.2
Synchronization With the Grid Voltage
Due to the presence of noise, disturbance and harmonics, the grid voltage cannot
be used directly as a synchronizing signal. A PLL is a nonlinear adaptive filter that
can extract the fundamental component of the grid voltage without any phase error.
Moreover, the PLL is able to accommodate frequency changes in the input. These
tasks are not easily achievable by linear and simple filtering techniques.
The output of the synchronization block is used to generate the reference for the
output current control loop. Therefore, if there is any distortion in this signal, the
quality of the output current will be degraded, that is highly undesirable.
Fig. 4.2(a) shows the structure of a standard PLL. The input signal is denoted
by vgrid . The loop consists of a Low Pass Filter (LPF),a Voltage-Controlled Oscillator
(VCO) and a multiplier. The input signal is multiplied by the VCO’s output signal, the
output of the multiplier is passed through the LPF and the result is input to the VCO.
One of the outputs of the VCO is a signal that is orthogonal to the input and it is this
signal that is multiplied by the input resulting in low frequency and double frequency
signals. The LPF filters out the double frequency signal and generates an error signal
that is proportional to the phase difference between the input and the VCO output.
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
Sync
signal
Sin
vgrid
99
ω̂g
LPF
∏
Cos
+
+
ωo
ϕ̂ v
VCO
(a)
vgrid
e
+
µ
∏
v̂grid
Vˆgrid
A
1
∏
Sync signal
Sin
Cos
ω̂g
∏
µ2
B
+
+
ωo
ϕ̂ v
(b)
Figure 4.2: (a) Standard Phase Locked Loop (PLL) (b) Enhance Phased Locked Loop
(EPLL)
Since the LPF is not ideal, the double frequency exists in the loop and generates a
phase error in single phase applications. To overcome this problem, there are methods
that generate a phase-shifted version of the signal and apply dq transformation to
a single-phase system [58–60]. Those methods are, however, either complicated to
adjust/implement or suffer from errors in changing and noisy conditions.
Another approach is the Enhanced Phase Locked Loop (EPLL) that is introduced
in [61, 62] and is shown in Fig. 4.2(b). In this structure it is the error signal, not the
signal itself that is multiplied by the orthogonal signal to generate B, so the double
frequency is canceled and only the frequency error is fed into the loop. By tuning the
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
100
gain µ2 the phase error can be reduced as desired. Moreover, if the input frequency
variation is high, the gain µ2 can be substituted by a PI controller to achieve zero
steady state phase error.
In this structure the outer loop estimates the amplitude of the input signal. It
is shown in [61, 62] that for steady state operation when the phase is estimated,
the signal A becomes proportional to the error of the input amplitude. Due to the
integrator at the output of the gain µ1 , the signal v̂grid becomes equal to the input
signal in the steady state condition. Therefore, because of the additional loop in the
structure, the EPLL avoids the harmful double-frequency ripples that are the main
shortcoming of conventional single-phase PLL systems.
The EPLL provides an accurate reference for synchronization even in the shortterm absence of the input signal. This is a desirable feature in cases where there are
short interruptions in the measurement system and if there is outage in the system.
Figures 4.3(a) and 4.3(b) contrast the performance of an EPLL and a conventional
PLL give an input which is a noisy sinusoidal signal with changing magnitude that
vanishes at t=0.09s. The synchronization signal of the EPLL is accurate but that of
the conventional PLL has large double frequency ripples and has large offset when
the input signal vanishes. When the input signal is absent, the output of the EPLL
also has a tiny offset in the phase but the extent of this offset can be controlled by
compromising the amplitude estimation feature. The EPLL is also able to estimate
the amplitude of its input signal, another feature that can be used in the reactive
power control loop.
Similar to any other system, EPLL has dynamic in its structure and thus it has
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
101
(a)
(b)
Figure 4.3: Standard PLL (in green) and EPLL (in blue) (a) outputs versus input
signals and (b) output phase errors in the presence of input with noise
and the absence of input
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
102
to pass through transients to reach a steady state condition. The experimental waveform showing this transient is displayed in Fig. 4.4. Since the EPLL provides the
reference signal, at the startup of the system these transients may cause some undesired overshoot or undershoot in the output current. To avoid this, the startup of the
system is designed to have two phases: in first phase the PLL and protection systems
are powered up and then the second phase starts when 20 cycles of the grid voltage
have passed and everything has reached the steady state.
4.3
Control Loop Based on Instantaneous Power
Control
This section presents a new method to control the flow of active and reactive powers in
a single phase grid-connected PV system. The method is based on the instantaneous
grid voltage and current waveforms and it appropriately shapes the instantaneous
power rather than active and reactive powers. In this method there is no need to
measure active and reactive powers individually and it is simpler than conventional
methods from FPGA implementation point of view. Nonlinear equations are derived
based on minimizing the error between the actual instantaneous power and its reference value. The nonlinear controller generates the reference signal for the output
injected current. It is worth mentioning that the proposed method in this section is
not limited to micro-inverter applications and can be utilized for any grid-connected
Distributed Generation (DG) system.
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
103
Figure 4.4: Experimental waveform showing the transients of EPLL at the startup
4.3.1
Instantaneous Power Control
The grid voltage at the point of coupling is available and denoted by vgrid and the
injected current is igrid . The objective is to control the current to ensure appropriate
injection of instantaneous power to the grid. The power is conveniently characterized
by its active and reactive components denoted by P and Q. In a sinusoidal situation
where vgrid (t) = Vgrid sin(ϕv ) and igrid (t) = Igrid sin(ϕi ), the instantaneous power is
p(t) = vgrid (t)igrid (t)
= 12 Vgrid Igrid cos ϕ[1 − cos(2ϕv )] − 12 Vgrid Igrid sin ϕ sin(2ϕv ) ,
= P [1 − cos(2ϕv )] − Q sin(2ϕv )
(4.1)
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
104
where ϕ = ϕv − ϕi , P = 12 Vgrid Igrid cos ϕ and Q = 12 Vgrid Igrid sin ϕ. Assume that the
ref
commands for active and reactive powers are denoted by Pout
and Qref
out , respectively.
Then if ϕ̂v is an estimation of the grid voltage total phase angle, then ϕ̂ = ϕ̂v − ϕ̂i
and the command for the instantaneous power is given by
ref
ref
pref
out (t) = Pout [1 − cos(2ϕ̂v )] − Qout sin(2ϕ̂v ).
Define the cost function
i2 1 h
i2
1 h ref
J[igrid (t)] =
pout (t) − p(t) =
pref
(t)
−
v
(t)
î
(t)
,
grid
grid
2
2 out
(4.2)
(4.3)
which is the instantaneous square error between the actual power and the reference
power. The objective as stated above can now be translated into finding an appropriate current igrid that minimizes J[îgrid (t)]. To address a solution to this problem,
Rt
the current is written as îgrid (t) = Iˆgrid sin(ϕ̂i ), where ϕ̂i = 0 ω̂g (τ )dτ − ϕ̂ in which
ω̂g is the estimation of the grid frequency. The voltage signal vgrid (t) = Vgrid sin(ϕv )
Rt
is taken as the reference such that ϕv = 0 ωg (τ )dτ . The cost function will then
be a function of the smooth unknown variables θ = (Iˆgrid , ϕ̂). The gradient descent
method is used to arrive at equations governing variations of these unknown variables
such that the cost function is minimized [63]. The gradient descent method is also
used to derive the enhanced phase-locked loop (EPLL) equations [61,62]. The general
expression is
θ̇ = −µ
∂J(θ)
,
∂θ
(4.4)
in which µ is a positive-definite 2×2 matrix. Assuming a diagonal structure as µ =
diag{µ1 , µ2 }, the resultant equations can be summarized as


 Iˆ˙grid (t) = µ1 e(t)vgrid (t) sin(ϕ̂i )


ϕ̂˙ i (t) = µ2 e(t)vgrid (t) cos(ϕ̂i ) + ω̂g ,
(4.5)
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
105
ˆ
where e(t) = pref
out (t) − p(t). Equation set (4.5) shows how variables Igrid and ϕ̂i
must be changed to ensure minimum error between the actual power and the desired
power. There still remain two issues to be addressed: (i) the instantaneous power
ref
reference pref
out must be synthesized from the active and reactive reference values Pout
and Qref
out and (ii) the system frequency ω̂g must be available (assuming that it can
have variations from the nominal value). The instantaneous power reference can be
synthesized from (4.2) if the voltage phase-angle ϕ̂v is available. To address both of
these issues, an EPLL can be employed on the voltage signal to estimate the phaseangle and frequency. Such an EPLL will also provide an estimate of the voltage
magnitude which is not being used in the context of the control application discussed
here. It can, however, be used for calculation of p(t) and the reactive power. The most
important advantage of the EPLL in this context is its ability to eliminate the double
frequency harmonics in single phase applications which makes it specifically attractive
for grid-connected single-phase applications. Similar to the method discussed above,
the equations governing the EPLL can be derived as follows:


˙

V̂grid (t) = µ3 ev (t) sin(ϕ̂v )




∆ω̂˙ g (t) = µ4 ev (t) cos(ϕ̂v )





 ϕ̂˙ v (t) = µ4 µ5 ev (t) cos(ϕ̂v ) + ω̂g = µ5 ∆ω̂˙ g + ω̂g ,
(4.6)
where ev (t) = vgrid (t) − V̂grid sin(ϕ̂v ), ∆ω̂g = ω̂g − ω0 , ω0 is the nominal value of the
grid angular frequency and µ3 to µ5 are real positive numbers. If ωg is assumed to
have slow and small variations from its nominal value, it is not necessary to implement
the second equation of (4.6) as shown in Fig. 4.2(b).
The overall control structure consists of the dynamics represented by (4.5) and
(4.6) whose block diagram is shown in Fig. 4.5. The EPLL estimates ϕv and ωg from
Qout
ref
ref
Pout
vgrid
EPLL
∏
∏
1
µ2
µ
+
+
∏
Current
Controller
∏
igrid
ϕ̂i
Cos
p(t)
∏
Iˆgrid
ω̂g
v̂ grid
+
e
Sin
ref
pout (t)
ϕ̂ v
Instantaneous
Power
Calculator
Current reference generator
Inverter
igrid
Output
Filter
vgrid
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
106
Figure 4.5: Block diagram of the proposed controller within the entire loop connecting
the PV to the grid through the converter
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
107
the measured voltage signal; a block diagram of the EPLL is shown in Fig. 4.2(b).
The complexity of the proposed controller is at the level of existing techniques with
the added advantage of flexible and independent control over both active and reactive
powers. In this structure there is no need to measure the active and reactive powers
separately as all of the calculations are based on instantaneous values. The proposed
controller shown in Fig. 4.5 has a structure suitable for digital implementation. The
EPLL and the Current Reference Generator have basically the same structure. This
serves as an advantage in sequential digital circuit implementations in FPGA because
once the EPLL structure is implemented, the same hardware can be used for the
current reference generator in a simple finite-state machine design.
4.3.2
Stability Analysis of the Proposed System
The proposed current reference generator consists of the EPLL – characterized by
the equations in (4.6) – which extracts the voltage phase/frequency and the current
estimator – characterized by equations (4.5) – which generates the current reference.
The whole system can be rewritten as

˙


Iˆgrid (t) = µ1 e(t)vgrid (t) sin(ϕ̂i )







ϕ̂˙ i (t) = µ2 e(t)vgrid (t) cos(ϕ̂i ) + ∆ω̂g + ω0




˙
V̂grid (t) = µ3 ev (t) sin(ϕ̂v )






∆ω̂˙ g (t) = µ4 ev (t) cos(ϕ̂v )






 ϕ̂˙ (t) = µ µ e (t) cos(ϕ̂ ) + ∆ω̂ + ω .
v
4 5 v
v
g
0
(4.7)
These equations constitute the controller that is placed within the loop shown in
Fig. 4.5. The controller provides the reference signal for the VSI. It is assumed
that the VSI is equipped with a fast and accurate current control loop which can
108
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
ensure rapid generation of whatever reference current is commanded by the nonlinear
controller. Design of such a current controller is discussed in Chapter 5.
A stability analysis for the closed loop system is presented in this section based
on the concept of linearization. Assume vgrid (t) = Vgrid sin(ϕv ) is the signal applied
to the system. Denote the EPLL output signal as v̂grid (t) = V̂grid sin(ϕ̂v ). Then
the voltage error is ev = Vgrid sin(ϕv ) − V̂grid sin(ϕ̂v ). Substituting ev in (4.7) and
expanding the trigonometric terms, we get

1

˙

V̂grid = µ3 (Vgrid cosβ − V̂grid )



2



1


∆ω̂˙ g = − µ4 Vgrid sinβ



2



1



β̇ = ∆ω̂g − µ4 µ5 Vgrid sinβ


2 "



ref

 ˆ˙
1
Pout
ref


 Igrid = 2 µ1 Vgrid Pout cosα + 2 cos(2β + α) · · ·
#

ref

ˆ
ˆ

Q
V
I
V
I
grid grid
grid grid


−
cos(2α)
· · · + out sin(2β + α) −


2
2
4



"


ref


1
Pout
ref


α̇
=
−
µ
V
P
sinα
+
sin(2β + α) · · ·
2 grid

out

2
2



#


ref

ˆ

Q
V
I
grid grid


· · · − out cos(2β + α) −
sin(2α) − ∆ω̂g ,


2
4
(4.8)
where the new variables α and β are defined as follows
α = ϕv − ϕ̂i ,
β = ϕ̂v − ϕv .
The equation set (4.8) has an equilibrium point at
(V̂ , ∆ω̂g , β, Iˆgrid, α) = (Vgrid , 0, 0, I0, αo ),
where Io is the ideal current magnitude and αo is the ideal phase displacement between
ref
the voltage and current waveforms (determined by the values of Pout
and Qref
out ).
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
109
It is worth mentioning that the equation set (4.8) contains simplified versions of
the actual equations. The actual equations have double and/or fourth order frequency
components that vanish as the system approaches its equilibrium point, since the high
frequency terms become zero as the system tends to its steady-state condition. For
example, the proof for the third equation of (4.7) is given below. Similar lines of
calculation and reasoning can be repeated for the other equations.
˙
V̂grid (t) = µ3 ev (t) sin(ϕ̂v ) = µ3 (Vgrid sin(ϕv ) − V̂grid sin(ϕ̂v )) sin(ϕ̂v )
= 21 µ3 (Vgrid cosβ − V̂grid ) +
µ3
[V̂grid cos(2ϕ̂v )
2
− Vgrid cos(ϕ̂v + ϕv )]
The term V̂grid cos(2ϕ̂v )−Vgrid cos(ϕ̂v +ϕv ) goes to zero as the estimated magnitude
and angle (V̂grid and ϕ̂v ) tend to their actual values (Vgrid and ϕv ). This fact shows
that the proposed control prevents higher order frequency ripples in its responses in
the steady-state condition.
The equation set (4.8) is nonlinear. A thorough analysis must resort to nonlinear
techniques to address the stability of such a system. Here, a linearization approach
is adopted to show the local stability of the equilibrium point of this system. The
Jacobian linearization matrix of this system is

−1µ
0
0
0
0
 2 3

 0
0
− 12 µ4 Vgrid
0
0


A=
1 − 12 µ4 µ5 Vgrid 0
0
 0


 0
0
0
A44 A45

2
0
−1 − 14 µ2 Vgrid
Io A54 A55
where






,





1
1
2
2
A44 = − µ1 Vgrid
(2 + cos2αo ), A45 = µ1 Vgrid
Io sin2αo
8
8
A54 =
1
1
2
2
µ2 Vgrid
sin2αo , and A55 = − µ2 Vgrid
Io (1 + 2 sin2 αo ).
8
8
(4.9)
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
110
Eigenvalues of the linearized matrix A determine the local stability of the system.
This matrix has a block diagonal structure which shows that the system is decoupled into two subsystems. The first subsystem is the EPLL whose eigenvalues are
determined by the matrix






− 12 µ3
0
0
0
0
− 12 µ4 Vgrid
0
1 − 12 µ4 µ5 Vgrid



,


and the second subsystem is characterized by the matrix


 A44 A45 

.
A54 A55
Eigenvalues of the first subsystem are λ1 = − 12 µ3 and two others, which are the
roots of the following second-order polynomial equation
1
1
λ2 + µ4 µ5 Vgrid λ + µ4 Vgrid = 0.
2
2
(4.10)
Eigenvalues of the second subsystem are specified by the roots of the equation
λ2 +
2
Vgrid
3
2
[µ1 (2 + cos2αo ) + µ2 Io (2 − cos2αo )]λ + µ1 µ2 Vgrid
Io = 0.
8
64
(4.11)
The requirements of the stability of a second-order polynomial and the above discussion show that the necessary and sufficient conditions for the local stability of
the system is that all five design parameters µ1 to µ5 are positive. The next section
examines how to design these parameters to obtain desired performance.
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
4.4
111
Design Guidelines
Performance of the proposed system is controlled by five parameters µ1 to µ5 . This
section presents guidelines to design these parameters to achieve a desired performance. The linear stability analysis shows that the overall system is linearly decomposed into the three decoupled subsystems described below.
• Subsystem I is specified by the first row of matrix A in (4.9) which has an
eigenvalue of λ1 = − 12 µ3 . This means that the voltage magnitude dynamics
are controlled solely by µ3 . A value of µ3 = 200, for example, corresponds to a
time-constant of 10 ms which is a settling time of about 40 ms (equivalent to
two cycles of 50 Hz or about 2.5 cycles of the 60 Hz system).
• Subsystem II is characterized by the second and the third rows of matrix A
and its eigenvalues are determined from (4.10). This shows that the voltage
phase-angle and frequency dynamics are coupled. The two parameters µ4 and
µ5 must be properly designed to yield desired performance for this subsystem.
We use the concept of root-locus to design these system parameters. Figure 4.6
shows the locus of variation for the roots of (4.10) when parameters µ4 and
µ5 vary over a specified range. This range is defined as {(µ4 , µ5 ) ∈ ([1000 −
7000], [0.01 − 0.07])} which is a rectangle. Figure 4.6(a) shows the case where
µ4 is fixed at 4000 and µ5 varies from 0.01 to 0.07. The roots start from close
to the imaginary axis and move towards the left. They meet at a point on
the real axis and then separate. Figure 4.6(b) shows that more or less the
same behaviour is observed when µ5 is fixed and µ4 increases in the range. To
provide a more complete picture of the locus, two more graphs are provided
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
112
Figure 4.6: Root-locus of (4.10) when: (a) µ4 = 4000 and µ5 varies from 0.01 to
0.07 (b) µ5 = 0.04 and µ4 varies from 1000 to 7000 (c) µ4 varies from
1000 to 4000 and µ5 = 0.00001µ4 (d) µ4 varies from 1000 to 4000 and
µ5 = 0.08 − 0.00001µ4
which address nearly the whole range of parameter values. Figure 4.6(c) shows
the locus when the variation is made along the rising diagonal of the rectangle.
This also proves that increasing µ4 and µ5 increases the speed of the system.
Figure 4.6(d) shows the root-locus when the parameters vary along the falling
diagonal of the rectangle. This plot shows that once µ5 becomes smaller, the
eigenvalues move towards the imaginary axis and the responses become more
oscillatory.
• Subsystem III is governed by the fourth and fifth rows of matrix A whose
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
113
Figure 4.7: Root-locus of (4.11) when: (a) µ1 varies from 0 to 1000 and µ2 = 500 (b)
µ2 varies from 0 to 1000 and µ1 = 500 (c) µ1 varies from 0 to 1000 and
µ2 = µ1 (d) µ1 varies from 0 to 1000 and µ2 = 1000 − µ1
characteristic equation is shown by (4.11). The root-locus plots of this subsystem are shown in Fig. 4.7 for the range of parameters given by the rectangle
{(µ1 , µ2 ) ∈ ([0 − 1000], [0 − 1000])}. Figure 4.7(a) shows the case where µ2 is
fixed at 500 and µ1 increases over the range. Both eigenvalues remain real and
move towards the left. This indicates not only more stable but at the same
time faster responses. In Fig. 4.7(b), µ1 is fixed at 500 and µ2 increases over
the range. This shows a similar behaviour to the part (a). When the parameters are increased along the rising diagonal of the rectangle, the root locus is
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
114
shown in Fig. 4.7(c). This also proves that increasing both parameters generates faster responses. Finally, the root-locus shown in Fig. 4.7(d) corresponds to
the case where the parameters vary along the falling diagonal of the rectangle.
The graphs conclude that a setting of µ1 = 500 and µ2 = 1000 corresponds to
eigenvalues of -120 and -200. Such eigenvalues are appropriate for a transient
and steady-state performance. It is worth noting that further increasing µ1
and/or µ2 moves eigenvalues too far from the real axis. This generates very
fast responses but causes the performance to be more sensitive to noise and
distortions.
4.4.1
Simulation Results
This section presents simulation results which confirm the desired performance of
the proposed controller. It is assumed that the converter can inject ideal sinusoidal
current into the grid which is modeled by an ideal voltage source. Nonlinear controller
gains are set using the methods discussed in Section 4.4. The selected parameter
values for simulations are µ1 = 300, µ2 = 1000, µ3 = 200, µ4 = 4000 and µ5 = 0.04.
Figure 4.8 shows how the step commands in the active and reactive references are
followed by the system. A command of one pu active power at t=0.1 and a command
of 0.5 pu VAR at t=0.2 are applied to the system as shown in Fig. 4.8(a). The grid
voltage and current are shown in Fig. 4.8(b). It is observed that the current has a
magnitude of 2 and is in phase with the voltage during the time interval [0.1, 0.2]
s. This shows a one pu active power and zero reactive power. For the time interval
after 0.2, the current magnitude increases and a phase shift is introduced to generate
0.5 pu VAR of the reactive power. The error in the instantaneous power is shown
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
115
in Fig. 4.8(c), which shows the very fast and accurate performance of the system.
Notice that the transient in this plot do not show excessive overshoot in the response
due to the delay of the whole system.
To test the system response to grid voltage variation while the system is operating
at Pref = 1 and Qref = 0.5, the grid voltage undergoes a short term fault which
generates a 50% voltage sag during the time interval [0.3, 0.4] s. The proposed
system adaptively adjusts the current to ensure that the power injection remains
unchanged. The grid voltage and the generated current are shown in Fig. 4.9(a), and
the instantaneous power error is shown in Fig. 4.9(b). The system settles in about
two cycles and the responses have no overshoot.
The proposed technique is also adaptive with respect to possible grid frequency
variations. Figure 4.10 shows the simulation results when a drop from 60 Hz to
50Hz occurs at t=0.5 s. The grid voltage and current signals are shown in part (a),
the instantaneous power error in part (b) and the estimated frequency in part (c).
The system has adjusted the operating frequency and the injected power remains
unchanged in the steady-state. Large frequency variations are not allowed in DG
systems and this simulation only addresses an extreme scenario.
The proposed technique is also highly immune with respect to grid voltage distortions and noise. Figure 4.11 shows a scenario in which the grid voltage undergoes
addition of 20% of the fifth harmonic at t=0.7 s and then a white noise with variance
0.01 is also added at t=0.8 s. The grid current is shown in part (b) and is highly
sinusoidal despite the extreme pollution which is present at the voltage terminals.
The proposed algorithm in this section controls the instantaneous power as generally formulated by (4.1). Thus, in situations where the grid voltage is distorted and/or
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
116
Figure 4.8: Performance of the proposed system in tracking active and reactive power
commands: (a) active and reactive commands in pu (b) grid voltage and
current in pu (c) instantaneous power error in pu
noisy, the grid voltage waveform cannot be used to generate the instantaneous power.
In such cases, the fundamental component of the grid voltage must be used instead
of the grid voltage. This signal is shown by v̂grid in Fig. 4.5 and is available from the
EPLL configuration as shown in Fig. 4.2(b).
4.5
Bus Voltage Control
The control objectives in grid-connected PV systems are (i) injection of the active
power absorbed from the primary source to the grid, (ii) maintaining the dc component of the bus voltage and (iii) providing control over reactive power exchange.
Existing methods are based on designing two control loops for bus voltage and for
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
117
Figure 4.9: Performance of the proposed system against the grid voltage variations:
(a) grid voltage and current in pu (b) instantaneous power error in pu
reactive power control [64]. The differential equations governing the system are nonlinear and thus trial and errors or linearization methods are often used to design the
controllers. Unlike the conventional methods, the method proposed in this section is
based on using an energy state variable, which makes the equations linear for all operating points. Usage of bus energy as a control variable rather than the bus voltage
has two advantages: it facilitates the design of a set of parameters that ensure global
stability, and because the bus energy has only double-frequency ripples while the bus
voltage has double-frequency and also higher-order ripples that results in a simpler
design of the bus voltage control loop.
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
118
Figure 4.10: Performance of the system against grid frequency variations: (a) grid
voltage and current in pu (b) instantaneous power error in pu (c) estimated frequency in Hz
Figure 4.11: Performance of the proposed system against grid voltage harmonics and
noise: (a) grid voltage in pu (b) grid current in pu
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
iinv
Inverter
Cbus
pin(t)
pinv(t)
igrid
L1
vinv
pout(t)
119
L2
vgrid
C
pgrid(t)
Figure 4.12: Block diagram of a single-phase grid-connected inverter system using
LCL filter
4.5.1
System Equations and Control Objectives
Figure 4.12 shows the block diagram of a single-phase grid-connected PV system.
The power pin shows the instantaneous power which is absorbed from the primary
source. This source can be the first stage in a micro-inverter or from a renewable
energy source such as wind or PV panel. The inverter output voltage and current are
denoted by vinv and iinv and the grid voltage is vgrid . The inverter is connected to
the grid through an LCL filter that attenuates the switching harmonics and provides
smooth current to the grid. With reference to Fig. 4.12, the grid side of the inverter
can be described as:

diinv


= vinv − vc
L1


dt


dvc
(4.12)
C
= iinv − igrid

dt




 L digrid = v − v .
2
c
grid
dt
The power balance equation can be used to derive an equation for the bus voltage
vbus as follows. In this section the inverter switching losses are neglected. Even
if those losses are not negligible, this assumption does not invalidate the analysis
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
120
since the final control methodology treats pin as a disturbance signal and the system
performance does not depend on its actual value. As a result it is assumed that pinv
(t)=pout (t), so
Cbus vbus
dvbus
= pin (t) − pinv (t).
dt
(4.13)
In (4.13), pinv (t) denotes the inverter instantaneous output power given by
pinv = vinv iinv = pLCL + pgrid ,
(4.14)
where pLCL and pgrid stand for the instantaneous power of the LCL filter and the
instantaneous injected power to the grid respectively. Using (4.12), it can be shown
that
1 di2
1 dv 2 1 di2grid
pLCL = L1 inv + C c + L2
.
2
dt
2 dt
2
dt
(4.15)
Thus, (4.13) can be written as
dvbus
1 di2inv 1 dvc2 1 di2grid
Cbus vbus
= pin − L1
− C
− L2
− vgrid igrid .
dt
2
dt
2 dt
2
dt
(4.16)
Equations (4.12) and (4.16) describe variations of the system state variables
[iinv , vc , igrid , vbus ].
The equations are apparently nonlinear in terms of these state variables. However,
2
if an energy variable, defined by Ebus = 12 Cbus vbus
(t), is used, the equation becomes
linear with respect to Ebus since
dEbus
= pin − pLCL − vgrid igrid .
dt
(4.17)
Assuming that the output current controller is fast enough to make grid current
and voltage in-phase, we have vgrid (t) = Vgrid sin(ωg t) and igrid (t) = Igrid sin(ωg t).
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
121
Therefore, using equations (4.15) and (4.12) the inverter output power is derived as
pout (t)
1
1
2
L1 ωg Iinv
sin(2ωg t + 2ϕiinv ) + Cωg Vc2 sin(2ωg t + 2ϕvc ) + · · ·
2
2
1
1
2
· · · + L2 ωg Igrid sin(2ωg t) + Vgrid Igrid (1 − cos(2ωg t),
(4.18)
2
2
=
where
Iinv =
Vc =
q
2
Vgrid
ωg2 C 2
+
2
Igrid
(1
q
2
2
Igrid
ωg2 L22 + Vgrid
,
−
L2 ωg2C)2 ,
Vgrid ωg C
ϕiinv = arctan
,
Igrid (1 − L2 ωg2 C)
Igrid ωg L2
and ϕvc = arctan
.
Vgrid
For steady state conditions to maintain stable operation pin must be equal to 12 Vgrid Igrid .
Therefore, using (4.18) and (4.16) we have:
Cbus
2
dvbus
dt
=
2
Vgrid Igrid cos(2ωg t) − L1 ωg Iinv
sin(2ωg t + 2ϕiinv ) − · · ·
2
· · · −Cωg Vc2 sin(2ωg t + 2ϕvc ) − L2 ωg Igrid
sin(2ωg t).
This differential equation can be solved to yield:
1
L1 2
DC 2
vbus (t) =
(Vbus
) +
Vgrid Igrid sin(2ωg t) +
I cos(2ωg t + 2ϕiinv )
2ωg Cbus
2Cbus inv
12
C
L2 2
2
···+
V cos(2ωg t + 2ϕvc ) +
I
cos(2ωg t) .
(4.19)
2Cbus c
2Cbus grid
This equation can be rewritten in a short form as
q
(2)
DC 2
vbus (t) = (Vbus
) + (Vbus )2 sin(2ωg t + β).
(4.20)
2
Equation (4.20) shows that the energy signal Ebus (t) = vbus
(t) comprises a dc and a
double-frequency term. The voltage signal v(t) is not and cannot be constant and it
has high-frequency ripples in addition to the double-frequency ripple, although the
dominant oscillation is at the double-frequency 2ωg . Obviously, as the value of the
bus capacitance Cbus increases, the peak-to-peak value of the ripples decreases. The
signal pin is an external signal which may or may not be known. However, compared
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
122
to the dynamic response of the controller, variations in pin can be considered slow
due to the nature of the source.
4.5.2
System Modeling and the Proposed Design Method
The structure of the bus voltage control loop is shown in Fig. 4.13. In Fig. 4.13 the
constant K is equal to 21 Cbus in order to generate an energy variable from the bus
voltage. In general the constant can be any arbitrary number that has been included
in the controller design. As a result of using this energy variable, the control loop
becomes linear (see equation (4.17)), while in conventional approaches, the control
loop is nonlinear that requires linearization and limits the performance and stability
of the controller for large signal variations. As mentioned before, the energy state
variable only contains double frequency harmonics; therefore, the notch filter used
in this structure completely blocks the harmonics in the loop. In this structure, an
EPLL generates two normalized signals so that one is in-phase with the grid voltage
sin
cos
(v̂grid
) and the other one is orthogonal to the grid voltage, (v̂grid
). The signal in phase
with the grid voltage when multiplied with the output of the bus voltage controller
ref
eE
Ebus
K( .)2
+
ref
PI
igrid
++
∏
sin
vˆ grid
cos
vˆgrid
EPLL
∏
PI
Current
Controller
+
ref
Vbus
Inverter &
Output filters
ref
Qout
Qout
vgrid
Notch
Filter
Figure 4.13: Bus voltage control loop
K( .)2
vbus
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
123
signal constitutes the active component of the reference for the current waveform.
cos
Similarly, v̂grid
is multiplied to the output of the reactive power control loop, to form
the reactive component of the reference signal. To highlight the bus voltage control
loop design method, the structure shown in Fig. 4.13 without the reactive power
feedback is discussed in this section.
Based on (4.17) a model of the system can be obtained as shown in Fig. 4.14(a).
The second-order notch filter that blocks 2ωg is described by the transfer function
s2 + 4ωg2
HNF(s) = 2
s + 4ζωg s + 4ωg2
and its block diagram implementation is shown in Fig. 4.14(c).
To further simplify the control loop of Fig. 4.14(a), notice that the signal of pgrid
has a dc and a double-frequency component:
pgrid (t) =
ref sin
cl
Igrid
v̂grid Hinv
vgrid
=
ref
Igrid
sin(ωg t)vgrid
ref
Igrid
Vgrid
=
(1 − cos 2ωg t),
2
ref
cl
where Igrid
denotes the PI output and vgrid = Vgrid sin ωg t. In this equation Hinv
is
the inverter closed loop transfer function. If the current control loop for the inverter
is designed to provide faster dynamic response than the bus voltage control loop,
then it is possible to assume that inverter closed loop transfer function is unity. Also
notice that according to (4.15), pLCL is a signal that has only a double-frequency
component with an amplitude that is a function of Igrid . Therefore, the overall system
can be simplified to what is shown in Fig. 4.14(b). There are two unknown control
parameters (ki and kp ) that should be designed to stabilize the loop and satisfy the
performance requirements.
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
pLCL
ref
Ebus
eE
+
ref
ref
PI
Inverter
and
Current
Controller
igrid
Igrid
∏
vˆ
igrid
∏
-vgrid
sin
grid
+
124
pin
Ebus
+
+
-pgrid
EPLL
vgrid
Notch
Filter
(a)
− Vgrid
ref
Ebus
+
pin
2
e E k s + k I ref
grid
p
i
Vgrid
s
2
cos( 2ω g t )
− PLCL(.)sin(2ωgt + θ )
∑
+
+
Ebus
pLCL
s 2 + 4ωo2
s 2 + 4ζωo s + 4ωo2
(b)
in
+
2ζ
+
∏
2ωg
out
∏
(c)
Figure 4.14: (a) Block diagram of the modified voltage control loop (b) Simplified
time variant model of the voltage control loop, (c) Transfer function
diagram of the notch filter
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
4.5.3
125
Design of the Modified Voltage Control Loop
The overall voltage control loop is shown in Fig. 4.14(b). This is a linear loop
that is obtained without any linearization nor any approximation. It is important to
note that the system block diagram shown in Fig. 4.14(b) is Linear Time Varying
(LTV). Stability analysis of such systems is not straightforward, because even if the
eigenvalues are all placed on the left hand side of the complex plane the system can
still be unstable. Only for systems that have very slow time-varying parameters may
the classical time invariant methods be used for stability analysis. However, since the
dynamic of the bus voltage control loop is not particularly slow, relatively speaking,
the variation of the system parameters is not so slow and classical time invariant
methods are not valid for this case. To design the controller, first the worst cases of
parameters are chosen and then the controller is designed given these selected values.
Afterwards, using the Lyapunov criterion, the stability of the LTV system is proven.
The variable gain of the system consists of a double frequency term with an
amplitude of Vgrid /2 and pLCL . Equation (4.15) shows that pLCL consists of a double
frequency term with an amplitude that is a function of Igrid . However, the magnitude
of the amplitude is small compared to Vgrid /2 and thus it has a minimal effect on the
amplitude of the double frequency term. Therefore, for the sake of simplicity the effect
of pLCL is neglected for controller stability and design purposes. The characteristic
equation of the closed loop system is given by
s2 (s2 + 4ξωg s + 4ωg2 ) − α(kp s + ki )(s2 + 4ωg2 ) = 0,
where α is the variable gain of the control loop and its maximum is Vgrid . The
Routh-Hurwitz table is used to derive the whole range of kp and ki values that ensure
stability of the closed-loop system. This range is shown in Fig. 4.15(a) for a value of
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
√
Vg = 110 2V. The lower limit is given by ki =
4ωg2 kp
4ξωg −αkp
126
which is determined by the
notch filter dynamics. Any set of kp and ki that is selected between the two limits
drawn in blue in Fig. 4.15(a) are acceptable. The location of the closed-loop poles for
different set of kp and ki within the acceptable range is shown in Fig. 4.15(b). This
locus is when kp varies from 0 to -4 and ki is equal to 100kp (shown in Fig. 4.15(a)).
The system shown in Fig. 4.14(b) has four closed loop poles as shown in Fig. 4.15(b).
It can be seen that for low enough values of kp and ki , the dominant poles are a result
of the PI controller and the integrator. To obtain values for the controller parameters
the notch filter is neglected and the time varying gain is replaced by its average value
α = −Vgrid /2. Therefore, the closed loop characteristic equation is approximated by
s2 − αkp s − αki = 0.
(4.21)
In this equation the undamped natural frequency is ωn2 = −αki and the damping
ratio is ζ = −αkp /(2ωn ). To obtain reasonable step responses an undamped natural
frequency of 200 is selected and the damping ratio is changed from 0.5 to 2. The step
responses to the input disturbance of pin changing from 0 to 200W for the LTI system
without neglecting the notch filter is shown in Fig. 4.16. It can be observed that for a
damping ratio equal to 2 the response is satisfactory and minimum overshoot occurs
for Vbus .
4.5.4
Stability Analysis of the Modified Voltage Control Loop
As mentioned before, since the system parameters change as a function of time, the
standard approaches for Linear Time Invariant (LTI) systems are not useful for the
stability analysis. Consider LTV systems of the form ẋ = A(t)x. Unlike LTI systems
the eigenvalues of such systems do not guarantee the stability of the systems. For
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
127
(a)
(b)
Figure 4.15: (a) Range of kp and ki that maintain stability, (b) Root locus of closedloop poles of the bus voltage control loop when −4 < kp < 0 and ki =
100kp
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
128
Figure 4.16: Step responses of the equivalent LTI system to the input pin changing
from 0W to 200W for damping ratios from 0.5 to 2
instance, consider a system whose A(t) is a two by two upper triangular matrix
with constant negative numbers on the main diagonal and exp t on the off-diagonal
term. For such a system the eigenvalues are constant and on the left hand side of the
complex plane, however due to the exponential term the system is unstable. To prove
the stability of such systems the Lyapunov theorem states that [65, 66]; LTV systems
of the form ẋ = A(t)x are stable if for P > 0 if there exists a positive-definite single
Lyapunov matrix
V (x(t)) = xT Px
such that
d
V (x(t)) < 0.
dt
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
129
Another form of the theorem states that the stability is guaranteed if there exists
P > 0 such that
A(t)T P + PA(t) < 0
at all admissible values and trajectories of time-varying parameters.
To use the Lyapunov stability criterion the closed loop state space model of the
system shown in Fig. 4.14(b) is derived, given as:

dx1

ref

= Ebus
− x2 + 4ζωg x4



dt


h
i

dx2
Vgrid
pin

ref

=
(cos(2ωg t) − 1) ki x1 + kp (Ebus − x2 + 4ζωg x4 ) +

dt
4Cbus
2Cbus
(4.22)

dx
3


= x4


dt




dx

 4 = x2 − 4ζωg x4 − 4ωg2 x3 .
dt
R
In this set of equations the states are defined as x1 = eE , x2 = Ebus , and x3 and
x4 are internal states of the notch filter. The equation set (4.22) has an equilibrium
point for x∗ = (x∗1 , x∗2 , x∗3 , x∗4 ) given by
ref
2pin
pin sin(2ωg t) Ebus
pin cos(2ωg t) pin sin(2ωg t)
ref
, Ebus
+
,
−
,
2
ki Vgrid
4Cbus ωg
4ωg
32Cbus ζωg3
16Cbus ζωg2
!
.
(4.23)
This is a limit cycle for the system and to transform the system to the form of
ẏ = A(t)y, linearization around the limit cycle is performed. Using the new state
variable y = x − x∗ , the system equation becomes

0
−1
0

 Vgrid sin2 (ωg t)ki Vgrid sin2 (ωg t)kp
−
0

2Cbus
2Cbus
ẏ = 

0
0
0


0
1
−4ωg2
4ζωg



2ζωg Vgrid sin2 (ωg t) 

Cbus
1
−4ζωg
 y.



(4.24)
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
130
Figure 4.17: Eigenvalues of Q as a function of time over a period of grid frequency
Using Matlab programming it can be found that a matrix P that satisfies the Lyapunov criterion over a period of grid frequency is


5.9552e − 005 −7.9162e − 007
−0.11073
0.00025405




−7.9162e − 007 3.1918e − 008 1.5451e − 006 −9.9233e − 006


P=
 . (4.25)


1.5451e − 006
417.966
0.48518
 −0.11073



0.00025405
−9.9233e − 006
0.48518
0.0054183
To show that Q = A(t)T P+PA(t) is negative definite for all parameter variations,
the eigenvalues of Q are drawn for a period of the grid frequency and shown in Fig.
4.17. It can be observed that all eigenvalues are negative at any given time and thus
the system is stable. Figure 4.18 shows the amplitude of the reference for the output
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
131
Figure 4.18: Magnitude of the current when the input power jumps from 100W to
200W at t=0.1s
ref
current (Igrid
) for two cases: (i) when the bus voltage is fed back and (ii) when the
energy is fed back; it shows the response when the input power steps from 100 W
to 200W. This graph shows the responses of the LTV system in Fig. 4.14(a) when
no simplification is made. It can be seen that with the voltage feedback method the
amplitude of the current has fourth order harmonics which translate into 3rd and
5th order harmonics on the grid current. The step response of the current amplitude
is also important because any overshoot or strange behavior will be reflected in the
output current and can cause stability problem for the current control loop. This is
especially important during the start-up procedure because high current overshoot
can trip the protection system. For the proposed bus voltage control loop the initial
values of the notch filter states are very important and before starting the converter
the notch filter should pass the transient period.
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
4.6
132
Modified Pulse Width Modulation for Output
Inverter
The decoupling control method used in Section 3.3 for series resonant converter removes all double frequency oscillations from the input PV source. As shown in Fig.
2.19, this pulsation will be displaced to the middle bus voltage that oscillates around
a dc value at twice the grid frequency. As derived in (4.19) the variation of the bus
voltage depends on the input power and the bus capacitor. The double grid frequency
oscillation causes a high harmonic injection into the grid. The conventional way to
avoid this is to increase the bus capacitor or increase the bus voltage,neither of which
are desired. Another possible way to prevent harmonic injection into the grid is to use
a proper controller so that the oscillations on the bus can be tolerated with minimum
possible capacitor as described below.
To enable the inverter to inject active power to the grid it is necessary that the
output of the inverter be larger than the grid voltage. However, the output voltage of
the inverter is made by the bus voltage and thus the maximum of the inverter output
is the bus voltage. Therefore, the bus voltage should be always larger than the grid
voltage to have control over power and output current and also to avoid discontinuous
modes of operation. Moreover, if a simple PWM is used to obtain a harmonic free
output voltage the bus voltage should be pure dc, however that is not the case in
the proposed micro-inverter in this dissertation. A modified pulse width modulation
(PWM) is developed to generate the output current in the presence of bus voltage
ripples.
If a conventional PWM technique is used in the presence of ripples, this double
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
133
vbus(t)
DC
Vbus
vgrid
Vref
Modification
of the modulator (Vref)
DC
mod
Vref =
Vbus
Vref
Vbus(t)
Magnified inverter
output pulses
Equal average
area is applied
Figure 4.19: Modified PWM to remove harmonics from the output current caused by
oscillations at the bus voltage
frequency harmonic is multiplied by the fundamental harmonic of the carrier and
creates first and third order harmonics at the output current. These are detrimental
low frequency harmonics and should be avoided. This problem can be avoided by
introducing an active compensation factor as shown in Fig. 4.19. If we define Vref as
the output of the inverter current controller, when this signal is applied to a PWM
generator it makes a voltage at the output of the inverter with a low frequency component equal to vbus Vref . To prevent any oscillation of vbus to appear at the inverter
output it is possible to measure the bus voltage and its dc value and multiply the
DC
reference by a modification factor vbus
/vbus (t) as shown in Fig. 4.19. It is clear that
the closer the instantaneous bus voltage is to its dc value, the closer the modification
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
134
Figure 4.20: Modified PWM to remove harmonics from the output current caused
by oscillations at the bus voltage for two cases (i) the bus voltage is
dc (denoted by xVdc in green) and when the bus voltage has oscillations
using the modified PWM (denoted by xmod in blue)
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
135
factor becomes to unity. When the oscillatory input dc voltage increases, the compensator decreases the modulation index proportionally, as shown in Fig. 4.19 with
the red curve. As a result, an increase in the dc current value is compensated for by
a reduction in the modulation pulse width and vice versa.
It can be observed that this modification makes a pulse width modulated output
R out
such that the vinv
over one switching period becomes equal to the case that there
was no oscillation on the bus voltage. As a result, according to (4.12), iinv does
not see the harmonics at the bus voltage and the current becomes harmonic free.
Fig. 4.20 shows the simulation results for one period of the grid voltage, comparing
two cases when the bus voltage is constant (in green) and when the bus voltage has
oscillations (in blue) and the modified PWM is utilized. It can be seen that from
mod
mod
modified reference voltage vref
, and the output of inverter using this reference, vout
mod
seem to be non-sinusoidal. However, the harmonic spectrum of vout
is shown in Fig.
4.21 and it is does not contain any low frequency harmonics, very similar to the case
with constant bus voltage shown in Fig. 4.22.
Fig. 4.23 shows the experimental graphs for the bus voltage, output current and
grid voltage. It can be seen that despite the oscillations on the bus, the output current
has high quality. Some of the spikes in the output current are because of measurement
noise: otherwise a big jump in the current of an inductor would be generated with a
large voltage change; that is clearly not the case for the inductor on the grid side.
Due to the oscillation in the bus voltage the output of the inverter has an envelope
of double frequency oscillations as shown in Fig. 4.24. The amplitude of the high
frequency ripple at the inverter output current also changes with the bus voltage, but
the average of the current does not have any low frequency harmonics. This ripple
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
136
Figure 4.21: Harmonics spectrum of the output of inverter with oscillatory bus voltage, modulated using modified PWM at 1200Hz showing (a) whole spectrum (b) higher frequency components (c) zoomed at low frequency components
Figure 4.22: Harmonics spectrum of the output of inverter with constant bus voltage, modulated using conventional PWM at 1200Hz showing (a) whole
spectrum (b) higher frequency components (c) zoomed at low frequency
components
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
137
Figure 4.23: Experimental result showing the bus voltage, output current and grid
voltage at full power
Figure 4.24: Experimental result showing the output of the inverter voltage and current at full power
CHAPTER 4. SYNCHRONIZATION AND BUS VOLTAGE CONTROL
138
is relatively large because the inductors are selected to be as small as possible for
a compact design. Since this current is fed back into the proposed output current
control system, the ripple can cause nonlinearity in the response. To mitigate this
problem, the sampling frequency is synchronized with the switching frequency and
thus by sampling the signal in the middle of the ripple, the average of the signal is
sensed instead of the actual signal.
4.7
Summary
This chapter first presents a synchronization method for single-phase applications.
The main characteristic of the method is that it removes the double frequency harmonic from the output reference signal. Then, a new method for direct instantaneous
power control is introduced that controls the flow of active and reactive powers by
shaping output current. The nonlinear equations are derived based on minimizing
the error between the actual instantaneous power and its reference value and the
complete design procedure and stability analysis are derived. It is shown that the
proposed method is not sensitive to grid frequency variations and it is robust against
grid harmonics.
In the second part of this chapter, a bus voltage control loop is discussed. It is
shown that by using an energy state variable, the conventional nonlinear equations
are linearized and thus a systematic design method is proposed to achieve the desired
performance. The stability analysis of the system using the Lyapunov method is also
studied. In the last section, it is explained how to modify the modulation scheme to
remove the double frequency oscillations of the bus voltage from the output current.
Simulation results are provided to verify the proposed concepts.
Chapter 5
Output Inverter Control
Distributed power generation may be connected to the power distribution grid in
various configurations of three basic elements: inverters, output filters, and controls.
Selection of the output filter has a direct impact on the overall system performance
and its operation. Although higher order filters can significantly reduce the size
and weight of circuit components without compromising the filtering strength, at the
same time they may cause stability problems. A powerful control is then required to
overcome such problems and recover the desired performance for the system. Such
a control system may require sensors to measure system parameters so that appropriate control can be effected. To reduce complexity and cost, a minimum number
of measuring sensors should be employed. This chapter first provides a detailed design procedure for the inverter output filter components. The it presents new control
method to overcome these problems. The derivation of the controller, the design
method, stability analysis and digitization of the controller are all elaborated in detail.
139
140
CHAPTER 5. OUTPUT INVERTER CONTROL
5.1
First-order Inductive Filter
A voltage source inverter (VSI) is often connected to the grid using a simple inductive
filter as shown in Fig. 5.1. Assuming the inductance is L, then the governing equation
is
L
digrid
= vinv − vgrid ,
dt
(5.1)
where ig shows the injected current to the grid, vinv is the inverter voltage and vgrid is
the grid voltage. The transfer function from the inverter voltage to the grid current
is
GL (s) =
Ig
1
=
.
Vi
Ls
(5.2)
Such a filter introduces an attenuation of 20 log(ωs L) dB to the switching frequency
ripples (generated by the inverter) when transferred to the injected current. This
means that at a given switching frequency ωsi , larger L provides higher ripple attenuation and at a given L, increasing the switching frequency reduces the ripples. It is
worth mentioning that the inverter is a full bridge converter with unipolar modulation.
Therefore, using a 25kHz switching frequency, the effective switching frequency at the
output of the inverter doubles to 50kHz. For a value of L=10 mH and fsi =50 kHz,
igrid
S1
S2
Cbus
L
vgrid
vinv
S3
S4
Figure 5.1: First-order L filter interfacing an inverter to the utility grid
141
CHAPTER 5. OUTPUT INVERTER CONTROL
the attenuation is about 70 dB. This means that inverter voltage switching ripples
are attenuated by a factor of about 3000 when transmitted to the grid current. This
seems to be a reasonable level of attenuation for normal practical applications. To
achieve further attenuation, L or ωs must be increased proportionally. Larger values of L mean bulky components, an inefficient solution for low-power applications.
Higher ωsi corresponds to a higher level of switching losses which may not be tolerable
either.
5.2
Third-order Inductive-Capacitive-Inductive Filter
A higher order interface filter can introduce the same level of filtering (or even more)
while having smaller circuit elements than the first-order filter. Consider for example
an LCL filter with inductance L1 (inverter side), capacitance C and inductance L2
iinv
S1
S2
Cbus
L1
vinv
S3
igrid
L2
vgrid
C
S4
Figure 5.2: Third-order LCL filter interfacing an inverter to the utility grid
142
CHAPTER 5. OUTPUT INVERTER CONTROL
(grid side), as shown in Fig. 5.2. The differential equations are

diinv


L1
= vinv − vc


dt


dvc
(5.3)
C
= iinv − igrid

dt




 L digrid = v − v ,
2
c
grid
dt
where iinv and vc stand for the inverter current and the filter capacitor voltage respectively. The transfer function from the inverter voltage to the grid current is
GLCL (s) =
where ωr = √ 1
Leq C
1
Ig
,
=
Vi
(L1 + L2 )s ( ωsr )2 + 1
is the resonance frequency (Leq = L1 ||L2 =
L1 L2
).
L1 +L2
(5.4)
In order to take
advantage of this filter, the resonance frequency must be smaller than the switching
2
frequency. Then this filter introduces an attenuation equal to 20 log[(L1 + L2 )ωs ( ωωs2 −
r
1)] dB to the switching ripples. Assuming that the same level of attenuation provided
by a single L is desired, then
L = (L1 + L2 )(k 2 − 1),
(5.5)
where k = ωs /ωr > 1. The larger the value of k is selected, the smaller the values
of L1 and L2 are needed. To increase k on the other hand, note that k 2 = Leq Cωs2 ,
either C or ωs must be selected to be sufficiently large.
To get a tenfold improvement in the size of inductances (L1 +L2 = 0.1L = 1 mH),
we must have k 2 − 1 = 10 or k = 3.32. Assume also for simplicity that L1 = L2 . It
can be shown that this assumption is reasonable in the sense that it corresponds to
minimum resonance frequency. Then, Leq = L1 /2 = 250 µH. As a result, the value
of capacitor is obtained as C =
k2
Leq ωs2
= 0.446 µF for the same value of switching
frequency, i.e. 50 kHz. The conclusion is that
fs = 50 kHz, L = 10 mH ⇔ fs = 50 kHz, L1 = L2 = 500 mH, C = 0.446 mF.
CHAPTER 5. OUTPUT INVERTER CONTROL
143
Figure 5.3: Filtering diagram of an L filter and an LCL filter (L=10mH,
L1 =L2 =220µH, C=2.2µF)
Let us discuss a scenario in which C is equal to 2.2 µF and the switching frequency
is 50 kHz. Then, k 2 = Leq Cωs2 = 69482L1 . Substituting this in the previous equation,
we will get L1 = L2 = 220 µH and k = 4.88. This scenario is shown in Fig. 5.3. If
we allow the capacitor to increase to C = 4.7 µF, then the inductances will be
L1 = L2 = 150 µH and k = 5.88.
The ratio of k = fs /fr plays a significant role in the design and control of an LCL
filter, because the switching frequency should be high enough to be able to control
the harsh behaviour of the filter at resonant frequency. Lower values of k correspond
to a smaller size of LCL circuit elements. For a capacitance of C = 2.2 µF, the values
of L1 = L2 = 220 µH are sufficient to supply the same filtering level that a 10 mH
inductance does. The value of k is then 4.88 which may not be adequate for control
purposes. Table 5.1 shows how this factor can be increased by increasing the values
144
CHAPTER 5. OUTPUT INVERTER CONTROL
of inductances.
Table 5.1: LCL Components versus Attenuation and Equivalent L Value
L1 (mH)
500
220
150
100
220
300
400
500
150
250
300
L2 (mH)
500
220
150
100
220
300
400
500
150
250
300
C (mF)
0.446
2.2
4.7
10
2.2
2.2
2.2
2.2
4.7
4.7
4.7
dB Att.
70
70
70
70
70
75
80
85
70
80
82
fs (kHz)
50
50
50
50
50
50
50
50
50
50
50
fr (kHz)
15.1
10.2
8.5
7.1
10.2
8.9
7.6
6.8
8.5
6.6
6
fs /fr
3.3
4.9
5.9
7.1
4.9
5.7
6.6
7.4
5.9
7.6
8.3
L (mH)
10
10
10
10
10
19
34
53
10
29
41
Assume that the LCL filter (with components L1 , L2 and C) should have the
same level of filtering that a pure inductance L has. Thus, L = (L1 + L2 )(k 2 − 1)
where k 2 = (fs /fr )2 = Leq Cωs2. For a given L, C and ωs , it is easy to show that
k is maximized when L1 = L2 . Variations of this value, called L12 , versus C and L
are shown in Fig. 5.4(a). It is observed that increasing C will reduce the value of
L12 . For a value of C = 2.2µF, L12 is equal to 220, 310, 380, 440 and 580µH when L
changes from 10mH to 50mH in 10mH steps. In other words, L1 = L2 = 220µF and
C = 2.2µF acts like L = 10mH etc. At a given C, increasing L12 increases the filtering
strength of the LCL and also increases k as shown in Fig. 5.4(b). Increasing L12 from
220µF to 580µF increases k from about 4.9 to about 7.5. It is worth mentioning that
in general there is no documented reference on the extent of this factor. A necessary
condition for controllability of the digital system is derived in [67] which states that
this factor should not be below 2 in order not to violate the controllability condition.
CHAPTER 5. OUTPUT INVERTER CONTROL
145
Figure 5.4: (a) L12 versus C and (b) k versus C for various values of L changing from
10mH to 50mH
Reference [68] suggests a lower bound of 5.8 in order to have a robust performance
using a deadbeat control.
The LCL filter obviously offers a great improvement in reducing the size of circuit
components. For a capacitor of 2.2µF, the inductors are just 220µH to achieve the
same level of attenuation as a single L=10mH inductor. The improvement in the
size of inductors is about 22.7 times: 10000/(2×220)=22.7. The drawback lies in the
harsh behavior of the LCL filter, which is not easy to control. Such behavior is due
to resonance phenomenon among the LCL circuit components. This resonance has a
p
frequency of ωr = 1/ Leq C. Damping of this resonance mode is zero (in a pure LCL
filter), which means that the circuit will oscillate with this frequency. In practice, the
resistive nature of components make this damping nonzero but still without a proper
control system poorly damped oscillations at this frequency will be generated by this
CHAPTER 5. OUTPUT INVERTER CONTROL
146
filter. There are two ways to overcome this problem:
• Passive Damping. In this method, certain amount of resistances are added to
the LCL components to increase damping of the resonant mode. Such resistors,
obviously, dissipate energy and increase the level of losses.
• Active Damping. In this method, an appropriate control strategy is used to
introduce adequate damping to the resonant modes. Design of such a controller
is discussed in next section.
5.3
Output Current Control Loop Design
5.3.1
Controller Objectives and Requirements
The control strategy plays a significant role in obtaining desirable performance when
an LCL filter is used. The filter is of third order and has three state variables. The
current injected to the grid is the most important variable and is controlled carefully.
The objective is to maintain this current as a smooth sinusoidal signal at 60 Hz for all
system operating conditions and all system uncertainties and changes in parameters.
Detailed explanations regarding system conditions and requirements are given below.
• Different system operating conditions stem from the fact that the power generation is an intermittent or variable source. This phenomenon causes a wide
range of current levels and other system variables for which the controller must
be able to operate.
• The filter is connected to the power distribution grid, which is theoretically an
infinite bus. However, such an infinite bus is not realizable in practice and we
CHAPTER 5. OUTPUT INVERTER CONTROL
147
may have different and variable impedances at the grid side. This phenomenon
generates large uncertainties on the grid-side inductor of the filter.
• The resonance phenomenon of the LCL filter should be controlled to avoid
undesirable oscillations during various operating conditions of the system.
• The power distribution grid voltage at the point of coupling is often assumed
to be a pure sinusoid, which is not necessarily the case. The injected current
must be smooth and must comply with the level of allowed harmonics despite
the presence of grid voltage distortions.
• A typical grid often experiences some variations in its frequency. The controller
must be able to operate synchronously with the grid despite such variations.
This issue is even more troublesome in weak grid systems or islanded systems.
• Components of the system may have nonlinearities, which can cause current
distortion. The controller must be able to minimize adverse impacts of these
phenomena on the quality of the injected current.
• The circuit components may undergo changes due to temperature and/or aging.
The controller must perform robustly in the face of such changes.
5.3.2
Control Approach
The reference signal for the output current control loop is a sinusoidal signal that is
obtained from the bus voltage control loop as described in Chapter 4. If a simple
proportional (P) or proportional-integrating (PI) type of controller is used for such a
system, a non-zero steady state error is achieved and sinusoidal disturbances can not
148
CHAPTER 5. OUTPUT INVERTER CONTROL
be rejected. In the micro-inverter application a closed-loop structure is selected based
on the internal model principle [69, 70] in order to ensure that the actual value of the
reference is achieved in the steady-state and the disturbance is completely rejected.
The internal model principle states that “a regulator is structurally stable only if the
controller utilizes feedback of the regulated variable, and incorporates in the feedback
loop a suitably reduplicated model of the dynamic structure of the exogenous signals
which the regulator is required to process” [69]. In other words, if a certain signal
must be tracked or rejected without steady-state error, the signal dynamic must be
inside the control loop. If the dynamic exists in the plant itself there is no need to
repeat it in the controller. Standard classical control literature includes this concept
implicitly when they introduce the system-type concept. This concept relates the
structure of the open-loop system with its closed-loop tracking/rejection capabilities
in steady state.
The proposed closed-loop structure is shown in Fig. 5.5, consisting of a statefeedback controller (SFC) plus an output feedback controller (OFC). In grid-connected
systems, the grid voltage can be assumed as a disturbance that is sinusoidal and has
the same dynamic as the input reference signal. Therefore, the resonant type controller as the OFC, can ensure the desired steady-state operation even with a variable
𝑑
𝑟
+
𝑒
+
OFC
−K𝑐
𝑢
+
+
ẋ = Ax + B𝑢
x
+
−
−K𝑝
Figure 5.5: The proposed closed-loop structure
𝑦
C
CHAPTER 5. OUTPUT INVERTER CONTROL
149
grid voltage. When the grid voltage contains harmonics, however, multiple resonant
units can be employed within the controller structure for a high level of THD reduction. Such a mechanism normally has many parameters which must be carefully
designed to ensure the desired transient response and stability of the system. This
chapter proposes a new method for employing and designing the resonant type controllers within a multi-loop control system. The proposed method is based on using
the classical notion of LQR of optimal control theory. Such a concept, which primarily was formulated to address a regulation problem, is extended to address the
tracking problem involved in grid-connected inverter systems. The formulation presented in this chapter provides an easy yet powerful method of tuning the controller
gains no matter how numerous they are. This is specially advantageous in designing
a multi-resonant controller to reduce the output voltage THD level.
5.4
Concept of Linear Quadratic Regulator (LQR)
A linear time-invariant system can generally be described by the state-space representation
ẋ = Ax + Bu, x(0) = x0 ,
(5.6)
y = Cx + Du,
where A ∈ R(n×n) , B ∈ R(n×m) , C ∈ R(p×n) , and D ∈ R(p×m) are constant matrices,
u is the control signal, x is the state vector, and y is the system’s output.
The conventional LQR problem is to design a full-state feedback law u = −Kx to
optimally regulate the states and the output of this system to zero [71], [72]. In the
CHAPTER 5. OUTPUT INVERTER CONTROL
LQR
problem, the optimality is measured by a cost function as
Z ∞
J(u) =
(xT Qx + uT Ru)dt,
150
(5.7)
0
where Q = QT ∈ R(n×n) is a positive (semi) definite and R = RT ∈ R(m×m) is
a positive definite matrix. In the cost function, matrices Q and R are predefined
constants, which are selected based on the importance of each state or input. Because
the LQR method minimizes the cost function, the larger each term of the matrices Q
and R, the smaller the energy of the corresponding state and the input signal during
the transients. In control theory literature it is shown that the optimal K is given by
K = R−1 BT F,
(5.8)
where the symmetric matrix F = FT ∈ R(n×n) is obtained from the following Algebraic Riccati Equation (ARE)
AT F + FA + Q − FBR−1 BT F = 0.
(5.9)
The closed-loop dynamics under state feedback law with u = −Kx is given by
ẋ = (A − BK)x = Acl x.
(5.10)
and the eigenvalues of Acl are the closed-loop poles.
A solution exists under the assumptions that (A, B) is stabilizable, (A, C) is
detectable, R > 0, Q ≥ 0 and (Q, A) has no unobservable mode on the imaginary
axis [72, pp. 48], [73]. The LQR design provides high robustness with respect to
system parameters uncertainties which translates into 60 degrees of phase margin
and an infinite gain margin [72, pp. 70-76], [74].
In a single-input system, R can be scaled to unity without losing generality. For
any given matrix Q, the closed-loop poles are optimally assigned by the LQR solution
to achieve optimal regulation.
CHAPTER 5. OUTPUT INVERTER CONTROL
5.5
151
Extension of the Regulating Problem to the
Tracking Problem
In practice, specifically in micro-inverter applications, we desire the control system’s
output to track some specific reference commands such as step or sinusoidal. However,
the formulation of the LQR only addresses the regulating problem. Since the output
is supposed to track a reference signal, an extra output feedback loop in addition to
the state-feedback loop is utilized as shown in Fig. 5.5. The optimal tracking index
is not, however, straightforward to define because direct extensions of the LQR index
will either become unbounded or face the nonexistence of a stabilizing solution [72].
To show this problem, assume that the reference is a step function and thus the input
u can become any nonzero value in the steady state. Since the matrix R is constant,
the cost function defined by (5.7) becomes unbounded as time goes to infinity.
In general there are few solutions to the optimal tracking problem. One solution
is proposed in [72] where a finite time tracking problem is solved and then the time is
chosen as a relatively large number. This formulation cannot be extended to infinitetime optimal tracking because the index again becomes infinite, and even if some
solution is obtained for large final time, the label optimal is a misnomer [72, page
85]. Another solution of overcoming the unboundedness of (5.7) for infinite time is
the concept of an overtaking criterion [75, 76]. Based on this concept, the control
obtained for large time intervals overtakes the one obtained for small time intervals.
An alternative method of overcoming the unboundedness of (5.7) is to substitute the
infinite time with a finite time, Tf and then divide the cost function by Tf and take
the limit when Tf tends to infinity. Such a cost function, however, is not suitable
CHAPTER 5. OUTPUT INVERTER CONTROL
152
because different transients leading to the same steady-state yield the same value for
the cost [77]. The proposed approach of [77] resembles the overtaking criterion and
the solution offered is the same as that offered by the overtaking criterion.
The following statements (some of which reflect serious drawbacks) apply to the
methods discussed above: (i) the reference state trajectory xr must be available
(or estimated), while in practice only the output trajectory may be known; (ii) the
dependence of state feedback controller coefficient on the plant parameters can cause
robustness problems; (iii) The closed-loop system does not offer disturbance rejection;
and (iv) the reference trajectory may or may not be achieved in the steady-state.
The LQR problem cannot directly be used to optimally design the whole gains
including those of the state-feedback and of the output feedback. In the next sections
it is shown how to directly addresses the tracking problem. The proposed methods
are specifically used to optimally design controllers for the micro-inverter system.
5.6
Problem Formulation
The grid side of the micro-inverter is shown in Fig. 5.2. The differential equations that
describe the dynamic behavior of this system are given in (5.3). In these equations
vinv = uvdc , where u is the modulated control variable which can take values of 1, 0,
or −1 depending on the state of switches and the modulation scheme.
Taking an average from (5.3) over one switching cycle, one can find the system
state-space equations. Since the bus voltage does not change rapidly we can assume
that it is constant over one switching period. Moreover, using the modified PWM
technique discussed in Section 4.6, the average of the output of the inverter is equal
to the product of the dc component of the bus voltage and a new control variable that
153
CHAPTER 5. OUTPUT INVERTER CONTROL
is obtained from a conventional PWM (see Fig. 4.19). As a result, although the bus
voltage is oscillating and a modified PWM is used, from an average and an analysis
point of view, we can assume that the bus voltage is dc and the conventional PWM
is used. Therefore, the average of vinv is just the amplified version of the output of
the controller, which for simplicity is called u. The amplification gain of the inverter
is called M.
The LCL filter may be described by the following state-space equations where the
index p stands for plant, xp is the state vector defined as xp = [iinv , vc , igrid ]T , and yp
is the output of interest, which is igrid :
ẋp = Ap xp + Bp u + B1 vgrid ,
(5.11)
yp = Cp xp + Dp u,
where

 0

1
Ap = 
 C

0
− L11
0
1
L2


M
L1
0 




− C1 
 , Bp =  0


0
0






 , B1 = 




0
0
− L12



 , Cp = [0, 0, 1] , and Dp = 0.


The command waveform and the disturbance signal are both sinusoids at the
fundamental frequency. We assume that the reference signal r and the disturbance
signal d are generated from the linear equations
ẋr = Ar xr , xr (0) = xr0 , r = Cr xr ,
(5.12)
ẋd = Ad xd , xd (0) = xd0 , and d = Cd xd .
(5.13)
This covers a wide class of signals such as polynomials (step, ramp, etc.), sinusoids
and their combinations. The characteristic polynomial of the OFC is given by
∆c (s) = det(sI − Ac ),
(5.14)
154
CHAPTER 5. OUTPUT INVERTER CONTROL
Output Feedback
Cotnroller
Converter and LCL filter Model
k4
vgrid
ref
igrid
+
+
∏
From
EPLL
+
+
k3
vinv
u
+
M
+
1 iinv +
L1s
1
Cs
vc
+
1 igrid
L2s
ω
k2
k1
∏
Figure 5.6: The proposed control Loop
and to satisfy the internal model principle, ∆c (s) must (at least) contain ∆r (s) =
det(sI − Ar ) and ∆d (s) = det(sI − Ad ). For the micro-inverter application where the
input signal and disturbances are sinusoidal a so-called proportional-resonant (PR)
controller given by
GP R (s) =
k3 s + k4 ωg
s2 + ωg2
(5.15)
is suitable for the OFC where ωg is the system frequency. A state-space representation
for this transfer function is given as follows. Such a state-space realization for the PR
controller as shown in Fig. 5.6, can accommodate frequency variations [78].
ẋc = Ac xc + Bc e,
where




 0 −ωo 
 1 
Ac = 
 , Bc =   ,
ωo
0
0
(5.16)
e = iref
grid − yp and xc is the m-dimensional state vector of OFC. The state variables
of the PR controller in the Laplace domain are
Xc (s) = (sI − Ac )−1 Bc =


E(s)  s 

.
s2 + ωg2 ω
g
(5.17)
CHAPTER 5. OUTPUT INVERTER CONTROL
155
The state space equations for the plant (5.11) and OFC, when augmented together
will make up a fifth order system which is described by the closed loop state-space
equations
ẋ = Ax + Bu + B2 vgrid + B3 iref
grid , and
(5.18)
y = Cx
where x = [xp , xr ]T is the vector of state variables, iref
grid is the reference signal and
the matrices are








0 
 Ap
 Bp 
 B1 
 0 
A=
,B = 
 , B2 = 
 , B3 = 
 , and C = [Cp , 0] .
−Bc Cp Ac
0
0
Bc
(5.19)
Note that the control signal u may be expressed as


 xp 
u = − [k1 , 0, k2 , k3 , k4 ] 
 = −Kx
xc
(5.20)
which is in the standard form of a state-feedback law and the combined system (described by matrices A and B) is completely controllable. It is worth mentioning that
it is challenging to design a standard feedback loop based on only one feedback from
the grid current to obtain stable and robust closed-loop system performance; this
difficulty is due to the marginal stability of the LCL filter. In this application a semistate-feedback strategy combined with an output feedback loop is used, as shown
in Fig. 5.6. The controller section includes an internal loop, which feeds back grid
current igrid and inverter current iinv , and an external loop, which ensures tracking
of a pure sinusoidal current without error. The micro-inverter output filter capacitor
voltage vc (see Fig 5.2) is not used as a feedback signal in the internal loop, to avoid
excessive usage of sensors. Analysis of the design shows that the controller section
CHAPTER 5. OUTPUT INVERTER CONTROL
156
operates desirably without using the capacitor voltage. The effect of this choice will
be discussed later in this chapter. A state estimator can also be used to estimate the
grid current from measurements of inverter current, also obviating the need to sense
the grid current. This, however, is not tackled in this dissertation and is left as a
future work.
The next section formulates a solution that corresponds to the optimal tracking
problem, i.e. the one that minimizes (5.7). It is shown that the LQR concept can be
extended to directly address the optimal tracking problem. Using this method, the
admissible qi ’s are obtained with much less effort and with a more transparent view
on the problem.
5.7
Proposed Solution
Define the operator ∆c (D) = det(DI − Ac ) where D is the differentiating operator,
and I is the identity matrix. ∆c (D) is a polynomial of order m of the operator D:
∆c (D) = D m + a1 D m−1 + · · · + am−1 D + am .
Since the internal model principle is followd, ∆c (D)r = ∆c (D)d = 0. Applying the
operator to both sides of (5.19) and (5.20) arrives at
ż = Az + Bv,
v = −Kz,
(5.21)
where the transformed (or pseudo) state vector z and the transformed (or pseudo)
input v are defined as
z = ∆c (D)x,
v = ∆c (D)u,
and z = [zTp , zTc ]T where zp = ∆c (D)xp and zc = ∆c (D)xc .
(5.22)
CHAPTER 5. OUTPUT INVERTER CONTROL
157
Now the transformed state space equations do not contain the disturbance or
reference signals and it is in the form of a standard regulation problem (LQR) in
which the objective is to regulate the state variables to “zero”.
Fig. 5.7 shows the block diagram presentation of the introduced transformation
for a simplified case. Assume that the OFC can be defined by a simple transfer
function Nc (s)/Dc (s) as shown in Fig. 5.7 (a). Fig. 5.7 (b) to (e) show how the
denominator of the controller is factored and passes through the block diagrams. In
this process it is assumed that blocks are linear and thus interchangeable. Fig. 5.7 (c)
shows that when the converter input has changed from u to v the states are changed
from x to z and it is clear that z = Dc (s)x. Since the controller is chosen based
on the internal model principle, iref
grid Dc (s) = 0 and thus the block diagram shown in
Fig. 5.7(e) is equivalent to (a) with new transformed state variables z and it is in the
standard form of an LQR problem.
For the micro-inverter the input signal is sinusoidal and it satisfies the equation
2 ref
ïref
grid + ωg igrid = 0, and in (5.21), the new state vector z and the new control signal v
are defined as z = ẍ + ωg2 x and v = ü + ωg2u. Moreover, from (5.17) it can be observed
that
z4 = ẍc1 + ωg2xc1 = ė, and
(5.23)
z5 = ẍc2 + ωg2xc2 = ωg e.
(5.24)
The new variables (z and v) characterize the deviation of the original variables from
a pure sinusoid at frequency ωg .
As a matter of fact, the above transformations on the state variables and control
signal transformed the tracking problem into a regulation problem. Such a problem
can optimally be addressed using the LQR technique. Applying the LQR technique to
158
CHAPTER 5. OUTPUT INVERTER CONTROL
ref
igrid
u
Nc(s)
Dc(s)
+
+
Converter
X
K
ref
igrid
+
Nc(s)
(a)
v
+
(b)
v
ref
igrid
+
Nc(s)
+
u Converter x1
1
Dc(s)
X
K
Dc(s)
x1
Converter
z1
1
Dc(s)
x1
Z
K
(c)
ref
igrid
Dc(s)
0
1
Dc(s)
+
Nc(s)
+
v
Converter
z1
Z
K
(d)
0
+
Nc(s)
Dc(s)
+
v
Converter
K
z1
Z
(e)
Figure 5.7: Block diagrams showing the process of states transformation
the transformed state space system provides the best controller gains that minimize
the quadratic cost function
Z ∞
Z
T
2
J=
(z Qz + v )dt =
0
∞
(q5 ωg2e2 + q4 ė2 + zTp Qp zp + v 2 )dt.
(5.25)
0
Matrix Q is positive semi-definite and e(t) = iref
grid (t)−igrid (t) is the tracking error. The
solution is obtained from the Algebraic Riccati Equation (ARE) and is conveniently
calculated in Matlab using the command K = lqr(A, B, Q, 1). The key point is
CHAPTER 5. OUTPUT INVERTER CONTROL
159
that by minimizing the cost function of the transformed state space system, the
components which are being minimized are important parameters in the original
system such as tracking error and its derivative. The LQR technique transforms the
problem of selecting closed-loop poles into selecting the matrix Q. This matrix is a
diagonal non-negative matrix and thus it has the same number of elements as those
of the controller gains K, i.e. Q = diag(q1 , q2 , q3 , q4 , q5 ). A simple option to minimize
only the tracking error is to select Q in (5.25) such that Q = diag(0, 0, · · · , 0, q) and
thus (5.25) becomes
J=
Z
∞
T
2
(z Qz + v )dt =
0
Z
∞
(qe2 + v 2 )dt.
(5.26)
0
In (5.26), e(t) = iref
grid (t) − igrid (t) is the tracking error, q is a positive scalar, and v is
a pseudo-input properly defined to convey transient properties of u without causing
the cost index to become unlimited. The index (5.25) combines optimal tracking of
the command signal iref
grid by the output igrid , optimal rejection of the disturbance d
from the output igrid , and avoids excessive energy consumed at v.
Unlike selection of closed-loop poles, selection of Q is performed with the clear
view that increasing each element qi decreases the deviation of state variable zi from
zero. Thus, using a systematic search one can lead to a suitable selection, which
results in a desirable behavior of the closed-loop system. It is very important to note
that, in this method, the designer is not worried about closed-loop instability because
the stability is guaranteed for any choice of non-negative Q. The selection of Q only
affects the transient response of the closed loop.
CHAPTER 5. OUTPUT INVERTER CONTROL
5.7.1
160
Selecting Matrix Q
The significance of the proposed method is that it reduces the complex problem of
designing of the controller gains to the design of LQR gains matrix Q. This offers
a great simplification because the LQR gains are positive and their impacts on the
system performance can be observed transparently. For example, it is observed from
(5.25) that q5 controls the tracking error and has the most significant impact on
generating a desirable response. The coefficient q4 controls the rate of change of the
tracking error and may be used to make the system responses smoother. Further
adjustments are possible by using q3 , q2 and q1 . Therefore, a design can be reached
by subsequently increasing qi ’s and observing their impacts on the response. There
are several characteristics which are of importance in the micro-inverter application.
1. Speed is represented by the settling-time of the response to a change in input
power or in the reference signal.
2. Overshoot shows the excessive increase in the response in percentage of its amplitude.
3. Output Current THD is caused by nonlinearities in the system or harmonic
components of the grid voltage.
4. Damping of LCL resonance mode shows how well the controller can avoid undesired oscillations caused by the LCL resonance mode.
5. System’s zero are generated by the OFC controller; it is preferred to remain
minimum-phase with an adequate distance from the origin.
CHAPTER 5. OUTPUT INVERTER CONTROL
161
6. Closed-loop bandwidth must be large enough to ensure the strength of control
signal and low enough to avoid excessive sensor noise propagation.
7. PWM switching frequency poses limitations on the PWM generated signal. A
fast-changing control signal cannot be generated by a low switching frequency.
This means that the loop must not have fast modes beyond the capacity supported by the switching frequency.
The design begins with increasing q5 which has the most significant impact on the
tracking error. The graphs in Fig. 5.8 plotted in blue show some of the the above
seven characteristics of the system versus q5 . Fig. 5.8(c) shows that the settling-time
of the response decreases when q4 is increased, and note that the overshoot is also
decreased as shown in part (b). The damping of the LCL-filter resonance mode is
shown in (d) and it remains constant. The system’s zero is shown in part (f) which
exhibits movement towards left hand side of the complex plane. The closed-loop
bandwidth from igrid to iinv is shown in (a). The bandwidth is observed because iinv
contains high frequency harmonics and this bandwidth shows the highest frequency
noise that appears at the output current. Part (e) shows the time-constant of the
fastest mode in the closed-loop system. It important to observe this mode carefully
because the PWM cannot generate fast-changing control signals due to limitation in
the switching frequency. An effective switching frequency of 40 kHz corresponds to
a switching time of 25 µs. A rule-of-thumb consideration is that a few switching
cycles must be placed within the time-constant of the fastest mode in order to be
generated successfully. This means that the fastest time-constant must not go below
about 50 µs.
CHAPTER 5. OUTPUT INVERTER CONTROL
162
Figure 5.8: Monitoring the closed-loop characteristics when qi s are increased one by
one: (a) Bandwidth of the closed loop system (b) overshoot in percentage
(c) settling time in ms (d) damping of LCL-filter resonance mode (e)
time-constant of the system’s fastest mode (f) system’s zero
At this stage, a value for q5 can be selected (for example at 1000) and the same
procedure is repeated for q4 . Results are shown in Fig. 5.8 in red. It is observed that
compared to q5 , increasing q4 has similar effects on most of the system parameters
except for the fastest mode of the system and zeros of the closed loop which are
increased. The parameter q4 is given a value of 100.
At this stage of the design, q5 and q4 have been selected. The system characteristics
as q3 and q2 change are shown in Fig. 5.8 in green and black respectively. The desired
CHAPTER 5. OUTPUT INVERTER CONTROL
163
Figure 5.9: (a)The loci of poles of the closed-loop system when qi s are increased one
by one (b) zoomed to show the loci close to the origin
impact of increasing q3 and q2 is a large increase in the damping ratio of the system.
The trade-offs are a gradual decrease in speed, movement of zero towards origin,
decrease in bandwidth and a decrease in the time-constant of the fastest mode. When
the desired damping is achieved, the last parameter, q1 , is increased and it can be
seen that this parameter does not have a significant positive effect on the system and
therefore, it is not increased much. Fig. 5.10 shows the trend of state feedback gains
while qi s are increased. The final value of the state feedback gains are used for the
controller.
The loci of poles of the closed-loop system are shown in Fig. 5.9. Such loci provide
much insight into the design process. When qi s vary from zero to the maximum values,
the loci of the poles are shown in different colors for each qi so that the effect of the
increase in each qi can be observed. These graphs confirm results exhibited in Fig. 5.8.
CHAPTER 5. OUTPUT INVERTER CONTROL
164
Figure 5.10: Plot of the state feedback gains while increasing qi s one after another
In summary the systematic method used herein is to start increasing q5 from an
initial positive value while all the other coefficients are set to zero. Once q5 reaches a
certain value, it becomes frozen and then q4 starts to increase. The system responses
together with the location of closed-loop poles and zeros are monitored while the q
coefficients are being increased. At each stage each coefficient is increased up to the
point that further increases no longer improve the monitored criteria. Fig. 5.11 shows
a sample of a PSIM simulation of the micro-inverter system designed by the method
proposed in this section. At 50ms the input power is stepped up to full power. It can
be seen that the output current does not have an excessive overshoot or ringing and
it settles down in 10ms.
It is worth mentioning that standard state-feedback techniques assume that all
state variables are used for feedback. Thus, the closed-loop poles deviate from their
pre-specified locations if the capacitor voltage gain is set to zero. The deviation is
in the direction of reduction of the response speed and a reduction of the damping
CHAPTER 5. OUTPUT INVERTER CONTROL
165
Figure 5.11: Simulation of a step response to the input power
Figure 5.12: Deviation of the closed loop poles when vc is fed back and is not fed
back.
CHAPTER 5. OUTPUT INVERTER CONTROL
166
of resonances, as can be seen in Fig. 5.12, which shows deviation of the closed-loop
poles for cases where vc is used, and where vc is not used.
5.8
Damping the LCL-filter Resonance Frequency
An LCL-filter has a resonance frequency that should be attenuated in the microinverter application because it can create undesirable harmonics in the output current.
This resonance is shown in Fig. 5.3, which shows that even a small noise at the input
of the LCL filter can create large output at the resonance frequency. Fig. 5.13(a)
shows that if the controller and state feedback gains are not designed correctly, the
closed loop bode plot still contains the resonance frequency. However, Fig. 5.14(a)
shows the case where the closed loop bode diagram does not show any resonance.
This can be obtained by selecting the state feedback gains as proposed in Section
5.7.1. The simulation results of the output current at the minimum input power for
well damped and undamped designs are shown in Fig. 5.15.
The root locus in Fig. 5.9 shows that the damping ratio is around 0.56. It is
important to note that this root locus demonstrates the path of the closed loop poles
chosen optimally by LQR and without solving the LQR problem it is not clear which
location in the complex plane corresponds to the optimal responses. As a result one
cannot simply choose the location of the poles to obtain only well-damped responses
and expect that all the criteria listed in Section 5.7.1 are satisfied. Such selections
may highly compromise the robustness and noise characteristics of the system.
CHAPTER 5. OUTPUT INVERTER CONTROL
167
(a)
(b)
Figure 5.13: Closed loop Bode diagram of the inverter (a) from the output current
to the reference input (b) from the output current to the disturbance
input, when the LCL resonance is not well damped
CHAPTER 5. OUTPUT INVERTER CONTROL
168
(a)
(b)
Figure 5.14: Closed loop Bode diagram of the inverter (a) from the output current
to the reference input (b) from the output current to the disturbance
input, when the LCL resonance is well damped
CHAPTER 5. OUTPUT INVERTER CONTROL
169
Figure 5.15: Simulation of the output grid current for minimum input power when
(a) the LCL resonance is not well damped (b) the LCL resonance is
damped
5.9
Robustness Against Grid Impedance
The micro-inverter is connected to the grid using an LCL filter whose parameters are
used in the design of the controller. However, since the grid side inductance depends
on the grid quality and is quite uncertain, the controller should be robust against the
grid impedance.
For every selection of Q, the closed-loop poles are arranged and placed at a specific
location in such a way that the cost function (5.25) is minimized. Such a solution is
optimal. This means that a blind selection of closed-loop poles would not necessarily
CHAPTER 5. OUTPUT INVERTER CONTROL
170
correspond to an optimal solution. A feature of the LQR technique is that it guarantees those locations of the closed-loop poles which are optimal. Such an optimality
also corresponds to certain degrees of system robustness in terms of classical concepts
of phase-margin and gain-margin, as already mentioned. Fig. 5.16 shows the result
of the proposed method in Section 5.7.1 for the loci of the closed loop poles when
the grid side inductor L2 is increased from its nominal value to 20 mH. Unlike the
conventional state feedback design that becomes unstable for an uncertainty as small
as 0.5 mH in L2 , the proposed technique maintains the stability for uncertainties as
large as 20 mH.
Investigations show that the standard pole-assignment technique of state-feedback
theory is not ideal for designing the controller gains, for various reasons. An appropriate set of locations for closed-loop poles is challenging to obtain, and the closed-loop
system will become sensitive to system uncertainties, calculation delays, and to estimation accuracy, and will exhibit poorly damped resonance oscillations. For example,
the impact of uncertainties on the grid-side inductor L2 (i.e., a change from 0.5 mH
to 1 mH), is shown in Fig. 5.17. In this example it can be observed that the poles
of the LCL-filter are located with good damping and the other two poles of the controller are placed as dominant poles that provide good transient response. However,
the root locus shows that a small increase in the grid-side inductor makes the closedloop system unstable. In contrast, the performance of the proposed controller against
large uncertainties in the grid-side inductor is shown in Fig. 5.16 and it can be seen
that the controller handles uncertainty levels that are twenty times larger without
instability.
CHAPTER 5. OUTPUT INVERTER CONTROL
171
Figure 5.16: The result of the method proposed in Section 5.7.1 for the loci of the
closed loop poles when the grid side inductor L2 is increased from its
nominal value to 20mH
Figure 5.17: The impact of uncertainties on the grid-side inductor L2 (a change from
0.5 mH to 1 mH) on the closed loop root locus when the standard poleassignment is used for designing the controller
CHAPTER 5. OUTPUT INVERTER CONTROL
5.10
172
Output Current Harmonic Cancelation
The control structure with the PR controller of Fig. 5.6 does not have a highly desirable level of attenuation of the grid current harmonics. The controller shown in
Fig. 5.18 is a further improvement that minimizes impacts of grid voltage distortion
on the quality of the injected current. This improvement is a result of incorporating
multiple resonant controllers in the outer feedback loop as shown in Fig. 5.18. The
design of such controllers may also be accomplished using the improved LQR technique as discussed in Section 5.7. Such a design involves the adjustment of several
controller coefficients that is very challenging using conventional techniques. The
method described herein facilitates such a design in a very convenient way without
any instability concern. The controller may be improved by following
X k3n s + k4n (nωo )
C(s) =
,
2 + n2 ω 2
s
o
n∈H
(5.27)
where H is the set of harmonics which are present. The implementation of this
controller, shown in Fig. 5.18, is robust against slight changes of grid frequency.
Such a controller completely removes all the harmonics in the set H because it has
high gain at the desired harmonics and it is clear that if the open loop transfer function
of the system has high gain at the disturbance frequencies all the disturbances will
be eliminated. The bode diagram of Fig. 5.19 shows the the magnitude and phase
of the open loop system and it can be observed that it has high gain at harmonic
components {1, 3, 5, 7, 9} which guarantees the tracking and disturbance rejection at
those harmonics. The controller structure becomes complicated as H becomes larger.
In practice, H should be as small as possible so as to include only dominant harmonics
without excessive controller structure. Typically, H = {1, 3, 5, 7, 11} is adequate for
173
CHAPTER 5. OUTPUT INVERTER CONTROL
most applications and this significantly reduces the output current THD to comply
with the Standards.
A main challenge with a high order controller such as that of (5.27) is appropriate tuning of its gains [79]. The technique proposed in Section 5.7 can easily be
extended to address such a challenge. To show that, form the controller state-space
representation as ẋc = Ac xc + Bc e where
Ac = blockdiag{Ac1 , · · · , AcN }, Bc = [BTc1 , · · · , BTcN ]T
in which




 0 −nωo 
 1 
Acn = 
 , Bcn =   .
0
nωo
0
The plant and controller, when augmented, will give the state-space representation in
(5.18). Similar to Section 5.7, define the augmented state variable as x = [xTp , xTc ]T
and z = ẍ + ωg2 x. Then z = [(ẍp + ωg2xp )T , ė, ωg e, z1 ]T where z1 shows the states
related to harmonic controllers. Also define ν = ü + ωg2 u. With this new set of
state variables and input, the whole system’s state-apace representation is ż = Az +
Bν where A and B are defined in (5.19) by replacing the new controller matrices.
Moreover, ν = −Kz which shows a regulation problem. The matrix Q is Q =
diag{q1 , q2 , · · · , qN }.
The controller gains are conveniently obtained by the method previously described. The complexity of the design method does not increase with the controller
order thanks to the availability of the lqr command in Matlab which solves the Riccati equation. Fig. 5.21 shows the performance of the controller in Fig 5.18 when the
grid voltage is distorted; this is contrasted with Fig. 5.20 which shows the controller
in Fig. 5.6 under the same conditions. The shown scenario corresponds to the case
ref
igrid
+
From
EPLL
From
EPLL
+
From
EPLL
nth harmonic
Cancellation
+
3rd harmonic
Cancellation
+
nω g
3ω g
ωg
Output Feedback
Cotnroller
∏
∏
∏
∏
∏
∏
k4n
k3n
k43
k33
k4
k3
+
+
+
+
+
+
+
+
+
+
∑
u
M
k2
k1
+
vinv
1 iinv
+
L1s
Converter and LCL filter Model
1
Cs
vc
+
vgrid
1 igrid
L2s
CHAPTER 5. OUTPUT INVERTER CONTROL
174
Figure 5.18: The controller structure to remove the effect of the grid voltage harmonics from the output grid current.
CHAPTER 5. OUTPUT INVERTER CONTROL
175
Figure 5.19: Open loop bode diagram of the system shown in Fig. 5.18.
where the irradiation level is increased from 10 percent to 100 percent at the time
instant 0.05 s. The fast and smooth grid current injection that signifies injection
of high-quality power is observed when the improved controller is applied. In these
simulations the grid voltage harmonics components with respect to the fundamental
component are 10% third , 5% fifth and 5% seventh harmonics.
CHAPTER 5. OUTPUT INVERTER CONTROL
176
Figure 5.20: Simulation of a step response to the input power when the grid voltage
has harmonics and no harmonic cancelation is used
Figure 5.21: Simulation of a step response to the input power when the grid voltage
has harmonics and the harmonic cancelation structure is used
CHAPTER 5. OUTPUT INVERTER CONTROL
5.11
177
Controlling the Start-up Transient
At start-up the output current may have an undesirable transient that can trip the
protection system or even damage the inverter. The high start-up current can be generated for various reasons such as (i) uncontrolled initial conditions, (ii) the transient
in the reference generating system and (iii) the grid voltage which is modeled as a
disturbance. By starting the controller at the zero crossing of the grid voltage all the
initial conditions can be set to zero. The EPLL and reference generation have startup transients whose effects on the output grid current can be avoided by introducing
a delay to the start of the controlling sequence after power up. Since the controller is
implemented in an FPGA these two tasks can be done by generating different enable
signals for different parts of the control circuit. The effect of the grid voltage on the
start-up is examined in this section.
Referring to Fig. 5.22 it can be observed that in the LCL model the grid voltage
exists as an independent input that can be considered a disturbance. If the disturbance was added right at the input of the model, which is the case for the L-filter,
through a simple addition we could remove its effect on the transients. However, in
the LCL-filter this is not the case and the effect of the disturbance can not be removed completely by simple addition. As a result the control loop shown in Fig. 5.22
is proposed for the LCL, employing the summation of a fraction of the grid voltage
at the input of the plant model. The coefficient kF F is a design parameter that can
be found by minimization of the output current transient as described here.
The augmented state space equations of the system shown in Fig. 5.22 is described
178
CHAPTER 5. OUTPUT INVERTER CONTROL
vgrid
LCL filter Model
kFF
ref
igrid
+
OFC
+
+
vgrid
vinv
u
M
+
1 iinv
+
L1s
1
Cs
vc
+
1 igrid
L2 s
k2
k1
Figure 5.22: The proposed control Loop to control start-up transients
by
ẋ = Ax + Bu + B2 vgrid + B3 iref
grid , and
(5.28)
y = Cx,
where x = [xp , xr ]T is the vector of state variables, iref
grid is the reference signal and
the matrices are








0 
 Ap
 Bp 
 B1 
 0 
A=
,B = 
 , B2 = 
 , B3 = 
 , C = [Cp , 0] .
−Bc Cp Ac
0
0
Bc
(5.29)
According to the controller structure, the control signal u may be expressed as
u = −Kp xp − Kc xc − kF F vgrid .
(5.30)
As a result the state space closed loop equations are


 



 Ap − Bp Kp Bp Kc   xp   B1 − kF F Bp 
 0  ref
ẋ = 

+
 vgrid + 
 igrid .
−Bc Cp
Ac
xc
0
Bc
(5.31)
179
CHAPTER 5. OUTPUT INVERTER CONTROL
The response of the output current to the input vgrid is
"
#
Z t
B
−
k
B
1
F
F
p
igrid (t) = Cx(t) = C
eA(t−τ )
vgrid (τ )dτ.
0
0
(5.32)
We want to find the coefficient kF F so that the start-up transient is minimized. This
can be quantified by minimization of a norm defined as
Z Tf
2
min kigrid (t)k = min
i2grid (t)dt.
(5.33)
0
Using (5.32) the output current norm is calculated by
Z Tf
Z Tf
T
2
igrid (t)dt =
CeAt (Λ1 ΛT1 − 2kF F Λ1 ΛT2 + kF2 F Λ2 ΛT2 )eA t CT dt,
0
(5.34)
0
where
Λ1 (t) =
Z
0
t
e−Aτ
"
B1
0
#
vgrid (τ )dτ,
Λ2 (t) =
Z
t
e−Aτ
0
"
Bp
0
#
vgrid (τ )dτ.
(5.35)
To minimize the norm defined by (5.33), we find the derivative of (5.34) with respect
to kF F and equate it to zero to find kF F . The optimum solution is
R Tf
T
CeAt Λ1 ΛT2 eA t CT dt
0
kF F = R Tf
.
CeAt Λ2 ΛT2 eAT t CT dt
0
(5.36)
The value of kF F can be numerically calculated for TF equal to half a cycle or one
cycle. For the LCL-filter the optimum solution is kF F = 0.0103. Figures 5.23 and 5.24
show a simulation of the start-up transients. It can be observed that when the branch
with kF F is introduced the overshoot at the grid current has decreased significantly
for both low and high input power levels.
CHAPTER 5. OUTPUT INVERTER CONTROL
180
Figure 5.23: Simulation of the start-up transients at full power, (a) without the kF F
branch (b) with thekF F branch
Figure 5.24: Simulation of the start-up transients at minimum input power, (a) without the kF F branch (b) with the kF F branch
181
CHAPTER 5. OUTPUT INVERTER CONTROL
5.12
Digitization of the Controllers Using Delta
Operator
The analysis and design of digital control systems may be done entirely in the zdomain, which is called Direct Digital Control Design (DIR), or entirely in the sdomain, which is called digitization techniques (DIG) where by using a transformation
the controller is transformed from s-domain to z-domain for digital implementation.
In this dissertation the DIG technique is utilized. In this method it is crucial that
the main properties of the controller such as stability remain unchanged and that
transient properties do not vary considerably. In the DIG technique the analog to
digital conversion block is modeled as a sampler and a Zero Order Hold (ZOH) in
cascade and their models are used in the s-domain design. To make the analysis
simpler the approximate model of ZOH is typically used. For example, the Pade
approximation can be used:
GZOH =
1 − e−sTs
2Ts
≈
.
s
Ts s + 2
(5.37)
For the micro-inverter, since the LCL components have small values, the sampling
time 1/Ts is selected to be 80Khz, which is far above the resonance frequency of the
LCL-filter and enables the damping of the resonance frequency of the LCL filter.
As a result, the transfer function of the sampler and ZOH that is
1
G
T ZOH
will tend
to unity for the frequency range of interest. There are several methods to derive
the z-domain transfer function from the s-domain transfer function, all basically an
approximation of z = esTs . One of the most common approximation methods is the
Tustin transformation, that is the substitution of sn by
n
2 1 − z −1
n
s ≈
.
Ts 1 + z −1
CHAPTER 5. OUTPUT INVERTER CONTROL
182
The interesting point is that the Tustin transformation is easy to implement and it
maintains the stability and dc gain properties of the s-domain controller. For the
controller structure shown in Fig. 5.6, the output feedback controller is a second
order transfer function whose analog implementation is presented. To digitize this
controller we can use the Tustin transformation that yields
b0 + b1 z −1 + b2 z −2
CP R (z) =
.
1 + a1 z −1 + a2 z −2
(5.38)
There different ways of implementing this transfer function. Direct form (DF)
structures are the most common forms for this transfer function. There are two
types of such forms, namely DFI and DFII or their transposed versions DFIt and
DFIIt, [80]. Fig. 5.25 shows the implementation of the DFII form.
Since the transformation maps the infinite half plane s-domain to a finite unity
circle in the z domain, the transformation is nonlinear and compresses the frequency
axis. This can create problems with finite word length and fixed-point arithmetic
implementations of the transfer function, especially when the sampling time is high.
Such a situation often causes the system to become numerically ill-conditioned. Delta
operator based filters alleviate this problem by characterizing the difference between
these poles and unity. This transformation usually brings much less roundoff noise
gain and more robust coefficient and frequency sensitivities [81].
The delta operator is defined as δ = (q − 1)/∆ where ∆ is a fixed parameter
that shows the magnification factor in the new transformed domain (γ) and q is the
shift operator in the discrete time systems (u[k + 1] = qu[k]). The shift operator is
replaced by z if the initial conditions are neglected [82]. In the same way one can
define the delta transformation variable as γ which is related to discrete time variable
183
CHAPTER 5. OUTPUT INVERTER CONTROL
u[k ]
y[k ]
b0
z −1
− a1
b1
z −1
− a2
b2
u[k ]
Figure 5.25: Direct form II (DFII) implementation of the digital controller CP R (z)
z by γ = (z − 1)/∆. In other words,
γu[k] =
u[k + 1] − u[k]
.
∆
Similar to the z-transformation where everything is expressed in terms of z −1 to obtain
a causal system, we have [83]:
γ −1 =
z −1 ∆
.
1 − z −1
Implementation of γ −1 in terms of z −1 is shown in Fig. 5.26.
All different forms of DF structures can be transformed to γ-domain by a simple
substitution, z = 1 + γ∆. As a result the transfer function will have the same form
u [k ]
z
∆
−1
γ −1u[k ]
γ −1
y[k ]
Figure 5.26: Implementation of γ −1 in terms of z −1
CHAPTER 5. OUTPUT INVERTER CONTROL
184
as (5.38) with new coefficients:
CP R (γ) =
β0 + β1 γ −1 + β2 γ −2
.
1 + α1 γ −1 + α2 γ −2
(5.39)
This transfer function can be presented in terms of the original variables in the zdomain transfer function:
2b0 + b1
b
+
b
+
b
0
1
2
b0 +
γ −1 +
γ −2
∆
∆2
CP R (γ) =
.
2 + a1
1 + a1 + a2
−1
−2
1+
γ +
γ
∆
∆2
(5.40)
Due to the unstable pole at z = 1 in the γ −1 formula, the DFI implementation is
not stable and cannot be used and the DFIt implementation requires double precision
internal arithmetic [80]. As a result, the DFII structure is used for delta domain
implementations as shown in Fig. 5.27.
In (5.40) ai s and bi s are known but ∆ need to be chosen. It can be seen that as
∆ is reduced, the coefficients are spread, and taking into consideration the maximum
coefficient length, ∆ can be selected. A detailed method to choose this parameter to
minimize the quantization noise is given in [80]. It is shown that if ∆ becomes too
small, the quantization noise also increases. As a result there is a trade off here and
this parameter should be selected in practice with great care and only after through
examination.
For a sample design of the micro-inverter after tustin transformation the z-domain
controller is
CP R (z) =
0.00160085 + 0.00000547z −1 − 0.00159537z −2
.
1.00000000 − 1.99997779z −1 + 1.00000000z −2
(5.41)
It can be observed that the coefficient a1 is very close to 2 and the roots of the
characteristic equation are very close to the unity circle and to each other (p1 =
0.99998889 + 0.00471237i and p2 = 0.99998889 − 0.00471237i). If the controller is to
185
CHAPTER 5. OUTPUT INVERTER CONTROL
u[k ]
y[k ]
β0
γ −1
∆
z −1
−α1
γ −1
β1
∆
z −1
−α2
β2
Figure 5.27: Direct form II (DFII) delta domain implementation of the digital controller CP R (γ)
be implemented in the z-domain a high number of bits and calculations are required
to achieve accurate results. In this example at least 24 bits are required.
Applying the delta transformation we obtain
0.02622845 + 1.68149384γ −1 + 0.18387339γ −2
.
CP R (γ) =
16.3840000 + 0.01164263γ −1 + 0.3725644γ −2
(5.42)
It can be observed that the coefficients are spread and the roots are not as close
to each other nor to the stability margin (p1 = −0.00035530 + 0.15079588i and p2 =
−0.00035530 − 0.15079588i). The ∆ parameter can be selected using either 16 or 32,
but 16 bit calculations are more than enough for this implementation.
The result of simulation of the micro-inverter system with all the controller parts
digitized in PSIM is shown in Fig. 5.28. In part (a) the grid current and the grid
current reference are shown. The grid current reference is generated by the reference
generation control system introduced in Chapter 4. It can be seen that the transient
at the start-up is created by the transient in the reference generation system and by
CHAPTER 5. OUTPUT INVERTER CONTROL
186
the grid voltage which is controlled using the method discussed in Section 5.11. It
can be observed that the resonance at the output current for the low input power
is slightly worse than the case shown in Fig. 5.15 (b) this stems from two reasons:
(i) the effect of digitization of the controllers and (ii) the lower switching frequency
(20khz) in the simulation of Fig. 5.28 as opposed to the 40khz frequency in Fig. 5.15
(b). In part (b) the bus and grid voltages are shown and it can be observed that
the average bus voltage is regulated at 250V as desired. In the bus voltage control
loop shown in Fig. 4.14(a), there is a notch filter to cancel all the double frequency
harmonics. Since this notch filter is also a second order filter with narrow rejection
band, all the problems associated with the digitization of OFC are true here. As a
result the notch filter has also been implemented using delta transformation and the
DFII structure.
5.13
Experimental Results
The experimental waveforms for full power are shown in Fig. 5.29. It can be observed
that the output current is in phase with grid voltage and has high quality. Fig. 5.30
shows the dynamic response of the output current to a step change in the input
power. It can be observed that the output current changes rapidly and reaches its
steady state in less than half of grid cycle. A portion of the transients in the response
is because of the reference signal generation dynamic and the rest is due to the output
current controller.
As discussed in Section 5.11, at the startup of the system, the output current can
have a large overshoot if the proper controller is not utilized. The implementation of
the controller discussed in the section results in a soft start as shown in Fig. 5.31.
CHAPTER 5. OUTPUT INVERTER CONTROL
Figure 5.28: Simulation of the micro-inverter with digitized controller.
187
CHAPTER 5. OUTPUT INVERTER CONTROL
188
Figure 5.29: Experimental results of the micro-inverter output for full power injection.
It is worth mentioning that before start-up the output current is not zero because of
the effect of the grid voltage on the output filter. This current is reactive current and
its amplitude depends on the grid voltage and the impedance of the output filter.
5.14
Summary
This chapter discusses the design and control of higher order filters to reduce the size
of the converter. A new design of an optimum control scheme is proposed to stabilize
the output current injection and to actively damp the oscillating mode of this filter.
The proposed control structure uses optimal control techniques and optimally assigns
closed-loop poles to locations that meet control objectives. An improved version
of the LQR technique is developed and used to suit single-phase PV applications.
The improvement involved solving the tracking problem rather than the regulation
CHAPTER 5. OUTPUT INVERTER CONTROL
189
Figure 5.30: Experimental results for a step change in the input power from full power
to half power
Figure 5.31: The effect of the controller introduced in Section 5.11 on the transient
of the output current in the startup
CHAPTER 5. OUTPUT INVERTER CONTROL
190
problem. Moreover, a resonant-type controller is incorporated to ensure zero steadystate error. Coefficients of this controller are optimally obtained using the improved
LQR
technique in a systematic method to arrive at a desirable response. Moreover,
a new controller and design method are proposed to minimize the start-up inrush
current. Finally, problems regarding digitization of such controllers are discussed and
suitable tool and method are described to solve them.
Chapter 6
Summary and Future Work
6.1
Summary of Contributions
In this thesis, analysis, design and experimental verification of a micro-inverter for PV
system have been presented. The objective of the proposed micro-inverter system is
to eliminate electrolytic capacitors and to achieve an inverter with high efficiency and
compact size. The main contributions and conclusions of this thesis are summarized
below.
(i) To eliminate electrolytic capacitors, a new power decoupling method is proposed. This method does not use any auxiliary circuits or additional stages and
minimizes the number of components. The proposed method keeps the input
voltage ripple within an acceptable range to maximize the power extraction efficiency by taking advantage of both the high switching frequency of the first
stage and a wide-band controller on the PV side.
(ii) A two-stage micro-inverter has been proposed by cascading an APWM series
191
CHAPTER 6. SUMMARY AND FUTURE WORK
192
resonant converter with a full bridge inverter. The APWM series resonant converter offers a compact, efficient and isolated topology with the capability of
switching at the high frequency essential to implement the power decoupling
method. A complete steady state analysis is carried out to arrive at a converter
design that can handle the large double grid frequency oscillations without losing
zero voltage switching. Moreover, variable frequency and variable bus voltage
control methods are proposed to extend the operating range of the converter
with guaranteed soft switching and also to minimize conduction losses.
(iii) At the input of the converter, the PV module is a highly nonlinear element.
In addition, high frequency oscillations and double frequency oscillations both
represent large signal variations in the converter operating points. Together
these characteristics make the analysis and design of the control system cumbersome. In this thesis, a nonlinear model of the converter is developed and
using a linearization technique and elimination of internal decoupled dynamics,
a simplified small signal model is derived. This model is used to design a controller to obtain the desired performance. The stability of the APWM resonant
converter and the associated control system is also studied.
(iv) A nonlinear control method is proposed based on controlling the instantaneous
power directly rather than controlling the active and reactive powers independently. The design procedure and stability analysis of the resulting system are
also elaborated. It is shown that the proposed method (i) does not require the
calculation of active and reactive powers, (ii) is not sensitive to grid frequency
variations, (iii) is robust against grid harmonics, (iv) is highly immune to noise
and distortions, (v) is suitable for digital implementation and (vi) can generate
CHAPTER 6. SUMMARY AND FUTURE WORK
193
high quality output current.
(v) Because of the proposed decoupling method, the bus voltage contains a dc component and a double grid frequency component. To regulate the average bus
voltage, a control loop is proposed based on controlling the energy. The choice
of state variables and the special notch filter in the loop make the original nonlinear system globally linear and facilitate the design of controller. Since this
system is time varying, the Lyapunov method is used to prove the stability.
(vi) An optimal current controller is proposed, based on a modified version of the
classical LQR method. The controller obtained using this method exhibits
strong robustness features because it is the unique global solution of a welldefined quadratic cost function. Furthermore, a systematic design approach is
developed to find optimum coefficients of the controller; a blind search is not
practical and may result in compromised solutions.
(vii) An optimum control strategy and design method are introduced to minimize
the inrush current at the startup of the system. The peak of this current is
particularly large in the micro-inverter design. This is because the impedance
of the LCL-filter, which connects the inverter to the grid, is small, and any
error of the inverter at the startup can create a very large transient at the grid
current.
(viii) The proposed analysis, methods and control structures are simulated and verified in an experimental setup. A maximum of 88% overall system efficiency was
recorded.
CHAPTER 6. SUMMARY AND FUTURE WORK
6.2
194
Suggested Future Work
There are a number of directions that this research could proceed in; three of the
most promising are outlined below.
(i) The dual of the proposed voltage source topology is a current source topology.
The feasibility of these types of converters for PV applications have been studied
but not included in this thesis. They have shown very promising results and an
experimental setup is required for the comparison of these topologies.
(ii) Since the output filter has three passive elements, the control system used for
the output current requires three sensors. The proposed method in this thesis
has eliminated one of the sensors. A state estimator can also be used to estimate
the grid current from the measurements of inverter current or vice versa. This
would obviate the need to sense the grid current.
(iii) The modification of the LQR for tracking problems for sinusoidal reference signals is proposed in Chapter 5. Existence of the solution and proof of the method
for a general input signal should be investigated.
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Appendix A
PV Cell Characteristic
A PV cell converts irradiation into dc power. An ideal solar cell can be represented
by a current source connected in parallel with a rectifying diode. For an output
voltage less than the open circuit voltage, the PV cell acts as a constant current
source and for an output current less than the short circuit current, the PV provides
a constant voltage. A PV module or panel is made of many PV cells in series. The
PV module chosen for micro-inverter has I-V characteristics similar to those shown
in Fig. A.1. As temperature increases, the band gap of the intrinsic semiconductor
shrinks, and the open circuit voltage VOC decreases. It can be seen that he short
circuit current and the open circuit voltage vary significantly with the insulation level
and the temperature of the cell respectively. The graphs in Fig. A.1 show that for
lower temperature the output voltage of the pv cell increases and the output power
also increases. The output voltage and current of the PV cell determine its operating
point and thus stipulate the output power of the cell. Therefore as shown in Fig. A.1,
if either voltage or current of a PV cell is controlled the other one can be determined
using the I-V characteristics, irradiation level and cell temperature. It is important
207
208
APPENDIX A. PV CELL CHARACTERISTIC
to note that from electrical point of view it suffices to model the I-V curve of the
PV to simulate a PV array. Moreover, it is also worth mentioning that the graphs
shown in Fig. A.1 are slightly exaggerating the dependency of PV to temperature.
The reason for that is to generate a model that covers a wider range of PV voltage
for the simulation and test purposes.
150
4
Irradidation
2
0
0
6
Current (A)
Power (W)
Irradidation
20
40
Voltage (V)
(a)
Tc = 80
2
0
0
◦
20
40
Voltage (V)
(c)
50
0
200
Tc = 0◦
4
100
0
60
60
Power (W)
Current(A)
6
20
40
Voltage (V)
(b)
60
Tc = 0◦
150
100
50
0
Tc = 80◦
0
20
40
Voltage (V)
(d)
60
Figure A.1: Typical Voltage-current characteristics of PV cells for (a) different irradiation levels, (c) different temperatures and typical Voltage-Power
characteristics of PV cells for (b) different irradiation levels, (d) different
temperatures.
209
APPENDIX A. PV CELL CHARACTERISTIC
A.0.1
PV Cell Modeling
The building block of the PV array is the solar cell, which is basically a p − n semiconductor junction that directly converts light energy into electricity. The equivalent
circuit is shown in Fig. A.2. This equivalent circuit is used in the simulations where
the PV output current, IPnlV , can be determined as described below.
IPnlV
= Iph − Irs exp
q VP V
kT A ns
−1
(A.1)
where IPnlV is the PV array output current (A) when there is no loss; VP V is the
PV array output voltage (V); ns is the number of cells connected in series; q is the
charge of an electron; k is Boltzmanns constant; A is the p−n junction ideality factor;
T is the cell temperature (K); and Irs is the cell reverse saturation current. In the
model shown in Fig. A.2, Rs and Rsh represent short circuit and open circuit power
losses in a PV cell. The factor A in (A.1) determines the cell deviation from the ideal
p − n junction characteristics. The ideal value ranges from 1 to 5 and in our case, A
equals 2.15. The cell reverse saturation current Irs varies with temperature and the
photocurrent Iph depends on the solar radiation and the cell temperature as shown
nl
IPV
Iph
ID
IPV
Rs
+
Rsh
VPV
_
Figure A.2: Equivalent circuit for a PV cell.
210
APPENDIX A. PV CELL CHARACTERISTIC
in the following equation:
Iph = [Iscr + ki (T − Tr )]
s
100
(A.2)
where Iscr is the cell short-circuit current at reference temperature and radiation,
ki is the short-circuit current temperature coefficient, and s is the solar radiation
in mW/cm2 . Using this PV array model it is possible to simulate the dynamic
performance of the power and control systems and MPPT strategy in response to
the radiation and temperature step changes. This equivalent circuit is used in the
simulation software (PSIM and MATLAB) to represent the PV source.
Appendix B
Micro-inverter PSIM Simulation
Schematics
In this section the PSIM simulation Schematics for the power circuit along with the
control systems are shown. The sampling frequency for the inverter is 80Khz and
that of PV signals is 800Khz. All control circuits are implemented in discrete time
systems, suitable for FPGA design. Since all calculations are fixed point with finite
word length, in PSIM simulations the number of bits at the input and after each
calculations are carefully considered and scalings are chosen so as to minimize the
fixed point calculations error. The implementation of the notch filter and resonant
controllers are all carried out in delta domain to optimize the quantization and roundoff errors as explained in section 5.12. Figures B.1, B.2 and B.3 show schematics to
verify the concepts of control structures. The power circuit and signal conditioning
circuits are simulated in PSIM as shown in figures B.4, B.5 and B.6. The controllers
are simulated in VHDL code by ModelSim, see appendix C, and the whole system is
simulated by connecting these two software programs with MATLAB.
211
APPENDIX B. MICRO-INVERTER PSIM SIMULATION SCHEMATICS
212
Figure B.1: First stage of the power circuit and the associated control systems
APPENDIX B. MICRO-INVERTER PSIM SIMULATION SCHEMATICS
213
Figure B.2: second stage of the power circuit and the associated control systems
APPENDIX B. MICRO-INVERTER PSIM SIMULATION SCHEMATICS
Figure B.3: Digital implementation of the enhanced phase lock loop
214
APPENDIX B. MICRO-INVERTER PSIM SIMULATION SCHEMATICS
Figure B.4: First stage of the power circuit and the associated circuits
215
APPENDIX B. MICRO-INVERTER PSIM SIMULATION SCHEMATICS
Figure B.5: Inverter and the associated circuits
216
APPENDIX B. MICRO-INVERTER PSIM SIMULATION SCHEMATICS
Figure B.6: Output filter and the associated circuits
217
Appendix C
VHDL Code
This section presents the VHDL codes to implement the control structure of the
micro-inverter.
library ieee;
use ieee.std_logic_1164 .all;
use ieee.numeric_std.all;
package my_sine_package is
constant max_table_value : integer := 255;
constant max_table_index : integer := 127;
constant output_range : integer := 9;
constant input_range : integer := 11;
constant
constant
constant
constant
constant
constant
constant
constant
ninty :integer := max_table_index ;
ninty1 :integer := max_table_index +1;
one_eighty :integer := (max_table_index +1)*2-1;
two_seventy :integer := (max_table_index +1)*3-1;
two_pi : integer := (max_table_index +1)*4-1;
ponsad : signed := "0000111111111 ";
REFGEN_INWIDTH : INTEGER := 10;
REFGEN_OUTWIDTH : INTEGER := 9;
constant BP_INWIDTH: INTEGER := 16;
constant BP_OUTWIDTH: INTEGER := 16;
constant LP_INWIDTH: INTEGER := 11;
constant LP_OUTWIDTH: INTEGER := 11;
constant MYOUTPUT: INTEGER := 16;
constant
constant
constant
constant
constant
constant
constant
constant
constant
constant
constant
constant
ADWIDTH: INTEGER := 16;
ADWIDTHR: INTEGER := 11;
Pcoef : integer :=6;
P_vdc : integer :=5;
Vdc_ref : signed(10 downto 0) := "00110101010";
Iref_coef : integer :=7;
Igrid_coef1 : SIGNED(5 DOWNTO 0) :="010110";
Igrid_coef : integer :=5;
IL1_coef : integer :=1;
Vgrid_coef : integer :=3;
DIVIDE_COEF : integer :=9;
PWM_COEF : integer :=12;
subtype table_index_type is integer range 0 to max_table_value ;
218
APPENDIX C. VHDL CODE
subtype table_value_type is integer range 0 to max_table_value ;
function get_table_value (table_index: table_index_type ) return table_value_type ;
function mysin (theta : signed) return signed;
function mycos (theta : signed) return signed;
Component regne
Generic(N:integer := 4);
Port(R :IN Std_logic_vector (N-1 downto 0);
Resetn :IN std_logic;
E,Clock:IN std_logic;
Q :OUT Std_logic_vector (N-1 downto 0));
END component;
Component shiftlne is
Generic(N:integer := 4);
Port(R :IN Std_logic_vector (N-1 downto 0);
L,E,W :IN std_logic;
Clock :IN std_logic;
Q :BUFFER Std_logic_vector (N-1 downto 0));
END component;
component muxdff is
Port(D0,D1,Sel,clock :IN std_logic;
Q :OUT Std_logic);
END component;
component downcnt is
Generic(modulus :integer := 8);
Port(Clock,E,L :IN std_logic;
Q :Buffer integer range 0 to modulus-1);
END component;
component divider IS
Generic (N : integer :=8);
PORT(Clock :IN STD_logic;
Resetn :IN STD_logic;
s,LA,EB :IN STD_logic;
DataA :IN std_logic_vector (N-1 downto 0);
DataB :IN std_logic_vector (N-1 downto 0);
R,Q :Buffer std_logic_vector (N-1 downto 0);
Done :OUT std_logic);
End component;
end my_sine_package ;
package body my_sine_package is
function mycos (theta : signed) return signed is
variable theta_var : signed(input_range-1 downto 0) := (others => ’0’);
variable myout : signed(output_range -1 downto 0);
begin
theta_var := theta + to_signed(ninty1,input_range);
myout := mysin(theta_var);
return myout;
end;
function mysin (theta : signed) return signed is
variable theta_var, theta_o4, Ain, Bin : signed(input_range-1 downto 0) := (others => ’0’);
variable negative_cycle : signed(1 downto 0) := (others => ’0’);
variable theta_i : integer range 0 to 511;
variable table_value: table_value_type ;
variable myout : signed(output_range -1 downto 0);
variable table_index: table_index_type ;
begin
theta_var := theta and resize(ponsad, input_range);
theta_i := to_integer(theta_var);
if theta_i <= ninty then Ain := theta_var;
elsif theta_i <= one_eighty then Ain := to_signed(one_eighty, input_range);
elsif theta_i <= two_seventy then Ain := theta_var;
elsif theta_i <= two_pi then Ain := to_signed(two_pi, input_range);
else Ain := (others => ’0’);
end if;
if theta_i <= ninty then Bin := (others => ’0’);
elsif theta_i <= one_eighty then Bin := theta_var;
219
APPENDIX C. VHDL CODE
elsif theta_i <= two_seventy then Bin := to_signed(one_eighty, input_range);
elsif theta_i <= two_pi then Bin := theta_var;
else Bin := (others => ’0’);
end if;
theta_o4 := Ain-Bin;
if (theta_i <= one_eighty) or (Ain = Bin) then negative_cycle := "00";
else negative_cycle := "01";
end if;
if (theta_i > one_eighty) and (theta_i <= two_seventy) then
theta_o4 := theta_o4 - negative_cycle ;
else null;
end if;
table_index := to_integer(theta_o4);
table_value := get_table_value ( table_index );
if (negative_cycle = "00") then
myout := to_signed(table_value, output_range );
else
myout := to_signed(-table_value , output_range );
end if;
return myout;
end;
function get_table_value (table_index: table_index_type ) return table_value_type is
variable table_value : table_value_type ;
begin
case table_index is
when 0 =>
table_value := 2;
when 1 =>
table_value := 5;
.
.
.
when 125 =>
table_value := 255;
when 126 =>
table_value := 255;
when 127 =>
table_value := 255;
when others =>
table_value := 0;
end case;
return table_value;
end;
end my_sine_package ;
library ieee;
use ieee.std_logic_1164 .all;
Entity regne is
Generic(N:integer := 4);
Port(R :IN Std_logic_vector (N-1 downto 0);
Resetn :IN std_logic;
E,Clock:IN std_logic;
Q :OUT Std_logic_vector (N-1 downto 0));
END regne;
Architecture behavior of regne is
begin
process(resetn, clock)
begin
if resetn = ’0’ then
q <= (others =>’0’);
elsif clock’event and clock = ’1’ then
if E=’1’ then
q <=R;
end if;
end if;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164 .all;
Entity shiftlne is
220
APPENDIX C. VHDL CODE
Generic(N:integer := 4);
Port(R :IN Std_logic_vector (N-1 downto 0);
L,E,W :IN std_logic;
Clock :IN std_logic;
Q :BUFFER Std_logic_vector (N-1 downto 0));
END shiftlne;
Architecture behavior of shiftlne is
begin
process
begin
wait until clock’event and clock=’1’;
if L=’1’ then
Q <= R;
elsif E=’1’ then
Q(0) <= w;
Genbits: for i in N-1 downto 1 loop
Q(i) <= Q(i-1);
end loop;
end if;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164 .all;
Entity muxdff is
Port(D0,D1,Sel,clock :IN std_logic;
Q :OUT Std_logic);
END muxdff;
Architecture Behavior OF muxdff IS
Begin
Process
begin
Wait until Clock’event and Clock=’1’;
IF Sel = ’0’ then
Q <= D0;
Else
Q <= D1;
End if;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164 .all;
Entity downcnt is
Generic(modulus :integer := 8);
Port(Clock,E,L :IN std_logic;
Q :Buffer integer range 0 to modulus-1);
END downcnt;
Architecture behavior of downcnt IS
Signal Count : Integer Range 0 to modulus-1;
Begin
Process
begin
Wait until (Clock’event and Clock=’1’);
IF L=’1’ then
Count <= modulus-1;
else
IF E=’1’ then
Count <= Count-1;
END if;
end if;
end process;
Q <= Count;
End Behavior;
library ieee;
use ieee.std_logic_1164 .all;
use ieee.numeric_std.all;
use work.my_sine_package .all;
Entity divider IS
Generic (N : integer :=16);
PORT(Clock :IN STD_logic;
Resetn :IN STD_logic;
s,LA,EB :IN STD_logic;
DataA :IN std_logic_vector (N-1 downto 0);
221
APPENDIX C. VHDL CODE
DataB :IN std_logic_vector (N-1 downto 0);
R,Q :Buffer std_logic_vector (N-1 downto 0);
Done :OUT std_logic);
End divider;
Architecture behavior OF divider IS
TYPE State_type is (S1,S2,S3);
Signal y:state_type;
Signal Zero,Cout,z : std_logic;
signal EA,Rsel,LR,ER,ER0,LC,EC,R0 : std_logic;
signal A,B,DataR: std_logic_vector (N-1 downto 0);
signal sum : std_logic_vector (N downto 0); -- adder outputs
signal Count: INTEGER RANGE 0 TO N-1;
BEGIN
FSM_transitions : PROCESS ( Resetn, clock)
BEGIN
IF Resetn =’0’ THEN y <= S1;
ELSIF (Clock’EVENT AND Clock =’1’) THEN
CASE y is
WHEN S1 =>
IF s=’0’ THEN y <= S1 ;
ELSE y <= S2;
END IF;
WHEN S2 =>
IF z=’0’ THEN y <= S2 ;
ELSE y <= S3;
END IF;
WHEN S3 =>
IF s=’1’ THEN y <= S3 ;
ELSE y <= S1;
END IF;
END CASE;
END IF;
END PROCESS;
FSM_outputs: PROCESS (s,y,Cout,z)
BEGIN
LR <= ’0’; ER <= ’0’; ER0 <= ’0’;
LC <= ’0’; EC <= ’0’; EA <=’0’; Done <= ’0’;
Rsel <= ’0’;
CASE y IS
WHEN S1 =>
LC <= ’1’; ER <= ’1’;
IF s=’0’ THEN
LR <= ’1’; EA<=’0’;ER0<=’0’;
ELSE
LR <= ’0’; EA<=’1’;ER0<=’1’;
END IF;
WHEN S2 =>
Rsel <= ’1’; ER <=’1’;ER0<=’1’;EA<=’1’;
IF Cout =’1’ THEN
LR <= ’1’;
ELSE LR <=’0’;
END IF;
IF z=’0’ THEN
EC <=’1’;
ELSE EC<=’0’;
END IF;
WHEN S3 =>
Done <=’1’;
END CASE;
END PROCESS;
--DEFINE THE DATA PASS CIRCUIT
Zero <= ’0’;
RegB: regne
GENERIC MAP (N => N)
PORT MAP (DataB,Resetn,EB,Clock,B);
shiftR: shiftlne
GENERIC MAP (N => N)
PORT MAP (DataR,LR,ER,R0,Clock,R);
FF_R0: muxdff
PORT MAP (Zero,A(N-1),ER0,Clock,R0);
ShiftA: shiftlne
GENERIC MAP (N => N)
PORT MAP (DataA,LA,EA,Cout,Clock,A);
Q <= A;
222
APPENDIX C. VHDL CODE
Counter: downcnt
GENERIC MAP (modulus => N)
PORT MAP (Clock, EC, LC, Count);
z <= ’1’ when Count =0 ELSE ’0’;
Sum <= std_logic_vector (signed (R & R0) + (signed (B(N-1) & NOT B) +1));
Cout <= Sum(N);
DataR <= (OTHERS => ’0’) WHEN Rsel =’0’ ELSE Sum (N-1 downto 0);
END Behavior;
LIBRARY ieee;
USE ieee.std_logic_1164 .ALL;
Use ieee.numeric_std.all;
use work.my_sine_package .all;
ENTITY REFGEN IS
Generic (
Constant INWidth : integer:=10;
Constant OUTWidth : integer:=9;
constant const1 : signed(11 downto 0) := "010111100100"; -- (1508)
Constant eta2 : signed (11 downto 0) := "010000101100 " --(1068)
);
PORT (
sample_CLK: IN std_logic;
higher_clk: IN std_logic;
resetn: IN std_logic;
Uk: IN std_logic_vector (INWidth-1 downto 0);
Yp: OUT std_logic_vector (OUTWidth-1 downto 0);
phase: OUT std_logic_vector (9 downto 0);
OVF : OUT std_logic;
OUT_RDY : OUT STD_LOGIC);
END REFGEN;
ARCHITECTURE RTL OF REFGEN IS
TYPE STATETYPE IS (S0,S1,S2,S3,S4,S5,S6,S7);
Signal CurState : statetype;
signal S_Vgrid : signed(9 downto 0) := (others => ’0’);
signal S_outsin : signed (8 downto 0) := (others => ’0’);
signal S_int2, S_int2_p : signed (17 downto 0) := (others => ’0’);
signal S_int3,S_int3_p, S_temp : signed (15 downto 0) := (others => ’0’);
signal ovf_int2, ovf_int3 : std_logic :=’0’ ;
begin
process(SAMPLE_CLK, resetn)
begin
if resetn=’0’ then
S_int2_p <= (others => ’0’);
S_int3_p <= (others => ’0’);
S_Vgrid <= (others => ’0’);
else
if rising_edge(SAMPLE_CLK) then
S_int2_p <= S_int2;
S_int3_p <= S_int3;
S_Vgrid <= resize (signed(Uk),S_Vgrid’length);
end if;
end if;
end process;
process(higher_clk, resetn)
variable
Variable
variable
variable
variable
variable
variable
variable
variable
Nextstate : statetype;
Vgrid,mul1, theta : signed(9 downto 0) := (others => ’0’);
Vfeedb,Verror, Vamp : signed(11 downto 0) := (others => ’0’);
outsin, outcos : signed (8 downto 0) := (others => ’0’);
int1 : signed (13 downto 0) := (others => ’0’);
int2,int2_p, int2_ex, maxnumber : signed (17 downto 0) := (others => ’0’);
int4,int3,int3_p, int3_ex, maxnumber1 : signed (15 downto 0) := (others => ’0’);
sum1 : signed (16 downto 0) := (others => ’0’);
OVF_P, flag :std_logic :=’0’ ;
begin
if resetn=’0’ then
Yp <= (others => ’0’);
phase <= (others => ’0’);
OVF <= ’0’;
OVF_p := ’0’;
223
APPENDIX C. VHDL CODE
OUT_RDY <= ’0’;
NextState:= S7;
CurState <= S7;
Vgrid := (others => ’0’);
int2_p := (others => ’0’);
int3_p := (others => ’0’);
theta := (others => ’0’);
outsin :=(others => ’0’);
Vamp :=(others => ’0’);
Vfeedb :=(others => ’0’);
outcos :=(others => ’0’);
Verror :=(others => ’0’);
int4 :=(others => ’0’);
int1 :=(others => ’0’);
int2 :=(others => ’0’);
int3 :=(others => ’0’);
sum1 := (others => ’0’);
mul1 :=(others => ’0’);
int2_ex :=(others => ’0’);
ovf_int2 <= ’0’;
int3_ex := (others => ’0’);
end if;
end if;
end process;
end RTL;
LIBRARY ieee;
USE ieee.std_logic_1164 .ALL;
Use ieee.numeric_std.all;
package lowpass_pack is
Constant ADWidth : integer:=11;
Constant OUTWidth : integer:=11;
constant
constant
constant
constant
subtype
subtype
subtype
subtype
burden : integer :=6;
delta1 : integer := 2;
alfa0shift : integer := 14;
alfa00shift : integer := 14-burden;
Int1_type is signed (15 downto 0);
Int2_type is signed (16 downto 0); -- NOTE size of (alfa1 or beta1)+int2<32
Int3_type is signed (20 downto 0); -- NOTE size of (alfa2 or beta2)+int3<32
myout is signed (ADWidth-1 downto 0);
constant
constant
constant
constant
Int1high : integer := 2**Int1_type’left-1;
Int2high : integer := 2**Int2_type’left-1;
Int3high : integer := 2**Int3_type’left-1;
outhigh : integer := 2**myout’left-1;
constant
constant
constant
constant
Int1low : integer := -2**Int1_type’left+1;
Int2low : integer := -2**Int2_type’left+1;
Int3low : integer := -2**Int3_type’left+1;
outlow : integer := -2**myout’left+1;
constant
constant
constant
constant
constant
alfa1
alfa2
beta0
beta1
beta2
:
:
:
:
:
signed
signed
signed
signed
signed
(10 downto 0) := "10111000110";
(5 downto 0) := "101001";
(7 downto 0) := "01000110";
(10 downto 0) := "01000110011";
(1 downto 0) := "00";
end lowpass_pack;
LIBRARY ieee;
USE ieee.std_logic_1164 .ALL;
Use ieee.numeric_std.all;
use ieee.std_logic_misc .or_reduce;
use ieee.std_logic_misc .and_reduce;
USE work.lowpass_pack .all;
ENTITY lowpass IS
PORT (
-- CLK: IN std_logic;
sample_CLK: IN std_logic;
higher_clk: IN std_logic;
resetn: IN std_logic;
Uk: IN std_logic_vector (ADWidth-1 downto 0);
224
APPENDIX C. VHDL CODE
Yp: OUT std_logic_vector (OUTWidth-1 downto 0);
OVF : OUT std_logic;
OUT_RDY : OUT STD_LOGIC);
END lowpass;
ARCHITECTURE RTL OF lowpass IS
TYPE STATETYPE IS (S0,S1,S2,S3,S4,S5,S6,S7);
Signal int1_p, int1_p_r, int1_p_s, int1 : Int1_type := (others => ’0’);
Signal u_p, y_out : myout := (others => ’0’);
signal int3_p, int3, int3_ex : Int3_type := (others => ’0’);
signal int2_p_r, int2_p_s, int2_p, int2, int2_ex, test : Int2_type := (others => ’0’);
signal a1_int2, u_s, a2_int3, b1_int2, b0_int1, b2_int3 : signed (31-burden downto 0) := (others => ’0’);
signal sum1, int1_28, sum2, temp1, temp2, u_s_temp : signed (33-burden downto 0) := (others => ’0’);
signal ovf_int1 , ovf_int2, ovf_int3, ovf_y, mybitp, mybitn, mybitp1, mybitn1, OVF_p, flag1, flag2 :std_logic :=’0’ ;
--signal std_temp : std_logic_vector (33-burden-Int1_type’left downto 0) := (others => ’0’);
--signal std_temp1 : std_logic_vector (33-burden-myout’left downto 0) := (others => ’0’);
SIGNAL int1_out: std_logic_vector (Int1_type’left downto 0);
Signal CurState : statetype;
constant maxhigh: Int2_type := to_signed(Int2high , Int2_type’left+1) ;
constant minlow: Int2_type := to_signed(Int2low,Int2_type’left+1);
constant maxhigh1: Int3_type := to_signed(Int3high,Int3_type’left+1) ;
constant minlow1: Int3_type := to_signed(Int3low,Int3_type’left+1);
constant maxhigh0: Int1_type := to_signed(Int1high , Int1_type’left+1);
constant minlow0: Int1_type := to_signed(Int1low, Int1_type’left+1);
constant maxhighy: myout := to_signed(outhigh , myout’left+1);
constant minlowy: myout := to_signed(outlow, myout’left+1);
begin
process(SAMPLE_CLK, resetn)
begin
if resetn=’0’ then
int2_p <= (others => ’0’);
int3_p <= (others => ’0’);
u_p <= (others => ’0’);
else
if rising_edge(SAMPLE_CLK) then
int2_p <= int2;
int3_p <= int3;
u_p <= resize (signed(Uk),u_p’length);
end if;
end if;
end process;
process(higher_clk, resetn)
variable Nextstate : statetype;
variable Varu_s : signed (31-burden downto 0);
variable std_temp : std_logic_vector (33-burden-Int1_type’left downto 0);
variable std_temp1 : std_logic_vector (33-burden-myout’left downto 0);
variable y_out1 : signed (33-burden downto 0);
VARIABLE ovf_p : STD_LOGIC;
begin
if resetn=’0’ then
Yp <= (others => ’0’);
OVF <= ’0’;
ovf_p := ’0’;
OUT_RDY <= ’0’;
NextState:= S7;
CurState <= S7;
Varu_s:= (others => ’0’);
temp1 <= (others => ’0’);
sum1 <= (others => ’0’);
a1_int2 <=(others => ’0’);
225
APPENDIX C. VHDL CODE
int2_p_s <=(others => ’0’);
b1_int2 <=(others => ’0’);
a2_int3 <=(others => ’0’);
b2_int3 <=(others => ’0’);
int1_28 <=(others => ’0’);
temp2 <=(others => ’0’);
int3_ex <=(others => ’0’);
std_temp := (others => ’0’);
std_temp1 := (others => ’0’);
int2_p_s <=(others => ’0’);
int3_ex <=(others => ’0’);
int2_ex <=(others => ’0’);
b0_int1 <=(others => ’0’);
y_out1 := (others => ’0’);
y_out <= (others => ’0’);
sum2 <= (others => ’0’);
int1 <= (others => ’0’);
int2 <= (others => ’0’);
int3 <= (others => ’0’);
ovf_int1
ovf_int2
ovf_int3
ovf_y <=
<= ’0’;
<=’0’;
<=’0’;
’0’;
else
if rising_edge(higher_clk) then
case CurState Is
when s7 => OUT_RDY <= ’0’;
if SAMPLE_CLK=’1’ then
NextState:=S0;
else NextState:=S7;
end if;
when S0 => Varu_s:= shift_left (resize(u_p, u_s’length), alfa00shift);
sum1 <= resize(Varu_s, sum1’length) + temp1;
a1_int2 <= resize(shift_right (int2_p*alfa1, burden), a1_int2’length);
int2_p_s <= shift_right (int2_p , delta1);
b1_int2 <= resize(shift_right (int2_p*beta1, burden), b1_int2’length);
a2_int3 <= resize(shift_right (int3_p*alfa2, burden), a2_int3’length);
b2_int3 <= resize(shift_right (int3_p*beta2, burden), b2_int3’length);
NextState:=S1;
when S1 => int1_28 <= shift_right (sum1, alfa0shift-burden);
temp1 <= resize(a1_int2, temp1’length)+resize(a2_int3, temp1’length);
temp2 <= resize(b1_int2, temp2’length)+resize(b2_int3, temp2’length);
int3_ex <= int2_p_s + int3_p;
NextState:=S2;
when S2 => std_temp := std_logic_vector (int1_28 (33-burden downto Int1_type’left));
if ( (int1_28 (33-burden)= ’0’) and (or_reduce (std_temp)= ’1’) ) then
int1 <= maxhigh0;
ovf_int1 <= ’1’;
elsif ( (int1_28 (33-burden)= ’1’) and (and_reduce (std_temp)= ’0’)) then
int1 <= minlow0;
ovf_int1 <= ’1’;
else
int1 <= int1_28 (Int1_type’left downto 0);
ovf_int1 <= ’0’;
end if;
if (( int2_p_s(Int2_type’left)= ’0’) and
( int3_p(Int3_type’left)= ’0’) and int3_ex(Int3_type’left)= ’1’ ) then
int3 <= maxhigh1;
ovf_int3 <= ’1’;
elsif ( (int2_p_s(Int2_type’left)= ’1’) and
(int3_p(Int3_type’left)= ’1’) and ( int3_ex(Int3_type’left)= ’0’)) then
int3 <= minlow1;
ovf_int3 <= ’1’;
else
226
APPENDIX C. VHDL CODE
int3 <= int3_ex;
ovf_int3 <= ’0’;
end if;
NextState:=S3;
when S3 => int2_ex <= shift_right (int1 , delta1) + int2_p;
b0_int1 <= resize(shift_right (int1*beta0, burden), b0_int1’length);
NextState:=S4;
when S4 =>
sum2 <= temp2 + resize(b0_int1, sum2’length);
if ((int1(Int1_type’left) = ’0’) and
( int2_p(Int2_type’left) =’0’) and (int2_ex(Int2_type’left)=’1’) ) then
int2 <= maxhigh;
ovf_int2 <= ’1’;
elsif ( (int1(Int1_type’left)=’1’) and
(int2_p(Int2_type’left)=’1’) and ( int2_ex(Int2_type’left)=’0’) ) then
int2 <= minlow;
ovf_int2 <= ’1’;
else
int2 <= int2_ex;
ovf_int2 <= ’0’;
end if;
NextState:=S5;
when S5 => y_out1 := u_p-shift_right (sum2, alfa00shift);
std_temp1 := std_logic_vector (y_out1 (33-burden downto myout’left));
if ((y_out1 (33-burden)= ’0’) and (or_reduce (std_temp1)= ’1’ )) then
y_out <= maxhighy;
ovf_y <= ’1’;
elsif ( (y_out1 (33-burden)= ’1’) and (and_reduce (std_temp1)= ’0’)) then
y_out <= minlowy;
ovf_y <= ’1’;
else
y_out <= y_out1 (myout’left downto 0);
ovf_y <= ’0’;
end if;
NextState:=S6;
when S6 => Yp <= std_logic_vector (resize(y_out,Yp’length));
OVF_P := ovf_p or ovf_int1 or ovf_int2 or ovf_int3 or ovf_y;
OVF <= ovf_p;
OUT_RDY <= ’1’;
if SAMPLE_CLK=’0’ then
NextState:=S7;
else
NextState:=S6;
end if;
when others => Null;
end case;
CurState <= NextState;
end if;
end if;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164 .all;
use ieee.numeric_std.all;
use work.my_sine_package .all;
ENTITY Invcontroller IS
PORT (
sample_CLK: IN std_logic;
higher_clk: IN std_logic;
Vhigher_clk: IN std_logic;
resetn: IN std_logic;
ResetController : IN std_logic;
227
APPENDIX C. VHDL CODE
OVP : IN std_logic;
VGRID : IN std_logic_vector (ADWIDTH-1 downto 0);
VDC : IN std_logic_vector (ADWIDTH-1 downto 0);
Ipv : IN std_logic_vector (ADWIDTH-1 downto 0);
Vpv : IN std_logic_vector (ADWIDTH-1 downto 0);
Igrid : IN std_logic_vector (ADWIDTH-1 downto 0);
IL1 : IN std_logic_vector (ADWIDTH-1 downto 0);
Yp: OUT std_logic_vector (MYOUTPUT-1 downto 0);
Phase: OUT std_logic_vector (9 downto 0);
Testing: OUT std_logic_vector (REFGEN_OUTWidth -1 downto 0);
LPFOut: OUT std_logic_vector (LP_OUTWidth-1 downto 0);
-- TestBPFH: OUT std_logic_vector(BP_OUTWIDTH-1 downto 0);
OVF : OUT std_logic;
Ready_Modulator : OUT std_logic
-- IL: out std_logic_vector(11 downto 0)
);
end Invcontroller ;
ARCHITECTURE control OF Invcontroller IS
component divider IS
Generic (N : integer :=8);
PORT(Clock :IN STD_logic;
Resetn :IN STD_logic;
s,LA,EB :IN STD_logic;
DataA :IN std_logic_vector (N-1 downto 0);
DataB :IN std_logic_vector (N-1 downto 0);
R,Q :Buffer std_logic_vector (N-1 downto 0);
Done :OUT std_logic
);
End component;
Component REFGEN
PORT (
sample_CLK: IN std_logic;
higher_clk: IN std_logic;
resetn: IN std_logic;
Uk: IN std_logic_vector (REFGEN_INWIDTH -1 downto 0);
Yp: OUT std_logic_vector (REFGEN_OUTWidth -1 downto 0);
phase: OUT std_logic_vector (9 downto 0);
OVF : OUT std_logic;
OUT_RDY : OUT std_logic
);
end component;
component BandpassFH
PORT (
sample_CLK: IN std_logic;
higher_clk: IN std_logic;
resetn: IN std_logic;
Uk: IN std_logic_vector (BP_INWIDTH-1 downto 0);
Yp: OUT std_logic_vector (BP_OUTWIDTH-1 downto 0);
OVF : OUT std_logic;
OUT_RDY : OUT std_logic
);
end component;
Component lowpass
PORT (
sample_CLK: IN std_logic;
higher_clk: IN std_logic;
resetn: IN std_logic;
Uk: IN std_logic_vector (LP_INWIDTH-1 downto 0);
Yp: OUT std_logic_vector (LP_OUTWidth-1 downto 0);
OVF : OUT std_logic;
OUT_RDY : OUT std_logic
);
end component;
TYPE STATETYPE IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL STATE : STATETYPE;
subtype LP_OUT_TYPE is signed (LP_OUTWidth-1 downto 0);
subtype VDC_error_type is signed (LP_OUTWidth+P_vdc-1 downto 0);
subtype Igrid_type is signed (ADWIDTHR+Igrid_coef-1 downto 0);
subtype IL1_type is signed (ADWIDTHR+IL1_coef-1 downto 0);
subtype Vgrid_type is signed (ADWIDTHR+Vgrid_coef-1 downto 0);
SIGNAL
SIGNAL
SIGNAL
SIGNAL
REFGEN_OUT : std_logic_vector (REFGEN_OUTWidth -1 downto 0):= (others => ’0’);
LOWPASS_OUT : std_logic_vector (LP_OUTWidth -1 downto 0):= (others => ’0’);
VDC_s : std_logic_vector (LP_INWidth-1 downto 0):= (others => ’0’);
BPFH_OUT : std_logic_vector (BP_OUTWidth-1 downto 0):= (others => ’0’);
228
APPENDIX C. VHDL CODE
SIGNAL Ierror_std : std_logic_vector (BP_INWidth-1 downto 0):= (others => ’0’);
SIGNAL REFGEN_OVF, LOWPASS_OVF, Iref_UF, BANDPASS_OVF , START, LOAD_NUM, ENABLE_DEN, DONE :std_logic ;
SIGNAL Ipv_p, Vpv_p, Ipv_p1, Vpv_p1, VGRID_P : signed(ADWIDTHR-1 downto 0) := (others => ’0’);
SIGNAL feedf,freeze_feedf : signed (2*ADWIDTHR-Pcoef-2 downto 0):= (others => ’0’);
-- signal outtemp : signed (adwidth-1 downto 0) := (others => ’0’);
SIGNAL Vdc_Error : VDC_error_type := (others => ’0’);
SIGNAL Iref_amp : signed (VDC_error_type ’left+1 downto 0):= (others => ’0’);
SIGNAL Iref_s, Iref_s1, Igrid_s : Igrid_type:= (others => ’0’);
SIGNAL IL1_s : IL1_type:= (others => ’0’);
SIGNAL Vgrid_s : Vgrid_type:= (others => ’0’);
-- SIGNAL Iref : signed (Igrid_type’left+Iref_coef downto 0) := (others => ’0’);
SIGNAL Ierror : signed (BP_INWIDTH-1 downto 0):= (others => ’0’);
SIGNAL CONT_OUT : SIGNED (BP_OUTWidth +2 downto 0):= (others => ’0’); --UP TO 8 HARMONIC BLCOKS CAN BE ADDED
SIGNAL CONT1_OUT : SIGNED (BP_OUTWidth+3 downto 0):= (others => ’0’); --UP TO 8 HARMONIC BLCOKS CAN BE ADDED
SIGNAL CONT2_OUT : SIGNED (BP_OUTWidth+4 downto 0):= (others => ’0’); --UP TO 8 HARMONIC BLCOKS CAN BE ADDED
SIGNAL BPFH_O1 : SIGNED (BP_OUTWidth-1 downto 0):= (others => ’0’); ---SHOULD BE REMOVED and changed IF HARMONIC BLOCKS ARE
ADDED flag1 <= ’0’;
SUBTYPE DIV_RESULT IS SIGNED (DIVIDE_COEF+2 DOWNTO 0);
SUBTYPE DIVISION_STD IS STD_LOGIC_VECTOR (LOWPASS_OUT’LENGTH+DIVIDE_COEF-1 DOWNTO 0);
SIGNAL NUM, DEN, RESULT : DIVISION_STD := (others => ’0’);
SIGNAL RESULT_P : DIV_RESULT := (others => ’0’);
SUBTYPE PWM_IN_TYPE IS SIGNED (10 DOWNTO 0);
--SIGNAL MODULATOR : PWM_IN_TYPE := (others => ’0’);
SIGNAL BP_RDY, LP_RDY : STD_LOGIC := ’0’;
Signal CurState, CurState_CNT , start_CurState : statetype;
signal startcounter : integer range 0 to 20000;
--- modified by pan
signal test: std_logic_vector (MYOUTPUT-1 downto 0);
BEGIN
DIV_FSM_transients : process(Vhigher_clk, ResetController ) is
begin
IF ResetController = ’0’ THEN STATE <= S0;
elsIF (FALLING_EDGE(VHIGHER_CLK)) THEN
CASE STATE IS
WHEN S0 => STATE <= S1;
WHEN S1 => STATE <= S2;
WHEN S2 => STATE <= S3;
WHEN S3 => IF (DONE = ’0’) THEN STATE <= S3;
ELSE
STATE <= S0;
RESULT_P <= RESIZE(SIGNED(RESULT), RESULT_P’LENGTH);
END IF;
WHEN S4 => STATE <= S0;
WHEN OTHERS => NULL;
END CASE;
ELSE NULL;
end if;
end process;
DIV_FSM_CONTROL : Process (STATE)
begin
CASE STATE IS
WHEN S0 =>
LOAD_NUM <= ’0’;
ENABLE_DEN <= ’0’;
START <= ’0’;
WHEN S1 =>
LOAD_NUM <= ’1’;
ENABLE_DEN <= ’1’;
START <= ’0’;
WHEN S2 =>
LOAD_NUM <= ’0’;
ENABLE_DEN <= ’0’;
START <= ’1’;
WHEN S3 =>
LOAD_NUM <= ’0’;
ENABLE_DEN <= ’0’;
START <= ’0’;
WHEN S4 => NULL;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
SAMPLING_INPUTS : process(SAMPLE_CLK, ResetController )
229
230
APPENDIX C. VHDL CODE
-- VARIABLE Igrid_p, IL1_p :signed(ADWIDTHR-1 downto 0);
VARIABLE Igrid_p :signed(ADWIDTHR-1 downto 0);
variable Nextstate : statetype;
VARIABLE IL1_p :signed(ADWIDTHR-1 downto 0);
begin
if ResetController =’0’ then
Ipv_p <= (others => ’0’);
Vpv_p <= (others => ’0’);
Igrid_p := (others => ’0’);
Igrid_s <= (others => ’0’);
IL1_p := (others => ’0’);
IL1_s <= (others => ’0’);
Vgrid_p <= (others => ’0’);
startcounter <= 0;
start_CurState <=S0;
NextState:=S0;
else
if rising_edge(SAMPLE_CLK) then
Vgrid_p <= RESIZE(SIGNED(Vgrid),Vgrid_P’LENGTH);
IL1_p := RESIZE(SIGNED(IL1),IL1_P’LENGTH);
IL1_s <= SHIFT_LEFT(RESIZE(IL1_P, IL1_type’LEFT+1), IL1_COEF);
Igrid_p := RESIZE(SIGNED(Igrid),Igrid_p’LENGTH);
Igrid_s <= resize(Igrid_p*Igrid_coef1,Igrid_s’length);
Ipv_p <= RESIZE(SIGNED(Ipv),Ipv_p1’LENGTH);
Vpv_p <= RESIZE(SIGNED(Vpv),Vpv_p1’LENGTH);
Case start_CurState Is
when S0 =>
startcounter <= 0;
NextState:=S1;
when S1 =>
if startcounter > 2047 then
NextState:=S2;
else
startcounter <= startcounter +1;
NextState:=S1;
end if;
when S2 => NextState:=S2;
when others=> NextState:=S2;
End case;
start_CurState <=NextState;
end if;
end if;
END process;
REF_GENERATE : process(higher_clk, ResetController )
variable
variable
variable
variable
variable
Nextstate : statetype;
Vdc_e : LP_out_type ;
Iref : signed (Igrid_type’left+Iref_coef downto 0);
flag : std_logic;
count : integer range 0 to 7;
begin
if ResetController =’0’ then
NextState:= S0;
CurState <= S0;
feedf <= (others => ’0’);
Vdc_e := (others => ’0’);
Vdc_Error <= (others => ’0’);
Iref_amp <= (others => ’0’);
Iref := (others => ’0’);
Iref_s <= (others => ’0’);
Iref_s1 <= (others => ’0’);
Iref_UF <= ’0’;
flag:=’0’;
231
APPENDIX C. VHDL CODE
count :=0;
else
if rising_edge(higher_clk) then
case CurState Is
when s0 =>
if SAMPLE_CLK=’1’ then
feedf <= resize(shift_right (Ipv_p*Vpv_p, Pcoef),feedf’length);
if (OVP = ’0’) then
if flag = ’1’ then
count := count+1;
else null;
end if;
if ((count > 4) or (flag =’0’)) then
freeze_feedf <= feedf;
flag := ’0’;
else null;
end if;
else flag:=’1’;
count :=0;
end if;
NextState:=S1;
else NextState:=S0;
end if;
when S1 =>
if LP_RDY=’1’ then
Vdc_e := (signed(Lowpass_OUT) - Vdc_ref);
Vdc_Error <= shift_left ( resize(Vdc_e,Vdc_Error’length) , P_vdc );
NextState:=S2;
else NextState:=S1;
end if;
when S2 =>
Iref_amp <= resize(VDC_error , Iref_amp’length) + resize(freeze_feedf , Iref_amp’length);
NextState:=S3;
when S3 =>
Iref := resize(signed(REFGEN_OUT(REFGEN_OUTWidth -1 downto 1))*Iref_amp, Iref’length) ;
if (Iref_amp(VDC_error_type ’left+1) = ’0’) then
Iref_UF <= ’0’;
else
Iref_UF <=’1’;
end if;
Iref_s1 <= resize(shift_right(Iref, Iref_Coef), Iref_s1’length);
NextState:=S4;
when S4 =>
if Iref_s1 < -11000 then
Iref_s <= to_signed(-11000, Iref_s’LENGTH);
elsif Iref_s1 > 11000 then
Iref_s <= to_signed(11000, Iref_s’LENGTH);
else
Iref_s <= Iref_s1;
end if;
NextState:=S5;
when S5 =>
if SAMPLE_CLK=’0’ then
NextState:=S0;
else
NextState:=S5;
end if;
when others => Null;
end case;
CurState <= NextState;
end if;
end if;
end process;
232
APPENDIX C. VHDL CODE
CONTROL_LOOP : process(higher_clk, ResetController )
Variable
VARIABLE
VARIABLE
Variable
variable
Nextstate : statetype;
OVF_P :STD_LOGIC;
MODULATOR : PWM_IN_TYPE ;
MODULATOR1 : SIGNED (BP_OUTWidth+4+DIVIDE_COEF+3 downto 0);
RESULT_P1 : DIV_RESULT;
begin
if ResetController =’0’ then
NextState:= S0;
CurState_CNT <= S0;
Ierror_std <= (others => ’0’);
CONT_OUT <= (others => ’0’);
CONT1_OUT <= (others => ’0’);
VGRID_S <= (others => ’0’);
CONT2_OUT <= (others => ’0’);
MODULATOR := (others => ’0’);
OVF_p := ’0’;
OVF <= ’0’;
TEST <= (others => ’0’);
Yp <= (others => ’0’);
Ready_Modulator <= ’0’;
MODULATOR1 := (others => ’0’);
Result_p1 := (others => ’0’);
else
if rising_edge(higher_clk) then
case CurState_CNT Is
when s0 =>
if SAMPLE_CLK=’1’ then
Ierror_std <= STD_LOGIC_VECTOR (resize((Iref_s- Igrid_s), BP_INWIDTH));
NextState:=S1;
Ready_Modulator <= ’0’;
else NextState:=S0;
end if;
when S1 =>
if BP_RDY=’1’ then
CONT_OUT <= RESIZE(SIGNED(BPFH_OUT),CONT_OUT’LENGTH); --+BPFH_O1;
NextState:=S2;
else
NextState:=S1;
end if;
WHEN S2 =>
CONT1_OUT <= RESIZE(CONT_OUT-IL1_s, CONT1_OUT’LENGTH);
VGRID_S <= SHIFT_LEFT(RESIZE(VGRID_P, VGRID_TYPE’LEFT+1), VGRID_COEF);
NextState:=S3;
WHEN S3 =>
CONT2_OUT <= RESIZE(CONT1_OUT, CONT2_OUT’LENGTH) + shift_right(VGRID_S,1);
if RESULT_P< 410 then
RESULT_P1 := to_signed(410, RESULT_P1’LENGTH);
elsif RESULT_P >768 then
RESULT_P1 := to_signed(768, RESULT_P1’LENGTH);
else
RESULT_P1 := RESULT_P;
end if;
NextState:=S4;
WHEN S4 =>
MODULATOR1 := SHIFT_RIGHT (CONT2_OUT*RESULT_P1, PWM_COEF); --
NextState:=S5;
WHEN S5 =>
if MODULATOR1< -512 then
MODULATOR1 := to_signed(-511, MODULATOR1’LENGTH);
elsif MODULATOR1 >511 then
MODULATOR1 := to_signed(511, MODULATOR1’LENGTH);
end if;
MODULATOR := RESIZE(MODULATOR1, MODULATOR’LENGTH);
Yp <= std_logic_vector (resize(MODULATOR ,Yp’length));
test <= std_logic_vector (resize(MODULATOR ,test’length));
OVF_P := OVF_P OR REFGEN_OVF OR LOWPASS_OVF OR BANDPASS_OVF;
OVF <= OVF_P;
--Ready_Modulator <= ’1’;
NextState:=S6;
WHEN S6 =>
APPENDIX C. VHDL CODE
if SAMPLE_CLK=’0’ then
Ready_Modulator <= ’1’;
NextState:=S0;
else
NextState:=S6;
end if;
when others => Null;
end case;
CurState_CNT <= NextState;
end if;
end if;
end process;
Testing<=std_logic_vector (resize(signed(REFGEN_OUT(REFGEN_OUTWidth -1 downto 1)),9));
LPFOut<=LOWPASS_OUT;
-- TestBPFH<=BPFH_OUT;
-- IL<=std_logic_vector(IL1_s);
COMP0 : REFGEN
PORT MAP(
sample_CLK => sample_CLK,
higher_clk => higher_CLK,
resetn => resetn,
Uk => VGRID(ADWIDTH-7 DOWNTO 0),
Yp => REFGEN_OUT,
phase => Phase,
OVF => REFGEN_OVF,
OUT_RDY => open
);
COMP1 : LOWPASS
PORT MAP(
sample_CLK => sample_CLK,
higher_clk => higher_CLK,
resetn => resetn,
Uk => VDC_s,
Yp => LOWPASS_OUT,
OVF => LOWPASS_OVF,
OUT_RDY => LP_RDY
);
COMP2 : BandpassFH
PORT MAP(
sample_CLK => sample_CLK,
higher_clk => higher_CLK,
resetn => ResetController ,
Uk => Ierror_std,
Yp => BPFH_OUT,
OVF => BANDPASS_OVF,
OUT_RDY => BP_RDY );
COMP3 : divider
Generic MAP (N => DIVISION_STD ’LEFT+1)
PORT MAP (
Clock => VHIGHER_CLK ,
Resetn => ResetController ,
s => START,
LA => LOAD_NUM,
EB => ENABLE_DEN,
DataA => NUM,
DataB => DEN,
R => OPEN,
Q => RESULT,
Done => DONE
);
VDC_s <= std_logic_vector (resize(signed(VDC),VDC_s’length));
NUM <= STD_LOGIC_VECTOR (SHIFT_LEFT(RESIZE(signed(Lowpass_OUT),DIVISION_STD ’LEFT+1), DIVIDE_COEF ));
DEN <= std_logic_vector (resize(signed(VDC_S),DIVISION_STD ’LEFT+1));
End control;
233