Planar FD-SOI Technology
at 28nm and below
for extremely power-efficient SoCs
J. Hartmann
Executive VP
Front-End Manufacturing & Process R&D
Digital Sector
2
Planar Fully Depleted Technologies:
FD-SOI Advantages
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
Bulk Transistor Reaching Limits at 20nm
FD-SOI = 2D
Limited body bias capability
gate
Weak process compensation
Low process/design co-optimization
Thin Silicon film
Complex channel architecture
High cost process flow (yield, cycle time, capex)
Source of variability (multiple steps)
Source of leakages currents
Heavily Doped Wells
High variability due to dopant fluctuation
Longer minimum gate length (less speed, less density)
Severe layout effects (wells proximity)
drain
height
Depleted devices deliver improved
electrostatic control and device scalability
source
gate
Thin Silicon film
FinFET = 3D
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
3
FD-SOI Provides Unique Value
•
Transistors run at max frequencies up to 30% faster than
bulk CMOS, enabling faster processors
•
This puts more powerful devices in the hands of the end
user
•
Transistors are significantly more power efficient than
bulk CMOS devices with lower leakage and much wider
range of operation points down to lower voltages
•
End user devices run cooler and last longer
•
The manufacturing process for FD-SOI is much simpler
than alternatives and makes extensive use of existing
fab infrastructure
•
Design porting from bulk is simple and fast
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
4
Planar UTBB FD-SOI: Structure &
Advantages
Ultra Thin Body & Box
Thin Silicon Channel
Source
Drain
Burried
oxide
Total dielectric isolation
No channel doping, no pocket implant
•  Lower S/D capacitances
•  Improved VT variation
•  Lower S/D leakages
Ultra-thin BOX option
•  Latch-up immunity
•  Back-bias control
= Faster, Cooler transistors
Ultra-thin Body (TSi~1/3LG)
Ground-plane implantation
•  VT adjustment
•  Excellent short-channel immunity
•  low SCE, DIBL
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
5
500%
+30%
+50%
Planar UTBB FD-SOI:
Best in class in core energy efficiency
100%
400%
80%
300%
60%
200%
40%
20%
3x
100%
20%
7%
0%
0%
0.3
0.4
0.5
0.6
0.7
Vdd
0.8
0.9
1.0
1.1
1.2
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
6
Planar UTBB FD-SOI: Body Bias Leverage
Dynamic Process Scaling
•  No area penalty compared to bulk
•  Reuse of bulk design techniques
•  Process/temperature compensation
•  Useful for both digital and analog design
•  Speed/Power control
Vt variation vs. Vbias, FD-SOI vs. bulk
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Planar UTBB FD-SOI: Analog Technology
No channel doping :
better matching for short channel devices
Eg Diff Pairs => More gain, Less Power
Application: High Speed ADC
No pocket implant :
better gain compared to bulk
Body Bias: 85mV/V VTh adjust in FD-SOI
VTSAT
VT
Nominal VTN
R BB
FBB 0
Nominal VTP
New AnalogTechniques:
FBB
VBS
RBB
-  Dyn Trimming in Diff Pairs
-  Built-in gain controlled amplifier (GCA)
-  Switch : 10x Ron/Roff ratio vs Bulk or Fin
28 UTBB FD-SOI
28 Bulk
Analog Gain= Gm/Gd
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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28nm UTBB FD-SOI Process Integration
FEOL modules
MEOL modules
BEOL modules
STI module
Spacers
M1 module
•  Gate-first type FEOL, same as ST/ISDA 28LP
•  No HP/G-type complex stressors
•  FE process: 80% common with ST/ISDA 28LP
20% specific
•  15% less steps in UTBB vs. 28LP
•  Same LDD implants for all GO1 devices, incl. SRAM
•  No pocket implants
•  BE process: identical to ST/ISDA 28LP
•  Already qualified for volume production (MAT30)
•  Similar defect density as ISDA 28LP
•  Far better than “HP” technologies
•  Faster cycle time, lower fixed costs
36 masks for
Wells i/i
Wells
- i/i
Mx
Wells
module
i/i
Wells i/i
SD
Dual VtRaised
core
oxide
-  1.8V I/O oxide
-  Full active/passives
offer
Hybrid block
M2x module
Junctions
-  Full bitcells offer
-  Deep Nwell
Ch. SiGe
MiM decap
blockBEOL stack
-  7 metal OP
levels
-  RDL
Gate
Wells
stack
i/i
Wells
Silicide
i/i
M8x
Wells
module
i/i
Gate
Wells i/i
patterning
Contact
Wells i/i
Far
BEOL
Wells
i/i
Caption:
Same as bulk
Adjustment vs bulk
New module
Not use in FD-SOI
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Why ST is so Advanced?
LEVERAGE DEVELOPMENT
ECOSYSTEM IN GRENOBLE/
FRANCE AREA
SEVERAL SOI SUBSTRATES VENDORS QUALIFIED
SOI WAFERS
SOURCING GUARANTEED
GRENOBLE
ADVANCED PROCESS
STEPS DEVELOPMENT
PROC. DEVELOP.
PROC. INTEGRATION
MANUFACTURING
SOI SUBSTRATES
R&D & MANUF.
BERNIN
CONTINUITY (ENHANCED) IN
LOW-POWER DESIGN
TECHNIQUES
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
10
Planar UTBB FD-SOI: A Reality Today!
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
11
Planar UTBB FD-SOI: Some Facts!
FEOL & BEOL construction
Contact
plug
Alu Pad
M10
M9
M1 to
Thin film
MiM cap
6
M7 to 8
MG
HK
Raised-SD
Thin Box
Thin box
Interconnection
cross-section
Handle wafer
FD-SOI Transistor
cross-section
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
12
Planar UTBB FD-SOI: Some Facts!
Dynamic & Static Performances
VGS=1V
VGS=0.8V
OI
FD-S
Freq.
+400%
Bulk
VGS=0.6V
Freq.
+33%
AC Performance
on inverter RO
VGS=0.4V
DC Transistor
Output Characteristic
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
13
Planar UTBB FD-SOI: Some Facts!
Reduced Devices Variability
28LP
28FDSOI
3σ/Med
21%
3σ/Med
11%
28FDSOI
28LP
3σ/Med
8%
3σ/Med
13%
Delay (ps/stage)
Icell (µA/bit)
28FDSOI
SRAM Icell
mapping
28LP
∆Icell=6µA/bit
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Planar UTBB FD-SOI: Some Facts!
Yield Learning Equivalent to Traditional Bulk Process
28nm FD-SOI
28LP (HKMG)
Past Bulk SiON
Technologies (avg.)
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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16
28nm planar UTBB FD-SOI
A full platform offer
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
Device Offer and Partitioning
17
•  Core devices
•  2Vt on UTBB SOI (RVT/LVT),
adjustable through body biasing
•  I/O devices
•  EG 1.8V device on UTBB SOI
•  Bit-cells
•  On UTBB SOI: HC 0.152µm², HP 0.152µm²,
HD 0.120µm², HC/LV 0.197µm², 2P 0.251µm²
•  Same layouts as ST 28LP bit-cells
•  Others
•  Full set of diodes, vertical bipolar, analog/RF MOS,
ESD protections
•  Metal stack
•  Same as ST/ISDA 28LP
•  ST supported: 5U1x-0U2x-2T8x, 6U1x-2U2x-2T8x
•  Added value options
•  Decoupling planar MIM, 20fF/µm²
Logic
SRAM
Capacitance, Varactor
Drift MOS (OTP)
Digital I/O
Analog MOS
RF MOS
Resistors
Diodes (antenna)
2Vt / PB0-16nm


ESD Devices
 (FET)
Vertical Bipolar




 (Poly)
 (Active)


(FET, diode, SCR)

Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
Design EcoSystem
•  Planar UTBB FD-SOI uses a conventional (bulk)
design flow
•  Cadence, Mentor, Synopsys,
•  Apache, Atrenta
Prototyping
Floorplan Finalization
Physical Implementation
SignOff
Low Power Digital Design Flow
•  4-terminals spice models available, from PSP
•  Major simulators supported
•  UTBB FD-SOI uses same low power design
techniques than for bulk. In addition :
•  Optimized power switches
•  Extended poly-bias
•  Reverse & forward Dynamic body bias
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
18
Planar UTBB FD-SOI: A Reality Today!
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
19
ST Design Platform offer
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
20
Design Platform Content
12T
ND2
Standard
cells
8T / 12T
RVT / LVT
Poly bias:
0,4,10,16nm
Low power:
Isolation,
LevelShifters
Memories
Specific
Analog IPs
Low Voltage
Single Port /
Dual Port
Process
Monitoring
Antifuse
memories
IOs
ROM
Ultra High
speed
SRAM
Metal ECO
4Tune
PLLs, V/T
sensors,
eSwitch
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
21
Planar UTBB FD-SOI: A Reality Today!
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
22
Performance of standard cell
compared to CAD nominal
Reduced Inter-Cell Dispersion
28nm BULK
2
23
28nm FD-SOI
2
CAD
Fast
vs.
nominal
CAD
nominal
CAD
Slow
vs.
nominal
Silicon
results
Different standard cells (INVs, NANDs, NORs, MUXs, …)
Same set of standard cells
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
Improved Memory Minimum Voltage
Single-Port High Density Cell [0.120um² ; 4Mb]
28FD
Vnom
Vmin 28LP
28LP
Vmin 28FD
-100mV
Vmin (V)
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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25
28nm planar UTBB FD-SOI
Silicon Facts from a Complex SoC
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
Multicore Silicon Results
28nm LP not fast
enough, dynamic
power penalized by
overdrive usage
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Multicore Silicon Results
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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High Speeds at Lower Vdd
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Dynamic Process Scaling
(Body Bias) Advantage
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Improved Leakage Control
IDDQ (a.u.)
Vdd (V)
28LP
FD-SOI
Diff %
1.00
1
0.61
-39%
0.85
0.61
0.39
-36%
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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31
Planar UTBB FD-SOI
From 28nm Node and Below
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
Planar UTBB FD-SOI Scalability: TSOI & TBOX
Si data for LG=15nm:
TSOI
TSOI
BOX
BOX
O. Faynot et al, IEDM 2010
TSOI
BOX
7.5 6.5 6 25 20 15 K. Cheng et al, VLSI 2011
  Electrostatic control improved by Thinning TBOX
  Scalability down to 10nm node
  Devices already processed with 3.5nm SOI film!
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Planar UTBB FD-SOI Scalability:
Boosters Roadmap
Boosted
back bias
Performance
10nm
FD-SOI
Raccess
at same Vdd
µ boost
sSOI
Vt and
µboost
14nm
FD-SOI
at same Vdd
Racces
28nm
FD-SOI
In situ
doped RSD
SiGe
channel
for PFET
15nm
TBOX
2nd gen RSD
+ cSiGe
Dual STI _ dual Epi S/D
L=20nm As
As
ISD Si S/D Dual STI Tsi=6nm 15 ~20 nm BOX Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Planar UTBB FD-SOI Scalability:
Device Performance Boost for 14nm via Back Bias
Grenouillet et al, IEDM 2012. LETI/IBM/ST/GF collaboration
  More than 2 decades IOFF reduction with
reverse back bias
  +20% ION boost with forward back bias
  Frequency can be boosted by 20% with
FBB
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Planar UTBB FD-SOI Scalability:
Additional Booster: Body Bias effect
  Thinning TBOX from 25nm to 15nm improves body factor by 60%!
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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Planar UTBB FD-SOI:
Enabling Moore’s Law with Planar Process & Design
0.9V
113CPP
90Mx
-3 0 %
+30
powe % speed
r (at
same
spe
ed)
0.8V
90CPP
64Mx
-25%
+20
pow % speed
er (a
t sam
e spe
ed)
0.7V
64CPP
48Mx
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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14nm FD-SOI Process Modules:
Silicon Achievements
NOSO patterning & epi regrowth
Shallow STI
Dual epi SD : SiGe:B PMOS & SiC:P NMOS
HM
SOI
Epi
BOX
Gate patterning
Si NMOS & SiGe PMOS channels
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
37
Conclusions, Q&A
•  ST is committed on FD-SOI technology
•  28nm FD-SOI open for risk production
•  Full 28nm Design Platform offer available and silicon qualified
•  Compelling silicon results obtained
•  FD-SOI technology for high energy efficiency: faster & cooler
•  Dynamic Process Scaling (thanks to extended body bias), the new design leverage
•  Allowing dynamically switching between high speed and static power optimization
•  Low gate capacitance (lower than bulk) and high speed devices: low dynamic power consumption
•  Allowing full reuse of low power bulk planar design techniques
•  FD-SOI technology: simpler & cheaper
•  High-K/Metal-Gate gate first technology, no complex “G” stressors
•  Less variability, less layout effects
•  Simplified process flow, same equipment as for bulk planar
•  FD-SOI technology: scalable
•  Roadmap already defined down to 10nm
•  14nm node in development
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
38
Thanks
•  Thanks to ST-Ericsson for teaming-up on NovaThor ModAp product
•  Thanks to IBM for collaborating on planar UTBB FD-SOI development
•  Thanks to SOITEC for collaborating on UTBB FD-SOI substrates
optimization
•  Special thanks to LETI’s teams, who decisively contributed to these
developments, from Grenoble, Crolles and Albany
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012
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40
Thank You!
Planar FD-SOI Technology at 28nm and below for extremely power-efficient SoCs
December 2012