HGA Technology Driver – The Need for Speed With Control
Robert Dodsworth and George Hare, 3M Microinterconnect Systems Division
Presented at the 2001 Head/Media Conference and published in DataStorage, September. 2001.
Reprinted with permission.
Abstract:
Rotating memory devices continue to be the most cost effective means of gigabyte size
storage. They maintain that reputation based on systematic, continuous improvement of
technology once obstacles are identified. A new area of concern is the interconnect
between the channel chip and the slider on the HGA. It has been assumed that 2 metal
rather than single metal flexures were needed for high data rate HDDs. 2 metal flexures
may add unnecessary costs where single metal flexures demonstrate excellent
performance. Single metal layer flex is compared to conventional 2 metal flexures used in
HGAs. Work at 3M shows that significant improvement in electrical properties can be
obtained using fine pitch circuit fabrication to create tightly, electrically coupled single
metal layer trace pairs. When properly designed, these pairs mimic classical 2 metal
layer structures. Single metal layer structures have been shown to achieve controlled 50
ohm impedances and have low common and differential mode crosstalk that is acceptable
in most HDD applications for data rates up to and exceeding 1 gigabit/sec.
Advancements in all components of the hard disk drive make the need for speed pervasive.
Recent network memory system advances assure that faster drives will not be technical
demonstrations but will find viable and sizable applications. In PCs, the 133 MHz and wide bus
backplane designs (64-bit or double 32-bit word sizes) will be coupled to wideband networks. In
server farms, high capacity Hard Disk Drives (HDDs) will dump data directly to switch
processors at GHz rates, as was recently demonstrated by APT Technologies using Seagate ATA
HDDs and Vittesse Semiconductor transceiver chips.
The fundamental problem is how to read and write data reliably at these extremely high data
rates. An enabling component is the interconnect between the pre-amp and slider. While higher
bit densities are causing the suspension mechanics to be reconsidered (both static and dynamic
mechanical characteristics), the new, high data rate requirements are causing the conductor path
characteristics to be reconsidered. The interconnect is now being classified as a transmission line
or even as an active component.
Current suspension design improvements are aimed at reducing track pitch and pos itioning
accuracy. Suspension design avenues are:
1) Extended base plate (4 piece) suspension designs (to increase stiffness to raise key resonance
frequencies)
2) Costly dual actuator suspensions, either the milli- (loadbeam) or micro- (head) actuator
designs.
Either approach means that the mechanical design of the signal conducting structure (TSA (Trace
Suspension Assembly) flexure or FSA (Flex Suspension Assemblies)) face new constraints. In
the gimbal region there is need for 1) reducing the absolute values of RSA (Roll Static Attitude)
/PSA (Pitch Static Attitude) and 2) reducing circuit impedance near the slider. The obvious
approach of implementing thinner leads will satisfy #1 but conflicts with #2. In the loadbeam
region, the circuit stiffness must be minimized (by reducing the trace thickness) to avoid
introducing offsets in the RSA/PSA or adding variability to the gram loading process. An
example of the such a compromise is in TSA design. Due to the subtractive process used in TSA
fabrication, the traces must be offset from the gimbal metal to reduce stiffness, but the key
electrical attribute of the TSA, having a inherent ground layer, is lost. The result is that the traces
in the body of the flexure are at 40-50 ohms impedance, but the gimbal area exceeds 80 ohms,
preventing a close impedance match with the GMR (Giant Magnetoresistive) read sensor on the
slider. Thus, although a single metal layer circuit structure would be best for mechanics, current
circuit fabrication capability is thought to have significant limitations in electrical performance
compared to future HDD needs.
READ signal paths must have lower impedances to closely match the mean slider output
impedance. Such matching couples more energy from the milli-volt level GMR or TMR
(Tunneling Magnetoresisitive) sensor into the pre-amp. The Writer IC must output a fast risetime
current pulse to drive the Write Coil. Controlled impedance with low inductance is ideal for
maintaining the sharp signal pulse slope to maximize the change in flux from the coil.
Extensive electrical modeling and sample part measurement confirms that constant impedance
paths can be designed using single metal flex attached to suspensions, (Flex On Suspension or
FOS) with complex shapes. 3M has the capability to design and manufacture Controlled
Impedance FOS circuits (CI FOS) which have lower nominal impedances – and impedance
tolerances – which exceed standard FSA and STTSA/BFC (Short Tail TSA / Bridge Flex Circuit
constructions.
At a 1 GHz data rate, the transit ion (rise and fall) time is typically 300ps or less. A transmission
line is considered any circuit path that is longer than 1/5 of a signal’s typical rise/fall time. For the
HGA, the transitions (rise time and fall time) define quality of the WRITE pulse. At high data
rates, typically having 300 pS or faster rise/fall times, controlled impedance transmission lines are
necessary to maintain the integrity of the WRITE signal transitions and the circuit must analyzed
as such. See Figure 1.
FIG. 1
Anatomy of a Data Pulse Shows Need For Transmission lines In HGAs
Write Pulse Graphic
Electrical Length of HGA
180-240 ps
6
Internal
Data Rate
5
2 GB
4
Volts
1 GB
3
500 MB
250 MB
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
-1
In HDD design, the objectives are to either write smaller bits or write bits faster. Either objective
requires short, well-defined current transitions from the Write Driver to the Write Coil. Because
a Write Coil is excited by a large change of current in the shortest time span (dI/dT), the shape of
the WRITE current must be maintained along the transmission line. Because energy transmission
is the purpose of the circuit, it should not have any abrupt changes in impedance, especially
inductance. Such changes distort the signal shape or cause loss of signal amplitude through
attenuation or reflection, reducing dI/dT.
Current “state of the art” HGA constructions use an STTSA mated to a solder bump or
ultrasonically welded BFC. The impedance along the HGA can be viewed using a TDR (Time
Domain Reflectometer, Tektronics 11801B w/SD24 sampling heads) as shown in Fig. 1. This
instrument injects a very short risetime pulse into a DUT (device under test) and calculates local
impedance of the conductors based on amplitude of reflections of the input pulse and the timing
of the reflection compared to the initial pulse’s launch. An instrument, such as the Tektronix
11801 Digital Sampling Oscilloscope with a TDR sampling head, outputs pulses with a risetime
of ~35 ps, and at small impedance changes has a distance resolution of a several millimeters.
Fig. 2, below, shows the difference in local impedances between a conventional HGA (STTSA +
BFC) and a LTTSA (Long Tail Trace Suspension Assembly). For WRITE pulses of ~50 ns.
(~200 Mbits/sec), the STTSA/BFC appears to be a lumped ~80 ohm impedance, although the
local impedance varies by ?30 ohms. At 700MB to 1.2 GB data rates the WRITE risetime will be
~ 300 ps. and the HGA must be treated as a transmission line. Thus, smoother trace profiles with
? 10 ohm tolerances will become the norm.
Fig. 2 TDR traces Show Instantaneous Impedance Along An HGA
LTTSA & BFC/TSA Impedance Profiles
TDR Probe Outside Tail Bond Window, Open Circuit
3M 8/00
140
STTSA/BFC
120
Ohms
100
LTTSA
70 Ohm
Trace
80
60
50 Ohm
Trace
40
BFC/TSA
U/S Bond
PCC Bond
Window
20
Open
Circuit
0
0
100
200
300
400
500
600
Measurements
Modeling and measurement of common HGA constructions with copper traces and ground layers
of various metal shows that electric fields are contained between them, effectively controlling
circuit impedance. Approximate field distributions are shown in Fig. 2 for various HGA crosssections.
Recently, 3M has been experimenting with single -metal layer and ground plane circuit forms to
achieve specific impedances. Analysis of circuit structures shows that it is possible to achieve
desirable electrical properties with a single layer structure. The key is to create tight coupling
between trace pairs by reduction of the absolute distance between them. This tight coupling
contains the electric field in a confined region between the traces, which reduces inductance and
reduces the influence of adjacent conductors, especially if the trace widths are small (such as
required in the gimbal area).
Adjustment of the trace layer geometry must include the effects of the suspension and E-block.
Adjustments to the circuit shape (trace width, trace pitch, thickness, modification of dielectric
layers) can be made to keep the single metal layer flex circuit’s electrical properties within
narrow electrical property ranges over its entire length. A carefully designed FOS with accurate
assembly to a suspension provides an appropriate transmission line for use in HGA applications.
In the use of fine pitch circuits (spacing between traces of 20-30 um), the actual shape of trace
sidewalls has an effect on the absolute lowest attainable impedance value. In “semi-additive”
circuit fabrication, photoresist is used to control the width and sidewall shape of the traces.
Traces are then “plated up” with their final shape determined by the resist. Subtractive circuits are
defined by imaged resist on the surface of the copper layer. Etchant then removes the unwanted
copper between leads and produces a sloped sidewall because of the flow pattern of the etching
bath.
Fig.3 Typical HGA Cross-sections Needed For Electrical Modeling
COVERCOAT
1
CU TRACES
SUBSTRATE
ADHESIVE
FLEXURE
TSA (no Adhesive) or FOS
ATTACHMENT TO FLEXURE
COVERCOAT
2
CU TRACES
SUBSTRATE
FOS IN E-BLOCK REGION
3
COVERCOAT
CU TRACES
SUBSTRATE
AIR GAP
FLEXURE
FOS IN PCC BOND AND OVER
LOAD BEAM REGION
4
Subtractive Circuit
Traces
Semiadditive Circuit
Traces
For example, at a target impedance of 70 ohms, a semi-additive trace (vertical sidewalls) will
have ~7 ohms lower impedance than subtractively processed trace pairs (~15? sidewalls) at the
same nominal spacing (Fig. 3(4)). At trace spacings ~2x the copper thickness actual trace shape is
not a major factor in electrical performance. However, as the spacing decreases, the effect
becomes stronger as shown and the target impedance is reduced from 80-100 ohms, typical of
standard FSA and STTSA/BFC HGAs to controlled impedance ranges of 50-70 ohms.
Samples using both fine pitch traces in a 1 metal layer construction and 2 metal layer parts (Trace
+ groundplane) were designed to a target 50 ohm impedance. An existing FOS circuit (which
originally had 80-120 ohm impedance sections) was used as the basis for the 50 ohm design. The
finished parts were tested using the TDR to measure the impedance along the circuit. Both part
constructions achieved the target as shown in Fig. 3.
Fig. 4
Experimental HGA Using Ground Place and Fine Pitch FOS For
Impedance Control on Same Suspension
Low Impedance FOS Circuit Constructions
Impedance
TDR Trace (35 ps Risetime)
Leaded FOS/No Slider
120
110
100
90
80
70
60
50
40
30
20
Fine Pitch,
1 Metal
Traces
w/Ground
Plane
Distance/Time Along HGA (output shorted)
Although single metal layer FOS may be appropriate for most applications (down to ~ 50 ohms),
2 metal layer constructions can reach lower absolute impedances. As usual, there are trade-offs.
Normal 2 metal layer flex is ~1.3-2.0 X the cost of single layer flex. Alternate ground plane
constructions are being evaluated at 3M to reduce the cost differential.
Use of high power pulses needed to write fast to take advantage of the increasing data density
capability of the disk also creates crosstalk. Ground planes reduce crosstalk through control of the
field between the conductor and ground plane. The results of modeling for both differential and
common mode (CM) crosstalk provide estimates of the peak voltage levels of crosstalk for
various HGA structures. Modeling of simple structures (i.e., parallel lines) can be misleading
when compared to modeling of actual HGAs. It was found that, when comparing structures,
simple parallel trace models would produce much higher (4X) peak crosstalk voltage values than
found in actual HGA designs.
Much of the crosstalk does come from specific and sometimes very short areas of the circuit.
Usually there is some traditional trace shapes where traces which are constrained by traditional
“mechanical “ requirements such as tail forming or gram loading . However, in the
gimbal/suspension area, the READ and WRITE signal pairs have additional separation and
crosstalk is correspondingly reduced due to reduced coupling in this area. Use of fine pitch, semiadditive FOS allows control of impedance in the gimbal which is not possible with the usual
subtractive circuit construction. Figure 4 below shows the TDR (impedance) trace along an FSA.
Note the reduced impedance in the trace area. With FSA, this is possible with no change in
RSA/PSA parameters since the electrical properties are inherently de-coupled from the electrical
properties.
Fig. 5 Actual HGA Using Fine Pitch FOS
FSA Impedance Profile - 80 Ohm HGA Target
Note Gimbal Impedance
140
130
Impedance, Ohms
120
Swage
Plate
Body
110
Gimbal
100
90
80
70
FSA1 Write
60
FSA1 Read
FSA2 Write
50
FSA2 Read
40
1
Distance/Time
Writer crosstalk to the READ circuit is a concern for designers. A Read Head is typically biased
at 5 mA and can tolerate maximum continuous current of about 10 mA. For a 50 ohm READ
circuit, this translates to a bias voltage of 250 mV leaving a margin of 250 mV rms for crosstalk.
Comparison of an 80 ohm, 1 metal layer FOS to an 80 ohm TSA-type structure (or 2ML FSA)
with full groundplane for a 3.5 inch format HGA, for differential and common mode crosstalk:
The levels shown are peak as shown in Figure 6A. Simulations were run on complete flexure
models (from bond pads to head connection points) with a typical head model at the output and
typical Reader IC input model. Simulations were run for Writer output impedances of 80 ohms
and 200 ohms. From a crosstalk standpoint, these are worst case waveforms for currently
available READ/WRITE preamp/driver circuits. In both HGA constructions, 2ML FSA/TSA and
1ML FSA, the levels of crosstalk are well within 250 mV margin for protection of the Reader
element. The source pulse waveforms are shown in Fig. 6B.
Fig. 6A Crosstalk Simulation, Peak, Far End (at GMR Head)
Differential and Common Mode Components
Far End X-talk
Peak Voltage @ GMR Head, 80 & 200 ? Write Drivers
GMR Damage
Threshold
Read Line X-talk, mv
250
200
150
1ML FSA
2ML FSA/TSA
Diffential Mode FE
100
50
Commom Mode FE
0
@ 80?
@ 200?
@ 80?
@ 200?
Fig. 6B
Differential and Common Mode Stimulus
CM Pulse
300 pS rise/fall Time
12
6
10
5
Amplitude (V)
Amplitude (V)
Diff Pulse
300 pS rise/fall time
8
6
4
4
3
2
1
2
0
0
0
1
2
3
Time (nS)
4
5
6
0
1
2
3
4
5
6
Time (nS)
Summary: Economical, single metal FOS-based HGAs can provide the necessary performance
for today’s, as well as tomorrow’s, high data rate HGA designs. Single metal FOS offers
controlled impedance with low levels of crosstalk. For HDD applications with data rates up to
and exceeding 1 gigabit/sec, use of single metal FOS meets and can typically exceed design
requirements by providing superior de-coupling of the mechanical components while
maintaining electrical design freedom.
Authors:
Robert Dodsworth, 3M, Product Development Specialist, with a 20 year background in advanced
interconnect technology. Recent experience in designing interconnects for flip chips, LCD
modules and portable electronics as well for HDD applications. BSME, University of Missouri,
MBA, College of St. Thomas.
George Hare, 3M, Product Development Specialist, with over 25 years of experience in product
development, test engineering, and cable, connector and system modeling experience. BSEE,
University of Texas, MBA, University of Texas.