BSIM Models: From MultiMulti-gate to
symmetric BSIM6
Yogesh S. Chauhan, Sriram Venugopalan,
Muhammed A. Karim, Pankaj Thakur, Navid
Paydavosi,
y
, Ali Niknejad
j
and Chenming
g Hu
BSIM Group
University of California, Berkeley
March 16, 2012
MOS-AK Workshop, Delhi
SPICE and Device Compact Models
Prof. at UCB – SPICE
designer (1925-2004)
Prof. at UCB/Emeritus Prof
Prof
Prof. at
CMU – CANCER designer which
later led to SPICE development
Ron R
R
Rohrer
h
Special Issue on 40th Anniversary of SPICE
2
SPICE Transistor Modeling for
Circuit Simulation
Medium of
information
exchange

Simulation Time



~ 10μs per DC data point
No complex
p
numerical
method allowed
Accuracy requirements

~ 1% RMS Error after
fitting

Excellent Convergence

Example: BSIM4

25,000 lines of C code

200+ parameters

Open-source software
i
implemented
l
d in
i all
ll EDA tools
l
3
BSIM Family of Compact Device Models
1990
BSIM1 2
BSIM1,2
1995
2000
2005
2010
BSIM3
Bulk MOSFET
BSIM4
New
BSIM5
BSIM6
Silicon on Insulator
BSIMSOI
MOSFET
BSIM-MG
Multi-Gate
Multi
Gate MOSFET
BSIM: Berkeley Short-channel IGFET Model
4
Bulk MOSFET Models


New

BSIM3
 Threshold Voltage based MOSFET Model
 First
Fi t CMC standard
t d d Model
M d l
BSIM4
 Threshold Voltage based MOSFET Model
with enhanced physics features (mobility,
BTBT, gate leakage…..)
BSIM6
 Charge based Symmetric MOSFET Model
 Charge
Ch ge b
based
ed core
o e
 BSIM4 physics models and parameters
 Under standardization review in CMC
5
BSIM6: Bulk MOSFET Model
6
Why new Bulk MOS Model: BSIM6

Harmonic Distortion




Output spectrum of RF signal at frequency  should
only
l contain
i ffundamental
d
l frequency
f

Nonlinear MOS behavior adds other frequency
components
p
((at 2, 3
3 …)) visible above noise floor
 harmonic distortion
Harmonics amplitude  higher order derivatives of
signal
Negative
g
capacitance
p
from BSIM4 model may
y
cause convergence problem
7
Why new Bulk MOS Model: BSIM6
Taylor Series Expansion
iout ( t )  f (V  v(t ))  f (V )
iout ( t )




f

x
x V
1 2 f
v 
2 x 2
1 3 f
v 
6 x 3
 v 3  ...
2
x V
x V
RF design needs correct derivatives
to predict harmonic distortion
Incorrect derivatives=Wrong
harmonic results
Model must satisfy both DC & AC
symmetry
Method of testing derivatives


Gummel Symmetry (DC)
AC Symmetry
BSIM4 simulationWrong derivatives
around VDS=0
8
BSIM6: Charge based MOSFET model






BSIM6 is the next BSIM Bulk MOSFET model
Charge based core derived from Poisson’s solution
Physical effects (SCE, CLM etc.) taken from BSIM4
Parameter names matched to BSIM4 parameters
Gummel Symmetry (symmetric @ VDS=0)
AC Symmetry



Continuous in all regions of operations
Physical
y
Capacitance
p
model


Capacitances/derivatives are symmetric @VDS=0
Short channel CV–
CV–Velocity saturation & other effects
No glitches – smooth current and capacitance
b h i
behavior
9
Physics of BSIM6 Model
Other models ignored
circled terms
 2nq
2qi  ln(qi )  ln 
 


 2nq


qi  2  2qi   p    p  2 f  vch



No approximation to solve the charge equation
We solved the charge equation using first &
second order NewtonNewton-Raphson
p
technique
q
to
obtain analytical expression of qi
10
Drain current expression
dQi 
dS

 VT
I D  I drift  I diff  W   Qi

dx 
dx


Drain current

Mobility model

Using charge linearization & normalization

ID 
v
dQi 
dS

 VT
W   Qi

2
dx
dx


  v dS 

1  
v
dx
 sat

Qi
ID
 Qi
2 V
, id 
, c  v t
 nq P  S , q 
W
Cox
2nq CoxVT
vsat L
2nq  v CoxVt 2
L
id 
q
2
s
 
 qs  qd2  qd

1
2 
1  1  c qs  qd  

2
11
Normalized IDS-VGS & derivatives
Error (%)
IDS vs VG
Red – Numerical Surf. Pot. model
Blue – BSIM6 model
2ndd derivative
d i i
3rdd derivative
d i i
1st derivative
12
BSIM6 Development Status

BSIM6 development started in Q4 2010

First beta code was released in Jan. 2011

BSIM6.0.0 Beta7 was released on 28th Feb. 2012 to
CMC members


BSIM6 to cover all technology nodes and applications




Continuously working with industry partners
Digital – Accuracy in entire bias range
Analog – Symmetry and accuracy in derivatives
RF – Symmetry and harmonics
Detailed BSIM6 technical presentation tomorrow
13
BSIM MultiMulti-Gate Models:
BSIM--CMG
BSIM
BSIM--IMG
BSIM
14
MOSFET in sub
sub--22nm era
FinFET
UTBSOI
Multi-Gate era has arrived
Why new MOSFET structures?
NY Times
SOI Consortium:
ST, SOITEC, …
15
Good Old MOSFET nearing Limits

Sub-threshold swing (SS) &
SubThreshold Voltage are bad


Random dopant fluctuation


Sensitive to gate length
V i bilit iis an iissue
Variability
Requirements


Low Vth and low Ioff  Low Power
Less variation
Courtesy – Chenming Hu
16
Making Oxide thin is NOT enough!


Gate can’t
can t control the leakage paths far from the gate
Drain has now much more influence compared to long
channel!
17
Why not remove PATHS far from Gate?
UTBSOI
Y.-K. Choi et al., IEEE EDL, 2000
FinFET
X. Huang et al., IEDM, 1999
18
Versatile Multi-Gate Compact Models
P+ back-gate
p-sub
BG ETSOI
BG-ETSOI
Fin
Gate
e1
BOX
UTBSOI
Gate 2
BSIM-IMG
Vertical Fin
IMG
BOX
BSIM-CMG
Lg
G
S
D
Tsi
FinFETs on Bulk and
SOI Substrates
19
BSIM--CMG
BSIM
20
Common--Multi
Common
Multi--Gate Modeling

Common MultiMulti-gate (BSIM
(BSIM--CMG):



All gates tied together
Surface-potential
Surfacepotential--based core II-V and CC-V
model
Supports doubledouble-gate, triple
triple--gate,
quadruple--gate, cylindrical
quadruple
cylindrical--gate; Bulk and
SOI substrates
21
Surface Potential Calculation

Vg
Surface potential obtained
by solving the 1D
Poisson’’s equation
Poisson
Vs
 2ψ qni

2
x
εSi

qV
qφ
qφB
 qψ

 B
 ch
kT
kT
kT
kT
  e
 e
e   e
 
Body Doping 
 Inversion Carriers
n+
x
y
NA
n+
Vd
Vg
A Perturbation approach is used to handle
M. V. Dunga et al.,TED 2006
finite body doping
ψ

Net Surface Potential

ψinv

Inversion Carriers only

ψ pert

P t b ti due
Perturbation
d to
t finite
fi it doping
d i
22
Surface Po
otential (V
V)
Surface Potential Calculation
0.8
Symbols
y
: TCAD
Lines : Model
0.4
1
15
Na = 1x10
18
Na = 1x10
18
Na = 3x10
18
Na = 5x10
0.0
-0
0.4
4
0.0
0.4
0.8
1.2
Gate Voltage (V)

Model
d l matches
h 2
2D TCAD
C
very well
ll
without fitting parameters for different
body doping.
doping
23
I-V Model & Verification

Drain current derived from driftdrift-diffusion
-3
Dra
ain Current (A)
Drain
n Currentt (A)
Na = 3e18cm
1m
Vg = 1.5V
500µ
Vg = 1.2V
Vg = 0.9V
0
0.0
0.5
1.0
Drain Voltage (V)
1.5
1m Na = 3e18 cm-3
Vd = 0.1
Vd = 0.2
Vd = 0.4
Vd = 0.6
500µ
0
0.0
0.5
1.0
1.5
Gate Voltage (V)
M. V. Dunga, UCB Ph.D. Thesis
24
Drain Current in Volume Inversion
Draiin Curre
ent (A)
10µ
µ Vds = 0.2V

10n
-3
Na = 1e15 cm
Tsi = 5nm
Tsi = 10nm
Tsi = 20nm
10p
10f
0.00
0.25
0.50
Li
Lines:
M
Model
d l
Symbols: TCAD
0.75
Gate Voltage (V)
In volume inversion Id  TSi in sub
sub-threshold.
threshold.
M. V. Dunga, VLSI 2007
25
1.0
-3
Na = 3e18cm Symbols : TCAD
Lines : Model
Vds = 1.5V
Cgg
0.5
Csg
Cdg
0.0
0.5
1.0
Gate Voltage (V)


1.5
Normalize
ed Capacittance
Normaliz
zed Capaciitance
C-V Model Verification
1.0
Cgg
Model
Symmetry
Symbols : TCAD
Lines : Model
Cgs
0.5
Csg
Na = 3e18
Vg = 1.5V
0.0
0.0
0.5
Cdg
Cgd
1.0
1.5
Drain Voltage (V)
C-V model
ode agrees
ag ees well
e with
t TCAD
C
without
t out
any fitting parameters.
The transcapacitances
p
exhibit the correct
symmetry behaviors.
26
BSIM--IMG
BSIM
27
Independent--gate Device Structure: BSIM
Independent
BSIM--IMG
Vfg

Asymmetric structure



Different Gate Workfunctions
Allows dissimilar Gate
Potentials
Different Oxide
thickness and Material !
F
Front
t Gate
G t
Tox1
Source
y
x
Tsi
Drain
NA
Tox2

Captures important
C
i
features


Threshold Voltage
tuning through BackBack
Gate
Multi-Vth technology
Vd
Vs
Back Gate
Vbg
28
Surface Potential Calculation

Analytical Solution for
s is
i k
known
VFG
TOX1
Y. Taur, TED 2001
H. Lu et al., TED 2006
ΦM1
D
S
TOX2


Newton iteration needed
for s calculation
VBG
ΦM2
Approximation for frontfront-, backback-surface
potential and charge developed

Better computational efficiency
D. Lu
D
L att el.,
l "A computationally
t ti
ll efficient
ffi i t compactt model
d l for
f fullyf ll
depleted SOI MOSFETs with independently-controlled front- and
back-gates," Solid State Electronics, 2011
29
Surface Potential: Verification with TCAD
0.7
Symbols: TCAD
Front Surface Pote
ential (V)
Front S
Surface Poten
ntial (V)
0.8
Lines : Model
0.6
0.5
Tox2
Tox2
Tox2
Tox2
T 2
Tox2
0.4
0.3
0.2
0.1
0.0
-0.4
-0.2
0.0
0.2
0.4
=
=
=
=
=
40 nm
20 nm
10 nm
5 nm
2.5
2 5 nm
0.6
0.8
1.0
Front Gate Voltage (V)
0.9
0.6
Vch = 0.0 V
Vch = 0.3 V
Vch = 0.6 V
Vch = 0.9 V
0.3
0.0
Tox1=1.2nm
Tox1=1
2nm Tox2 = 20nm
Tsi = 15nm Vbg = 0
-0.3
0.0
0.5
1.0
Front Gate Voltage (V)
Front S
Surface Pote
ential (V)
0.9
0.8
0.7
0.6
05
0.5
Symbols: TCAD
Lines : Model
Scalable w.r.t. physical
parameters like Tsi, Tox (front and
back) and node voltages etc.
T ox2=1.2nm
0.4
0.3
Tsi
Tsi
Tsi
Tsi
0.2
0.1
00
0.0
-0.1
-0.2
-0.4
-0.2
0.0
0.2
0.4
=
=
=
=
5
10
15
20
0.6
nm
nm
nm
nm
0.8
Front Gate Voltage (V)
1.0
30
Drain Current Model
Drain Current
W
I ds   
L
 Qinv , s  Qinv ,d
 s1,d  s1,s     kT Qinv,s  Qinv,d 

2
q


Drift
Diffusion
  2
2 si Es 2
Qinv  2 si Es 2
Qinv: inversion carrier density
Es2: back-side electric field
ψs1: front-side surface potential
Very high accuracy
No Charge-sheet Approximation
250
200
Errror Relative to
o TCAD (%)
15
Drrain Current (A)

Vfg = 0.2v, 0.4v, 0.6v, 0.8v, 1.0v
Charge sheet
This Work
TCAD
150
100
50
0
0.0
0.2
0.4
0.6
Drain Voltage (V)
0.8
1.0
Charge-sheet Model
This Work
10
5
0
-5
-10
-15
-0.5
0.0
0.5
1.0
Front Gate Voltage (V)
31
Capacitance Model

Model inherently exhibits symmetry


Cij = Cji @ Vds= 0 V
Model overlies TCAD results

No tuning parameters used
Toxf = 1.2nm, Toxb = 20nm,
Tsi = 15nm, Vbg = 0 V
1.0
Vfg = 0.8V,
0 8V Vbg = 0 V
0.4
0.3
Cds
Csd
Css
Cdd
0.2
0.1
0.0
0
0
0.0
0.2
0.4
0.6
Drain Voltage (V)
0.8
1.0
Normalized C
N
Capacitance
Normalized Capacitance
e
0.5
0.8
0.6
Tox1 = 1
1.2nm
2nm
Tsi = 15nm
Tox2 = 20nm
Vbg = 0 V
Cfg,fg
0.4
02
0.2
Cbg,fg
0.0
Cd,fg
-0.2
-0.4
-0.5
Cs,fg
0.0
0.5
1.0
1.5
Front Gate Voltage (V)
Symbols: TCAD Results; Lines: Model
32
Gummel Symmetry Test

Drain Current Symmetry
V fg=0.2
0.00
V fg=0.4
-0.02
V fg=0.6
V fg=0.8
08
-0.04
0 04
Vbg=0
3
3
3
d Ix / dVx (A / V )
0.02
-0.06
-0.10
-0.05
0.00
0.10
Vx (V)
Analog /RF Ready
AC (charge) Symmetry
20
10
-1
dccsd / dVx (V )
V bg=0
16
V fg =0.2
12
8
V fg =0.6
V fg =0.8
V fg =0.4
4
0
-0.10
-0.05
8
V bg=0
V fg =0.2
=0 2
-1
dcgg / dVx (V )

0.05
0.00
Vx (V)
0.05
0.10
V fg =0.6
6
V fg =0.8
4
V fg =0.4
2
0
-0.10
-0.05
C. C. McAndrew, TED 2006
0.00
Vx
0.05
0.10
33
Real Device Effects
Channel Length
Modulation and
DIBL
Mobility
Degradation
g
Velocity
Saturation
GIDL Current
Short
Channel
Effects
Core
SPE
I-V
Q
Quantum
Effects
Temperature
T
t
Effects
C-V
Fringe
Capacitances
Impact Ionization
current
Direct tunneling
gate current
S/D Resistance/
Parasitic
Resistance
Noise models
Overlap
capacitances
34
Short Channel Effects
BOX
P+ back-gate
back gate
p-sub
BOX
Lg↓
p-sub
Vt Rolll-off (V)
0.00
-0.05
-0.10
Vds = 50mV
Vds = 1.0V
-0.15
-0.20
-0.25
-0.30
0 01
0.01
Symbols: TCAD
Lines: Model
01
0.1
1
Lg (um) T = 8nm
si
Tbox = 4nm
Scale
L
Length
th
35
Self Heating Model

Thermal Node: Rth/Cth
methodology
T

Relies on Accurate physical
modeling of Temperature
Effects in the model
Draiin Curren
nt (A)
1000
800
Without Self Heating
With Self Heating
Vgs=1.0
600
Vgs=0.8
400
Vgs=0.6
g
200
Vgs=0.4
0
0.0
0.2
0.4
0.6
0.8
1.0
Vds (V)
36
BSIM--CMG: Global Extraction
BSIM
Validation on SOI FinFETs
Hfin=60nm, Tfin=22nm, EOT=2nm, L=75nm, 85nm, 90nm, 235nm, 1um
37
BSIM--CMG: Global Extraction
BSIM
Validation on SOI FinFETs
Hfin=60nm,
=60nm Tfin=22nm,
=22nm EOT=2nm
38
BSIM--IMG validation
BSIM
Measurement from CEA-LETI

Tbox=145nm
EOT=1.6nm
L = 50nm
Na=1e15
Vbg = 10V, 15V, 20V, 25V
Id,lin
-2
Id,lin
10
-3
10
-4
10
W=50 x 0
0.5
5m
L = 50 nm
-5
10
Vbg = 10v, 15v,
-6
10
20v, 25v
-7
10
Cross: Measurements
Lines: BSIM-IMG
-8
10
-9
10
Tsi= 8nm
g22 = 5.0
50
Drain Current (mA)

Drain
n Current (A)

-0.2
0.0
0.2
0.4
0.6
0.8
Gate Voltage (V)
1.0
W=0.5um x 50
g11 = 4.55
4 55 (fitted)
2.5
2.0
Cross: Measurements
Lines: BSIM-IMG
1.5
Vbg = 10v,
10 15
15v,
20v, 25v
Increasing Vbg
1.0
0.5
W=50 x 0.5m
L = 50 nm
0.0
-0.4 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
G t V
Gate
Voltage
lt
(V)
39
Summary

BSIM6 – New bulk MOSFET model in BSIM family




Ready for immediate use and under standardization at
CMC
BSIM-CMG and BSIM-IMG are Production Ready model

BSIM-CMG
BSIM
CMG – First CMC standard FinFET Model

BSIM-IMG submitted to CMC for standardization
Physical, Scalable Core Models with plethora of Real
Device Effects
Available in Verilog-A code and validated on
measurements from different technologies

Available in major EDA tools

Ready for Technology/Design Evaluation

Verilog-A code and Well-documented Technical
Manual
40