BSIM-IMG: A Turnkey Compact
Model for Back-gated FDSOI
MOSFETs
Principle Investigators: Prof. Chenming Hu and Prof. Ali
Niknejad
Students: Sriramkumar V., Darsen Lu,
Yogesh Chauhan, Muhammed Karim, Angada Sachid
UC Berkeley
Apr. 28, 2011
FDSOI Workshop, Hsinchu, Taiwan
SPICE Transistor Modeling for
Circuit Simulation
Medium of
information
exchange
UC Berkeley - 2
BSIM Family of Compact Device Models
1990
1995 1998 2000
2005
2010
BSIM3
Conventional
BSIM4
MOSFET
New
BSIM6
Silicon on Insulator
BSIMSOI
MOSFET
BSIM-MG
Multi-Gate
MOSFET
BSIM: Berkeley Short-channel IGFET Model
UC Berkeley - 3
Versatile Multi-Gate Compact Model: BSIM-MG
BOX
UTBSOI
P+ back-gate
p-sub
BG-ETSOI
Fin
Gate 1
Gate 2
BSIM-IMG
Vertical Fin
IMG
BOX
BSIM-CMG
Lg
G
S
D
Tsi
FinFETs on Bulk and
SOI Substrates
UC Berkeley - 4
Independent Double-gate SOI
Tsi=7nm
Tbox=10nm
Tsi
BOX
UTBSOI
Y. Choi et al. EDL 2000
(UC Berkeley)
ETSOI
UT2B
K. Cheng et al. IEDM 2009 F. Andrieu et al. VLSI 2010
(IBM / ST)
(LETI / ST / IBM / SOITEC)
UC Berkeley - 5
Executive Summary/ Outline : BSIM-IMG
-2
10
Real Device Effects
Core SPE
I-V
C-V
-3
10
-4
10
W=50 x 0.5µm
L = 50 nm
-5
10
-6
Vbg = 10v, 15v,
10
5.0
20v,
25v
Cross:
Measurements
Lines: BSIM-IMG
4.0
Cross: Measurements
W=50 x 0.5µm
3.5BSIM-IMG
Lines:
L = 50 nm
-7
10
-8
10
-9
10
-0.2
0.0
Transconductance (mS)
Production Ready Compact Model for FDSOI
Physical Core Model
Palette of Real Device Effects
Validated to Hardware Silicon Data
Synchronized with EDA Vendors Tools
Drain Current (A)
0.2
4.5
3.0
0.4
2.5
0.6
0.8
1.0
Gate Voltage
(V)
2.0
1.5
1.0
Increasing Vbg
0.5
0.0
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate Voltage (V)
BSIM-IMG
Validation
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Where Are We!
Introduction
Core Model
Surface Potential
Equation
Drain Current
Capacitance Model
Real Device Effects
Model Validation & QA
Conclusion
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Independent-gate Device Structure: BSIM-IMG
Vfg
Asymmetric structure
Different Gate Workfunctions
Allows dissimilar Gate
Potentials
Different Oxide
thickness and Material !
Front Gate
Tox1
Source
y
x
Tsi
Drain
NA
Tox2
Captures important
features
Threshold Voltage
tuning through BackGate
Multi-Vth technology
Vs
Vd
Back Gate
Vbg
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Computationally Efficient Core
Fast !
BSIM-IMG Ψs
Cumulative Percentage
100
80
Iterative
Method A
60
40
Iterative
Method B
20
0
0
2
4
6
8
Efficient Non-iterative
Surface Potential
calculation
Investigated NR,
Shooting Secant etc.
Surface potential needs to
solved atleast twice Source and Drain side
Obtain ψs / Qis and ψd / Qid
10
Computational Time (µs)
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Surface Potential: Verification with TCAD
0.7
Symbols: TCAD
Front Surface Potential (V)
Front Surface Potential (V)
0.8
Lines : Model
0.6
0.5
Tox2
Tox2
Tox2
Tox2
Tox2
0.4
0.3
0.2
0.1
0.0
-0.4
-0.2
0.0
0.2
0.4
=
=
=
=
=
40 nm
20 nm
10 nm
5 nm
2.5 nm
0.6
0.8
1.0
0.9
0.6
Vch = 0.0 V
Vch = 0.3 V
Vch = 0.6 V
Vch = 0.9 V
0.3
0.0
Tox1=1.2nm Tox2 = 20nm
Tsi = 15nm Vbg = 0
-0.3
0.0
0.5
1.0
Front Gate Voltage (V)
Front Gate Voltage (V)
Front Surface Potential (V)
0.9
0.8
0.7
0.6
0.5
Symbols: TCAD
Lines : Model
Scalable w.r.t. physical
parameters like Tsi, Tox (front and
back) and node voltages etc.
T ox2=1.2nm
0.4
0.3
Tsi
Tsi
Tsi
Tsi
0.2
0.1
0.0
-0.1
-0.2
-0.4
-0.2
0.0
0.2
0.4
=
=
=
=
5
10
15
20
0.6
nm
nm
nm
nm
0.8
Front Gate Voltage (V)
1.0
Volume Inversion
Preserves Important Property like Volume Inversion
0.01
- - - - - - -
2
Charge Density, Qi (coul/m )
Toxb = 10μ
μm
In sub-threshold (Low field), the charge density Qi is
proportional to the body thickness Tsi
1E-3
1E-4
1E-5
Tsi = 5nm
Tsi = 10nm
Tsi = 20nm
1E-6
1E-7
Qi Ratio
1E-8
1E-9
1E-10
-1.0
1E-11
1E-12
-0.6
5
4
3
2
1
-0.5
-0.4
-0.3
Tsi ↑
-0.5
Ψsf (V)
-0.2
0.0
-0.1
Front Surface Potential, Ψsf (V)
0.0
- - - - - - - - - - - - -
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Drain Current Model
Drain Current
W
I ds = µ ⋅
L
 Qinv , s + Qinv ,d
(ψ s1,d −ψ s1,s ) + η ⋅ kT (Qinv,s − Qinv,d )
⋅
2
q


Drift
Diffusion
η = 2−
2ε si Es 2
Qinv + 2ε si Es 2
Qinv: inversion carrier density
Es2: back-side electric field
ψs1: front-side surface potential
Very high accuracy
No Charge-sheet Approximation
250
200
Error Relative to TCAD (%)
15
Drain Current (µA)
Vfg = 0.2v, 0.4v, 0.6v, 0.8v, 1.0v
Charge sheet
This Work
TCAD
150
100
50
0
0.0
0.2
0.4
0.6
Drain Voltage (V)
0.8
1.0
Charge-sheet Model
This Work
10
5
0
-5
-10
-15
-0.5
0.0
0.5
1.0
Front Gate Voltage (V)
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Capacitance Model
Model inherently exhibits symmetry
Cij = Cji @ Vds= 0 V
Model overlies TCAD results
No tuning parameters used
Toxf = 1.2nm, Toxb = 20nm,
Tsi = 15nm, Vbg = 0 V
1.0
Vfg = 0.8V, Vbg = 0 V
0.4
0.3
Cds
Csd
Css
Cdd
0.2
0.1
0.0
0.0
0.2
0.4
0.6
Drain Voltage (V)
0.8
1.0
Normalized Capacitance
Normalized Capacitance
0.5
0.8
0.6
Tox1 = 1.2nm
Tsi = 15nm
Tox2 = 20nm
Vbg = 0 V
Cfg,fg
0.4
0.2
Cbg,fg
0.0
Cd,fg
-0.2
-0.4
-0.5
Cs,fg
0.0
0.5
1.0
1.5
Front Gate Voltage (V)
Symbols: TCAD Results; Lines: Model
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Where Are We!
Introduction
Core Model
Surface Potential
Equation
Drain Current
Capacitance Model
Real Device Effects
Model Validation & QA
Conclusion
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Short Channel Effects
BOX
P+ back-gate
p-sub
BOX
Lg↓
p-sub
Vt Roll-off (V)
0.00
-0.05
-0.10
Vds = 50mV
Vds = 1.0V
-0.15
-0.20
-0.25
-0.30
0.01
Symbols: TCAD
Lines: Model
0.1
1
Lg (um) T = 8nm
si
Tbox = 4nm
Scale
Length
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Length Dependent γ Model
Capacitive coupling ratio
Front Gate
Cox1
Vds = 1V
Cd1(Leff)
Cox2
Cd2(Leff)
0.22
Back 10Gate
-2
0.20
0.18
0.01
Tsi=8nm
-3
10
TCAD
Model
0.1
1
Gate Length (µm)
Tbox=4nm
Drain Current (A)
Gamma (γ)
0.24
Csi
Source /
Drain
-4
10
W=50 x 0.5µm
L = 50 nm
-5
10
-6
Vbg = 10v, 15v,
10
20v, 25v
-7
10
Cross: Measurements
Lines: BSIM-IMG
-8
10
-9
10
γ degraded at short channel
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
Captures Vbg effect in I-V
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QM Effect: Inv. Charge Centroid Model
Vdd = 0.9 V ; Vfb = 28 mV
TBOX = 140nm; Tsi = 6nm; Nsub = 1e16 cm3
BOX
60
p-sub
Vgs↑
Cgtotal (fF/µm^2)
50
EOTphys = 0.65nm
Tinv = 1.13nm
EOTeff = 0.95nm
40
30
20
SCHRED_Clas
BSIM-IMG
10
SCHRED_QM
BSIM-IMG Fitted
0
0
0.5
1
1.5
Gate Voltage (V)
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Self Heating Model
Thermal Node: Rth/Cth
methodology
T
Relies on Accurate physical
modeling of Temperature
Effects in the model
Drain Current (µA)
1000
800
Without Self Heating
With Self Heating
Vgs=1.0
600
Vgs=0.8
400
Vgs=0.6
200
Vgs=0.4
0
0.0
0.2
0.4
0.6
0.8
1.0
Vds (V)
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Real Device Effects
Channel Length
Modulation and
DIBL
Mobility
Degradation
Velocity
Saturation
GIDL Current
Short
Channel
Effects
Core
SPE
I-V
Quantum
Effects
Temperature
Effects
C-V
Fringe
Capacitances
Impact Ionization
current
Direct tunneling
gate current
S/D Resistance/
Parasitic
Resistance
Noise models
More Effects?
Overlap
capacitances
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Where Are We!
Introduction
Core Model
Surface Potential
Equation
Drain Current
Capacitance Model
Real Device Effects
Model Validation & QA
Conclusion
UC Berkeley - 20
Validation to Hardware Data
Device from CEA-LETI
Tbox=145nm
EOT=1.6nm Tsi= 8nm
L = 50nm
Na=1e15
Φg2 = 5.0
Vbg = floating, 10V, 15V, 20V, 25V
Id,lin
-2
Id,lin
10
-3
10
Drain Current (mA)
Drain Current (A)
-4
10
W=50 x 0.5µm
L = 50 nm
-5
10
-6
Vbg = 10v, 15v,
10
20v, 25v
-7
10
Cross: Measurements
Lines: BSIM-IMG
-8
10
-9
10
-0.2
0.0
0.2
0.4
0.6
0.8
Gate Voltage (V)
1.0
W=0.5um x 50
Φg1 = 4.55 (fitted)
2.5
2.0
Cross: Measurements
Lines: BSIM-IMG
1.5
Vbg = 10v, 15v,
20v, 25v
Increasing Vbg
1.0
0.5
W=50 x 0.5µm
L = 50 nm
0.0
-0.4 -0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Gate Voltage (V)
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Validation Contd.
4.0
3.5
3.0
Cross: Measurements
Lines: BSIM-IMG
W=50 x 0.5µm
L = 50 nm
2.5
2.0
1.5
1.0
Increasing Vbg
0.5
0.0
Drain Current (mA)
0
10
W=50 x 0.5µm
L = 50 nm
-1
10
-2
10
Vbg = 10v, 15v,
-3
10
20v, 25v
-4
10
Cross: Measurements
Lines: BSIM-IMG
-5
10
-6
Gate Voltage (V)
15.0
1
10
10
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2
Id,sat
20.0
Id,sat
Drain Current (mA)
4.5
10
Cross: Measurements
Lines: BSIM-IMG
Vbg = 10v, 15v,
20v, 25v
10.0
Increasing Vbg
5.0
W=50 x 0.5µm
L = 50 nm
0.0
-0.4 -0.2
0.0
0.2
0.4
0.6
0.8
Gate Voltage (V)
1.0
1.2
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage (V)
Gm,sat
25
Transconductance (mS)
Transconductance (mS)
Gm,lin
2
5.0
20
Cross: Measurements
Lines: BSIM-IMG
15
W=50 x 0.5µm
L = 50 nm
10
5
Increasing Vbg
0
-0.4 -0.2
0.0
0.2
0.4
0.6
0.8
Gate Voltage (V)
1.0
1.2
Global Parameter Extraction for ETSOI
Calibration of the model
Through internship at IBM T.J. Watson
Work by Darsen Lu
Global Extraction performed for NMOS & PMOS at
L=24nm …… 66nm
Excellent agreement for I-V across all gate lengths
C-V extracted and fine-tuned to match ring oscillator
delay v.s. Vdd
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Gummel Symmetry Test
Drain Current Symmetry
V fg=0.2
0.00
V fg=0.4
-0.02
V fg=0.6
-0.04
Vfg=0.8
Vbg=0
3
3
3
d Ix / dVx (A / V )
0.02
-0.06
-0.10
-0.05
0.00
Analog /RF Ready
0.10
Vx (V)
AC (charge) Symmetry
20
10
-1
dδcsd / dVx (V )
V bg=0
16
V fg =0.2
12
V fg =0.6
8
V fg =0.8
V fg =0.4
4
0
-0.10
-0.05
8
V bg=0
V fg =0.2
-1
dδcg / dVx (V )
0.05
0.00
Vx (V)
0.05
0.10
V fg =0.6
6
V fg =0.8
4
V fg =0.4
2
0
-0.10
-0.05
C. C. McAndrew, TED 2006
0.00
Vx
0.05
0.10
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Convergence Tests
Excellent Convergence Properties
Ex: 17-stage ring oscillator
0.8
Vbgn = 0 V
0.6
0.4
Vbgp = 1 V
0.2
0.0
0.0
20.0p
40.0p
60.0p
80.0p
100.0p
120.0p
140.0p
1.0
Vout (V)
Various
Back-Gate
Potential
Conditions
Vout (V)
1.0
Vbgn = -3 V
0.8
0.6
Vbgp = 4 V
0.4
0.2
0.0
0.0
20.0p
40.0p
60.0p
80.0p
100.0p
120.0p
140.0p
Time (sec)
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Speed Tests
Circuit
# MOSFETs
1-Transistor Id-Vds
Model
Runtime per iteration per
transistor (μs)
1
BSIM4
IMG
40.7
29.1
17-Stage Ring
34
BSIM4
IMG
31.3
18.8
Coupled Rings
2020
BSIM4
IMG
41.0
22.6
Speed of BSIM-IMG v101 and BSIM v4.5 compared
Both model compiled with the in-built Verilog-A
compiler of HSpice
Note: Each model uses its own default parameter.
Parameters are not extracted for a real technology.
GIDL, Ig, Self-heating turned off.
Averaged over 5 runs on a Linux box with a single-core AMD Opteron Processor (2.39GHz)
Where Are We!
Introduction
Core Model
Surface Potential
Equation
Drain Current
Capacitance Model
Real Device Effects
Model Validation & QA
Conclusion
UC Berkeley - 27
Technology Transfer
Release of BSIM-IMG 101 (April 2011)
Available in EDA tools: SimuCAD, ProPlus,
Accelicon
Implementation In Progress @ Cadence,
Synopsys
Package Ready for Technology Evaluation and
Design under NDA
Verilog-A code and Well-documented
Technical Manual
Provide some support and Commitment to
improve the model
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Summary
BSIM-IMG is a Turnkey , Production Ready model
Will be submitted to the CMC for standardization
Physical, Scalable Core Model for FDSOI devices
Plethora of Real Device Effects modeled
Advanced Device Effects – Quantum, Back-gate
bias
Validated on Hardware Data from two
FDSOI/UTBSOI technologies
Available in major EDA tools
UC Berkeley - 29
Publications
D. D. Lu, M. V. Dunga, C-H. Lin, A. M. Niknejad and C. Hu, "
A Multi-Gate MOSFET Compact Model Featuring
Independent-Gate Operation", IEDM, December 2007
D. D. Lu, M. V. Dunga, C-H. Lin, A. M. Niknejad and C. Hu,
“ A Computationally Efficient Compact Model for fullydepleted SOI MOSFETs with independently-controlled
front- and back-gates", Solid State Electronics, in Press,
available online
D. D. Lu, C-H. Lin, A. M. Niknejad and C. Hu, “ Multi-Gate
MOSFET Compact Model BSIM-MG", a chapter in Compact
Modeling Principles, Techniques and Applications, Springer
2010
.
UC Berkeley - 30
Acknowledgement
Funding
Data
SRC Task 2055
Grant from SOITEC
LETI-SOITEC
IBM
Feedback
EDA Vendors and Users
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