HIGH-TEMPERATURE BULK CMOS INTEGRATED
CIRCUITS FOR DATA ACQUISITION
by
XINYU YU
Submitted in partial fulfillment of the requirements
For the degree of Doctor of Philosophy
Dissertation Adviser: Dr. Steven L. Garverick
Department of Electrical Engineering and Computer Science
CASE WESTERN RESERVE UNIVERSITY
May, 2006
CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the dissertation of
Xinyu Yu
______________________________________________________
candidate for the Ph.D. degree *.
Steven L. Garverick
(signed)_______________________________________________
(chair of the committee)
Mehran Mehregany
________________________________________________
Christian Zoraman
________________________________________________
Darrin Young
________________________________________________
Chung-Chiun Liu
________________________________________________
________________________________________________
4/3/2006
(date) _______________________
*We also certify that written approval has been obtained for any
proprietary material contained therein.
To my family
List of Contents
List of Contents.................................................................................................................... i
List of Tables ..................................................................................................................... iv
List of Figures ..................................................................................................................... v
Acknowledgements............................................................................................................. x
Abstract .............................................................................................................................. xi
1
Introduction................................................................................................................. 1
1.1
Motivation........................................................................................................... 1
1.2
Background ......................................................................................................... 3
1.2.1
High temperature behavior of MOSFET .................................................... 3
1.2.1.1 Energy bandgap, intrinsic carrier density and carrier concentration ...... 3
1.2.1.2 Carrier mobility....................................................................................... 5
1.2.1.3 Threshold voltage.................................................................................... 6
1.2.1.4 Leakage current....................................................................................... 7
1.2.2
SPICE simulation for high temperature.................................................... 10
1.2.3
Existing high temperature circuit techniques............................................ 10
1.2.3.1 Zero temperature coefficient gate biasing............................................. 10
1.2.3.2 Leakage current cancellation ................................................................ 11
1.2.3.3 Substrate bias feedback......................................................................... 15
1.2.3.4 Constant-Gm biasing ............................................................................. 15
1.2.4
Published work in high-temperature bulk CMOS .................................... 16
1.3
Objectives ......................................................................................................... 18
2
Architecture............................................................................................................... 20
2.1
System Overview .............................................................................................. 21
2.2
Sensor Interface Architecture ........................................................................... 23
2.2.1
Selection of sensor interface architecture ................................................. 23
2.2.2
Stimulus to the Wheatstone bridge: AC vs. DC ....................................... 27
2.2.3
Offset......................................................................................................... 29
2.3
Electronic System Architecture ........................................................................ 29
3
High-Temperature, Mixed-Signal Circuit Modules.................................................. 31
3.1
Circuit Topology............................................................................................... 31
3.2
Process and Device Parameters ........................................................................ 31
3.3
Bias Circuit ....................................................................................................... 32
3.4
Oscillator........................................................................................................... 35
3.4.1
Architecture............................................................................................... 36
3.4.2
Circuit implementation ............................................................................. 36
3.4.2.1 Delay cell .............................................................................................. 36
3.4.2.2 Differential-to-single-ended converter.................................................. 38
3.5
Temperature Sensors......................................................................................... 39
3.5.1
Internal thermometer circuit ..................................................................... 39
3.5.2
RTD sensor interface ................................................................................ 41
3.5.2.1 Specifications and architecture ............................................................. 41
3.5.2.2 Circuit implementations........................................................................ 44
3.5.2.2.1 Design of the OPAMP .................................................................... 44
3.5.2.2.2 RTD sensor interface ...................................................................... 46
i
4
High-Temperature, Mixed-Signal Instrumentation Amplifier.................................. 48
4.1
Overview........................................................................................................... 48
4.2
Delta Modulator ................................................................................................ 49
4.2.1
Principle of operation................................................................................ 49
4.2.2
Slope overload .......................................................................................... 50
4.2.3
Quantization noise .................................................................................... 50
4.3
Noise Analysis and Design ............................................................................... 51
4.3.1
Matched maximum slew rate .................................................................... 51
4.3.2
Matched thermal and quantization noise .................................................. 52
4.3.3
Ratioed thermal and quantization noise.................................................... 53
4.4
Detailed Circuit Design..................................................................................... 54
4.4.1
Double-sampling pre-amplifier................................................................. 54
4.4.1.1 Specifications and architecture ............................................................. 55
4.4.1.2 Circuit implementation ......................................................................... 58
4.4.2
Switched-capacitor comparator ................................................................ 61
4.4.2.1 Architecture........................................................................................... 61
4.4.2.2 Circuit implementation ......................................................................... 63
4.4.3
Switched-capacitor, binary integrator....................................................... 65
4.4.4
Offset cancellation circuitry...................................................................... 68
4.4.4.1 Architecture........................................................................................... 68
4.4.4.2 Systematic offset................................................................................... 69
4.4.4.3 Random offset....................................................................................... 70
4.4.4.4 Reference generator .............................................................................. 71
4.5
Test Results....................................................................................................... 73
4.5.1
First test chip............................................................................................. 73
4.5.1.1 Overview............................................................................................... 73
4.5.1.2 High-temperature test setup .................................................................. 74
4.5.1.3 Bias circuit ............................................................................................ 75
4.5.1.4 Oscillator............................................................................................... 77
4.5.1.5 FDOA.................................................................................................... 81
4.5.1.5.1 Test setup ........................................................................................ 81
4.5.1.5.2 Offset............................................................................................... 82
4.5.1.5.3 DC transfer characteristics.............................................................. 83
4.5.1.5.4 AC test ............................................................................................ 85
4.5.1.6 Instrumentation amplifier...................................................................... 85
4.5.1.6.1 Test setup and typical waveform .................................................... 85
4.5.1.6.2 AC response .................................................................................... 87
4.5.2
Second test chip ........................................................................................ 89
4.5.2.1 Overview............................................................................................... 89
4.5.2.2 High- temperature test setup ................................................................. 90
4.5.2.3 Oscillator............................................................................................... 92
4.5.2.4 Internal thermometer circuit ................................................................. 94
4.5.2.5 RTD interface circuit ............................................................................ 96
4.5.2.6 Offset cancellation circuitry.................................................................. 99
4.5.2.6.1 Test setup ........................................................................................ 99
4.5.2.6.2 Room-temperature tests ................................................................ 100
ii
5
6
7
8
4.5.2.6.3 High-temperature tests .................................................................. 103
4.5.2.7 Instrumentation amplifier.................................................................... 106
4.5.2.7.1 Amplitude sweep .......................................................................... 106
4.5.2.7.2 Frequency response....................................................................... 110
4.5.2.7.3 Harmonic distortion ...................................................................... 112
4.5.2.7.4 Noise ............................................................................................. 115
High-Temperature, Sigma-Delta Modulator........................................................... 119
5.1
Overview......................................................................................................... 119
5.2
Sigma-Delta Modulator .................................................................................. 120
5.2.1
Background ............................................................................................. 120
5.2.2
Architecture............................................................................................. 124
5.2.3
High-temperature design considerations................................................. 126
5.2.3.1 Integrator gain..................................................................................... 126
5.2.3.2 OPAMP DC gain ................................................................................ 126
5.2.3.3 OPAMP bandwidth............................................................................. 126
5.2.3.4 Slew rate.............................................................................................. 127
5.2.3.5 Signal range ........................................................................................ 128
5.2.3.6 Electrical noise and offset................................................................... 130
5.2.3.7 Clock jitter .......................................................................................... 132
5.3
Detail Circuit Design ...................................................................................... 133
5.3.1
Improved double-sampling pre-amplifier ............................................... 133
5.3.1.1 Architecture......................................................................................... 133
5.3.1.2 Circuit implementation ....................................................................... 135
5.3.2
First-stage integrator ............................................................................... 136
5.3.2.1 Architecture......................................................................................... 136
5.3.2.2 Noise analysis and design ................................................................... 137
5.3.2.2.1 kT/C noise..................................................................................... 137
5.3.2.2.2 Amplifier thermal noise ................................................................ 138
5.3.2.2.3 Total noise..................................................................................... 139
5.3.2.3 Circuit implementation ....................................................................... 139
5.3.3
Sigma-delta modulator............................................................................ 140
5.4
Test Results..................................................................................................... 143
5.4.1
Overview................................................................................................. 143
5.4.2
Test setup ................................................................................................ 144
5.4.3
Sigma-delta modulator............................................................................ 146
5.4.3.1 Room temperature tests....................................................................... 146
5.4.3.2 High temperature test.......................................................................... 151
5.4.4
Sigma-delta modulator with CDS pre-amplifier..................................... 155
Conclusions............................................................................................................. 169
6.1
Achievements.................................................................................................. 169
6.2
Future Work .................................................................................................... 172
Appendix................................................................................................................. 174
Bibliography ........................................................................................................... 177
iii
List of Tables
Table 1.1: Temperature range for typical high temperature applications (from [4]). (Note:
“breaks” should be brakes”)........................................................................................ 1
Table 1.2: Summary of published high-temperature amplifiers. ...................................... 17
Table 1.3: Summary of published high-temperature ADCs. ............................................ 18
Table 2.1: Preliminary piezoresistive flow sensor specifications (after [27]). ................. 20
Table 2.2: Requirements for IC development (after [27]). ............................................... 20
Table 3.1: Key device parameters using hand calculations (after [31]). .......................... 32
Table 4.1: Reference levels of offset cancellation circuitry for different gain settings.... 70
Table 4.2: Oscillator temperature stability for the 5-04 lot. ............................................. 78
Table 4.3: Oscillator temperature stability for the 5-05 lot. ............................................. 79
Table 4.4: Oscillator temperature stability (9-05 lot). ...................................................... 93
Table 4.5: Summary of oscillator temperature stability for three lots. ............................. 94
Table 4.6: Temperature stability of the output current of the RTD interface circuit........ 98
Table 4.7: Instrumentation amplifier gain stability for several temperature ranges and
low-clock setting (fclk = ~1.5 MHz, 9-05 lot).......................................................... 107
Table 5.1: Nominal operating conditions of sigma-delta modulator. ............................. 125
Table 5.2: Measured SNR and SNDR of the sigma-delta modulator with CDS preamplifier vs. gain settings for a 701.904 Hz, -42.7-dBV input at 25 °C. ............... 156
Table 5.3: CDS pre-amplifier gain stability for several temperature ranges and a 701.904Hz, -42.7-dBV input tone (nominal operating conditions). .................................... 158
Table 5.4: CDS pre-amplifier gain stability for several temperature ranges and a 421.5Hz, -42.7-dBV input tone (fclk = 1.2288 MHz). ...................................................... 160
Table 5.5: Measured SNR and SNDR vs. gain settings for a 701.904 Hz input and an
input level of -6 dBFS at the modulator input at 25 °C and 300 °C. ...................... 163
Table 6.1: Comparison of the instrumentation amplifier and published high-temperature
amplifiers. ............................................................................................................... 170
Table 6.2: A comparison of the sigma-delta modulator and published high-temperature
ADCs....................................................................................................................... 172
iv
List of Figures
Figure 1.1: Electron density in silicon as a function of reciprocal temperature, for a donor
impurity concentration of 1015 cm-3 (after [11]).......................................................... 4
Figure 1.2: Measured channel mobility of electrons vs. temperature for a 50 µm x 50 µm
NMOS in bulk CMOS (after [12]).............................................................................. 5
Figure 1.3: Parasitic diodes at drain and source junctions of a NMOS transistor. ............. 8
Figure 1.4: Measured leakage currents of drain junctions of an NMOS and a PMOS
transistor, respectively. The p-type epitaxial layer has a doping concentration NA =
1015 cm-3 and the n-well doping concentration is ND = 4 x 1016 cm-3. The area of
both junctions is 2 x 20 mm2 and they are reverse biased with 2 V (from [5]). ......... 9
Figure 1.5: Measured drain current characteristics at selected temperature (from [15]).. 11
Figure 1.6: Complementary diode leakage current cancellation (from [12]). .................. 12
Figure 1.7: Leakage current compensation using replica device (from [18])................... 13
Figure 1.8: Doughnut shaped layout for analog switch (from [20]). ................................ 13
Figure 1.9: Leakage current cancellation feedback (from[21]). ....................................... 14
Figure 1.10: Constant-Gm biasing circuit.......................................................................... 16
Figure 2.1: Basic system architecture. .............................................................................. 21
Figure 2.2: Proposed system architecture in high temperature environment.................... 22
Figure 2.3: Traditional approach to Wheatstone bridge interface circuit. ........................ 23
Figure 2.4: bridge interface using ac transimpedance amplifier and synchronous
demodulation............................................................................................................. 24
Figure 2.5: Bridge interface using high-temperature ac voltage amplifier and synchronous
demodulation............................................................................................................. 25
Figure 2.6: Bridge interface using high-temperature IC with baseband output and internal
oscillator/demodulator. ............................................................................................. 25
Figure 2.7: Bridge interface using high-temperature, correlated double-sampling
amplifier with internal oscillator/demodulator. ........................................................ 26
Figure 2.8: Bridge interface using correlated double-sampling amplifier with delta
modulator. ................................................................................................................. 26
Figure 2.9: Alternative implementation of CDS bridge interface with DC biasing of the
bridge and chopping of bridge outputs. .................................................................... 28
Figure 2.10: Proposed electronics architecture using HTIC............................................. 30
Figure 3.1: Schematic of bias circuit. ............................................................................... 33
Figure 3.2: Simulated IR1 vs. temperature......................................................................... 35
Figure 3.3: Block diagram of the fully-integrated oscillator for clock generation. .......... 36
Figure 3.4: Delay cell designs for a ring oscillator........................................................... 37
Figure 3.5: Schematic of the differential-to-single-ended converter. ............................... 39
Figure 3.6: Internal thermometer circuit........................................................................... 40
Figure 3.7: SC voltage-to-current source (from [36])....................................................... 42
Figure 3.8: Implementation of SC voltage-to-current source used in this work (after [37]).
................................................................................................................................... 43
Figure 3.9: Nested Miller compensation with zero cancellation (from [38]). .................. 45
Figure 3.10: Schematic of the three-stage OPAMP.......................................................... 46
Figure 3.11: Schematic of the RTD sensor interface........................................................ 47
Figure 4.1: Block diagram of the instrumentation amplifier. ........................................... 48
v
Figure 4.2: (a) Block diagram of a delta modulator; (b) typical tracking waveform for a
delta modulator (from [39]). (Note: in (b), y(t) is Vy, q(t) is Vy’, Q is y, and σ is H.)
................................................................................................................................... 49
Figure 4.3: Calculated gm and slew rate vs. thermal-to-quantization noise ratio (x) for the
highest gain setting (T = 125 °C).............................................................................. 54
Figure 4.4: Simplified schematic of the double-sampling amplifier. ............................... 56
Figure 4.5: Schematic of FDOA with voltage buffers...................................................... 58
Figure 4.6: Switched-capacitor common-mode feedback. ............................................... 60
Figure 4.7: Switched-capacitor comparator...................................................................... 62
Figure 4.8: Timing of the CDS pre-amplifier and SC comparator. .................................. 63
Figure 4.9: Schematic of the comparator preamplifier. .................................................... 64
Figure 4.10: Schematic of regenerative comparator. ........................................................ 65
Figure 4.11: Simplified schematic of the integrator design using 1-bit IDAC (from [42]).
................................................................................................................................... 66
Figure 4.12: Block diagram of a closed-loop switched-capacitor integrator.................... 66
Figure 4.13: Proposed open-loop switched-capacitor integrator with only one integration
capacitor.................................................................................................................... 67
Figure 4.14: Architecture of the offset cancellation circuitry. (For simplicity, a singleend version is shown here.)....................................................................................... 69
Figure 4.15: Detailed block diagram of random offset cancellation (single-ended version).
................................................................................................................................... 71
Figure 4.16: Schematic of reference generator. ................................................................ 72
Figure 4.17: Die micrograph of the 5-04 instrumentation amplifier prototype ................ 73
Figure 4.18: High-temperature test setup for first test chip (from [53])........................... 74
Figure 4.19: Measured constant-gm bias current............................................................... 76
Figure 4.20: Log-lin fit on measured bias current over temperature (T0 = 25 °C). .......... 77
Figure 4.21: Measured oscillation frequency vs. temperature (5-04 lot).......................... 78
Figure 4.22: Measured oscillation frequency vs. temperature (5-05 lot).......................... 79
Figure 4.23: Schematics of (a) dynamic D flip-flop and (b) Clocked inverter................. 80
Figure 4.24: Schematic of pseudo-static D flip-flop (the complementary clock inputs of
the clocked inverters are eliminated for clarity). ...................................................... 81
Figure 4.25: FDOA test setup (after [12]). ....................................................................... 82
Figure 4.26: Measured FDOA offset vs. temperature....................................................... 83
Figure 4.27: Measured DC transfer characteristic of the FDOA at various temperatures.84
Figure 4.28: Extracted FDOA output swing from 25 °C to 235 °C.................................. 84
Figure 4.29: Measured FDOA (single-ended) open-loop frequency response for
temperatures from 25 ºC to 250 ºC. Measurements at this highest temperature are
limited by instrumentation difficulties...................................................................... 85
Figure 4.30: Instrumentation amplifier test: (a) test setup, and (b) the measured
differential output of 622 mVrms for a sinusoidal input of 54 mVrms @ 35 Hz and
250 °C. ...................................................................................................................... 86
Figure 4.31: Measured amplifier gain vs. temperature at different gain settings, with 250
Hz input (5-04 lot). Inputs are adjusted to obtain a differential output of 0.447 Vrms
in each gain setting.................................................................................................... 87
vi
Figure 4.32: Measured amplifier gain vs. temperature at different gain settings, with 250
Hz input (5-05 lot). Inputs are adjusted to obtain a differential output of 0.447 Vrms
in each gain setting.................................................................................................... 88
Figure 4.33: Measured amplitude response at a variety of temperatures with amplifier
gain set to twelve and an input signal frequency of 250 Hz (5-04 lot)..................... 89
Figure 4.34: Die micrograph of second version of the instrumentation amplifier test chip
(9-05 lot). .................................................................................................................. 90
Figure 4.35: Improved version of the high-temperature test setup................................... 91
Figure 4.36: Measured oscillation frequency vs. temperature (9-05 lot).......................... 93
Figure 4.37: Measured voltage output of the internal thermometer circuit vs. temperature.
................................................................................................................................... 95
Figure 4.38: Comparison between measured and calculated output of the internal
thermometer circuit vs. temperature. ........................................................................ 96
Figure 4.39: Measured output current of the RTD interface circuit for various VDD and
swept clock frequency, at room temperature. ........................................................... 97
Figure 4.40: Measured output current from RTD interface vs. temperature for two
frequency settings. .................................................................................................... 98
Figure 4.41: Block diagram of offset cancellation test setup............................................ 99
Figure 4.42: Measured and calculated transfer characteristics of the offset DAC at
different clock frequencies (GA=6, GD=2). ........................................................... 101
Figure 4.43: Transfer characteristics of offset DAC at different gain settings (room
temperature). ........................................................................................................... 102
Figure 4.44: Transfer characteristics of the offset DAC with varied VDD (GA=6, GD=2).
................................................................................................................................. 103
Figure 4.45: Measured transfer characteristics of the offset DAC vs. temperature
(GA=24, GD=8)...................................................................................................... 104
Figure 4.46: Measured transfer characteristics of the offset DAC vs. temperature (GA=6,
GD=2). .................................................................................................................... 104
Figure 4.47: Two-stage R-2R ladder. ILx is defined as the leakage current flowing into
node x...................................................................................................................... 105
Figure 4.48: Measured amplifier gain vs. temperature for different gain settings and highfrequency clock setting, with 250-Hz input (9-05 lot). Inputs are adjusted to obtain a
differential output of 1.414 VPP in each gain setting. ............................................. 106
Figure 4.49: Measured amplifier gain vs. temperature for different gain settings and lowfrequency clock setting, with 250-Hz input (9-05 lot). Inputs are adjusted to obtain a
differential output of 1.414 VPP in each gain setting. ............................................. 107
Figure 4.50: Measured peak-to-peak output swing of the instrumentation amplifier vs.
temperature. ............................................................................................................ 108
Figure 4.51: Setting issue occurring at the delta modulator inputs................................. 109
Figure 4.52: Frequency response of instrumentation amplifier at various temperatures for
GA = 6, GD = 2, Vin-diff = 89.32 mVpp.................................................................... 110
Figure 4.53: Frequency response of the instrumentation amplifier at room temperature
with varied input amplitude (GA =6, GD = 2). ...................................................... 111
Figure 4.54: Measured 3-dB cut-off frequency vs. output amplitude............................. 112
Figure 4.55: AC response of the instrumentation amplifier with 35-Hz, ~0.5-Vpp output.
(GA=24, GD=8, GO =1, fclk =~1.5 MHz, Cint = 1.5 nF). ........................................ 113
vii
Figure 4.56: Harmonic distortion vs. temperature for a ~0.5-Vpp output at 35 Hz......... 114
Figure 4.57: Harmonic distortion vs. temperature for a 5-Vpp output at 35 Hz.............. 114
Figure 4.58: Measured output-referred noise spectral density at room temperature with
zero differential input.............................................................................................. 115
Figure 4.59: Output-referred noise spectral density for various integration capacitors, at
room temperature. ................................................................................................... 117
Figure 4.60: Measured output-referred rms noise using a DVM with 3-kHz bandwidth vs.
temperature and various gain settings based on three measurements..................... 118
Figure 5.1: Block diagram of the sigma-delta IC. .......................................................... 119
Figure 5.2: (a) Block diagram of sigma-delta modulator. (b) Linearized model of the 1storder sigma-delta modulator (after [57]). ............................................................... 121
Figure 5.3: Second-order sigma-delta modulator (from [60]). ....................................... 123
Figure 5.4: Modified architecture of the 2nd-order sigma-delta modulator (from [62]). 124
Figure 5.5: Matlab® simulation showing influence of integrator output slew rate on
SNDR of 2nd-order sigma-delta modulator. Input amplitude is -6 dBFS and OPAMP
bandwidth is set to infinity...................................................................................... 128
Figure 5.6: Revised coefficients to extend signal range at high temperature. ................ 130
Figure 5.7: Offset- and gain-compensated SC amplifiers (from [29]): (a) narrowband
compensated SC amplifier [70]; (b) wideband compensated SC amplifier [71]; (c)
wideband compensated SC amplifier with storage capacitor [72].......................... 134
Figure 5.8: Schematic of the gain-compensated CDS pre-amplifier used in the sigmadelta modulator. In this drawing, the random offset sign bit is set to zero............ 135
Figure 5.9: Single-ended version of the CDS first-stage integrator. CP is the parasitic
capacitance at amplifier input and Vna is the input-referred amplifier noise. ......... 136
Figure 5.10: Detailed block diagram of the sigma-delta modulator and its timing diagram.
................................................................................................................................. 141
Figure 5.11: Difference between simulated and calculated integrator outputs for a DC
input of 54% full scale. ........................................................................................... 142
Figure 5.12: AC simulation of the sigma-delta modulator with half-scale input at 1.343
kHz. Sampling rate is 2 MHz and OSR is 256. 16k samples were collected. ...... 143
Figure 5.13: Die micrograph of high-temperature sigma-delta test chip........................ 144
Figure 5.14: Measured spectral content of the sigma-delta modulator for a 701.904-Hz, 6-dBFS input tone. .................................................................................................. 147
Figure 5.15: In-band (4 kHz) spectral content for data of Figure 5.14........................... 148
Figure 5.16: Measured SNR and SNDR for 4-kHz bandwidth vs. input level referred to
full scale. ................................................................................................................. 149
Figure 5.17: Measured spectral content of the sigma-delta modulator with zero signal
input, using internal oscillator as sampling clock................................................... 150
Figure 5.18: Measured spectral content for a 256.984-Hz, -15-dBFS input tone using
internal oscillator as sampling clock....................................................................... 151
Figure 5.19: Measured spectral content of the sigma-delta modulator output for a
701.904-Hz, -6-dBFS input tone at 25 °C and 300 °C. .......................................... 152
Figure 5.20: In-band (4 kHz) spectral content for data of Figure 5.19........................... 152
Figure 5.21: Measured SNR and SNDR vs. input level at 300 °C. ................................ 153
Figure 5.22: Measured SNR vs. input level for various temperatures............................ 154
Figure 5.23: Measured SNDR vs. input level for various temperatures......................... 154
viii
Figure 5.24: Measured peak SNR and SNDR vs. temperature....................................... 155
Figure 5.25: In-band (4 kHz) spectral content for a 701.904-Hz, -42.7-dBV input tone
and various pre-amplifier gain settings at 25 °C..................................................... 156
Figure 5.26: In-band (4 kHz) spectral content for a 701.904-Hz, -42.7-dBV input tone
and various pre-amplifier gain settings at 300 °C................................................... 157
Figure 5.27: Extracted CDS pre-amplifier gain vs. temperature on linear scale for a
701.904-Hz, -42.7-dBV input tone (nominal operating conditions)....................... 158
Figure 5.28: Extracted input-referred offset voltage vs. temperature for zero differential
input (nominal operating conditions)...................................................................... 159
Figure 5.29: Extracted CDS pre-amplifier gain vs. temperature on linear scale using fclk =
1.2288 MHz for a 412.5-Hz, -42.7-dBV input tone................................................ 160
Figure 5.30: Extracted input-referred offset voltage vs. temperature for zero differential
input. (fclk = 1.2288 MHz). ..................................................................................... 161
Figure 5.31: In-band (4 kHz) spectral content for a 701.904-Hz input tone and an input
level of -6 dBFS at the modulator input at 25 °C. .................................................. 162
Figure 5.32: In-band (4 kHz) spectral content for a 701.904-Hz input tone and an input
level of -6 dBFS at the modulator input at 300 °C. ................................................ 162
Figure 5.33: Measured SNR of sigma-delta modulator with CDS pre-amplifier vs. input
level at 25 °C........................................................................................................... 164
Figure 5.34: Measured SNR of sigma-delta modulator with CDS pre-amplifier vs. input
level at 300 °C......................................................................................................... 164
Figure 5.35: Measured SNDR of modulator with CDS pre-amplifier vs. input level at 25
°C. ........................................................................................................................... 165
Figure 5.36: Measured SNDR of modulator with CDS pre-amplifier vs. input level at 300
°C. ........................................................................................................................... 165
Figure 5.37: Measured peak SNR of modulator with CDS pre-amplifier vs. temperature.
................................................................................................................................. 167
Figure 5.38: Measured peak SNDR of the modulator with CDS pre-amplifier vs.
temperature. ............................................................................................................ 167
ix
Acknowledgements
I am forever indebt to my advisor, Dr. Steven L. Garverick for his guidance,
encouragement and patience over last six years. Without his help, this work would not
go through. It was a great pleasure experience to work with him, and I will certainly miss
it.
I would like to thank my committee members Dr. Mehran Mehregany, Dr. Darrin
Young, Dr. Chung-Chiun Liu and Dr. Christian Zorman for their valuable help and
suggestion on my thesis.
I am grateful to my friends, including Shuyu Lei, Jianyun Zhang, Yawei Guo,
Cong Peng, Run Wang and Jun Guo, for their suggestion, comments and assists on my
work. I would like to thank Hari Rajgopal for his cooperation in the Prolusion 21 project.
I am grateful to fellow members of Mixed-signal IC group both past and present
for their friendship and help. Also, I would like to thank the members of Prof. Young’s
group for technical discussion and assists.
I would like to thank my parents for their invaluable supports over the years of
my study.
Finally, I would like to acknowledge NASA and GE for the opportunity to be a
part of such a fascinating project.
x
High-Temperature Bulk CMOS Integrated Circuits for Data Acquisition
Abstract
by
XINYU YU
In this research, a monolithic, high-temperature bulk CMOS data acquisition
system for Wheatstone-bridge sensors has been developed. The main design challenges
were 1) excess leakage current, 2) decreased carrier mobility, and 3) unstable threshold
voltage. Design techniques were developed to overcome these high-temperature effects
and allow the bulk CMOS IC to operate at temperatures > 250 °C. Two generations of
data acquisition ICs have been designed and characterized: an instrumentation amplifier
and a sigma-delta modulator. Both were fabricated using the AMI 1.5-μm bulk CMOS
process.
The Instrumentation Amplifier IC features a fully-differential, adjustable-gain
amplifier with digitally programmable offset cancellation, and features a constant-gm
biasing circuit, a fully monolithic oscillator, internal thermometer circuit and RTD sensor
interface. The thermometer and RTD sensor interface perform well at temperatures for T
< 225 °C. The oscillator demonstrates a temperature stability of ~97 ppm/°C for T < 290
xi
°C at the fast clock setting. The instrumentation amplifier shows excellent stability for T
< 300 °C. With GA = 6 and GD = 8, gain stability is 128 ppm/°C for 25 °C < T < 300 °C.
The Sigma-Delta IC includes a sigma-delta modulator with correlated doublesampling (CDS) pre-amplifier, a stand-alone sigma-delta modulator, constant-gm biasing
circuit, oscillator and internal thermometer circuit. The CDS pre-amplifier has an
adjustable gain and digitally programmable offset cancellation. The stand-alone sigmadelta modulator has a peak SNR and SNDR of 94 dB and 90 dB, respectively, at 25 °C,
and 94 dB and 87 dB at 300 °C. The gain stability of the CDS pre-amplifier for GA = 6,
12 and 24 is 62, 66 and 95 ppm/°C, respectively, for 25 °C < T < 300 °C. At 300 °C, the
modulator with CDS pre-amplifier achieves a dynamic range of 110 dB including the
stand-alone modulator range.
xii
1 Introduction
1.1 Motivation
Analog and mixed-signal electronics are required to operate at elevated
temperatures to support sensor applications in a number of industries, including
automotive, aerospace and geothermal [1]-[3]. A majority of applications for high
temperature electronics are below 300 °C, as summarized in Table 1.1. Due to noise and
interference considerations, the sensor interface electronics must be located in close
proximity to the sensors. These electronics are typically required to operate with high
resolution but at low or moderate speed, and usually consist of a pre-amplifier stage and
an analog to digital converter (ADC), where the pre-amplifier converts the sense signal
(capacitance, resistance, temperature and etc.) to voltage or current, and the ADC
converts the resulting signal to a digital format that has high noise immunity.
Table 1.1: Temperature range for typical high temperature applications (from [4]).
(Note: “breaks” should be brakes”)
Silicon technology dominates today’s semiconductor business. The use of
Complementary Metal-Oxide-Semiconductor (CMOS) allows analog and digital circuits
to be fabricated on a single die, and offers extremely low power consumption when used
1
for digital circuits. At high temperature, however, Metal-Oxide-Semiconductor Field
Effect Transistors (MOSFETs) in conventional bulk CMOS have many drawbacks,
including increased junction leakage, unstable threshold voltages, and reduced mobility
[1], [2]. Among these drawbacks, excess leakage current at high temperature is the most
serious problem, and can reduce circuit performance due to loss of bias current or cause
the loss of charge stored at dynamic node, or more seriously, destroy the chip due to
latch-up [2]. Despite these high-temperature issues, an instrumentation amplifier in bulk
CMOS has been demonstrated at temperatures as high as 300 °C [5], and a switchedcapacitor (SC) 14-bit sigma-delta modulator has been shown to be functional at 255 °C
[6].
Silicon on insulator (SOI) technology significantly reduces the leakage current by
eliminating the reverse-biased diodes between source/drain region and substrate/well, and
it has most of the good properties of conventional bulk CMOS technology, so it is easy to
migrate designs from bulk CMOS to SOI CMOS. The downside of SOI is that it is much
more expensive than bulk CMOS. SOI CMOS analog circuits, discussed in [4], [7], [8],
have shown that the elimination of junction leakage can enable the operation of a variety
of analog circuits at temperatures near 300 °C or above.
Recent work has been performed in developing integrated circuit technologies in
wide band-gap semiconductors such as gallium arsenide (GaAs), gallium phosphide
(GaP), gallium nitride (GaN), silicon carbide (SiC), and diamond [9], which are
fundamentally better suited to high temperatures than silicon. The major drawback of all
of these approaches is that materials and processing are in their infancy and much more
expensive than Si.
2
In addition to the device material, the MOS structure is more suitable for high
temperature operation than JFET or BJT structures because an insulated gate is used. In a
JFET the gate is formed by a junction, and in a BJT the base is also formed by a junction.
Each of these junctions is in effect a diode. At high temperature, these diodes are leaky
and degrade biasing and small-signal resistance.
The goal of this work is to explore high temperature integrated circuit (IC) design
techniques to develop a piezoresistive sensor interface in inexpensive bulk CMOS
functioning at as high as 250 °C, for use in sensor signal conditioning using Wheatstone
bridge sensors. The IC should be as much self-contained as possible to save off-chip
components and package cost.
1.2 Background
1.2.1 High temperature behavior of MOSFET
1.2.1.1 Energy bandgap, intrinsic carrier density and carrier concentration
The energy bandgap of silicon Eg decreases weakly with increasing temperature
according to [10]
Eg (T ) = 1.17 −
4.73 ×10−4 T 2
.
(T + 636 )
(1.1)
(Note: default units of temperature T are K unless specified.) A reduced bandgap leads
to larger intrinsic carrier densities and larger leakage current in p-n junctions.
The temperature dependence of the intrinsic carrier density ni of a semiconductor
is given by [11]
3
ni (T ) = N C NV e
− Eg 2 kT
,
(1.2)
where N C and NV are the effective density-of-states for electrons and holes,
respectively. Most semiconductor devices are based on the creation of charge carriers in
excess of the thermal equilibrium values ni by impurities, i.e. “doping.” The majority
carrier density inside a doped semiconductor material is determined by the ionized
doping concentration, providing 1) impurities are ionized, and 2) ND, NA >> ni. As an
example, Figure 1.1 shows the temperature dependence of electron concentration ne in a
doped n-type Si. At very low temperature, donor electrons are bounded to donor atoms
and negligible intrinsic electron-hole pairs exist. In the ionization range (< 75 K), some
impurities are ionized and ne is determined by the ionization fraction. In the extrinsic
rage (~100 – 400 K), ne remains constant and approximately equals to the doped
concentration. In the intrinsic range (>400 K), the intrinsic carrier density is larger than
the background doping and devices fail.
Figure 1.1: Electron density in silicon as a function of reciprocal temperature, for a
donor impurity concentration of 1015 cm-3 (after [11]).
4
1.2.1.2 Carrier mobility
Carrier mobility in silicon is affected by two basic scattering mechanisms: lattice
scattering and impurity scattering. In lattice scattering, a carrier traveling through the
crystal is scattered by the vibration of the lattice. As temperature increases, the mobility
from the lattice scattering decreases with a temperature dependence of T-3/2 [10]. On the
other hand, impurity scattering is scattering from crystal defects such as ionized
impurities, and it has temperature dependence of T3/2 [10]. Impurity scattering becomes
less significant at higher temperature because the carriers are moving faster and exposed
to impurities for a shorter time.
Measured
μn(T) = 623.3∗ (Τ/300)
500
−1.76
2
-1 -1
Measured mobility (cm V s )
600
400
300
200
300
350
400
450
500
550
Temperature (K)
Figure 1.2: Measured channel mobility of electrons vs. temperature for a 50 µm x 50
µm NMOS in bulk CMOS (after [12]).
The carrier mobility at 250 °C is less than ½ the mobility at 25 °C [13]. A plot of
measured mobility versus temperature is shown in Figure 1.2, where the flattening curve
5
at the last two points may be due to measurement error. The measured results were fitted
using a simplified model [2]
⎛T ⎞
μ (T ) = μ (T0 ) ⎜ ⎟
⎝ T0 ⎠
−m
.
(1.3)
1.2.1.3 Threshold voltage
According to [10], then threshold voltage VT of a long-channel MOSFET without
substrate bias can be expressed as
VT = φms −
QSS
± 2φF ± γ n , p 2φF ,
Cox
(1.4)
where + is for NMOS, - is for PMOS. Here, QSS is the surface-state charge density, Cox is
the gate capacitance, γn,p is body-effect constant, φF is the Fermi potential of the bulk that
is φF =
kT ⎛ N B ⎞
ln ⎜
⎟ where NB is the bulk doping level, and φms is the contact potential
q ⎝ ni ⎠
difference between gate and substrate. The gate doping is usually n-type. For a
conventional n-well process, φms = −
kT ⎛ N B N g ⎞
kT ⎛ N g ⎞
ln ⎜
ln ⎜
⎟ for NMOS and φms = −
⎟
2
q ⎝ ni ⎠
q ⎝ NB ⎠
for PMOS, where Ng is the gate doping level.
The temperature dependences of φms and φF are given by [14]
E 3kT ⎞
∂φms 1 ⎛
= ⎜ φms + g +
⎟ , (NMOS)
T⎝
q
q ⎠
∂T
∂φms φms
, (PMOS)
=
∂T
T
E 3kT ⎞
∂ ( 2φF ) 1 ⎛
= ⎜ 2φF − g −
⎟.
T⎝
q
q ⎠
∂T
(1.5)
(1.6)
(1.7)
Thus, the temperature dependence of the threshold voltage of NMOS is given by [15]
6
γ ∂φF
∂VT φms 2φF
=
+
+ n
.
T
T
∂T
2φF ∂T
(1.8)
For a typical CMOS process, at 300 K, the first term in (1.8) is -3.10 mV/°C, the second
is 2.70 mV/°C and the last term is approximately -0.4 mV/°C [15].
For a PMOS device, the temperature dependence of its threshold voltage becomes
γ ∂φF 1 ⎛ Eg 3kT ⎞
∂VT φms 2φF
=
−
− p
+ ⎜
+
⎟.
∂T
T
T
q ⎠
2φF ∂T T ⎝ q
(1.9)
Compared to (1.8), the magnitude of first term decreases to be about -0.5 mV/°C [14], the
signs of second and third terms become negative and one more term is added with a value
of about 4.3 mV/°C at 300 K. Therefore, as temperature increases, the threshold voltage
of NMOS becomes more negative and that of PMOS becomes more positive, in addition,
the change of PMOS threshold voltage is faster than NMOS. Experimental result shows
a half-volt change of threshold voltage from 25 °C to 250 °C for a typical CMOS process
for both NMOS and PMOS [13].
1.2.1.4 Leakage current
There are two basic types of leakage current in a MOSFET: subthreshold channel
current and junction leakage current. In the subthreshold region, the gate-to-source
voltage VGS is below the threshold, but the channel of the transistor is “weakly” inverted.
The drain current is mainly due to carrier diffusion through the channel, and it has a
strong temperature dependence because of changes in mobility, threshold voltage, and the
parameter n0, which acts as ideality factor. Subthreshold current may be written as [16]
2
⎡ q[VGS −Vth (T )] ⎤
⎥
n0 (T ) kT ⎦
2
⎛ W ⎞ Cox ⎡ n0 (T )kT ⎤ ⎢⎣
I D (T ) ≈ μ (T ) ⎜ ⎟
⎢
⎥ e
q
⎝ L ⎠ Cox + Cd ⎣
⎦
where Cd is the depletion capacitance per area of space-charge region.
7
(1.10)
In bulk CMOS technology, reverse biased diodes, as shown in Figure 1.3, are
used to isolate devices, and the leakage current from these diodes are typically the
limiting factor for high temperature operations.
Gate
Source
Drain
iLEAK
iLEAK
Bulk
Figure 1.3: Parasitic diodes at drain and source junctions of a NMOS transistor.
At room temperature, the leakage current is very small, usually on the order of
pA. As temperature rises, two effects cause the increase of the junction leakage current
[10]. First, a drift current will flow due to thermally generated electron-hole pairs in the
depletion region. Generated carriers will be swept across the junction by the electric
field. This effect, proportional to the intrinsic carrier concentration, usually dominates to
temperatures up to 100–150 °C.
At higher temperature, the junction leakage is dominated by diffusion of
thermally generated minority carriers away from the junction area, which is proportional
to the square of the intrinsic carrier concentration. When these carriers reach the edge of
the depletion region, they are swept across the junction by the electric field. The
concentration of minority carriers is a strong function of the temperature but is inversely
proportional to the doping concentration. Therefore, PMOS transistors have much less
leakage current than NMOS in an N-well process, as shown in Figure 1.4.
8
Figure 1.4: Measured leakage currents of drain junctions of an NMOS and a PMOS
transistor, respectively. The p-type epitaxial layer has a doping concentration NA =
1015 cm-3 and the n-well doping concentration is ND = 4 x 1016 cm-3. The area of both
junctions is 2 x 20 mm2 and they are reverse biased with 2 V (from [5]).
The total leakage current of a reverse biased diode is given by [10]
⎡ n
I L = I L ,diff + I L , gen = qAni ⎢ i
⎣ ND
DP
τ
+
W ⎤ qVA / kT
VA ⎥ ( e
− 1) ,
2τ ⎦
(1.11)
where A is the area of the p-n junction, VA is the voltage applied to the diode, ND is the ntype doping density, W is the width of the junction depletion region at applied voltage VA,
DP is the minority carrier diffusion constant, and τ is the minority carrier lifetime. For
negative VA (reverse bias) greater than a few tenths of a volt at temperatures below 1000
°C, the exponential terms are insignificant compared to –1, so that (1.11) simplifies to
⎡ n
I L ≅ − qAni ⎢ i
⎣ ND
DP
τ
+
W ⎤
VA ⎥ .
2τ ⎦
(1.12)
As temperature increases from 25 °C to 250 °C, the junction leakage current can rise by
~5 orders of magnitude [13]. Excess leakage current increases self-heating of the circuit,
shifts operating points in an analog circuit, lowers output resistance of high-impedance
9
nodes, erases charge stored in the memory node and can be the source of latchuptriggering current. It can also greatly increase offset among matching devices [5], [12].
Therefore, it is among the most serious challenges in silicon high temperature electronics.
1.2.2 SPICE simulation for high temperature
Accurate simulation of analog integrated circuits is essential for successful
development. However, foundries usually supply SPICE models valid up to 125 °C, and
existing SPICE models do not accurately model the MOSFET behavior above 150 °C
[12]. A SPICE preprocessor [12], [17] for high-temperature circuit simulation has been
developed to correct the inaccuracy of the simulator. This preprocessor can obtain
correct model at high temperature by substituting the major performance parameters used
by the SPICE model, specifically threshold voltage and mobility, at selected high
temperatures.
Successful designs must focus on circuit architectures which are less sensitive to
device degradation and do not rely on accurate simulator models. For this work, hand
calculations are used to determine the variation in device parameters [13], and then
derived parameters are applied back to simulation at room temperature to examine
potential problems at high temperature.
1.2.3 Existing high temperature circuit techniques
1.2.3.1 Zero temperature coefficient gate biasing
It has been shown in [2], [13], [15] that the opposing effects of threshold variation
and mobility variation with temperature allow a MOSFET to exhibit a low temperaturecoefficient drain current within certain temperature range when biased at the zero-
10
temperature coefficient (ZTC) bias point. A ZTC point may exist in both the triode
region and the saturation region of operation [13].
Shoucair [13] used an experimentally fitted SPICE model to find the gate bias
voltage at the ZTC point. Filanovsky and Allam [15] derived an analytical model of the
bias voltage at ZTC point based on semiconductor physics and foundry parameters, using
measured data shown in Figure 1.5. The ZTC point is process dependent, however, and
may not be reproduced. Also, the biasing technique has limited applicability since stable
bias current may not be the primary goal.
Figure 1.5: Measured drain current characteristics at selected temperature (from
[15]).
1.2.3.2 Leakage current cancellation
The easiest way to reduce leakage current is to lower the power supply voltage
[2], but this also reduces circuit speed, noise margins and dynamic range.
11
A more involved approach to reduce the effect of leakage current has been
suggested in [13] that for a given node, the leakages into the node from VDD must be
matched by leakages out of the node to VSS. Figure 1.6 shows a diagram of an NMOS
transistor whose source and drain have been connected to complementary diodes in order
to cancel leakage current into these nodes, as proposed by Harvey [12]. The requirement
of cancellation is that the complementary diodes have matched leakage current over
temperature. For a conventional N-well process, a PMOS drain diode has much less
leakage current than for NMOS at high temperature, as shown in Figure 1.4, so this openloop approach cannot work.
Gate
Source
Drain
VSS
i LEAK
iLEAK
VDD
Figure 1.6: Complementary diode leakage current cancellation (from [12]).
An alternative method to cancel leakage current is shown in Figure 1.7, proposed
in [18]. The basic idea is to copy the leakage current through a replica of M1, invert its
polarity with a current mirror, then inject into the drain of M1 to compensate its leakage
current. This approach is better than the complementary diode leakage current
cancellation since cancellation current is produced by the same type of device as the
source of leakage current.
12
Figure 1.7: Leakage current compensation using replica device (from [18]).
Leaky analog switches limit the performance of switched-capacitor circuit at
shigh temperature. Finvers, et al. used a doughnut shaped layout (Figure 1.8) for the
sample/hold (S/H) switches to minimize leakage current [19]. The center diffusion of the
doughnut is connected to the hold capacitor, so the area of the drain/source region
connected to the hold capacitor is minimized.
Figure 1.8: Doughnut shaped layout for analog switch (from [20]).
Wong, et al. proposed a leakage current feedback cancellation scheme for analog
switches [21], as shown in Figure 1.9. A replica S/H circuit is added with the same
13
switches as the main circuit but smaller holding capacitor Crep and M1, M4 M5, M8 are
“constant leakage generators.” When the circuit is in the hold state, the leakage current
(I1 + I2 + I3) from the switch will discharge corresponding holding capacitor. Due to the
difference between Chold and Crep, an equal leakage current generates a voltage difference
(Vhold – Vrep). This differential voltage is amplified by the amplifier A1 to drive the
leakage current source and generate a cancellation current Icancel that makes the voltage
difference zero. When the loop is stabilized, Icancel = I1 + I2 + I3, and both Vhold and Vrep
do not drift any further. Experimental results presented in [21] show this technique can
reduce the natural leakage of the CMOS switch at room-temperature operation from 0.1
pA to ~0.01 pA. Although the circuit is currently used in a very low frequency S/H
circuit for room temperature, it can also be potentially useful for canceling leakage
current at high temperature.
Figure 1.9: Leakage current cancellation feedback (from[21]).
14
1.2.3.3 Substrate bias feedback
It has been shown that temperature sensitivity of threshold voltage can be reduced
by applying a constant, non-zero substrate bias voltage [2]. Therefore, it is possible to
keep threshold voltage constant over temperature by applying a proper substrate bias
voltage. However, in a standard bulk N-well process, all NMOS transistors share the
same substrate, so individual transistors can not be stabilized using substrate biasing.
1.2.3.4 Constant-Gm biasing
Transconductance (gm) is a critical parameter in many analog circuits, affecting
bandwidth, stability and gain. Neglecting channel length modulation and the backgate
effect, the transconductance of a MOS in saturation region is given by [22]
⎛W
g m = 2 μ Cox ⎜
⎝L
⎞
⎟ ID ,
⎠
(1.13)
where W and L are the channel width and length of the transistor, respectively. Equation
(1.13) shows that gm decreases as temperature rises due to decrease in mobility.
In order to reduce the variation of transconductance with changing temperature, a
bias circuit (Figure 1.10) has been proposed to generate a bias current IB with a
temperature dependence inversely proportional to that of mobility [12], [23]. If channel
length modulation and the backgate effect are neglected,
2
⎛ L1
L2 ⎞
2
IB =
−
⎟ .
2 ⎜
W2 ⎟⎠
μnCox RB ⎜⎝ W1
The gm of a transistor biased by this current is
15
(1.14)
gm =
L2 ⎞
2 W ⎛ L1
−
⎜⎜
⎟.
RB L ⎝ W1
W2 ⎟⎠
(1.15)
If RB has a zero temperature coefficient, Gm will be stable over temperature. Of course,
there is no such low-temperature coefficient resistor available in standard CMOS.
VDD
M7
M8
M6
M5
M3
M4
M1
M2
RB
IB
VSS
Figure 1.10: Constant-Gm biasing circuit.
1.2.4 Published work in high-temperature bulk CMOS
A summary of published high-temperature amplifiers is shown in Table 1.2. Most
successful work in high-temperature bulk CMOS has been based on robust architectures
to tolerate variation in device parameters over temperature, in addition to the design
techniques discussed in the pervious session. A 200-°C precision amplifier described in
[19] uses a continuous-time auto-zero scheme to achieve low offset. A 300-°C
instrumentation amplifier uses dynamic feedback to compensate for resistor mismatch
and realize an average gain error below 25 ppm up to 250 °C, without calibration or
16
trimming [5]. However, the dynamic feedback compensation requires a large number of
resistors and switches and complex addressing, so a wide range of programmable gain is
not feasible. The amplifier was applied to a pressure transducer interface obtaining 15-16
bits accuracy at 250-275 °C [24].
[5]
[19]
[7]
[8]
Process
Reported Tmax
(°C)
HighTemperature
Techniques
Performance summary
Bulk
CMOS
300
Dynamic
feedback
The instrumentation amplifier achieves an
average gain error < 25 ppm up to 250 °C and <
500 ppm at 300 °C.
Continuoustime auto-zero
The OPAMP achieves an input-referred offset <
60 μV at 25 °C and < 200 μV at 200 °C, and a
unity-gain bandwidth (CL = 100 pF and RL = 10
kΩ) of 3.3 MHz at 25 °C and 2.2 MHz at 200
°C.
Not reported
One OPAMP achieves a DC gain of 65 dB at 25
°C and 55 dB at 300 °C, and a unity-gain
bandwidth (10 pF load) of ~2 MHz at 25 °C and
1 MHz at 300 °C; the other OPAMP achieves a
DC gain of 35 dB at 25 °C and 25 dB at 300 °C,
and a unity-gain bandwidth (10 pF load) of 100
MHz at 25 °C and ~30 MHz at 300 °C.
Not reported
The transimpedance amplifier achieves a DC
transimpedance gain of 139 dBΩ at 25 °C and
126 dBΩ at 300 °C, and a pass-band bandwidth
of 1.2 MHz at 25 °C and 400 kHz at 300 °C.
Bulk
CMOS
SOI
200
300
SOI
300
[25]
SOI
225, guaranteed
300, derated
performance
Not reported
The OPAMP achieves a DC gain of 44 dB at 25
°C and 30 dB at 225 °C, and unity-gain
bandwidth (RL = 10 kΩ, CL = 100 pF) of 1 MHz
at 25 °C and 2 MHz at 225 °C.
[26]
SOI
225
Ping-pong
amplifier with
auto-zero
The OPAMP achieves a DC gain > 114 dB and a
unity-gain bandwidth (RL = 10 kΩ, CL = 20 pF)
of 2.2 MHz from 25 °C to 225 °C.
Table 1.2: Summary of published high-temperature amplifiers.
A summary of published high-temperature ADCs in both bulk CMOS and SOI is
given in Table 1.3. A charge balancing pulse-width modulator was developed to provide
15 bits of absolute accuracy up to 175 °C [20]. More recently, a 2nd-order sigma-delta
17
converter, which has superior tolerance to imperfection of circuit components [25], was
designed to provide over 14 bits of resolution at 225 °C and over 13 bits of resolution of
255 °C [6].
OSR
Peak
SNR
@25 °C
(dB)
Peak
SNDR
@25 °C
(dB)
Peak
SNR
@Tmax
(dB)
Peak
SNDR
@Tmax
(dB)
Architecture
Process
Reported
Tmax (°C)
[6]
2nd-order
sigma-delta
Bulk
CMOS
255
256
Not
reported
88
Not
reported
80
[6]
3rd-order
(2-1 MASH)
sigma-delta
Bulk
CMOS
255
256
Not
reported
88
Not
reported
80
[28]
1st-order
sigma-delta
SOI
350
128
58
Not
reported
30
Not
reported
[29]
2nd-order
sigma-delta
SOI
350
64
58
Not
reported
30
Not
reported
[30]
2nd-order
sigma-delta
SOI
225
256
95.4
93.9
77.6
72.6
[30]
4th-order
(2-2 MASH)
sigma-delta
SOI
225
256
97.4
94.8
77.6
72.6
[59]
1st-order
sigma-delta
SOI
275
64
54
Not
reported
30
Not
reported
SOI
225,
guaranteed,
300, derated
performance
N/A
[31]
12-bit SAR
12-bit
linearity
12-bit
linearity
Table 1.3: Summary of published high-temperature ADCs.
1.3 Objectives
The primary objective of this work was to develop a flow sensor interface IC
operating at temperatures up to 250 °C using a conventional bulk CMOS process. The
following intermediate goals were established.
18
1. Develop an electronic system architecture to provide the interface between a flow
sensor operating at high temperature and a control platform at room temperature,
as per Propulsion 21 requirements described in Chapter 2.
2. Explore circuit design techniques to compensate for high-temperature effects of
MOSFETs that allow bulk CMOS IC to operate at temperature up to 250 °C.
3. Employ these techniques to design mixed-signal building block circuits including
oscillator, amplifier, comparator and integrator. (Chapter 3)
4. Develop a high-temperature instrumentation amplifier IC, as per system
requirements. (Chapter 4)
5. Develop a high-resolution (≥ 12 bit), high-temperature analog-to-digital
converter, as per system requirements. (Chapter 5)
19
2 Architecture
In the Propulsion 21 project, a high-speed MEMS valve is placed in an engine to
control fuel flow to obtain maximum engine performance, and a piezoresistive flow
sensor is used to maintain the flow [32]. The piezoresistive sensor is configured as a
Wheatstone bridge.
Specifications of the sensor are summarized in Table 2.1, where all numbers are
preliminary. Based on these sensor specifications, the requirements for IC development
have been derived and summarized in Table 2.2. Since system power is readily available,
IC power is not a primary concern, but should be limited in view that 22 such sensors are
to be deployed to operate a single engine.
Nominal resistance of each piezoresistor R0
500 Ω
Maximum offset resistance
3Ω
Minimum required resolution
2.5 mΩ
Sensor signal bandwidth
dc - 2 kHz
Resonant frequency fr
250 kHz
Table 2.1: Preliminary piezoresistive flow sensor specifications (after [33]).
Operating Conditions:
VDD= 5 ± 0.5 V, VSS = 0 V
Power supply
200 °C
Maximum operating temperature
IC specifications:
± VDD/2 = ±2.5 V
Max differential output voltage
12 bits
Dynamic range
5 V/ 212 = ~1.2 mV
Differential output resolution
25 µV
Nominal input resolution
dc - 2 kHz
Signal bandwidth
Voltage gain
AV = 48 * (¼, ½, 1, 2, 4)
Table 2.2: Requirements for IC development (after [33]).
20
2.1 System Overview
In consideration of noise and interference, the high-temperature sensor interface
IC must be placed in proximity to the piezoresistive flow sensor, while the reminder of
the signal processing and control platform may operate at room temperature, as shown in
Figure 2.1. A change of resistance in the piezoresistive flow sensor is sensed and
amplified by the interface IC. The interface IC provides stimulus to the flow sensor and
its power is obtained from the room temperature circuit board.
In addition to the resistive signal, the sensor temperature must be measured and
also sent to the control platform. The control platform provides high-voltage, feedback
control signals to drive the MEMS valves. The number of wire connections and off-chip
components at high temperature should be minimized in order to simplify packaging. In
a first generation design, the high-temperature sensor interface IC (HTIC) output will be
an analog voltage, with the ADC on the room temperature circuit board.
Hot Environment (200 °C)
Room-Temperature Environment
Drive
MEMS valves
Piezoresistive flow sensor
Stimulus
R0+ R
R0
R0
Power
Room-Temperature
Signal Processing
Circuitry
High-Temperature
Sensor Interface IC
R0+ R
Resistance
change
Signal
Gas outlet
Figure 2.1: Basic system architecture.
21
Figure 2.2 shows additional details of the proposed high-temperature sensor
module. There are three twisted-pair wire connections between circuitry at high
temperature and room temperature. All signals are connected differentially to improve
the rejection of background noise from the noisy engine environment. Temperature
measurement is incorporated into the differential output Vout through its common-mode
level. Only two high-temperature capacitors are required: Cbypass is used to filter the
power supply noise and Cint is used as an integration capacitor for the tracking,
instrumentation amplifier, which will be covered in Chapter 4. It is likely that Cint can be
implemented on the room-temperature end of the twisted pair, and possible that Cbypass
can also be removed, eliminating all high-temperature off-the-shelf components.
Cbypass
D
DD
T
SS
)
(T
R
Cint
R 0+ R
R0
sense
R0
out
stim
R0+ R
Figure 2.2: Proposed system architecture in high temperature environment.
22
2.2 Sensor Interface Architecture
2.2.1 Selection of sensor interface architecture
Figure 2.3 shows a basic measurement setup using a traditional interface to a
Wheatstone bridge. The most straightforward operation is to use DC excitation with a
baseband voltage amplifier, but the accuracy of this method will be greatly reduced if
there are DC offsets and low frequency noise (such as 1/f and power supply noise), which
are usually present in sensing systems.
Figure 2.3: Traditional approach to Wheatstone bridge interface circuit.
Low-frequency noise can be mitigated using ac excitation and synchronous
demodulation [34], which translates the signal to a higher frequency where lowfrequency noise and interference can be avoided. In this approach, shown in Figure 2.4,
sinusoidal signals Ve+ and Ve- generated in the controller board excite the Wheatstone
bridge, and the resistance change is converted to a differential voltage Vout using a
transimpedance (Rm) amplifier that provides a low-impedance interface to the sensor.
23
The output from Rm amplifier goes through a synchronous demodulator and low-pass
filter (LPF) referenced by the excitation signals. The differential output is
Vout ≅ 2
Rm ΔR
⋅
Ve , where Ve is the amplitude of the excitation.
R0 R0
Piezoresistive
Flow Sensor
Ve+
Controller board (Room Temperature)
Ve+
Ve-
Rm
R0
R0+ R
R0+ R
R0
OSC
-
+
+
-
+
Vout
-
Synchronous
Demodulator
LPF
ADC
To
Controller
Transimpedance Amplifier
Rm
Ve-
Figure 2.4: bridge interface using ac transimpedance amplifier and synchronous
demodulation.
Even though the Rm amplifier can provide a low-impedance interconnection that
can help manage parasitic-dependent signal delay and attenuation, these long wires are
subject to interference that corrupts the signal. Also, the amplifier gain would have a
temperature dependence that is significantly different from the piezoresistor, since Vout
has a temperature dependence related to the ratio of R0 and Rm.
To improve temperature stability, a capacitor-based ac voltage amplifier is
proposed, as shown in Figure 2.5. The output is Vout ≅
ΔR CS
⋅
⋅ VS , where ΔR and R0, as
R0 CF
well as CS and CF, are made of the same materials so that their temperature dependences
are cancelled. A high-impedance interconnection to the sensor is enabled by proximity,
but the sensor IC must operate in the same high-temperature environment as the sensor.
24
Piezoresistive
Flow Sensor
Controller board (Room Temperature)
Ve+
Ve+
High-Temperature Sensor Interface IC
R0
R0+ R
OSC
CF
CS
-
+
+
-
R0+ R
CS
R0
Ve-
+
Vout
-
Synchronous
Demodulator
LPF
ADC
To
Controller
Voltage Amplifier
CF
Ve-
Figure 2.5: Bridge interface using high-temperature ac voltage amplifier and
synchronous demodulation.
Figure 2.6 shows a revision of the capacitor-based amplifier approach in which
both synchronous demodulator and oscillator are located with the high-temperature IC to
eliminate one pair of wires Ve at the expense of complexity in the high-temperature IC.
The IC output is a baseband signal that would be prone to interference, but its signal level
is greatly amplified and driven from a low impedance.
Piezoresistive
Flow Sensor
High-Temperature Sensor Interface IC
Controller board (Room
Temperature)
R0
R0 + R
CF
CS
-
R0+ R
+
R0
CS
+
Synchronous
Demodulator
-
LPF
+
Vout
-
ADC
To
Controller
Voltage Amplifier
CF
Ve-
OSC
Ve+
Figure 2.6: Bridge interface using high-temperature IC with baseband output and
internal oscillator/demodulator.
The approaches discussed above use sinusoidal excitation and continuous-time
signal processing. It is difficult to generate a high quality sinusoidal signal in
conventional CMOS, and continuous-time signal processing is limited by linearity of the
components. A square wave is much easier to generate and linearity is easier to preserve
25
in a discrete-time (switched-capacitor) circuit. The discrete-time format accommodates
correlated double-sampling (CDS) [35], as illustrated in Figure 2.7. Similar to ac
excitation with synchronous demodulation, a correlated double-sampling circuit can
significantly reduce low-frequency noise and interference.
Figure 2.7: Bridge interface using high-temperature, correlated double-sampling
amplifier with internal oscillator/demodulator.
Figure 2.8 shows a further revised approach in which the CDS demodulator and
LPF are replaced by a tracking loop, also known as delta modulator, which demodulates
and low-pass filters the signal, and provides a continuous-time differential analog output.
This approach was selected and implemented in the first version of the test chip.
Piezoresistive
Flow Sensor
High-Temperature Sensor Interface IC
Delta Modulator
Correlated Double-Sampling Amplifier
R0
CF
CS
R0+ R
R0+ R
R0
-
+
+
-
CS
VDD
Cint
C1
VDD
Ve-
C2
C1
Controller board (Room
Temperature)
VSS
CF
+
Vout
-
ADC
To
Controller
Optional
Digital Output
C2
OSC
Ve+
VSS
Figure 2.8: Bridge interface using correlated double-sampling amplifier with delta
modulator.
26
The power supply voltage was chosen for the voltage reference for both the delta
modulator and the excitation signals so that the differential output voltage and the
quantization noise of the delta modulator are both proportional to the supply voltage.
Consequently, dynamic range is constant over temperature power supply voltage, even
though amplitude is proportional to supply. If this supply voltage is used as the reference
of the ADC, the digital output will be insensitive to power supply.
The analog output from the delta modulator is a baseband voltage signal, and
prone to interference. A digital output is more favorable for transmission from a noisy
environment. The delta modulator provides an optional digital output that is proportional
to the derivative of the signal, but an integrator with matched initial condition is required
to recover the signal, which makes the delta modulator unfavorable as an analog-todigital converter. Ultimately, a sigma-delta modulator can replace the delta modulator to
interface with the CDS pre-amplifier.
2.2.2 Stimulus to the Wheatstone bridge: AC vs. DC
Instead of chopping the bridge excitation, an alternative approach is to power the
bridge using the supply voltage and chop the bridge output using a cross-bar switch, as
illustrated in Figure 2.9. Compared to the approach of chopping the bridge (approach I),
this approach (approach II) has the following advantages and disadvantages:
1. A cross-bar switch can be implemented inside the HTIC and clocked by the
internal clock, so two interconnections (Ve+ and Ve-) between the sensor and the
IC are eliminated.
27
2. In order to effectively pass a wide range of voltage, the cross-bar switch must be
implemented using complementary transmission gate, so eight transistors are
needed. For approach I, only four transistors are required since the excitation
signals Ve+ and Ve- will only be connected to VDD or VSS. However, these four
transistors must be much wider than those in approach II since they carry the
bridge current.
3. For the consideration of noise, these two approaches are equivalent.
4. Approach I uses AC stimulus and approach II uses DC stimulus. Thus, the
second approach can only be used with resistive sensors, while the first approach
can also be used with capacitive sensors by simply shorting the input capacitors
CS. Also, some sensors do not favor DC excitation which causes drift in their
value.
In the second version of the prototype of this IC, both approaches were implemented,
while in the first version, only approach I was employed.
DD
e
0
S
0
0
0
S
SS
Figure 2.9: Alternative implementation of CDS bridge interface with DC biasing of
the bridge and chopping of bridge outputs.
28
2.2.3 Offset
The resistance change ΔR of the piezoresistive sensor is a unipolar signal, which
sacrifices half the dynamic rage of the interface IC which accepts bipolar, differential
inputs. A simple solution to recover this dynamic range is to add an offset equal to
negative full scale, which could be done using a second set of input capacitors of size
CS
(gA is the gain of the CDS pre-amplifier) that are driven by chopper switches
4g A
connected to the power supply (reference) and clocked using the complement of the input
phase to match the bottom of the input range. This operation does require, however, that
the current is very linear for inputs near negative full scale.
The reduction of the random offset due to the fabrication requires calibration by
setting the flow to zero, measuring the offset in situ, and storing it in an array of binaryweighted capacitors. The LSB capacitor should be equal to half the desired resolution.
The MSB capacitor would need to be as large as the largest random offset, 3 ohms for
example. The capacitors would be driven by chopper switches connected to a voltage
that equal to negative half the maximum output excepted from bridge and the polarity of
the chopper clocks could be set to + or - by blowing a fuse. During normal operation, the
stored offset can automatically cancel the random offset of the bridge.
2.3 Electronic System Architecture
A block diagram of the proposed electronic system architecture is shown in
Figure 2.10. To meet overall system performance objectives, a final feature has been
added to the high-temperature sensor interface IC (HTIC): sensor temperature will be
measured using resistor RT and conveyed to the controller as the common-mode level of
29
the sensor signal. On the controller board, the common-mode and differential output
from the IC are processed by low-pass filters to recover temperature (common-mode) and
flow signals (differential). The control platform receives filtered signals and then
generates control signals to high-voltage amplifiers to drive the MEMS valves in the
high-temperature environment.
Hot Enviroment
Controller board (Room Temperature)
Air flow
Actuator Driver (per channel)
High Voltage Amplifier
MEMS Valves
+
VD
Gain/
Offset
-
Piezoresistive Flow
Sensor
VT+
RT
+
VSS
5V
-
5V
Reference Voltage
Generator
Vcm
Cbypass
VDD
0V
GND
-5 V
VSS
Real-Time
Control Platform
Anti-Aliasing Filter/Signal Conditioning
(per channel)
R0
VIN+
VIN-
R0
VDD
VT-
R0+ R
data
Transducer Signal
Conditioning
HTIC
+
+
Active AAF/
Temperature signal
conditioning
temp
+
-
Active AAF/
Flow signal conditioning
flow
R0+ R
+
Vout
Ve-
-
Cint
Ve+
Signal Conditioning Board
Air flow
Figure 2.10: Proposed electronics architecture using HTIC.
30
3 High-Temperature, Mixed-Signal Circuit Modules
3.1 Circuit Topology
A prototype high-temperature IC was implemented using a switched-capacitor
(SC) topology with fully-differential configuration. Fully differential, SC circuits are
relatively invulnerable to bulk leakage current providing that the charge loss over a clock
cycle is small and differentially well matched. Precise transient behavior is unimportant
providing that the circuitry is fully settled at the end of each clock cycle.
Thus, the accuracy of SC circuits depends primarily on capacitor ratios and the
ratio of clock frequency fs to OPAMP unity-gain bandwidth f0. The fs/f0 ratio can be
stabilized, despite Gm variation with temperature, if the oscillator and OPAMP topologies
are both designed to have performance proportional to Gm [36]. Both fs and f0 can be
individually stabilized if Gm is stabilized.
3.2 Process and Device Parameters
All circuitry was designed for the AMI 1.5-µm ABN process available through
MOSIS. This process has two polysilicon layers (poly1 and poly2) and two metal layers,
and has a design feature size of λ = 0.8 µm, which is the unit dimension size used in all
schematics.
Room temperature device parameters used for hand calculations were obtained
from MOSIS parametric test results on run T42N [37]. Mobility at high temperature was
estimated according to (1.3) with m = 1.5, as suggested in [13]. Threshold voltage was
estimated using [22]
31
VT (T ) = VT (T0 ) − TC (VT ) ⋅ (T − T0 ) ,
(3.1)
where Tc(VT) is approximately ±2 mV/°C for PMOS/NMOS according to measured
results in [12]. Device parameters used in the design are listed in Table 3.1, assuming
gate capacitance has negligible temperature dependence. Unless otherwise noted, all
hand calculations in this work were based on the device parameters at 125 °C.
Device Parameters
NMOS
27 °C
125 °C
PMOS
250 °C
27 °C
125 °C
Cox (aF/µm2)
1100
1100
γ( V )
0.62
0.48
250 °C
Mobility (cm2 V-1 s-1)
649
425
282
209
137
91
k’ = µCox/2 (µA/V2)
35.7
23.4
15.5
11.5
7.5
5.0
Threshold voltage (V)
0.58
0.38
0.13
-0.95
-0.75
-0.50
Table 3.1: Key device parameters using hand calculations (after [37]).
3.3 Bias Circuit
The bias circuit (Figure 3.1) employs the technique of constant-gm bias [23]
mentioned earlier. According to (1.15), the transconductance of a transistor biased by
such a current has a temperature dependence simply proportional to 1
R1
. The most
readily available biasing resistor in a simple CMOS process is a poly1 resistor having a
temperature coefficient (TC) of about +1000 ppm/ºC [13]. Such a resistor was used for
R1 in this work. A triode transistor biased at its resistive ZTC point could be the ultimate
solution to provide an on-chip resistor with low temperature dependence.
32
Start-up circuit
Constant-Gm bias circuit
Cascode bias generator
Bias test current
Figure 3.1: Schematic of bias circuit.
Among second order effects, the backgate effect can most significantly affect the
temperature coefficient of gm. The bias circuit is based on
VGS 7 = VGS 8 + I R1 R1
(3.2)
where VGS is voltage between gate and source and IR1 is current through R1. Ignoring
channel length modulation, the saturation current through a MOSFET is given by [22]
μ Cox W
(VGS − VT )
2
.
QSS
+ 2φF + γ n 2φF + VSB = VT 0 + γ n
Cox
(
ID =
2
L
(3.3)
With backgate effect, (1.4) becomes
VT = φms −
)
2φF + VSB − 2φF ,
(3.4)
where VSB is voltage between source and bulk and VT0 is the threshold voltage for VSB = 0
V [38]. The current mirror formed by transistors M1,2 and M5,6 force the current through
M7 to be equal to the current through M8. Substituting (3.3) and (3.4) into (3.2) yields
33
2 I R1
+ VT 0 =
⎛ W7 ⎞
μnCox ⎜ ⎟
⎝ L7 ⎠
The quantity
(
2 I R1
+ VT 0 + γ n
⎛ W8 ⎞
μnCox ⎜ ⎟
⎝ L8 ⎠
) can be written
2φF + I R1 R1 − 2φF
approximated as
(
)
2φF + I R1 R1 − 2φF + I R1 R1 . (3.5)
⎛
⎞
I R
2φF ⎜⎜ 1 + R1 1 − 1⎟⎟ , which can be
2φF
⎝
⎠
⎛1 I R ⎞
I R
2φF ⎜ ⋅ R1 1 ⎟ since R1 1 is designed to be << 1. Then, (3.5) is
2φF
⎝ 2 2φF ⎠
2 I R1
μnCox
⎛ L7
L8 ⎞ γ n I R1 R1
−
+ I R1 R1 .
⎜⎜
⎟⎟ = ⋅
W
W
2
2
φ
7
8 ⎠
F
⎝
(3.6)
Solving (3.6) yields
2
I R1 =
⋅
μnCox
2
⎛ L7
L8 ⎞
−
⎟⎟ .
2 ⎜
⎜ W
W
⎛
⎞
7
8
⎝
⎠
γn
R12 ⎜1 +
⎜ 2 2φ ⎟⎟
F ⎠
⎝
1
(3.7)
Substituting (3.7) into (1.13) yields
gm ∝
1
⎛
γn ⎞
R1 ⎜1 +
⎜ 2 2φ ⎟⎟
F ⎠
⎝
,
(3.8)
where 2φF has a temperature dependence of about -2.3 mV/°C at 300 K [15]. Equation
(3.8) shows that the backgate effect tends to make the temperature coefficient of gm
negative. Its effect could be avoided by connecting source to body of the cascode
transistor, but this cannot be done in a standard bulk CMOS process.
The bias current must be sufficiently large to minimize the leakage current effect
on bias. In this work, IR1 = 9 µA at 300 K was chosen. Since M8 is twice the size of M7,
then R1 should be 11.9 kΩ according to (3.7) with φF = 0.35 V. SPICE simulation shows
that R1 needs to be 8.6 kΩ to obtain the desired current. The difference between hand
34
calculation and SPICE is due to the neglected second order effects, such as channel
length modulation. Figure 3.2 shows the simulated current through R1 vs. temperature, in
which the TC(R1) was set to 1000 ppm/°C and room temperature MOSFET models were
used. SPICE simulation above ~125 °C is not reliable, and results are not shown.
16uA
14uA
12uA
10uA
8uA
20
30
40
-I(X2.R1)
50
60
70
80
90
100
110
120
130
TEMP
Figure 3.2: Simulated IR1 vs. temperature.
3.4 Oscillator
A stable, all-silicon oscillator is essential for high-temperature applications, since
it reduces the number of off-chip components, such as crystal and capacitors, both of
which are hard to obtain for such an environment. Since good inductors are not available
in a conventional CMOS process, a ring oscillator topology is proposed for this work.
Moreover, a fully-differential configuration is selected to improve temperature
performance, though a single-ended configuration would achieve a slightly better noise
performance [39].
35
3.4.1 Architecture
The oscillator circuit, as shown in Figure 3.3, employs a three-stage differential
ring [23]. Its output is converted to a rail-to-rail single-ended signal using a differentialto-single-ended converter. This logic signal is frequency-divided by two to obtain a 50%
duty cycle clock using a D-flipflop.
+
fx_sin
-
Differential
to Singleended
Converter
Clock
Divider
fx_div2_dig
Three-Stage Differential Ring Oscillator
Figure 3.3: Block diagram of the fully-integrated oscillator for clock generation.
The transfer function of the delay cell of the ring oscillator can be approximated
using a 1st-order linear model:
vout
Av
=
vin 1 + ω
, where Av is the small-signal gain at the
ω1
passband and ω1 is the dominant pole. To satisfy the oscillation criterion, Av must be ≥ 2,
and the oscillation frequency of the ring oscillator is the frequency with 60° phase shift
per stage, i.e. f x _ sin =
3ω1
[23].
2π
3.4.2 Circuit implementation
3.4.2.1 Delay cell
Ring oscillators can be classified according to the switching behavior of the delay
cell: saturated or non-saturated. The saturated-type ring oscillator, such as the crosscoupled circuit shown in Figure 3.4a [40], allows full-switching operations in some
devices in the delay cell, so it cannot be modeled as a linear circuit. The oscillation
36
frequency is determinate by the large-signal slew rate instead of the transconductance, so
this type of oscillator was not considered for this work.
The delay cell of the non-saturated oscillators, however, can be modeled as a
linear circuit. Figure 3.4b shows a design, in which a single PMOS transistor is used as
load. The load can be operating in the saturation or triode region depending on Vbias.
An alternative design, as illustrated in Figure 3.4c, uses a symmetric PMOS load
[41]. It can be shown [39] that the symmetric load design has better noise performance
than with single PMOS load, and it is easier to achieve the necessary voltage gain. Thus,
the symmetric load design was chosen for this work.
VDD
VDD
M3
M4
M5
CL
Vout-
Vbias
Vout-
Vout+
Vin+
pbias
M4 M6
M7
M6
M6
VDD
Vbias
M1
M2
Vin-
CL
Vout-
Vout+
Vin+
M7 M5
M1
Vout+
M2
Vin-
CL
Vin+
M1
M2
Vin-
nbias
nbias
M3
VSS
VSS
VSS
(a) Cross-coupled pair loads
(Saturated type)
M3
(b) Single PMOS loads
(Non-saturated type)
(c) Symmetric PMOS loads
(Non-saturated type)
Figure 3.4: Delay cell designs for a ring oscillator.
The gain of the delay cell is determined by Av =
frequency is proportional to
g m 4,5
CL
g m1,2
g m 4,5
, and the oscillation
. The differential pair in each stage is a 1/5 scale
replica of the differential pair in the FDOA, such that the oscillator frequency fosc is
proportional to the gain-bandwidth of the FDOA, which in turn corresponds to the
settling speed of the amplifier. Therefore, the settling time of the FDOA is locked to the
37
oscillator frequency, and the oscillation frequency is stabilized by the constant-gm biasing
scheme. Therefore, accurate settling is maintained over a wide temperature range, and
sampling rate, which sets resolution and/or throughput in an ADC, or cutoff frequency in
an SC filter, is also stabilized.
Small-signal simulation results at 25 °C with CL = 1 pF shows that the delay cell
has a gain of 2.9 and a 3-dB cut-off frequency of 3.5 MHz, and transient simulation
shows that the ring oscillator has an oscillation frequency which is also 3.5 MHz, not the
theoretical value. The difference between the transient simulation and the theoretical
frequency based on small-signal simulation may result from the effect of large-signal
slew effect, which is proportional to the ratio of the tail current to load capacitance.
Since bias current increases with temperature, increasing slew rate, the
dependence of oscillation frequency on slew rate may help to cancel the negative
dependence on bias resistor, shown by (3.8).
3.4.2.2 Differential-to-single-ended converter
The differential-to-single-ended converter, shown in Figure 3.5, is a simple
comparator that amplifies the differential outputs from the ring oscillator to generate a
rail-to-rail, single-ended output. The differential stage is also a 1/5 scale replica of the
FDOA differential pair, and the common-source stage M10 and M7 is used to obtain a railto-rail output swing.
38
Figure 3.5: Schematic of the differential-to-single-ended converter.
3.5 Temperature Sensors
Since the piezoresistive sensors have a strong temperature dependence, the sensor
temperature should be measured and sent to the control board for temperature
compensation. For this reason, two types of temperature sensors have been designed: an
internal thermometer circuit for monitoring chip temperature, and an RTD sensor
interface for monitoring the temperature of the sensor die.
3.5.1 Internal thermometer circuit
The internal thermometer circuit (Figure 3.6) produces a PTAT (Proportional to
Absolute Temperature) voltage of n ⋅ kT , where n is the scale factor determined by the
q
ratios of several circuit components. In this circuit, the currents through Q8 and Q9 are
forced equal by the PMOS current mirror M1-2, M5-6, and the bias voltages at the source
39
of M7 and M8 are constrained to be equal by the feedback around M1, M2, M5 – M10.
Therefore, the current through R15 is
IR =
ln ( nBJT ) kT
,
×
R0
q
(3.9)
where nBJT is the ratio of Q9 to Q8 and R0 is the resistance of R15. After current mirroring,
the voltage Vx at the drain of M200 is
Vx = nI × nR × ln(nBJT ) ×
kT
,
q
(3.10)
where nI is the ratio of M15 to M1,2 and nR is the ratio of R16 to R15.
M=1
M=1
M=4
Vx
IR
4R0
R0
M=1
Startup
M=10
Thermometer
Level shifter
Figure 3.6: Internal thermometer circuit.
M106 – M108 are PMOS transistors all having the same size. They serve as a level
shifter that adjusts the final output voltage to be centered near VDD/2, and also scale the
output swing to match the preferred range. The final voltage is given by
40
2
kT 1
Vout = × ln(nBJT ) × nI × nR ×
+ VDD .
3
q 3
(3.11)
As suggested in Chapter 2, the temperature output Vout can be used to bias the commonmode of the differential output by choosing device ratios are nBJT = 10, nI = 4, nR = 4, the
output range of the thermometer circuit was designed to be 2.3 V to 2.7 V for temperature
from 25 °C to 250 °C, which provides adequate sensitivity with minimum reduction of
differential output swing. .
3.5.2 RTD sensor interface
3.5.2.1 Specifications and architecture
As suggested in Chapter 2, a resistor can be placed on the sensor die to measure
its temperature. It would be made using the same piezoresistor as used in the sensor
bridge and have a nominal value of 12.5 kΩ, with a temperature dependence of ~3000
ppm/°C. To measure this resistance, an RTD interface circuit must provide a stable bias
current over temperature to convert resistance to voltage with temperature dependence
determined only by the RTD.
Implementation of a temperature-stable current source typically requires a resistor
with low temperature coefficient, which is not available in a standard CMOS process.
However, with a stable clock source, a stable current source can be implemented using a
switched-capacitor topology. Figure 3.7 shows one implementation of an SC voltage-to
current source [42]. In steady state, the feedback integrator supplies a current I0 to
balance the charge C0*Vref with a charge I0*Tφ2. Thus, the output current I0 is V0*C0/Tφ2.
The duration of the clock phase cannot be well controlled over temperature, however,
41
since it depends on non-overlap delays, rise/fall times, switch thresholds, etc, which
makes this approach suspect for this work.
Figure 3.7: SC voltage-to-current source (from [42]).
An alternative implementation [43], illustrated in Figure 3.8, uses a conventional
architecture for V-to-I conversion, but replaces the passive resistor with a switchedcapacitor resistor. The resistance of the SC resistor is 1
produced by the circuit is
Vref
( f clk CR )
( f clk CR )
, and the output current
. The capacitor CR has very low temperature
coefficient and a low-TC bandgap voltage reference is also possible. If the clock
frequency and OPAMP offset voltage are stable over temperature, the output current will
be stable.
42
Ripple =
CR
Vref
CH
Figure 3.8: Implementation of SC voltage-to-current source used in this work (after
[43]).
The OPAMP in this circuit is used to force the node Vx to be the same as Vref, and
its bandwidth is designed to be much lower than the clock frequency so that it acts as a
low-pass filter for clock feedthrough. During each φ1, a charge ~CR*Vref is removed from
the node Vx, which produces a ripple of ∼
CR
Vref . If the ripple is too large, the OPAMP
CH
may not maintain its proper operating region, so the hold capacitor CH should be large
enough to limit the ripple to be less than ~200 mV.
In this work, CR is chosen to be 0.3 pF, Vref is VDD/2 = 2.5 V, and CH is 6 pF, so
the ripple is 125 mV. The on-chip oscillator is used as the clock source, which has a
nominal clock frequency of 2.2 MHz that was obtained from the test results of the first
test chip. The equivalent resistance of the SC resistor is, therefore, about 1.5 MΩ, and
the output current is 1.67 μA. This current must be further low-pass filtered and scaled to
be compatible with the desired signal level of the RTD described in section 3.5.1.
43
3.5.2.2 Circuit implementations
3.5.2.2.1 Design of the OPAMP
The OPAMP must have low offset voltage and sufficient DC gain such that the
voltage at the node Vx ≈ Vref. The combination of M1 and the SC resistor in Figure 3.8
can be considered to be an additional output stage for the OPAMP. However, the current
through M1, CR*Vref*fclk, is different from the bias current of the OPAMP provided by the
constant-gm bias circuit. This difference causes a systematic input-referred offset voltage,
which is a function of the OPAMP voltage gain. If the OPAMP is implemented using a
single-stage amplifier, the amplifier gain decreases as temperature increases and the
systematic offset becomes significant, which reduces the temperature stability of the
output current. Therefore, a two-stage OPAMP has been used and the overall feedback
loop has three-stage behavior, where the third stage consists of M1 and the SC resistor.
Internal compensation of the amplifier can be avoided if the output pole is
adequately dominant. This would require a very large CH, however, which makes this
approach impractical. Fortunately, there are well-known approaches to compensate a
three-stage amplifier, as summarized in [44]. Nested Miller compensation with zero
cancellation provides a relatively simple compensation scheme with good stability.
Design guidelines for a stable system are given in [44] and listed here:
44
Rm =
1
,
g mL
⎛g ⎞
Cm1 = 4 ⎜ m1 ⎟ CL ,
⎝ g mL ⎠
2 ⎛ gm2 ⎞
Cm 2 =
C .
g m 2 ⎜⎝ g mL ⎟⎠ L
1−
g mL
(3.12)
(3.13)
(3.14)
Figure 3.9: Nested Miller compensation with zero cancellation (from [44]).
In this work, a large bandwidth is not required, and (3.13) and (3.14) have been
modified to give additional phase margin and provide better stability over temperature, as
follows:
⎛g ⎞
Cm1 = 9 ⎜ m1 ⎟ CL ,
⎝ g mL ⎠
⎛g ⎞
Cm 2 = 3 ⎜ m 2 ⎟ C L .
⎝ g mL ⎠
(3.15)
(3.16)
A schematic of the OPAMP is illustrated in Figure 3.10. M9 acts as the transistor M1 in
Figure 3.8. Its size is 36λ/3λ and it has a relatively large transconductance of 24 μA/V at
room temperature with 1.67-μA bias current in order to reduce the size of the
compensation capacitors. The size of M1 and M2 is 12λ/9λ, gm1,2 is 7.5 μA/V, and M5 is
6λ/28λ with a transconductance of 3.88 μA/V. C1 and C2 are 18 pF and 3 pF,
respectively. M13 is the zero resistor Rm, and PMOS has been used to have the same
45
mobility dependence as M9. Hence, the condition (3.12) is maintained over temperature.
The output mirror_out can be used to obtain additional copies of the output current.
Rm
1st stage (inverting)
2nd stage (non-inverting)
SC-R
3rd stage (inverting)
Figure 3.10: Schematic of the three-stage OPAMP.
Simulation results showed that the OPAMP has a DC gain of 93 dB and 90 dB,
unity-gain bandwidth of 71 kHz and 74.5 kHz, and phase margin of 88 degree and 90
degree at 25 °C and 125 °C, respectively. The systematic offset voltage is ~0.5 mV. The
random offset of the amplifier can potentially affect the accuracy and temperature
stability of the output current. A chopper stabilization technique could be applied if
necessary.
3.5.2.2.2 RTD sensor interface
Figure 3.11 shows the schematic of the complete RTD sensor interface. A
mirrored version of the reference current I0 is produced by M15. The current has a ripple
at the clock frequency, which is filtered by two cascaded low-pass filters provided by M14
C10, and M22 C12. The cut-off frequency of each filter is set about 150 kHz. The current
through M14 and M22 are the same as I0 so their small-signal resistance is large, which
46
helps to reduce the size of C10 and C12. The sizes of M14 and M22 are 6λ/12λ and 6λ/9λ,
respectively. Capacitors C10 and C12 are 10 pF and 8 pF, respectively.
Figure 3.11: Schematic of the RTD sensor interface.
The design uses the same level shifter as the internal thermometer circuit. Since
the nominal resistance of the RTD sensor is 12.5 kΩ, the desired output current fed into
the sensor should be 72 μA to be compatible with the thermometer output. For this
purpose, M23 serves as a current amplifier to scale the reference current by 42 times. In
other words, the output current from the Rin port is
I out = 42 ×
VDD
× f clk × CR = 21× f clk × CR × VDD .
2
(3.17)
Simulation results with nominal clock frequency showed the reference current I0
has an average value of 1.75 μA and a peak-to-peak ripple of 0.85 μA, and the output
current going into the RTD sensor has an average value of 71.95 μA and a peak-to-peak
ripple of 0.13 μA.
47
4 High-Temperature, Mixed-Signal Instrumentation
Amplifier
4.1 Overview
A high-temperature, mixed-signal instrumentation amplifier was designed based
on the architecture proposed in Figure 2.8 to provide an interface to the piezoresistive
sensor, and a differential continuous-time analog output. A block diagram is illustrated
in Figure 4.1, where supporting circuitry including the oscillator, bias and temperature
sensor were implemented using the mixed-signal circuit modules discussed in the
previous chapter. An offset cancellation DAC is placed at the input of the CDS preamplifier to remove the offset at the IC inputs to prevent the amplifier from saturating, as
proposed in section 2.2.3.
Figure 4.1: Block diagram of the instrumentation amplifier.
Referring to Figure 2.8, the CDS pre-amplifier provides a selectable gain GA of 6,
12 or 24, which is set by the ratio of CS/CF (3, 6, or 12) and a CDS gain of 2, and the
48
delta modulator gives an additional gain GD (2, 4, or 8) that is set by the ratio of C1/C2.
The total gain is GA * GD.
4.2 Delta Modulator
4.2.1 Principle of operation
The operating principle of the delta modulator can be explained using Figure 4.2.
The input signal Vy is differenced with its predicted version Vy’, and the resulting error
signal ε is quantized at the sampling rate of fs to give a one-bit digital code y which
indicates the direction of rate of change of the input signal Vy, in other words, the
derivative of Vy. This binary output is applied to a local demodulator implemented using
a 1-bit DAC followed by an integrator to produce the prediction Vy’. If y is positive, Vy’
increases by a voltage step H, otherwise, Vy’ decreases by H. If the sampling rate is
sufficiently high compared to the input signal, Vy’ can track Vy to drive the error ε to be
within the range of ±H, as illustrated in Figure 4.2b.
Vy
y∝
d
dt
(V )
y
V y′
d
dt
(V ′ )
y
Figure 4.2: (a) Block diagram of a delta modulator; (b) typical tracking waveform
for a delta modulator (from [45]). (Note: in (b), y(t) is Vy, q(t) is Vy’, Q is y, and σ is
H.)
49
4.2.2 Slope overload
Since the input of the delta modulator is not filtered, the tracking signal Vy’ will
fail to track the input when Vy changes too rapidly, a condition called “slope overload”
[46]. For a sinusoidal input of frequency fB with amplitude A, the requirement slew rate
(SR) to avoid slope overload is [45]
SR = H ⋅ f s ≥ 2π ⋅ A ⋅ f B .
(4.1)
When the inequality is not met, the digital output y will generate a series of ‘+1’ or ‘-1’
bits and Vy’ will suffer large distortion. Slope overload can be considered to be a noise
source, as discussed in [47]. In this work, however, slope overload is avoided by design
and test conditions.
4.2.3 Quantization noise
In each clock cycle, the integrator output will increase by H or decrease by H,
even with constant DC input, a disturbance called quantization or granular noise [47].
The quantization noise power vn2,q can be estimated under the assumption that the noise is
uniformly distributed over ±H/2 [25]:
2
n,q
v
=∫
H
2
−H
2
H2
⎛ 1⎞ 2
.
⎜ ⎟ ε dε =
12
⎝H⎠
(4.2)
In the ideal case, the quantization noise is white, i.e. the quantization error is
uncorrelated from one each clock cycle to the next. For this case, the noise can be greatly
reduced by oversampling and low-pass filtering at the delta modulator output.
In practice, however, low-frequency noise and interference and step imbalance can
cause the positive and negative steps to differ in a slowly varying manner, such that the
average value of the prediction drifts slowly up/down, and the delta modulator is forced
50
to occasionally output consecutive +1s or -1s [49]. This drift causes the high-frequency
quantization noise to be aliased into the signal band. Consequently, the benefit of
oversampling the quantization noise has been significantly reduced, which was shown by
the experimental results reported in [48], [45] and [50]. In this work, the quantization
noise is assumed to be unaffected by oversampling when analyzing noise.
4.3 Noise Analysis and Design
The requirements of the instrumentation amplifier have been described in Chapter
2. Some important requirements are as follows: maximum signal bandwidth fB is 2 kHz,
maximum differential output swing VFS is 5 V, dynamic range ND is 12 bit, and output
resolution VLSB is 1.2 mV. Three approaches to determine the key specifications of the
circuitry have been derived and are described here.
4.3.1 Matched maximum slew rate
The maximum slew rate condition occurs when the output is a sinusoidal output
signal with amplitude A = VFS/2 and frequency fB. According to (4.1), the slew rate
required by the delta modulator to avoid slope overload is
SRmin = π ⋅ f B ⋅ VFS ≅ 31V
m sec
.
(4.3)
Using (4.1) with H = 1.2 mV yields fs ≥ 26 MHz.
The loop bandwidth f0 of the double-sampling amplifier must be greater than 4*fs
to achieve 12-bit of settling accuracy in 1/3 of the sampling clock period. Thus, f0 would
need to be about 100 MHz, which is not practical in the 1.5-µm process at 200 °C,
especially considering the closed-loop gain of 12. Therefore, this constraint is not
practical.
51
In practice, this slew rate requirement can be relaxed since the maximum sensor
signal will occur only at low frequency [33]. Therefore, the slew rate constraint is
neglected and noise constraints will be considered.
4.3.2 Matched thermal and quantization noise
It is generally efficient design practice to match the noise power of the thermal
and quantization noise, i.e. let
2
n ,th
v
=v
2
n,q
=
vn2,tot
2
.
(4.4)
The total allowable noise power is
vn2,tot =
2
VLSB
= 0.12 mV 2 .
12
(4.5)
The input pair of the double-sampling amplifier is the dominant thermal noise source due
to the high noise gain at this stage, and the thermal noise power referred to the delta
modulator output is
2
⎛
C ⎞ 8kT
× f0 ,
v = 2π × G × ⎜1 + GAmp + in ⎟ ×
CF ⎠ 3 g m
⎝
2
na
2
D
(4.6)
where gm is the transconductance of the double-sampling amplifier input pair, GD is the
gain of the delta modulator, GAmp is the ratio of CS/CF, Cin is the parasitic capacitor at the
FDOA input and f0 is the closed-loop 3-dB bandwidth of the CDS pre-amplifier.
Assuming Cin/CF = GAmp/2 for a worst case estimation, and with f0 = 4fs and oversampling
ratio of OSR =
fs
2 fB
(fB is the signal bandwidth), the thermal noise power after filtering
becomes
52
2
vn2,th =
2
vna
⎛ 3
⎞ 8kT
= 16π × GD2 × ⎜1 + GAmp ⎟ ×
× fB .
OSR
⎝ 2
⎠ 3g m
(4.7)
The worst case output-referred thermal noise occurs with GAmp = 12 and GD = 8, for
which substituting (4.7) with (4.4) into (4.5) (4.7) yields gm ≅ 574 µA/V at 125 °C.
Given an effective shunt capacitance CS,eff = 15 pF, the closed-loop bandwidth is f0 ≅ 6
MHz, which leads to a maximum sampling rate fs = 1.5 MHz, very much consistent with
requirements.
Solving (4.2) for vn2,q = 0.06mV 2 yields H ≅ 0.85 mV. Thus, the maximum slew
rate is ~1.3 V/msec, which means that the output amplitude can be no greater than 0.2 V
at the maximum signal bandwidth. This slew rate is too low.
4.3.3 Ratioed thermal and quantization noise
In order to improve the slew rate, either the step height or the sampling rate must
increase. An increased step height leads to larger quantization noise, which means that
the thermal noise must be decreased to maintain total noise power. Higher sampling rate
requires higher amplifier bandwidth, and higher gm, which also leads to lower thermal
noise.
The ratio of thermal noise to quantization noise is defined as
x=
vn2,th
vn2,q
.
(4.8)
The ratio x should be selected to obtain the highest slew rate with a reasonable value of
gm. Figure 4.3 shows a plot of calculated gm and slew rate vs. x with fixed VLSB at the
highest gain setting. When x is very small, the contribution from thermal noise to the
53
total noise is insignificant, and both the sampling rate and slew rate can be high, but a
very large gm is required.
7.0
6.0
16
SR
gm
5.0
12
4.0
3.0
8
2.0
Transconductance (mA/V)
Maximum Allowable Slew Rate (V/msec)
20
4
1.0
x = 1/3
0
0.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Ratio x
Figure 4.3: Calculated gm and slew rate vs. thermal-to-quantization noise ratio (x)
for the highest gain setting (T = 125 °C).
In this work, x = 1/3 was chosen for this work, which requires gm to be about 1
mA/V and yields a slew rate (SR) of around 3 V/msec. The step height is 1.1 mV and
sampling rate is ~2.7 MHz. Details of the analysis are given in the following section.
4.4 Detailed Circuit Design
4.4.1 Double-sampling pre-amplifier
Correlated double sampling (CDS), which was originally introduced to reduce the
noise produced in charged-coupled devices [51], is an effective method to remove lowfrequency noise and reduce offset and charge injection effects in SC circuits [35]. The
input of a typical CDS pre-amplifier samples twice per clock cycle: first in the reset
54
phase and second in the evaluation phase. Since offset and low-frequency (1/f) noise at
these two moments do not vary much, in other words, are highly correlated, subtracting
the two samples can mostly eliminate them.
Correlated double sampling acts inherently as a high-pass filter that eliminates 1/f
noise [52]. A disadvantage of CDS is that white noise energy is doubled, since it is
uncorrelated in the two samples. This must be considered when selecting the bandwidth
of the system and the input stage must be designed to meet the tighter thermal noise
requirement. Guidelines for CDS design in a SC circuit are given in [53].
Chopper stabilization (ChS) [35] is another popular technique to reduce offset and
low-frequency noise in precision analog circuits. A comparison of ChS versus CDS
given in [35] shows that for many applications, CDS excels in many aspects.
1) Compared to ChS, the dc offsets are eliminated by CDS, not just modulated to
higher frequency, which may improve the allowable signal swing.
2) CDS, inherently a sampled-data system, is more compatible with SC circuits,
which have been shown to be effective for high-temperature applications [6].
3) CDS can be also used to enhance the effective gain of the OPAMPs used in the
signal processing [35].
4.4.1.1 Specifications and architecture
Figure 4.4 shows a simplified schematic of the fully-differential double-sampling
amplifier used in this work. Its closed-loop gain is simply AV = −
CS
, and CF has been
CF
made digitally selectable so that the closed-loop gain can be -3, -6 or -12. The capacitors
are made using poly1-poly2 layers, where poly2 is connected to virtual ground to
55
minimize the effect of substrate noise and parasitic capacitance. CS was chosen to be 3.6
pF so CF = 0.3 pF is used for highest gain. All analog switches, unless otherwise noted,
were made of CMOS transistors to reduce on-resistance of the switches for wide-range
inputs. There are no dummy switches or OPAMP offset cancellation schemes since the
CDS system is inherently able to eliminate both offset and charge injection.
Figure 4.4: Simplified schematic of the double-sampling amplifier.
During the amplification phase, the feedback factor β is
β=
CF
,
CS + Cin + CF
(4.9)
where Cin is the input shunt capacitance of the FDOA. The effective shunt capacitor in
determining closed-loop bandwidth is [22]
CS ,eff =
CL
β
+ CS + Cin ,
(4.10)
where CL is the actual load capacitance. Load CL must be minimized to meet bandwidth
requirements. Output voltage buffers are used to isolate the fully-differential operational
56
amplifier (FDOA) from the following stage to reduce the loading on the FDOA and
increase its closed-loop bandwidth.
To achieve Nb bits of settling accuracy within 1/3 of clock period, the closed-loop
3-dB bandwidth of the FDOA f0 must satisfy
f0 ≥
3 ⋅ N b ⋅ ln ( 2 ) ⋅ f s
2π
.
(4.11)
In this work, f0 has been designed to be 4*fs to provide 12 bits of setting accuracy.
Since the bandwidth of the FDOA is used to bandlimit the white noise, the
thermal noise at the output of the double-sampling amplifier is given by [53]
2
n ,tha
v
2
π ⎛
C ⎞ 8kT
= 2 × 2 × × ⎜1 + GAmp + in ⎟ ×
× f0 ,
CF ⎠ 3 g m
2 ⎝
(4.12)
where GAmp is the closed-loop gain of the double-sampling amplifier and gm is the
transconductance of the input pair. The first factor of two is due to the differential pair,
the second factor of two is due to double sampling of thermal noise, and π/2 is the
spectral leakage of a first-order low-pass filter. Since the sensor signal is highly
oversampled with OSR =
fs
2 fB
, the thermal noise after low-pass filtering with the cutoff
frequency fB is
2
n ,th
v
=
vn2,tha
OSR
As per the system requirement for thermal noise,
.
(4.13)
vn2,th must be less than 23 µVrms. In
the worst case, assuming that Cin is half the size of CS, GAmp = 12 and fB = 2 kHz, solving
(4.13) at 125 °C yields gm = 1.05 mA/V.
57
4.4.1.2 Circuit implementation
As shown in Figure 4.5, the FDOA was implemented using a conventional foldedcascode transconductance amplifier that has moderate gain and excellent stability [23]. A
PMOS input pair is typically used for low flicker noise [54], but in this work, an NMOS
input pair was used to achieve large transconductance (~ 1 mA/V) at high temperature,
with reasonable device sizes.
Fully-differential operational amplifier
Voltage buffers
SC common-mode feedback
Figure 4.5: Schematic of FDOA with voltage buffers.
Since gm is held relatively constant over the temperature using the constant-gm
biasing, bias current increases at high temperature, and gate drive voltage VDSAT = VGS –
VT increases. To obtain a minimum practical value of VDSAT at low temperature, the VDSAT
of the input pair was designed to be 0.3 V at 125 °C. To achieve the desired gm, (W/L)1,2
was designed to be 70, and L = 4λ was used to give relatively high output resistance.
The resulting bias current of each input transistor is 180 µA at 125 °C. M9,10 and M3,4 are
biased by 270 µA and 450 µA, respectively, to prevent saturation of the output stage.
58
The relatively large bias current helps to reduce the effect of leakage current at high
temperature. The cascode transistors M7,8 and M5,6 were designed to have a relatively
large VDSAT to reduce the transistor size, and loading of the output nodes. Thus, DC gain
and output swing are sacrificed for speed.
Output voltage buffers are implemented using the common-drain configuration,
which upwardly shifts the signal level. To prevent the buffer output from saturating at
VDD during maximum swing, the driver device M26,27 and the current source M29,30 were
designed to have a VDSAT of just 0.1 V and 0.15 V at 25 °C, respectively. The bandwidth
of the voltage buffer was designed to be 32 MHz for a 4-pF load of CI1 and CI2, which is
faster than the folded-cascode amplifier.
A switched-capacitor common-mode feedback circuit (SC-CMFB), shown in
Figure 4.6 [55], was used to set the common-mode of the differential output to be equal
to Vcm, half of the power supply. Vcmfb is the output bias control of the common-mode
feedback circuit and Vpbias is the nominal bias voltage required at Vcmfb. During φ1
(amplification phase), the capacitors CS1 and CS2 sample the difference between Vcm and
Vpbias; during φ2 (reset phase), CS1 and C1, as well as CS2 and C2, are connected in parallel
and charge is quickly redistributed between C1 and C2 to establish the required
differential voltage. In steady state, the common-mode level between Vcmfb and Vo will be
equal to Vcm – Vpbias, which are both DC voltages [38]. Since Vpbias ≅ Vcmfb, Vo,CM ≅ VCM.
Any difference is related to device mismatch and will be less than 10 mV.
59
Figure 4.6: Switched-capacitor common-mode feedback.
At high temperature, the common-mode output voltage tends to drift towards
ground (Avss) due to the greater leakage current of NMOS compared to PMOS
transistors, as described in section 1.2.1.4. The common-mode feedback circuit will
lower Vcmfb to allow the PMOS current source to supply more bias current to compensate
for the increased leakage current of the NMOS transistors, such that the output commonmode is still held at the desired value. If Vcmfb was instead connected to control the
NMOS current source, the common-mode feedback would cause the NMOS current
source to supply no bias current and the circuit would fail. This may be one reason that
the FDOA in [6] failed at 255 °C.
Although the leakage effect can be significantly reduced through the use of
common-mode PMOS feedback and fully-differential configuration, the small-signal
output resistance of MOS devices decreases significantly at high temperature due to the
reverse-biased drain diode, which reduces output impedance and the DC gain of the
FDOA.
Simulation results show that this FDOA in open-loop configuration has a DC gain
of 56 dB and a unity-gain frequency of 9.4 MHz for a 15-pF effective shunt capacitor at
125 °C, where 15 pF was obtained using (4.10) at worst case. The relatively low DC
gain is due to low output impedance caused by large bias current. Low DC gain causes
60
some closed-loop gain error, which is less than capacitor mismatch and can be calibrated
in situ. If necessary, the DC gain could be increased “gain-boosting” [56] or by
cascading more amplifier stages [5].
4.4.2 Switched-capacitor comparator
The precision of the comparator is critical in most data acquisition systems. The
comparator gain must be large enough to make correct comparisons for input voltages as
small as ½ of the least significant bit (LSB). The comparator must be able to quickly
recover from evaluation of a large input. Input-referred offset should be less than ½ LSB
to guarantee monotonicity in multi-stage ADCs. Most of these requirements are relaxed
in the delta-modulator since comparator error is oversampled, but offset voltage directly
affects the modulator offset.
4.4.2.1 Architecture
Figure 4.7 shows the architecture of the offset-compensated switched-capacitor
comparator used in this work. The front-end switching network is used to subtract its
differential inputs to produce a differential voltage at the sub-comparator input equal to
Vin ,comp = Vin1
C1
C2
.
− Vin 2
C1 + C2
C1 + C2
(4.14)
Within the delta modulator, Vin2 will be adjusted to force Vin,comp to zero, i.e.,
Vin 2 = Vin1
C1
. C2 has been made digitally selectable (2x, 4x, 8x) so this comparator can
C2
weight its inputs to scale the signal range. The smallest value of C2 is 0.5 pF, while C1 is
4 pF.
61
Figure 4.7: Switched-capacitor comparator.
The sub-comparator uses three pre-amplifier stages and a regenerative amplifier,
where the former amplify the difference at the sub-comparator input to a large level so
the latter can make a rapid, correct comparison. The regenerated outputs are stored using
two D flip-flops (DFFs), clocked by the Latch phase, synchronous with the rest of the
circuit. The overall comparator has been designed to resolve a minimum differential
input of 1.25 mV, which is attenuated by 9 when C2 = 8*C1 as per equation (4.14),
yielding a signal of just 140 µV at the input of the 1st sub-comparator pre-amplifier.
Three cascaded preamplifier stages were used to provide a total gain of about
1000 using a multi-stage offset cancellation scheme [57]. The details of the timing are
shown in Figure 4.8. During the reset phase, all reset switches are closed so that each of
the pre-amplifier stages is connected as a unity-gain buffer, whose offset is stored on its
input capacitors. During the evaluation phase, the reset switches are sequentially opened,
and the offsets are subtracted from the inputs. As the reset switches are opened
62
sequentially from left to right, charge injection and other errors produced in one stage are
cancelled by the next [57].
Figure 4.8: Timing of the CDS pre-amplifier and SC comparator.
4.4.2.2 Circuit implementation
The comparator preamplifier, shown in Figure 4.9, has a DC gain of about 9.3 and
a 3-dB cut-off frequency near 20 MHz, with 0.5-pF load capacitors at 125 °C. The use of
diode-connected PMOS loads eliminates the need for common-mode feedback. The gain
of the amplifier, set by the ratio of
g m1,2
g m 3,4
, is relatively constant over temperature thanks
to the constant-gm biasing, assuming NMOS and PMOS transistors have the same
mobility dependence on temperature. The 3-dB bandwidth that is set by
g m 3,4
CL
is stable
over temperature. (W/L)1,2 and (W/L)3,4 are designed to be 40 and 5, respectively, with L
= 2λ. Transistors M11 and M12 are connected as clamp diodes to limit the voltage swing
of the differential outputs with large input level. M8 and M9 are reset switches, and only
PMOS is used since the DC bias levels of the outputs are near VDD.
63
Figure 4.9: Schematic of the comparator preamplifier.
Figure 4.10 shows the schematic of the regenerative amplifier stage, which
includes a regenerative amplifier followed by a static latch [58]. When Regen is low, the
output nodes of the regenerative stage cmp_reg+ and cmp_reg- are pulled to VDD, so the
static latch holds its value. When Regen goes high, the difference of the inputs causes the
1st stage outputs to pull down quickly, but at different rates determined by Vin+ and Vin-,
until the positive feedback of M4, M5, M14 and M18 forces complementary, binary levels.
The latch stage is forced to this new level, which is held when Regen returns to low.
64
Regenerative Amplifier
Latch
Figure 4.10: Schematic of regenerative comparator.
4.4.3 Switched-capacitor, binary integrator
In oversampled data acquisition systems, an integrator is required to perform 1-bit
digital-to-analog conversion (DAC) and integration. In the delta modulator, small, binary
steps must be taken and held continuously valid. Since the required integrator gain is
low, a large, off-chip integration capacitor is required. In prior work [48], one such
integrator ( Figure 4.11) uses a current DAC (IDAC) loaded by an off-chip integration
capacitor Cint. The IDAC was implemented using a FDOA with a large-signal input such
that it is saturated and supplies a constant current Iref to charge or discharge the
integration capacitor, depending on the polarity of the differential input. The gain of this
integrator is ∼
I ref ⋅ T
Cint
, where T is the clock period, but depends on clock rise/fall times.
65
This topology is not well suited to a high-temperature application since it is difficult to
obtain an adequately stable reference current and clock.
Vin± 2.5V
±10μA Vo+
Cint
FDOA
± 10μA Vo−
Vin+
Figure 4.11: Simplified schematic of the integrator design using 1-bit IDAC (from
[48]).
A fully-differential, closed-loop switched-capacitor integrator, shown in Figure
4.12, can be used to eliminate the need for precise current reference and clock. The
complementary comparator outputs Din+ and Din- control the crossbar switches to
determine charge/discharge of the integration capacitors. The gain of this integrator is
Vref Cref
Cint
, where Vref = (Vref+ - Vref-) can be a bandgap voltage reference that has excellent
temperature stability, as does the capacitor ratio. This approach requires two wellmatched off-chip capacitors to obtain low integrator gain, however, since Vref must be
chosen to be much grater than voltage offsets and charge-injection errors.
Figure 4.12: Block diagram of a closed-loop switched-capacitor integrator.
66
An open-loop, fully-differential, switched-capacitor integrator that requires just
one off-chip integration capacitor is proposed in Figure 4.13. For each clock cycle,
charge is injected into the virtual ground nodes X and Y by the charge samplers, and then
transferred to the integration capacitor Cint after the transient is settled. The settling time
of the pedestal is determined by the transconductance of the NMOS cascode devices and
Cref. The magnitude of injected charge difference on X and Y is Cref (Vref + − Vref − ) , and
its polarity depends on the comparator output Din, so the gain of the integrator is
Cref (Vref + − Vref − )
Cint
. Cref is 0.5 pF and nominal value of H is 1.1 mV in this design.
Because the output nodes have high impedance, a common-mode feedback circuit is
required to maintain the output common mode level at Vcm to ensure that all transistors
are biased in their proper operating region and to maximize the output swing.
Figure 4.13: Proposed open-loop switched-capacitor integrator with only one
integration capacitor.
The decay time constant of the integrator is simply
67
τ int = Rout Cint ,
(4.15)
where Rout is the differential output impedance of the output stage, which resembles that
of a folded cascode OPAMP. In fact, the output stage of the integrator is identical to the
output stage of the FDOA used in this work, including common-mode compensation
capacitors.
There are some disadvantages of the reused circuitry: the output impedance is
only a few MΩ, and that leads to a decay time constant on the order of milliseconds with
1-nF integration capacitor. Also, the output swing was not large enough to achieve the
desired differential output range of ± 2.5 V. In a future version, the output impedance
could be improved by incorporating a gain-boosting technique, and the output swing can
be increased by better tuning the device sizes and bias levels. Degradation in
performance at high temperature is similar to the FDOA discussed previously.
4.4.4 Offset cancellation circuitry
4.4.4.1 Architecture
Random sensor offset must be corrected at the input of the instrumentation
amplifier, prior to any amplification. In addition, since the sensor input is unipolar and
the instrumentation amplifier is bipolar, an offset equal to half full scale should be
subtracted from the input. In this work, these offset adjustments have been incorporated
using a DAC that is integral with the front-end CDS pre-amplifier, as shown in Figure
4.14.
68
ran_os
ref,os
F
sys_os
ref,os
in
S
D
out
Figure 4.14: Architecture of the offset cancellation circuitry. (For simplicity, a
single-end version is shown here.)
4.4.4.2 Systematic offset
The systematic offset comes from the mismatch between the unipolar senor signal
and the bipolar IC signals. Referred to the instrumentation amplifier output, the signal
should be shifted by -VFS/2, where VFS is the full-scale differential output that is equal to
VDD. This offset is created using Csys_os, a fixed capacitor which is chosen to be 0.3 pF,
the same value as the minimum CDS pre-amplifier feedback capacitor. To obtain the
desired shift at the output, the reference changes must be
G
1 V
ΔVref ,os = × FS × A,max ,
2 2 GD GA
(4.16)
where the factor of 1/2 comes from the differential configuration. Equation (4.16) shows
that the offset reference ΔVref,os should be scaled according to the gain settings, as
presented in Table 4.1
69
Gain setting ( GD * GA )
ΔVref,os
12
VFS/2
24
VFS/4
48
VFS/8
96
VFS/16
192
VFS/32
Table 4.1: Reference levels of offset cancellation circuitry for different gain settings.
4.4.4.3 Random offset
As shown in Figure 4.14, the random offset cancellation circuitry is implemented
in a similar way as for systematic offset cancellation. As per the system requirement, the
random offset adjustment can be twice as large as the maximum signal, with both
positive and negative polarities. For simplicity, this circuit shares the same reference
voltage ΔVref,os used by the systematic offset circuitry, so the maximum value of Cran_os is
4*Csys_os. In this case, however, polarity must be adjustable.
The detailed block diagram is illustrated in Figure 4.15. The digitally controlled
capacitor Cran_os is implemented using a combination of two four-bit capacitor arrays to
save area [21]. The effective value of the right (LSB) bank of the capacitor array is
scaled by 1/16, by the coupling capacitor. The unit capacitor C0 is 0.075 pF, so
maximum capacitance is 1.2 pF. The capacitor array provides 8 bits of resolution,
sufficient for this application. The digital codes B7:B0 set the capacitance value. An
additional control bit (not shown) determines the polarity of ΔVref,os (i.e. high to low or
low to high) to permit random offset correction for either polarity. Thus, the random
70
offset cancellation provides a 13-bit dynamic range with 9-bit resolution, i.e. 8 bits plus
sign, plus 1-16 gain. The input-referred value of the random offset correction is
C
B
1
Vos = ± × 2 × Bin × 0 × ΔVref ,os ÷ CS = ± in × ΔVref ,os ,
2
16
768
(4.17)
where ± is determined by the sign bit, the factors of ½ and 2 come from double sampling
gain and the differential configuration, respectively, Bin is the 8-bit offset codes, and
ΔVref,os is the reference level given by Table 4.1. For example, with GA = 6, GD = 2, and
Bin = 128, the input-referred offset is 0.417 V.
Figure 4.15: Detailed block diagram of random offset cancellation (single-ended
version).
4.4.4.4 Reference generator
A simple R-2R array is used to generate the required reference levels listed in
Table 4.1. The reference voltage is referenced to VDD so that low-leakage PMOS
transistors may be used for all switches in the offset cancellation circuitry. The reference
output is selected by control bits G6, G12, G24, G48 and G96, which are generated by a
71
gain decoder, according to the status of the gain bits GA6, GA3, GD4 and GD2. Two
additional control bits “os_en” and “sys_os_en” (not shown in the figure) are used to
enable offset cancellation circuitry and systematic offset cancellation, respectively, to
improve testability. If these bits are set to low, the corresponding reference voltage input
for the offset DAC will be set to VDD, in other words, ΔVref,os is zero.
ref,os
SS
1
VDD
2
3
VDD
4
0
0
0
15
VDD
16
7
VDD
8
0
31
VDD
32
0
0
0
0
0
0
0
DD
Figure 4.16: Schematic of reference generator.
The resistors are implemented using the N-well, which provides high sheet
resistance, but probably higher leakage due to its low doping concentration. In the future,
a poly resistor could be used but it will take considerable more area to achieve the same
resistance. The unit resistor is 10 kΩ and resistor current is relatively large, to reduce
the effect of leakage current.
72
4.5 Test Results
4.5.1 First test chip
4.5.1.1 Overview
Prototypes were fabricated using the AMI 1.5-µm CMOS process via MOSIS.
The IC includes the instrumentation amplifier without offset cancellation circuitry,
oscillator, constant-gm bias circuit, sensor driver and a test structure for the FDOA. A die
photomicrograph is shown in Figure 4.17, in which the entire instrumentation amplifier
consisting of all labeled circuits occupies 1.6 mm2 active area, while unidentified circuits
are test structures. In high-temperature tests, the IC was housed in a ceramic DIP
package that can sustain temperatures of at least 300 °C.
Figure 4.17: Die micrograph of the 5-04 instrumentation amplifier prototype
Two lots of this design were fabricated: one was May 2004 (5-04 lot), the other
was May 2005 (5-05 lot). The second lot has no FDOA test circuit, but includes a
73
chopper switch to allow DC stimulus to drive the bridge. Both lots have been tested and
results are reported in the following sections.
4.5.1.2 High-temperature test setup
Characterization of mixed-signal ICs in a high-temperature environment is
challenging. For high-temperature tests of the first test chip, the test setup (Figure 4.18)
used in Toygur’s work [59] was used. The IC was placed on the hot plate upside down,
with a thermal couple affixed under the DIP package to record the temperature. Heatresistant teflon-coated wires were used to make connections between the IC in high
temperature and instruments and supporting circuitry in room-temperature environment.
Instruments
Connector
Tube
Hot Plate
.. . .
Thermal grease
Thermocouple
DIP
Figure 4.18: High-temperature test setup for first test chip (from [59]).
Since the temperature reading from the thermal couple under the DIP package
might not represent the real temperature of the IC, temperature calibration has been
performed using a dummy DIP package and two thermal couples: one is under the DIP
and the other one is inside the DIP cavity. A look-up table was built to calibrate the
temperature difference between the two locations to ensure accurate temperature readings
for this test setup.
The following instruments were used during these tests:
•
Corning PC-200 Hot Plate,
74
•
Omega HH-306 Thermometer,
•
Keithley 2001 Multimeter (DVM),
•
Agilent E3631A Power Supplies,
•
Agilent 33220A Function Generator,
•
Agilent 4395A Specturm/Network/Imepedance Analyzer, and
•
HP 54615B Oscilloscope.
The nominal test conditions use VDD = 5 V with oscillator sets to high-frequency
mode, unless stated otherwise. Where reported, the temperature coefficient for
temperature from T1 to T2 is defined by
TC (Y ) =
1 ΔY
,
Y1 (T2 − T1 )
(4.18)
where Y is the measured quantity, Y1 is the nominal value at T1 (generally 25 °C) and ΔY
is the variation of Y within the temperature range. For example, if the oscillator
frequency changes from 1 MHz to 1.1 MHz when temperature increases from 25 °C to
225 °C, the temperature coefficient is 500 ppm/°C.
4.5.1.3 Bias circuit
The measured constant-gm bias current is presented in Figure 4.19. Its magnitude
is 2x the unit bias current used within the IC. The bias current increases with increased
temperature, as expected from equation (1.14), but after 200°C the current begins to
saturate due to the effects of junction leakage current.
75
26
24
Ibias (uA)
22
20
18
16
14
25
50
75
100
125
150
175
200
225
250
Temperature (°C)
Figure 4.19: Measured constant-gm bias current.
According to (1.14), ln(IB) can be expressed as
ln ( I B (T ) ) = ln ( C ) − ln( μn (T )) − 2 ln( RB (T )) ,
(4.19)
2
L2 ⎞
2 ⎛ L1
where C is
−
⎜⎜
⎟ , a constant over temperature, and T is the absolute
Cox ⎝ W1
W2 ⎟⎠
temperature. The temperature dependence of µn is given in (1.3), and RB is modeled by
RB = RB 0 (1 + α R (T − T0 )) ,
(4.20)
in which the TC of a poly1 resistor αR is 500 – 1500 ppm/°C. Then, (4.19) becomes
⎛ ΔT
ln ( I B (T ) ) = ln ( C ') − nμ ln ⎜1 +
T0
⎝
⎞
⎟ − 2 ln (1 + α R ΔT ) ,
⎠
(4.21)
where C’ represents all factors with weak or no temperature dependence and ΔT = T-T0.
When ΔT is small, the second term in (4.21) can be approximated as nμ
76
ΔT
. Since αR is
T0
small, the third term can be approximated as 2α R ΔT . Therefore, (4.21) can be simplified
as
ln ( I B (T ) ) ≅ ln ( C ') − nμ
⎛n
⎞
ΔT
− 2α R ΔT = ln ( C ') − ⎜ μ + 2α R ⎟ ΔT .
T0
⎝ T0
⎠
(4.22)
A log-lin fit, as shown in Figure 4.20, has been made to the measurement data,
where T0 is 25 °C, the room temperature. The extracted slope is 0.00268, so αR is 1160
ppm/°C, assuming that nµ is -1.5. The result is in good agreement with foundry
information that estimated ~1000 ppm/°C.
ln(IB)
log-lin fit of In(IB)
-10.7
-10.8
ln(IB)
-10.9
-11.0
ln(IB)=A+B*ΔT
A=-11.1156 + 0.00735
B= 0.00268 + 8.15153E-5
-11.1
-11.2
-20
0
20
40
60
80
100
120
140
160
ΔT (K)
Figure 4.20: Log-lin fit on measured bias current over temperature (T0 = 25 °C).
4.5.1.4 Oscillator
The oscillator measurement results for 5-04 lot are shown in Figure 4.21, where f0
and f1 denote the two operating frequencies selected by the binary control bit GO. The
77
oscillator demonstrates excellent temperature stability up to 250 °C, as listed in Table
4.2.
Oscillation frequency vs. temperature (5-04 lot)
oscillation frequency (MHz)
2.5
2.0
f0
1.5
1.0
f1
0.5
0.0
25
50
75
100
125
150
175
200
225
250
Temperature (°C)
Figure 4.21: Measured oscillation frequency vs. temperature (5-04 lot).
Temperature stability (ppm/°C)
Temperature range (°C)
f0
f1
25 – 200
8
129
25 - 250
31
156
Table 4.2: Oscillator temperature stability for the 5-04 lot.
In fact, the oscillator shows much better temperature stability than predicted by
the model of gm ~ 1/RB. It is suggested that the oscillation frequency is a function of both
small-signal bandwidth and large-signal slew rate, where the former (gm/CL) has a
78
slightly negative TC and the latter (IB/CL) has a slightly positive TC. These two terms
tend to cancel such that the overall oscillator TC is very low.
The oscillator measurement results of 5-05 lot are presented in Figure 4.22. Its
temperature stability, as listed in Table 4.3, is not nearly so good as 5-04 lot. Stability is
far better than predicted by gm ∝ 1/RB (1000 ppm/°C), however.
Oscillation frequency vs. temperature (5-05 lot)
3.5
Frequency (MHz)
3
2.5
2
f0(MHz)
f1(MHz)
1.5
1
0.5
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 4.22: Measured oscillation frequency vs. temperature (5-05 lot).
Temperature stability (ppm/°C)
Temperature range (°C)
f0
f1
25 – 200
149
308
25 - 250
164
344
25- 275
265
N/A
Table 4.3: Oscillator temperature stability for the 5-05 lot.
79
The f1 setting of the oscillator stopped functioning at 275 °C and the f0 setting
failed at about 285 °C. When the oscillator is near the temperature of failure, the duty
factor of the clock output reduces rapidly and oscillation frequency increases. This
implies that the failure may be due to the dynamic D flip-flop used in the clock divider.
The dynamic D flip-flop was designed using the C2MOS configuration [60], two clocked
inverters triggered by complementary phases of the clock, as shown in Figure 4.23. Node
A and B are high-impedance nodes, where node A holds data while clk is high, and B
holds data while clk is low. As temperature increases, leakage current increases and
tends to pull the high-impedance nodes towards ground due to the leakage current
mismatch between PMOS and NMOS. Eventually, the leakage is large enough that the
charge stored in the nodes A and B is erased before the clock toggles, so the D flip-flop
stops functioning. It is not surprising that the lower frequency setting is first to fail.
Figure 4.23: Schematics of (a) dynamic D flip-flop and (b) Clocked inverter.
80
In the later versions of the IC, a pseudo-static D flip-flop, as shown in Figure
4.24, was used. In this implementation, the nodes A and B are not floating during either
clock phase. For example, the node A is driving by clkinv1 when clock is low, and
clkinv2 when the clock is high. If the leakage current is greater than the driving current,
the node will be unable to hold its value. So there is still a limited operating temperature
range.
Figure 4.24: Schematic of pseudo-static D flip-flop (the complementary clock inputs
of the clocked inverters are eliminated for clarity).
4.5.1.5 FDOA
4.5.1.5.1 Test setup
The FDOA test circuit includes two on-chip analog buffers to permit an off-chip
load. The FDOA test setup (Figure 4.25) described in Harvey’s thesis [12] was used for
this work. Only the FDOA was heated. The OPAMP (AD8618) in the feedback loop
sums Vout+ with Vfb and Vi- to provide Vin+ for feedback biasing. The open-loop DC
transfer characteristic was measured by sweeping Vfb. The AC response was measured
by connecting the network analyzer between VAC and Vout- with Vfb and Vi- grounded. Vicould be varied to measure low-frequency common-mode rejection ratio (CMRR) of this
81
amplifier, but CMRR is not essential in this application, and the measurement of
common-mode response was not performed. Tests were performed using one IC from
the 5-04 lot.
Figure 4.25: FDOA test setup (after [12]).
4.5.1.5.2 Offset
The offset of the amplifier was measured at the differential amplifier inputs with
Vfb and Vi- grounded. Only one chip was tested. The measurement results are presented
in Figure 4.26. This particular test circuit has a relatively large random offset, which
would be eliminated by correlated double sampling in the CDS pre-amplifier. The
measured offset does not change very much over temperature, but above 235 °C, the
feedback loop had stability problems due to the long wires between the DUT and roomtemperature circuit board and reduced FDOA bandwidth.
82
Offset vs. temperature
5
Offset (mV)
4
3
2
1
0
0
50
100
150
200
250
Temperature (°C)
Figure 4.26: Measured FDOA offset vs. temperature.
4.5.1.5.3 DC transfer characteristics
DC transfer characteristics were measured by varying Vfb with Vi- grounded. The
measured DC transfer characteristic over temperature for one IC is shown in Figure 4.27.
The extracted amplifier output swing is plotted in Figure 4.28. Vmin and Vmax are defined
for the differential amplifier output when
dVout − diff
dVin − diff
= 1 . Output swing (Vmax – Vmin) is
reduced at high temperatures since the bias current IB and (VGS-VT) of the transistors
increase. Not surprising, Vmax and Vmin behave symmetrically since the circuit is fully
differential.
83
DC Transfer Characteristic
4
3
Vout-diff (V)
2
1
0
-20
-15
-10
-5
0
5
10
15
20
-1
25 °C
50 °C
100 °C
150 °C
200 °C
225 °C
235 °C
-2
-3
-4
Vin-diff (mV)
Figure 4.27: Measured DC transfer characteristic of the FDOA at various
temperatures.
4
3
Vmax
Output Swing(V)
2
1
0
-1
-2
Vmin
-3
-4
0
50
100
150
200
Temperature(°C)
Figure 4.28: Extracted FDOA output swing from 25 °C to 235 °C.
84
250
4.5.1.5.4 AC test
The open-loop frequency response of the FDOA was measured using an input
amplitude of 4.4 mVrms, and results are shown in Figure 4.29. For temperatures from 25
ºC to 200 °C, the gain and GBW vary by ~2.5% and ~4.7%, respectively. Above 225 ºC,
the high-impedance nodes are shunted by the small-signal resistance from junction
leakage, which decreases rapidly with temperature. At 235 °C, the gain and GBW are
~6% and ~40% less than the room temperature values, respectively. Above 235 °C,
increasing leakage current and FDOA offset made measurement of open-loop response
very difficult, so the 250 °C curve in Figure 4.29 is suspect.
60
25, 50, 75, 100, 125, 150, 175, and 200 °C
50
open-loop gain (dB)
235 °C
225 °C
40
30
20
10 250 °C
0
1000
10000
100000
1000000
10000000
frequency (Hz)
Figure 4.29: Measured FDOA (single-ended) open-loop frequency response for
temperatures from 25 ºC to 250 ºC. Measurements at this highest temperature are
limited by instrumentation difficulties.
4.5.1.6 Instrumentation amplifier
4.5.1.6.1 Test setup and typical waveform
As illustrated in Figure 4.30a, the overall instrumentation amplifier from both lots
was tested using a single-ended-to-differential driver (AD8131) to convert the single85
ended input from a signal generator to a differential signal, which was then chopped
using a crossbar switch (MAX4365) controlled by the clock generator in the DUT.
Integration capacitor Cint is 1.5 nF, and the reference of the integrator is VDD, whose
nominal value is 5 V, so the nominal step height H is 1.67 mV. The high-frequency
clock, ~2.2 MHz and ~2.8 MHz for 5-04 lot and 5-05 lot, respectively, are used. Figure
4.30b shows a typical differential output with amplifier gain set to minimum (twelve) for
a sinusoidal input at 250 °C. The measured voltage gain is 11.5.
AMP
out+
int
out-
Hot Enviroment
in
out-d
Figure 4.30: Instrumentation amplifier test: (a) test setup, and (b) the measured
differential output of 622 mVrms for a sinusoidal input of 54 mVrms @ 35 Hz and
250 °C.
86
4.5.1.6.2 AC response
Figure 4.31 shows amplifier gain vs. temperature (5-04 lot) with different gain
settings when the differential output is ~0.447 Vrms. Measurements below 100 °C could
not be reported here due to IC damage that occurred during handling of the fragile hightemperature setup at the early stages. Instrumentation amplifiers of later lots functioned
well below 100 °C. The handling difficulty inspired the development of a better test
setup.
Instrumentation amplifier gain vs. temperature (5-04 lot)
50
Gain (dB)
40
30
20
GA=24, GD=8
GA=12, GD=8
GA=6, GD=8
GA=6, GD=4
GA=6, GD=2
10
0
75
125
175
225
275
Temperature (°C)
Figure 4.31: Measured amplifier gain vs. temperature at different gain settings, with
250 Hz input (5-04 lot). Inputs are adjusted to obtain a differential output of 0.447
Vrms in each gain setting.
For temperatures ranging from 100 °C to 250 °C, the amplifier has an average
gain variation of 205, 222, 214, 570, and 1179 ppm/°C for gain settings of 12, 24, 48, 96,
and 192, respectively. Beyond 285 °C, the amplifier fails due to oscillator failure but
87
resumes operation when cooled. The gain variation is large at the highest temperature
and large CDS gain, which could be attributed to decreasing FDOA gain.
The same test has been performed using the 5-05 lot and measured results are
plotted in Figure 4.32, which shows better temperature stability and wider operating
temperature range. For temperatures ranging from 25 °C to 250 °C, the amplifier has a
gain variation of 272, 228, 153, 554, and 1294 ppm/°C for gain settings of 12, 24, 48, 96,
and 192, respectively. For comparison to the first lot, the second lot at temperatures
ranging from 100 °C to 250 °C has a gain variation of 152, 139, 109, 594, and 1078
ppm/°C for gain settings of 12, 24, 48, 96, and 192, respectively. Again, the gain is less
stable for large CDS gain.
Instrumentation amplifier gain vs. temperature (5-05 lot)
50
Gain (db)
40
30
20
GA=24, GD=8
GA=12, GD=8
GA=6, GD=8
GA=6, GD=4
GA=6, GD=2
10
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 4.32: Measured amplifier gain vs. temperature at different gain settings, with
250 Hz input (5-05 lot). Inputs are adjusted to obtain a differential output of 0.447
Vrms in each gain setting.
88
Figure 4.33 shows the input amplitude sweep at 250 Hz for amplifier gain of
twelve with varying temperature. The differential output swing starts to decreases at 250
°C, but good overall behavior is maintained until 275 °C.
Power sweep vs. temperature (Gain =12, 5-04 lot)
25
Gain (dB)
20
100°C
150°C
200°C
225°C
250°C
265°C
275°C
15
10
5
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Vin-diff (Vpp)
Figure 4.33: Measured amplitude response at a variety of temperatures with
amplifier gain set to twelve and an input signal frequency of 250 Hz (5-04 lot).
4.5.2 Second test chip
4.5.2.1 Overview
The second version of the instrumentation amplifier was fabricated on Sept. 2005
(9-05 lot), which included all the circuits illustrated in Figure 4.1. The chip layout is
shown in Figure 4.34. The active area occupies about 3 mm2.
89
Figure 4.34: Die micrograph of second version of the instrumentation amplifier test
chip (9-05 lot).
4.5.2.2 High- temperature test setup
The test setup used in the first version of the test chip contains long wires running
between DUT at high temperature to circuit board and instruments at room temperature,
which add parasitic capacitor and interference. This test setup is very fragile, where two
pins close to each other can easily be shorted.
90
Figure 4.35: Improved version of the high-temperature test setup.
An improved version of the high-temperature test setup was assembled, as shown
in Figure 4.35. The DUT housed in the DIP40 package is placed on the top of the PCB
through one-inch-long extension pins, which separate the hot DIP from the PCB. A hightemperature flexible heating tape (Omega FGS00321-010) was wrapped around the DUT
to provide local heat. A temperature controller (Omega CN2110) provides on/off control
of the heating tape power via a solid-state relay, and senses the DUT temperature using a
thermal couple placed on the package. Heating power is provided by 110-V 60-Hz AC
source. The controller maintains the DUT temperature using Proportional-Integral
control [61]. A cooling fan is used to take extra heat away when a relatively low
temperature (≤ 100 °C) is needed. Two additional thermal couples are placed on the
91
package and PCB (below the package) to monitor their temperature while heating. It is
noted that the temperature reading for this test setup can have an uncertainty of ±10 °C
due to the difficulty of calibration.
The heating tape has sufficient power to heat the low-thermal-loss DIP to at least
300 °C. Some heat will be transferred to the PCB via the extension pins or air, but most
of it is removed by the surrounding air. When the DIP is at 300 °C, the PCB area below
it is about 105 °C and the reminder of the PCB is well below 70 °C. Thus, the supporting
circuitry and the PCB are operating within their temperature ratings. The new setup is
very reliable and provides better noise immunity by eliminating long wires involved in
the previous one.
All the instruments listed in section 4.5.1.2 were used, except the hot plate. The
nominal test condition for this chip is VDD = Vref,DM = 5 V, Cint = 1.5 nF and fclk = ~1.5
MHz (GO = 1), unless stated otherwise. Vref,DM is the reference level for the delta
modulator.
4.5.2.3 Oscillator
The measured oscillation frequency of the 9-05 lot is plotted in Figure 4.36. The
calculated temperature stability over various temperature ranges are listed in Table 4.4.
The stability is near the 5-04 lot, but not as good. More importantly, in this version, the
oscillator can function at temperatures beyond 285 °C, mainly because the dynamic D
flip-flop in clock divider was replaced by a static one. At 300 °C, the high-frequency
setting fails but the low frequency setting still functions well. This may be due to the
inability of the differential-to-single-ended converter in the oscillator to make correct
comparisons as temperature increases, because the differential output amplitude of the
92
ring oscillator reduces over temperature and the high-frequency setting has smaller
amplitude than the lower one.
Oscillation frequency vs. temperature (9-05 lot)
3.5
Frequency (MHz)
3
2.5
2
f0
f1
1.5
1
0.5
0
0
50
100
150
200
250
300
350
Temperature (°C)
Figure 4.36: Measured oscillation frequency vs. temperature (9-05 lot).
Temperature stability (ppm/°C)
Temperature range (°C)
f0
f1
25 – 200
59
238
25 - 250
63
284
25 - 275
57
267
25 - 290
97
251
25 - 300
N/A
242
Table 4.4: Oscillator temperature stability (9-05 lot).
93
A summary of oscillator temperature stability for all three lots is given in Table
4.5.
Temperature stability (ppm/°C)
Temperature
f0
range (°C)
f1
4-04 lot
4-05 lot
9-05 lot
4-04 lot
5-04 lot
9-05 lot
25 – 200
8
149
59
129
308
238
25 - 250
31
164
63
156
344
284
25 - 275
N/A
268
57
N/A
N/A
267
25 - 290
N/A
N/A
97
N/A
N/A
251
25 - 300
N/A
N/A
N/A
N/A
N/A
242
Table 4.5: Summary of oscillator temperature stability for three lots.
4.5.2.4 Internal thermometer circuit
The measured output of the internal thermometer circuit demonstrates expected
linear behavior up to 225 °C, as shown in Figure 4.37. The nonlinear results beyond 225
°C may be caused by excess leakage current in NMOS M9 and M10 in Figure 3.6. The
PMOS current mirror copies the desired current plus leakage from those two transistors,
and then feeds into R16. When temperature increases, leakage current becomes so large
that it dominates the current through R16 and distorts the linear relationship shown in
(3.11). It may be possible to extend the useful temperature range using a dummy diodeconnected NMOS transistor with four times size of M10, placed between the drain of M200
and the gate of M106 to absorb most of the leakage current from M10.
94
4
3.5
3
Vtemp (V)
2.5
2
1.5
1
0.5
0
0
50
100
150
200
250
300
350
Temperature (°C)
Figure 4.37: Measured voltage output of the internal thermometer circuit vs.
temperature.
Measured and calculated data using (3.11) over the temperature ranged from 25
°C to 225 °C are in a good agreement, as shown in Figure 4.38. The 86-mV offset is
likely due to the mismatch in threshold voltage between the level shifter transistors. The
slopes are very closely matched considering the matching required of various circuit
components.
95
Comparison between measured and calculated thermometer output
2.8
2.7
y = 2.129E-03x + 1.667
Vtemp (V)
2.6
2.5
2.4
y = 2.076E-03x + 1.581
2.3
Measured Data
Theoretical
Linear (Measured Data)
2.2
2.1
2
300
350
400
450
500
Temperature (K)
Figure 4.38: Comparison between measured and calculated output of the internal
thermometer circuit vs. temperature.
4.5.2.5 RTD interface circuit
The measured output current from the RTD interface circuit at room temperature
demonstrates excellent linearity characteristics with varied clock frequency and VDD, as
shown in Figure 4.39. These results, obtained using an external clock source, are in good
agreement with the theoretical model. The extracted value of CR, using (3.17) is 0.355
pF assuming the current multiplication ratio is exactly 42. The difference between the
extracted and designed value of 0.3 pF is near the extreme of the process variation
specified for the poly2-to-poly capacitor, and may be partly due to fringe capacitance,
which was ignored in our calculation.
96
160
y = 36.263x + 0.3871
140
120
y = 39.907x + 0.3594
Iout(uA)
100
Vdd=4.5V
Vdd=5V
Vdd=5.5V
Linear (Vdd=5V)
Linear (Vdd=4.5V)
Linear (Vdd=5.5V)
y = 32.439x + 0.6377
80
60
40
20
0
1
1.5
2
2.5
3
3.5
4
fclk(MHz)
Figure 4.39: Measured output current of the RTD interface circuit for various VDD
and swept clock frequency, at room temperature.
The measured output current vs. temperature is presented in Figure 4.40. In this
test, the internal oscillator was used as the clock source. The current shows excellent
stability over temperatures up to 225 °C, as summarized in Table 4.6. These values are
very close to the oscillator test results reported in Table 4.4, demonstrating that the
temperature stability of the current depends primarily on the clock frequency, as
predicted. The measured rms value of the output current was less than 1.5 μA over the
entire temperature range, which implies that the on-chip low-pass filter effectively
reduces the ripple of the output current.
97
160
140
120
Iout (uA)
100
GO=0,fclk=~2.9MHz
GO=1,fclk=~1.5MHz
80
60
40
20
0
0
50
100
150
200
250
300
350
Temperature (°C)
Figure 4.40: Measured output current from RTD interface vs. temperature for two
frequency settings.
Temperature stability (ppm/°C)
Temperature range (°C)
GO = 0 (fclk = f0)
GO = 1 (fclk = f1)
25 – 200
57
171
25 - 250
110
150
Table 4.6: Temperature stability of the output current of the RTD interface circuit.
Similar to the thermometer circuit, the output current of RTD interface increases
rapidly with temperature beyond 225 °C. It is possible that excessive NMOS leakage, as
discussed in the thermometer test section, can also be used to explain this phenomenon.
Referring to Figure 3.11, the leakage current from the drains of NMOS transistors M21
and M18 and the source of M21 could cause the problem. The same solution suggested in
the previous section could also be applied here.
98
4.5.2.6 Offset cancellation circuitry
4.5.2.6.1 Test setup
The effective value of the input-referred voltage provided by the on-chip, offset
cancellation DAC was measured using a feedback loop, shown in Figure 4.41, which
automatically forces an amplifier input to cancel the DAC output. The corresponding
offset can be measured between the AD8131 differential driver outputs using a DVM.
Figure 4.41: Block diagram of offset cancellation test setup.
99
The instrumentation amplifier outputs are first buffered by two OPAMPs
(AD8618). The signals are subtracted from each other and low-pass filtered by the third
OPAMP to remove the high frequency component. The third OPMAP also provides an
additional gain of ~50 to provide sufficient loop gain to force the instrumentation
amplifier output adequately near zero when its gain is set to lowest value, i.e. twelve.
A Labview® program was written to automate the offset test. For each code, the
program first sends the digital I/O setup information to the test chip through a USB-toparallel converter, then collects the measured data from the DVM via the GPIB interface,
after waiting a few hundred milliseconds to allow the loop to stabilize. A complete
sweep of 512 offset cancellation codes takes about 10 minutes to complete.
“os_en” and “sys_os_en” have been defined in section 4.4.4.4. The control bit
“cap_int” is used to enable the capacitance interface. When it is set to high, the input
capacitors are shorted and the CDS pre-amplifier becomes a charge amplifier. This
function has not yet been tested.
4.5.2.6.2 Room-temperature tests
Transfer characteristics of the offset DAC at minimum gain (GA=6 and GD=2)
are presented in Figure 4.42. The measured values are in close agreement with the
theoretical model, but the slope of the measurement results is slightly larger than theory.
This difference may be due to the mismatch of the unit capacitors used by the offset
cancellation circuitry and the CDS pre-amplifier, where the first is 0.075 pF but the
second is 0.3 pF. In a future version, a 0.075-pF unit capacitor could be used in both
circuits to eliminate this issue, but the penalty would be increased die area.
100
Transfer characteristics of offset DAC (GA=6, GD=2, Room temperature)
1
Generated offset voltage (V)
0.75
0.5
0.25
0
-300
-200
-100
0
100
200
300
fclk=1.5 MHz
fclk=2.9 MHz
Theoretical
-0.25
-0.5
-0.75
-1
Offset codes
Figure 4.42: Measured and calculated transfer characteristics of the offset DAC at
different clock frequencies (GA=6, GD=2).
It is also observed that measurements for the higher frequency setting become
non-linear when the offset voltage is large, which may be caused by an internal settling
problem. The step input from the on-chip offset cancellation circuitry happens earlier
than the external input change produced by the chopper switch. The CDS pre-amplifier
will respond to the offset DAC first, then the external input. When the offset voltage is
large, the CDS pre-amplifier may be slow to recover, and not settle to the accurate level.
To reduce this error, the lower frequency setting is used for the remainder of tests of the
offset cancellation circuitry.
Measured transfer characteristics of the offset DAC for the five different gain
levels are plotted in Figure 4.43. A linear fit was performed to each set of data. The
extracted slopes are ratioed by factors of two, as expected from (4.17). The DAC-output-
101
referred offsets are between 1 and 2 mV and maybe be due to limited loop gain and offset
from the instrumentation amplifier and the AD8618s.
1
GA=6, GD=2
y = 3.4776E-03x + 2.0178E-03
Input-referred generated offest(V)
0.8
GA=6, GD=8
y = 8.9759E-04x + 1.2144E-03
GA=24, GD=8
y = 2.2954E-04x + 1.0359E-03
0.6
0.4
0.2
0
-300
-200
-100
0
-0.2
-0.4
100
200
300
GA=12, GD=8
y = 4.5327E-04x + 1.2873E-03
-0.6
-0.8
GA=6, GD=4
y = 1.7727E-03x + 1.6590E-03
-1
code
Figure 4.43: Transfer characteristics of offset DAC at different gain settings (room
temperature).
The maximum differential non-linearity (DNL) and integral non-linearity (INL)
are 2.7*LSB and 2.2*LSB, respectively, and are mainly due to the sub-ranging structure
used in the capacitor array. This structure reduces die area, and in this application,
linearity is not essential.
The measurement results of the offset DAC with varied power supply voltage and
GA=6 and GD=2 exhibit expected behavior, as shown in Figure 4.44.
102
GA=6 GD = 2, fclk =1.5 MHz, Room Temperature
1.5
Input-referred generated offset(V)
VDD = 5 V
1
VDD = 5.5 V
0.5
VDD = 4.5 V
0
-300
-200
-100
0
100
200
300
-0.5
-1
-1.5
Offset code
Figure 4.44: Transfer characteristics of the offset DAC with varied VDD (GA=6,
GD=2).
4.5.2.6.3 High-temperature tests
Measured results of the offset DAC over temperature for GA=24, GD=8 and
GA=6, GD=2 are shown in Figure 4.45 and Figure 4.46, respectively. For both gain
settings, the offset cancellation circuit functions well up to 200 °C. Beyond that
temperature, the slope of the curves reduced, as the settling problem becomes significant.
For the low gain setting, the transfer curve at 300 °C shows the offset DAC fails to
perform, which may be due to the settling problem for large-signal inputs.
103
fclk = 1.5 MHz, GA=24 GD=8
Input-referred generated offset (V)
0.08
25, 50, 100, 150,200°C
0.06
0.04
300°C
290°C
250°C
0.02
0
-300
-200
-100
0
100
200
300
-0.02
-0.04
275°C
-0.06
-0.08
Offset code
Figure 4.45: Measured transfer characteristics of the offset DAC vs. temperature
(GA=24, GD=8).
fclk = 1.5 MHz GA=6 GD=2
1
25, 50, 100, 150, 200°C
Input-referred generated offset (V)
0.8
0.6
0.4
290°C
300°C
0.2
0
-300
-200
275°C
250°C
-100
-0.2
0
100
200
300
-0.4
-0.6
-0.8
-1
offset code
Figure 4.46: Measured transfer characteristics of the offset DAC vs. temperature
(GA=6, GD=2).
104
The reduced slope of the transfer characteristics over temperature implies that the
reference level decreases due to excess leakage current. The effect can be examined
using a simple two-stage R-2R ladder, as shown in Figure 4.47. It is easily shown that
nodes V1 and V2 are affected by leakage current, as follows:
1
1
1
V1 = VDD + I L1 R0 + I L 2 R0 , and
2
2
4
3
1
5
V2 = VDD + I L1 R0 + I L 2 R0 ,
4
4
8
(4.23)
(4.24)
where ILx is defined positive when it flows into node x. These equations illustrate that
leakage current at any node affects all other nodes, with the largest effect at the node of
injection.
Figure 4.47: Two-stage R-2R ladder. ILx is defined as the leakage current flowing
into node x.
When a given node is not selected as Vref,os, leakage from N-well resistors to
ground will dominate, pulling all nodes towards ground. When a node is selected as the
reference level Vref,os, there are many PMOS switches connected to it. In the worst case,
(B7:0 = FF for the offset DAC), there are 33 PMOS drains and 17 PMOS sources with
size of 36λ/2λ and 10 PMOS drains and 3 PMOS sources with size of 96λ/2λ connected
to the node in the design. Thus, the leakage current for VDD is dominant, even though
105
PMOS junctions have relatively low leakage. As a result, the potential of the selected
reference node is increased by leakage, reducing ΔVref,os.
This temperature dependence is worsened by a single-ended reference level in this
design. In a future revision, a differential reference could be implemented to greatly
reduce this leakage effect in the R-2R ladder.
4.5.2.7 Instrumentation amplifier
4.5.2.7.1 Amplitude sweep
The measured instrumentation amplifier gain vs. temperature for different gain
settings, and clock frequencies of ~2.9 MHz (GO = 0) and ~1.5 MHz (GO =1) are shown
in Figure 4.48 and Figure 4.49, respectively. The measurements were taken with the
differential amplifier output adjusted to 1.414 Vpp. The measurements with lower clock
frequency setting show much better gain stability than the higher setting, which could be
due to a settling problem.
GO =0, fclk = ~2.9 MHz, VDD= 5V, 250 Hz input, 1.414 Vpp differential output
45
40
35
Gain (dB)
30
25
20
15
GA=24, GD=8
GA=12, GD=8
GA=6, GD=8
GA=6, GD=4
GA=6, GD=2
10
5
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 4.48: Measured amplifier gain vs. temperature for different gain settings and
high-frequency clock setting, with 250-Hz input (9-05 lot). Inputs are adjusted to
obtain a differential output of 1.414 VPP in each gain setting.
106
(GO = 1, fclk=~1.5MHz, VDD=5V, Input =250Hz, 1.414 Vpp differential output)
50
45
40
Gain (dB)
35
30
25
20
GA=24, GD=8
GA=12, GD=8
GA=6, GD=8
GA=6, GD=4
GA=6, GD=2
15
10
5
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 4.49: Measured amplifier gain vs. temperature for different gain settings and
low-frequency clock setting, with 250-Hz input (9-05 lot). Inputs are adjusted to
obtain a differential output of 1.414 VPP in each gain setting.
Due to the improvement of the oscillator, the instrumentation amplifier has
extended its operating temperature range and also exhibits slightly better temperature
stability than the earlier version. The gain setting with the highest CDS pre-amplifier
gain still has significantly less temperature stability than others. In the following chapter,
this problem will be revisited and an improved version of the pre-amplifier is described.
Temperature stability (ppm/°C)
Temperature
GA=6
GA=6
GA=6
GA=12
GA=24
GD=2
GD=4
GD=8
GD=8
GD=8
25 – 250
111
84
71
106
215
25 – 275
126
89
76
130
251
25 – 290
150
99
96
149
317
25 - 300
160
121
128
162
347
range (°C)
Table 4.7: Instrumentation amplifier gain stability for several temperature ranges
and low-clock setting (fclk = ~1.5 MHz, 9-05 lot).
107
The use of a 250-Hz input signal causes slope overload of the delta modulator
when the differential output signal is large. Therefore, a 40-Hz input signal was to
examine the output swing of the instrumentation amplifier, defined as the differential
output peak-to-peak amplitude when the amplifier gain is 0.3 dB below its maximum at
current gain setting. The choice of 0.3 dB gives a confident margin of determining the
level of input when output starts clipping since the transfer characteristics have some
fluctuations around 0.2 dB. The measured output swing over temperature for different
gain settings is shown in Figure 4.50.
Output swing vs. temperature (GO = 1, fclk = ~1.5 MHz)
9
8
Output swing (Vpp)
7
6
5
4
3
GA=24 GD=8
GA=12 GD=8
GA=6 GD=8
GA=6 GD=4
GA=6 GD=2
2
1
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 4.50: Measured peak-to-peak output swing of the instrumentation amplifier
vs. temperature.
The output swing reduces as temperature increases, because the gate voltage (VGS
–VT) of transistors increases. For the three highest gain settings, the amplifier output
swing exceeds the 5-V objective up to 290 °C. For the two lower gain settings, the
108
output swing is much less than for higher gain settings. At these two lower gain settings,
the amplifier output saturates early, which may be due to a settling problem at the delta
modulator front end, as explained with the help of Figure 4.51. This settling problem
arises because the two competing inputs of the comparator have vastly different rise
times; the output of the CDS pre-amplifier is intentionally limited by the finite bandwidth
of the CDS pre-amplifier, while the feedback from delta modulator output is changing
almost instantaneously since it is limited only by the RC time constant of the switch and
C2. Therefore, similar to the offset cancellation circuitry, the comparator may not have
enough time to recover from the first event in order to respond to the second, and does
not give an accurate comparison. To solve this issue, the delta modulator feedback could
be band limited.
Figure 4.51: Setting issue occurring at the delta modulator inputs.
109
4.5.2.7.2 Frequency response
Figure 4.52 shows the measured frequency response of the instrumentation
amplifier at various temperatures with a fixed input peak-to-peak amplitude of 89.32 mV
and a gain setting of GA=6 and GD=2. A classic 1st-order low-pass response is observed,
but bandwidth is determined by slope overloading in the delta modulator. The slope
overload point is stable over temperature, corresponding to a 3-dB bandwidth of about
900 Hz at this amplitude, since the oscillation frequency and quantization step H are
stable over temperature.
Frequency response (GA=6,GD=2, fclk=~1.5MHz, Vin-diff =89.32mVpp, Vdd=5V)
25
20
Gain (dB)
15
10
5
25°C (f=1.5MHz)
50°C (f=1.5MHz)
100°C (f=1.5MHz)
150°C (f=1.5MHz)
200°C(f=1.5MHz)
250°C(f=1.5MHz)
275°C(f=1.5MHz)
290°C(f=1.5MHz)
300°C(f=1.5MHz)
0
-5
100
1000
10000
Frequency (Hz)
Figure 4.52: Frequency response of instrumentation amplifier at various
temperatures for GA = 6, GD = 2, Vin-diff = 89.32 mVpp.
The frequency response of the instrumentation amplifier with varied input
amplitude is shown in Figure 4.53. The slope overload point shifts to lower frequency as
the input amplitude increases.
110
Frequency response ( GA=6, GD=2, fclk =~1.5MHz, Vdd = 5V)
25
20
Gain (dB)
15
Vin-diff = 126mVpp
Vin-diff = 89.3mVpp
Vin-diff = 63.2 mVpp
Vin-diff = 44.8mVpp
Vin-diff = 31.7mVpp
10
5
0
-5
-10
100
1000
10000
Frequency (Hz)
Figure 4.53: Frequency response of the instrumentation amplifier at room
temperature with varied input amplitude (GA =6, GD = 2).
The overload condition (4.1) can be rewritten as
f BW ≥
H ⋅ f clk
,
π ⋅Vo , pp
(4.25)
where fBW is the 3-dB cut-off frequency of the instrumentation amplifier frequency
response, and Vo,pp is the peak-to-peak output amplitude. The measured 3-dB cut-off
frequency is plotted vs. output amplitude in Figure 4.54. The data is fitted to the model
f BW =
K
, where K is found to be 698 Volts*Hz, in good agreement with the
Vo , pp
theoretical prediction of 796 Volts*Hz using (4.25). The difference may be due to
process variation of CREF and the tolerance of the off-chip integration capacitor.
111
3.6
3.4
Model: y ≅ -x + 2.90079
3.2
log(fBW)
3
2.8
Fitted data: y = -1.0172x + 2.8438
2.6
Measured
Model
Linear (Measured)
2.4
2.2
2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
log(Vo, pp)
Figure 4.54: Measured 3-dB cut-off frequency vs. output amplitude.
4.5.2.7.3 Harmonic distortion
In this test, a 35-Hz, 2.5-mVpp sinusoidal signal produced by a signal generator
was applied to the AD8131 input, and the output was measured using a spectrum
analyzer. The amplifier was set in its highest gain setting (192), which gives a
differential output of ~0.5 Vpp. The 35-Hz frequency is low enough to ensure that there is
no slew-rate limit.
The measurement results for 25 °C and 300 °C are presented in Figure 4.55. The
distortion is almost indistinguishable from the noise floor. The heating tape is powered
using 110-AC and maybe the source of the 60-Hz interference in this measured result.
There are three visible tones with frequencies that are not multiple of either 60 Hz or the
signal frequency of 35 Hz, which are likely from low-frequency wandering of the delta
modulator.
112
1
0
50
100
150
200
250
300
350
400
Fundamental
Differential output (Vpp/sqrt(Hz))
0.1
Tones caused by low-frequency wandering
0.01
25 °C
300 °C
0.001
HD3
HD2
0.0001
60 Hz harmonics
0.00001
Frequency (Hz)
Figure 4.55: AC response of the instrumentation amplifier with 35-Hz, ~0.5-Vpp
output. (GA=24, GD=8, GO =1, fclk =~1.5 MHz, Cint = 1.5 nF).
The measured harmonic distortion vs. temperature for ~0.5-Vpp differential output
at 35 Hz is plotted in Figure 4.56. The major contribution of second harmonic distortion
may be the mismatch of the external components at the amplifier inputs, which have not
been trimmed. The third harmonic is less than -65 dBc (dBc is defined as dB below the
level of the fundamental) except at 25 °C. For most of the temperature range, the third
and fourth harmonic distortion is indistinguishable from the noise floor.
113
Harmonic distortion for ~0.5-Vpp output
(GA=24, GD=8, fclk=~1.5MHz, Cint=1.5nF)
-40
Harmonic distortion (dBc)
-45
HD2
HD3
HD4
-50
-55
-60
-65
-70
-75
0
50
100
150
200
250
300
350
Temperature(°C)
Figure 4.56: Harmonic distortion vs. temperature for a ~0.5-Vpp output at 35 Hz.
The measurement result for a 5-V differential output at 35 Hz is shown in Figure
4.57. Harmonic distortion, especially the third harmonic, for this large output becomes
obviously worse as temperature is increased. This behavior is expected since the
increased (VGS-VT) at high temperature reduces available circuit swing.
Harmonic distortion for ~5-Vpp output
(GA=24, GD=8, fclk=~1.5MHz, Cint=1.5nF)
0
Harmonic distortion (dBc)
-10
HD2
HD3
HD4
-20
-30
-40
-50
-60
-70
0
50
100
150
200
250
300
350
Temperature (°C)
Figure 4.57: Harmonic distortion vs. temperature for a 5-Vpp output at 35 Hz.
114
4.5.2.7.4 Noise
There were two methods used to measure amplifier noise: RMS noise was
measured using a high-resolution DVM, and noise spectral density was measured using a
spectrum analyzer. In both measurements, the AD8131 and MAX4635 were
disconnected from the DUT inputs. A 3-V battery was connected between both
differential inputs and ground to provide a clean source of zero differential input.
The measured output-referred noise spectrum at room temperature for different
gain settings is shown in Figure 4.58. Noise was measured using a 4395A spectrum
analyzer, which has a noise floor of -110 dBm/Hz at 10 Hz and -120 dBm/Hz at 110 Hz
[62]. In these measurements, a 10x probe was used, which reduces the resolution of
noise measurement to be -100 dBm/Hz at 110 Hz, i.e. 2.2 μV/sqrt(Hz).
Output referred noise specturm at room temperature (GO =1, fclk =~1.5 MHz,
Cint = 1.5nF)
Output-referred noise (V/sqrt(Hz))
5.0E-05
GA=24 GD=8
4.0E-05
GA=12 GD=8
3.0E-05
2.0E-05
1.0E-05
GA=6 GD=8;GA=6 GD=4;GA=6 GD=2
0.0E+00
0
400
800
1200
1600
2000
Frequency (Hz)
Figure 4.58: Measured output-referred noise spectral density at room temperature
with zero differential input.
115
The noise spectrum appears to be white without any obvious tones within the
application bandwidth of 2 kHz. The noise floor is scaled by the overall gain except at
the lowest gain setting, which is limited by the finite resolution of the analyzer. Thus, the
output-referred noise with zero input is mainly dominated by the thermal noise from the
CDS pre-amplifier. Correlated double sampling obviously performs as expected, since
flicker noise is not apparent at low frequency.
The thermal noise appears to be larger than expected. For the highest gain setting,
the output-referred noise caused by thermal noise from the CDS pre-amplifier was
designed to be 184 μVrms in the bandwidth of 2 kHz, i.e. 4.1 μV/sqrt(Hz). The sampling
rate was designed to be 2.7 MHz, and the low-pass filter that band-limits the thermal
noise has a bandwidth of ~18 MHz, which is too large for the current sampling rate of 1.5
MHz. In the model used for hand calculations, only the input pair is considered as a
noise source of the FDOA. Simulations indicate that the input pair contributes just half
of the total noise power of the FDOA. The combination of slower sampling clock, excess
bandwidth of the low-pass filter, and previously unaccounted FDOA noise power leads to
~six times higher noise floor, which is then very close to the measurement results. In a
future revision, the bandwidth of the low-pass filter could be reduced but it should be
large enough to allow 12-bit settling accuracy. It is difficult to reduce the thermal noise
from the FDOA because its size is already large.
The measured, output-referred noise spectrum within a 2-kHz bandwidth for
various integration capacitors is shown in Figure 4.59. The noise floors for the three
larger integration capacitors are about the same, but that for the 0.15-nF capacitor is
116
noticeably larger than the others and has obvious tones, which may be caused by large
quantization steps aliased into the baseband.
Output-referred noise specturm for different integration capacitors
(GA=24, GD=8, GO=1, fclk = 1.5 MHz)
Output referred noise (V/sqrt(Hz))
7.0E-05
6.0E-05
5.0E-05
4.0E-05
3.0E-05
2.0E-05
0.15 nF (fclk=1.5MHz)
1 nF (fclk=1.5MHz)
1.5 nF (fclk=1.5MHz)
3.3 nF (fclk=1.5 MHz)
1.0E-05
0.0E+00
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Frequency(Hz)
Figure 4.59: Output-referred noise spectral density for various integration
capacitors, at room temperature.
The Keithley 2001 DVM has a maximum sample rate of 6k samples/sec in the
burst mode. For comparison with spectrum analyzer results, the output-referred rms
noise was measured by taking the standard deviation of 6000 samples collected by the
DVM. The measurement results are shown in Figure 4.60. The slight peaking of noise at
150 °C may be due to low-frequency wandering caused by circuit imbalance occurring at
this temperature.
117
Measured output noise vs. temperature (GO=1, fclk =~1.5 MHz, Cint = 1.5 nF)
0.002
0.0018
Output noise (Vrms)
0.0016
0.0014
GA=24 GD=8
GA=12 GD=8
GA=6 GD=8
GA=6 GD=4
GA=6 GD=2
0.0012
0.001
0.0008
0.0006
0.0004
0.0002
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 4.60: Measured output-referred rms noise vs. temperature, using a DVM
with 3-kHz bandwidth and various gain settings. Three sequences of measurements
were taken.
Assuming that noise is white and DVM bandwidth is 3 kHz, the calculated rms
noise voltages within a 2 kHz BW at 25 °C, for lowest gain setting and highest gain
setting, are 113 μV and 1.34 mV, respectively, while the maximum differential output for
highest gain setting is ~8 Vpp. Thus, the instrumentation amplifier has a total dynamic
range of 88 dB. For the highest gain setting, the dynamic range is 66 dB.
118
5 High-Temperature, Sigma-Delta Modulator
5.1 Overview
This chapter describes the design of a high-resolution (≥ 12 bit), high-temperature
sigma-delta modulator developed to replace the delta modulator and provide a digital
output proportional to input voltage. An improved version of the correlated doublesampling amplifier was implemented to provide better immunity to finite FDOA gain and
improved settling in the pre-amplifier, a problem that was discovered in the
instrumentation amplifier test.
High-temperature Sigma-Delta ADC
DD
Vref+
in2+
nd
out2
in2-
Vref-
SS
DD
0
Vref+
nd
8
0
DAC
out1
0
Vref-
0
SS
e-
e+
Figure 5.1: Block diagram of the sigma-delta IC.
The block diagram of the Sigma-Delta IC is given in Figure 5.1. The CDS preamplifier has a digitally-controllable gain of 6x/12x/24x, as in the Instrumentation
119
Amplifier IC. There are two copies of the modulator, one of which is connected with the
CDS pre-amplifier to interface with the flow sensor. The other can be used for
temperature sensing or any other application. All other supporting circuitry remains the
same as the Instrumentation Amplifier IC, except the RTD sensor interface which was
removed due to space limitation.
5.2 Sigma-Delta Modulator
5.2.1 Background
In general, an N-bit ADC has Q quantization levels, where
Q = 2N .
(5.1)
If the ADC full-scale range is –VR to +VR, the quantization level spacing is
Δ=
2VR
.
2N
(5.2)
The quantization noise power of an ideal N-bit quantizer is [63]
2
σ e2 =
Δ 2 1 ⎛ 2VR ⎞
= ⎜
⎟ .
12 12 ⎝ 2 N ⎠
(5.3)
If the signal power is σx2, the signal-to-noise ratio (SNR) is
⎛σ 2 ⎞
⎛σ 2 ⎞
SNR = 10 log ⎜ x2 ⎟ = 10 log ⎜ x2 ⎟ + 4.77 + 6.02 ⋅ N (dB) .
⎝ VR ⎠
⎝ σe ⎠
(5.4)
In other words, for an extra bit resolution of the ADC, there is about 6-dB increment of
SNR. If the input is a full scale sinusoid, σ x2 =
VR2
, and
2
max SNR = 1.76 + 6.02 ⋅ N (dB ) .
(5.5)
A sigma-delta modulator [64] is a robust analog-to-digital converter. A simple
block diagram is given in Figure 5.2a, and a linearized model used to estimate the
quantization noise is given in Figure 5.2b. The comparator/DAC is modeled as a unity120
gain transfer function with additive white noise e[n], and the discrete-time integrator has
z −1
transfer function of
.
1 − z −1
+VR
Vin
Yout
∫
-VR
(a)
Discrete Time Integrator
x[n]
e[n]
z-1
DAC
(b)
Figure 5.2: (a) Block diagram of sigma-delta modulator. (b) Linearized model of
the 1st-order sigma-delta modulator (after [63]).
The modulator output is given by
Y ( z ) = X ( z ) ⋅ z −1 + E ( z ) ⋅ (1 − z −1 ) .
(5.6)
Hence, the transfer functions of signal and quantization noise are H x ( z ) = z −1 and
H e ( z ) = 1 − z −1 . The output is a delayed version of the input, and the quantization noise
is shaped by a first-order high-pass filter. The corresponding time-domain version of the
modulator is
y[n] = x[n − 1] + ( e[n] − e[n − 1]) ,
where (e[n]-e[n-1]) is the first-order difference of e[n].
121
(5.7)
Since H e ( z ) contains a zero at z=1, i.e., quantization noise has a zero response at
dc. In general, H e ( z ) has large attenuation at low frequencies and amplification of ~2 at
higher frequencies such that the total noise power is the same. If the signal bandwidth fB
is much smaller than the sampling frequency fS and a low-pass filter is used at the output,
it is possible to obtain low quantization noise, i.e. high resolution, in the signal band.
Since a 1-bit DAC is guaranteed linear (there is only one line between two
points), it is common to use a 1-bit DAC and a corresponding 1-bit quantizer, which is
simply a comparator. If fS is large enough, the in-band noise power (i.e., the noise in the
frequency range 0 to fB ) at the output of a first-order sigma-delta modulator is [63]
σ =σ ⋅
2
ey
2
e
π 2 ⎛ 2 fB ⎞
3
⎜
⎟ .
3 ⎝ fs ⎠
(5.8)
The SNR is thus
⎛ f ⎞
⎛π2 ⎞
σ x2
SNR = 10 log( 2 ) − 10 log ⎜ ⎟ + 30 log ⎜ s ⎟ (dB) .
σe
⎝ 3 ⎠
⎝ 2 fB ⎠
(5.9)
⎛ f ⎞
Defining R = log 2 ⎜ S ⎟ , the oversampling rate in octaves, (5.9) becomes
⎝ 2 fB ⎠
⎛ σ x2 ⎞
⎛ σ x2 ⎞
SNR = 10 log ⎜ 2 ⎟ − 5.17 + 9.03 ⋅ R (dB) = 10 log ⎜ 2 ⎟ − 0.40 + 9.03 ⋅ R (dB) , (5.10)
⎝ VR ⎠
⎝ σe ⎠
in which we have used Δ = 2VR to compute σ e2 .
For every doubling of the oversampling ratio, i.e. every increment in R, the SNR
improves by 9 dB, or equivalently, the resolution improves by 1.5 bits. Thus, the
resolution can be traded for signal bandwidth. Compared to the ideal quantizer of (5.4),
there is an “overhead” in this technique of 5.17 dB, approximately 1b.
122
A 2nd-order sigma-delta modulator (Figure 5.3), first introduced by Candy [65],
provides better resolution with the same oversampling ratio compared to the first-order
modulator. The modulator output is
Y ( z ) = X ( z ) z −2 + E ( z )(1 − z −1 ) 2 .
(5.11)
The SNR is [63]
⎛σ 2 ⎞
⎛σ 2 ⎞
SNR = 10 log ⎜ x2 ⎟ − 12.90 + 15.05 ⋅ R (dB) = 10 log ⎜ x2 ⎟ − 8.13 + 15.05 ⋅ R (dB) .(5.12)
⎝ VR ⎠
⎝ σe ⎠
For every doubling of the oversampling ratio, the SNR of a second-order sigma-delta
modulator improves by 15 dB, in other words, the resolution improves by 2.5 bits.
Compared to the ideal quantizer of (5.4), there is an overhead of 12.9 dB, about 2b.
Figure 5.3: Second-order sigma-delta modulator (from [66]).
Both sigma-delta architectures described above are single-bit, single-loop, lowpass modulators. There are many other published sigma-delta architectures, including
multibit, bandpass, cascaded loops, etc., which allow higher resolution with reduced
oversampling ratio [25]. Single-loop, single-bit modulators have been shown to be less
sensitive to circuit parameter imperfections, e.g., OPAMP DC gain and switch onresistance [67], however.
123
The conventional architecture shown in Figure 5.3 requires a signal range at the
outputs of the two integrators to be several times the full-scale analog input range [68].
This requirement limits the dynamic range of the circuit. A modified architecture (Figure
5.4) was proposed by Boser and Wooley [68] to allow considerably smaller signal ranges
at the integrator outputs by placing a scale factor of ½ on each integrator stage.
Furthermore, a forward path delay is included in both integrators to simplify the
implementation of the modulator.
Figure 5.4: Modified architecture of the 2nd-order sigma-delta modulator (from
[68]).
5.2.2 Architecture
A 1st-order modulator requires a sampling rate of >1.5 MHz to achieve 12-bit
resolution with an input signal bandwidth of 2 kHz, but a 2nd-order modulator only needs
~220 kHz to obtain the same performance. Therefore, the 1st-order modulator is
marginally adequate for this application. To ensure margin and to challenge the state of
the art, a 2nd-order sigma-delta modulator was chosen.
The architecture shown in Figure 5.4 was chosen for this work. The nominal
operating conditions of the modulator are similar but more aggressive than the
instrumentation amplifier specifications, as summarized in Table 5.1. The modulator
requires a 1minimum 4-bit dynamic range to replace the instrumentation amplifier with
124
programmable gain in the immediate application. The maximum differential output of
the instrumentation amplifier is ±2.5 V differentially and the minimum gain of the delta
modulator is two, so the maximum delta modulator differential input is ±1.25 V, same as
the modulator maximum input. The sensor output and modulator reference are both
scaled by the power supply VDD, so the converter output is independent of supply
voltage.
Operating Conditions:
Power supply
VDD= 5 ± 0.5 V, VSS = 0 V
Operating temperature
Try to maximize
Sigma-delta modulator specifications:
±VDD/2 = ±2.5 V
Reference level
Max differential input voltage
± VDD/4 = ±1.25 V
ADC full-scale
VFS = VDD = 5 V
Oversampling ratio
256
Sampling clock rate
2 MHz
Signal bandwidth
dc - 4 kHz
Dynamic range
14 bits required
16.5 bits simulated
Table 5.1: Nominal operating conditions of sigma-delta modulator.
According to (5.12), the theoretical SNR is 109 dB for a full-scale input and 103
dB for a half-scale sinusoidal input. Matlab simulation shows that the SNR is 101 dB for
a half-scale input. Thus, the modulator performance should exceed the project
requirement, and may exceed the best published high-temperature modulator in standard
CMOS, which has greater than 13-bit resolution, at temperatures of 250 °C [6].
125
5.2.3 High-temperature design considerations
5.2.3.1 Integrator gain
For the single-bit 2nd-order architecture shown in Figure 5.4, an integrator gain
variation of up to 20% from nominal has a minor effect on the modulator performance
[68]. The gain of a SC integrator is set by the ratio of capacitors, which has very low
temperature coefficient.
5.2.3.2 OPAMP DC gain
The integrator is implemented by an OPAMP with finite DC gain, which results
in integrator leakage that reduces the attenuation of the quantization noise in the
baseband, and increases the in-band quantization noise. The degradation in modulator
performance is about 1 dB when the OPAMP DC gain is comparable to the oversampling
ratio [68]. In this work, the OPAMP DC gain at room temperature was designed to be
greater than 1000. The OPAMP DC gain decreases over temperature, and can be halved
from 25 °C to 250 °C, but there is margin to ensure the required gain of 256 at high
temperature.
5.2.3.3 OPAMP bandwidth
In many switched-capacitor circuits, the OPAMP gain-bandwidth must be an
order of magnitude greater than the sampling rate. For example, according to (4.11), the
OPAMP bandwidth must be five times larger than the sampling clock fs to provide15 bits
of linear settling accuracy within 1/3 of the clock period. Consequently, the amplifier
gain-bandwidth needs to be about 10 MHz. In this work, the OPAMP transconductance
has been designed to be as large as ~1 mA/V to compensate for relatively low output
resistance at high temperature, as described in section 4.4.1.2. Thus, the load capacitor
126
should be smaller than 16 pF, which is easily achievable requirement. Through the use of
constant-gm biasing, the OPAMP bandwidth is maintained over temperature.
In fact, it has been shown that the OPAMP bandwidth can be comparable to the
sampling rate providing that the settling is not slew-rate limited [68]. Therefore, the
gain-bandwidth requirement of the sigma-delta modulator is easily achieved.
5.2.3.4 Slew rate
If the integrator settling is slew-rate limited, the signal-to-noise and distortion
ratio (SNDR) degrades rapidly, as shown in Figure 5.5. In this Matlab® simulation, the
sinusoidal input amplitude is set to -6 dBFS, i.e. -6 dB relative to the full-scale amplitude.
The full-scale level is VFS = 2*VR = VDD. The simulation shows that the slew rate must be
larger than 0.77*VFS*fs to ensure that the integrator settling process is linear. In the
nominal condition of this work, the minimum slew rate must be 7.7 V/μsec. As
temperature increases, the constant-gm bias circuit will compensate for degraded
mobility, as demonstrated in the bias circuit test result. In other words, the slew rate
increases over temperature. Therefore, slew rate will not be an issue at high temperature.
127
120
100
SNDR (dB)
80
60
40
20
0
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
Slew rate (VFS*fs)
Figure 5.5: Matlab® simulation showing influence of integrator output slew rate on
SNDR of 2nd-order sigma-delta modulator. Input amplitude is -6 dBFS and
OPAMP bandwidth is set to infinity.
5.2.3.5 Signal range
When the modulator input approaches full scale, the OPAMPs used in the
integrators reach their maximum output swing, the signal starts to clip, and distortion
increases rapidly. With the architecture shown in Figure 5.4, for signals as large as 1 dB
below full scale, the performance penalty is negligible when the signal range of both
integrators is about 70% larger than the full-scale input range, that is 1.7*VFS [68]. For a
-6-dBFS sinusoidal input, Matlab® simulation shows that the signal range of the
integrators is within 1.4*VFS, that is ±0.7*VFS. Hence, an output swing of ±0.7*VDD,
since VFS = VDD, is required for the OPAMP, which is achievable at room temperature.
128
The gate drive ΔV of a transistor biased by the constant-gm biasing technique
tends to increase as temperature increases. Substituting (3.3) into (1.14) yields
ΔV ≡ (VGS − VT ) ∝
If μ ∝ T
−
3
2
1
.
μnCox RB
(5.13)
and the temperature coefficient of RB is 1000 ppm/°C, ΔV increases by ~90%
from 25 °C to 250 °C. For the fully-differential folded-cascode OPAMP used in this
design, output swing is ± (VDD − Σ ( ΔV ) ) , where Σ ( ΔV ) is the sum of the gate drives of
the four transistors on one leg of the output stage. Σ ( ΔV ) has been designed to be
0.3*VDD, at 25 °C, so output swing is ±0.7*VDD at 25 °C. At 250 °C, Σ ( ΔV ) becomes
~0.57*VDD, and the output swing reduces to about ±0.43*VDD, which significantly
reduces the usable signal range of the modulator.
To allow high-temperature operation, the coefficients of the architecture in Figure
5.4 have been modified, as shown in Figure 5.6. The first-stage integrator gain is reduced
to 0.25 and the inner loop feedback coefficient is 0.5 to reduce the amplitude of all
signals gain in the feed-forward path by half, without affecting noise shaping, since
amplitude at quantizer input is irrelevant. Simulation result shows that the first-stage
integrator output is now bounded by ±0.33*VDD for an input of 50% full scale and
±0.39*VDD for an input of 70% full scale. Therefore, high-temperature overload should
occur above 70% full scale.
129
z −1
1 − z −1
z −1
1 − z −1
Figure 5.6: Revised coefficients to extend signal range at high temperature.
The scale factor of the first-stage integrator could be further decreased to obtain
even larger single range at high temperature. The penalty would be increased thermal
noise, due to the attenuation of the input signal.
5.2.3.6 Electrical noise and offset
Electrical noise and offset from the second-stage integrator are attenuated by the
large DC gain of the first-stage integrator, while noise and offset from the comparator are
suppressed by the gain of both integrators, but noise and offset from the first-stage
integrator are not attenuated. Therefore, the performance of the first-stage integrator is
critical. OPAMP offset reduces the usable signal range, and flicker noise increases the
in-band noise significantly since it cannot be noise-shaped or oversampled.
A simple approach to flicker noise management is to use large PMOS devices in
the input pair of the OPAMP [69]. In this case, given the desired large transconductance,
the device size would be unreasonable large. Similar to the pre-amplifier implementation
discussed in section 4.4.1, two other methods were considered: chopper stabilization and
correlated double-sampling.
Chopper stabilized switched-capacitor integrators have been widely used in lowbandwidth, high-resolution sigma-delta ADCs [70]-[73]. A chopper stabilized circuit
130
systematically removes offset and low-frequency noise by moving them to high
frequency and eliminating them with a low-pass filter. The chopping frequency is often
set to fs/OSR so that a sinc filter [74], commonly used as the decimation filter in sigmadelta ADCs, can effectively remove the translated noise and offset.
There are two major issues related to this technique. When the chopping occurs,
the amplifier inputs and outputs swap their polarities, which can cause a significant
glitch. If the amplifier cannot settle within the sampling period, distortion increases
greatly. Due to the nature of the chopper stabilization, high-frequency noise is
demodulated into baseband while baseband noise, mostly offset and flicker noise, is
moved to high frequency. It is possible that the high-frequency spectrally shaped
quantization noise could be demodulated down, and then coupled into the baseband [72],
[73]. As mentioned in section 4.4.1, the chopper stabilization technique removes offset
systematically, so increasing offset at high temperature still shrinks the integrator signal
range, which makes this technique unfavorable for high-temperature application.
The correlated double-sampling (CDS) technique, however, removes offset and
low-frequency noise every clock cycle [75]. Consequently, the signal range is improved.
The drawback of this technique is that compared to the conventional SC integrator [68],
more switches and capacitors are involved in each clock event, which contribute more
kT/C noise. After consideration of these factors, CDS has been chosen for the first-stage
integrator in this work.
The white noise, including OPAMP thermal noise and switch kT/C noise, cannot
be removed by the techniques described above. In theory, the sigma-delta ADC can
achieve higher resolution with increased oversampling ratio, but, in practice, the white
131
noise sets the upper bound of the SNR. For a signal bandwidth of 4 kHz, given nominal
maximum input level of -6 dBFS, since e 2
(V
=
FS
2N )
2
12
= −107 dBFS for N = 16, the
noise floor must be less than -134 dBFS/sqrt(Hz) and -140 dBFS/sqrt(Hz) for 15-bit and
16-bit dynamic range, respectively.
5.2.3.7 Clock jitter
Sigma-delta modulators are generally very tolerant to sampling clock jitter. The
error resulting from sampling a sinusoidal signal with amplitude A and frequency fx at an
instant with a error δ is [68]
x ( t + δ ) − x ( t ) ≈ 2π f xδ A cos ( 2π f x t ) .
(5.14)
Assuming the sampling clock jitter is white in frequency with a standard deviation of Δt,
the power of this error signal is [68]
A2
2
Sδ =
( 2π f x Δt ) .
2
(5.15)
The upper-bound of in-band error power SΔt is given by [68]
V 2 ( 2π BΔt )
,
SΔt ≤ FS
OSR
8
2
(5.16)
where B is the maximum signal frequency. The in-band quantization noise power of 2ndorder sigma-delta modulator is [68]
SB =
π4
1 VFS2
.
5 OSR 5 12
(5.17)
Comparing (5.17) and (5.16) shows that the maximum tolerable rms clock jitter that is
Δt ≤
1 π
1
.
B 30 OSR 2
(5.18)
For a maximum signal frequency of 4 kHz and oversampling ratio of 256, the proposed
sigma-delta modulator can tolerate an rms jitter of 2.2 nsec.
132
5.3 Detail Circuit Design
5.3.1 Improved double-sampling pre-amplifier
The gain of the CDS pre-amplifier used in the instrumentation amplifier is
noticeably reduced at high temperature and large gain setting, probably due to decreasing
FDOA DC gain at high temperature. For the CDS pre-amplifier shown in Figure 4.4, the
effective gain Aveff is [35]
Aveff =
Av
,
1 − Av
1+
ADC
(5.19)
where ADC is the DC gain of the FDOA and Av is the ideal CDS pre-amplifier gain of CS/CF. In the Sigma-Delta IC, an improved CDS pre-amplifier architecture is used to
provide better immunity to finite OPAMP DC gain.
5.3.1.1 Architecture
Several CDS pre-amplifiers with low sensitivity to finite OPAMP gain have been
reported [76]-[78], as shown in Figure 5.7. The terms “narrowband” and “wideband” are
referred to the speed of the input signal they can process accurately. The narrowband SC
amplifier [76] depends on the use of an additional capacitor C3 to hold the output when
the feedback capacitor C2 is resetting. During the reset phase φ1, the error voltage
including finite OPAMP gain error, as well as low frequency noise and offset, is held at
the summing node A and sampled at the left plate of C2. During amplification phase φ2,
the stored error voltage is subtracted from the amplified output. If the input signal is
slowly varying compared to the sampling rate, in other words, the input is greatly
oversampled, the amplifier output does not change from one sample to the next, and the
133
finite amplifier gain error can be nearly cancelled by the CDS. Detail analysis [79]
shows that for a slow-varying input, the effective gain of this architecture is
Aveff =
Av
.
1 − Av
1+ 2
ADC
(5.20)
Thus, an OPAMP having 60-dB gain in the architecture of Figure 5.7a is equivalent to a
120-dB OPAMP in the conventional CDS architecture. Furthermore, the amplifier output
is not reset to zero each clock phase, so the slew rate requirement is relaxed.
Figure 5.7: Offset- and gain-compensated SC amplifiers (from [35]): (a)
narrowband compensated SC amplifier [76]; (b) wideband compensated SC
amplifier [77]; (c) wideband compensated SC amplifier with storage capacitor [78].
The wideband compensated SC amplifiers use an additional predictive path to
produce the output while the main loop is resetting [77][78]. Providing the amplifier
input change much from phase to phase is accurately predicted, the finite gain error can
be effectively cancelled. Compared to the narrowband CDS architecture, these variations
134
provide better attenuation of non-linearity [80]. These architectures can be cascaded, but
more capacitors and switches are involved.
5.3.1.2 Circuit implementation
Figure 5.8 shows the schematic of the fully differential, gain-compensated CDS
pre-amplifier used in this work. It is based on the narrowband, conventional SC amplifier
[76], but includes offset cancellation circuitry and digitally controlled gain. The FDOA
is the same as in the instrumentation amplifier. For simplicity, CH was chosen to be the
same as CF. The output common-mode level VCMo is VDD/2, while the input commonmode level VCMi is a PMOS level-shifted version of VCMo that allows the use of PMOS
switches on the summing nodes. φ1 and φ2 are non-overlapping clock phases, and the
clock phases φ1d and φ2d are delayed turn-off versions of φ1 and φ2, respectively. Unlike
the CDS pre-amplifier in the instrumentation amplifier, the kT/C noise from the reset
switch cannot be eliminated by CDS, so thermal noise is increased by these switches.
VCMi
2d
Cran
2
Csys
1
CH
1d
VDD
Vref_os
1d
VCMo
CF
1d
2d
2d
CS
Vin+
+
-
1x
Vout-
FDOA
Vin-
-
CS
+
1x
Vout+
VDD
2d
Vref_os
1d
1d
2d
Csys
1
CF
1d
2d
VCMo
Cran
2
CH
VCMi
Figure 5.8: Schematic of the gain-compensated CDS pre-amplifier used in the
sigma-delta modulator. In this drawing, the random offset sign bit is set to zero.
135
5.3.2 First-stage integrator
5.3.2.1 Architecture
The implementation of the CDS integrator used in the first-stage of the sigmadelta modulator is based on the design proposed in [81] (Figure 5.9). The reference and
input signals use different input capacitors, instead of sharing the same capacitor, as in
[75]. This modification serves two purposes. First, it permits reference scaling, so VDD
and VSS can be used for Vref+ and Vref-, while choosing C2 =
C1
sets the maximum
2
modulator differential input range to ±2.5V. Second, capacitor sharing could result in
harmonic distortion since the current drawn from the reference would be signaldependent [82]. A detailed analysis of this problem can be found in [83] with further
discussion in [84]. Minor disadvantages of separating input capacitors include increased
die area, gain error due to mismatch and increased thermal noise due to extra switches
and capacitors, as compared to the conventional design.
Figure 5.9: Single-ended version of the CDS first-stage integrator. CP is the
parasitic capacitance at amplifier input and Vna is the input-referred amplifier
noise.
136
The clock phases of the first-stage integrator are the same as those used by the
pre-amplifier. As per discussion in section 5.2.3.5, C4 = 4*C1. The size of C3 is not
critical, but it should be larger than CP to provide sufficient flicker noise attenuation [85].
5.3.2.2 Noise analysis and design
As mentioned in section 5.2.3.6, the first-stage integrator is the major contributor
of total thermal noise of the modulator. It is difficult to obtain an exact model of thermal
noise in such a complicated SC circuit, although several estimates of SC integrator
thermal noise have been reported in [86] and [87], for example. In this section, an
approximate noise analysis of the integrator is presented to provide an upper bound, i.e.
worst case noise.
Switch (kT/C) noise and OPAMP thermal noise are treated separately. In view of
CDS, flicker noise was neglected in this analysis. For convenience, C3 = α*C1 and CP =
β*C1 were defined.
5.3.2.2.1 kT/C noise
In this calculation, the settling of the OPAMP is assumed to not be the limiting
factor, and all capacitors except CP are considered individually. At the end of sampling
phase (φ2), the mean-square noise charge trapped in C1, C2, C3 and C4 is kTC1, kTC2,
kTC3, kTC4, respectively. At the end of integration phase (φ1), these capacitors acquire a
second noise sample of similar variance. The noise charge from both phases is ultimately
transferred to the integration capacitor C4. The noise is referred to the input voltage by
dividing by C12, yielding
137
2
nt _ sw,C1
v
2
2
⎞
2 ⎛
kT ⎛ C1 + C2 + C4 ⎞ ⎛ CP + C3 ⎞ 2
= 2 × ⎜ kTC1 + kTC2 +
C4 + kTC4 ⎟ , (5.21)
⎜
⎟
⎜
⎟
⎟
C1 ⎜
C3 ⎝
C4
⎠ ⎝ C3 ⎠
⎝
⎠
where the first, second and fourth terms are due to charge redistribution of noise charge at
C1, C2 and C4, respectively, while the third term is obtained by amplifying the noise
voltage related to C3 by the reciprocal of the loop gain,
C3
C4
and
, and
CP + C3
C1 + C2 + C4
by the reciprocal of the closed-loop gain (C4/C1). Substituting C1 = 2*C2 = ¼*C4 =
(1/α)*C3 = (1/β)*CP into (5.21) yields
2
nt _ sw,C1
v
2
30.25 ( β + α ) ⎞
2kT ⎛
⎜ 5.5 +
⎟.
=
3
⎟
α
C1 ⎜
⎝
⎠
(5.22)
5.3.2.2.2 Amplifier thermal noise
Thermal noise is calculated assuming that the noise bandwidth is limited by the
OPAMP. A factor of two is added for correlated double sampling. Referred to the input,
the total noise power due to amplifier thermal noise is
2
2
nt _ amp ,C1
v
2
2
⎛ C + C2 + C4 ⎞ ⎛ CP + C3 ⎞ ⎛ C4 ⎞
π
= 2× v ×⎜ 1
⎟ × ⎜ ⎟ BW × ,
⎟ ⎜
2
C4
⎝
⎠ ⎝ C3 ⎠ ⎝ C1 ⎠
2
na
2
where vna
is input-referred amplifier noise, BW is the OPAMP bandwidth
(5.23)
g m,in
2π ( C1 + C2 )
,
and gm,in is the transconductance of the amplifier input pair. Assuming OPAMP noise is
2
=
dominated by the input pair, vna
8kT
8
kT
2
, and vna
× Bw × π =
. Substituting C1
3g m,in
3 ( C1 + C2 )
= 2*C2 = ¼*C4 = 1/α*C3 = 1/β*CP into (5.23) yields
138
(β +α )
121kT
=
.
3C1 α 2 (1.5β + (1.5 + β ) α )
3
2
nt _ amp ,C1
v
(5.24)
5.3.2.2.3 Total noise
Considering that actual circuit is fully differential, the total noise referred to the
input is
2
nt ,C1
v
3
⎞
121( β + α )
kT ⎛
60.5( β + α ) 2
⎜11 +
⎟.
= 2×
+ 2
3
C1 ⎜
α
3α (1.5β + (1.5 + β ) α ) ⎟⎠
⎝
(5.25)
If CP is neglected, i.e. β = 0, (5.25) can be simplified to be
vnt2 ,C1 =
kT
C1
⎛⎛
⎞
121 ⎞
⎟ + 53.8 ⎟ ,
⎜ ⎜ 22 +
α ⎠
⎝⎝
⎠
(5.26)
where the term (22+121/α) is from the thermal noise and 53.8 is from the amplifier noise.
Parameter α was chosen to be four to approximately match the contribution from kT/C
noise and amplifier thermal noise, i.e. (5.22) and (5.24). The total noise power referred
to the input is ~106*kT/C1, which is divided by the oversampling ratio to give the inband thermal noise power. Capacitor C1 was set to 3 pF to give 24 μVrms = -133
dBFS/sqrt(Hz) noise floor at 25 °C, adequate for 15 bits of SNR for -6 dBFS input. A
further increase in C1 could reduce the noise floor, but the die area would increase
significantly.
5.3.2.3 Circuit implementation
The FDOA design used in the instrumentation amplifier (Figure 4.5) was revised
to provide increased output swing. The gate drive voltage of both PMOS and NMOS
cascode devices was reduced to 0.1 V, and the devices used as current sources have a
gate drive of about 0.4 V. With these changes, the simulated amplifier is capable of
about ±4-V differential output swing with a 5-V supply. A separate set of bias voltages is
139
generated to properly bias the new FDOA. The tail bias current of the FDOA is about
100 μA and the slew rate is 11 V/μsec, which exceeds the requirement of the nominal
condition calculated in section 5.2.3.4.
5.3.3 Sigma-delta modulator
A detailed block diagram of the modulator is shown in Figure 5.10. The firststage integrator was discussed in the previous section. Capacitor values are C1 = 3 pF,
CREF1 = 1.5 pF, CCDS = 12 pF, and C2 = 12 pF. The φ2in clock phase used by the input
sampling switch is designed to be turned off one half unit delay ahead of φ2d to avoid the
glitch at the preamplifier output at the end of φ2d. Since the pre-amplifier output is
buffered by a PMOS level shifter, VCMin of the modulator with pre-amplifier is set to
(VCMo + VSGP) that is also VCMi, to avoid large input common-mode change the can cause
common-mode feedthrough. The VCMin of the stand-alone modulator is set to VCMO.
The second-stage integrator was implemented using the simple integrator
architecture with C3 = 1.2 pF, CREF2 = 0.3 pF, and C4 = 2.4 pF. The same FDOA as in
first-stage integrator is reused here, although it could be scaled down to reduce power
consumption.
The comparator is a single-input version of that used in the instrumentation
amplifier. Such a high-resolution comparator is probably unnecessary for a single-bit
single-loop sigma-delta modulator, which is very tolerant to comparator imperfections
[68]. However, this comparator has proved itself at high temperature for the
instrumentation amplifier, so was reused here.
140
in+
1d
1d
1d
D-
D-
CREF1
C1
1d
1d
C1
CREF1
VDD VSS
D+
2d
2in
2in
2d
D+
VCMo
VCMo
in-
VCMo
1d
1
VCMi
CCDS
2
2
CCDS
1
2
2
+
C2
+
FDOA
-
C2
Vint1o+
Vint1o-
1d
VDD VSS
1d
D-
CREF2
C3
1d
1d
C3
2d
2d
D+
VCMo
VCMo
2d
D-
CREF2
1d
2d
D+
VCMo
1d
VSS VDD
2d
1d
2
2
1
1
VCMi
+
C4
+
FDOA
-
C4
Vint2o-
Vint2o+
Conventional SC integrator
(2nd stage)
2in
1
VCMo
2d
2d
1d
1d
1ee
-
1
Preamp
1
+
+
-
-
Preamp
+
+
-
1ee
-
+
-
+
Regen
SC regenerative comparator
with three-stage offset-compensated pre-amplification
(one stage omitted for clarity)
DFF
D-
D+
latch
DFF
141
VSS VDD
CDS SC integrator
(1st stage)
MCLK
2
1e
Regen
1ee
Latch
Figure 5.10: Detailed block diagram of the sigma-delta modulator and its timing
diagram.
A transistor-level simulation of the modulator was performed using both DC and
AC inputs, mainly for verification of connections. A DC input of 54% full scale was
applied to the modulator input in the simulation. The difference between the simulated
and calculated integrator outputs is plotted in Figure 5.11. The calculated outputs were
generated by an EXCEL® chart that implements the ideal architecture. The difference is
quite small, considering the non-idealities modeled in the SPICE simulation. The second
integrator accumulates the error from the first integrator in addition to its own error,
which results in much greater difference than the first one.
Difference between simulation and calculation
0.005
0
-0.005
Difference (V)
-0.01
1st integrator
2nd integrator
-0.015
-0.02
-0.025
-0.03
-0.035
0
-0.04
5
10
15
20
25
30
35
40
No. of Cycles
Figure 5.11: Difference between simulated and calculated integrator outputs for a
DC input of 54% full scale.
An AC simulation result with a half-scale input at 1.343 kHz is presented in
Figure 5.12. The simulated SNR in the 4-kHz baseband is about 93 dB, which is limited
142
by numerical noise in SPICE, since there is no thermal noise modeled in the transient
simulation.
PSD of a 2nd-Order Sigma-Delta Modulator
0
-20
-40
-60
PSD [dB]
-80
-100
-120
-140
-160
-180
-200
3
10
4
10
Frequency [Hz]
5
10
6
10
Figure 5.12: AC simulation of the sigma-delta modulator with half-scale input at
1.343 kHz. Sampling rate is 2 MHz and OSR is 256. 16k samples were collected.
5.4 Test Results
5.4.1 Overview
The test chip that implements the block diagram in Figure 5.1 was fabricated
using the AMI 1.5-μm bulk CMOS process in a lot started November, 2005. The chip
micrograph is given in Figure 5.13. The chip size is 2.2 mm x 2.2 mm including the pad
ring. Active area almost fills up the whole interior that is around 1.8 mm x 1.8 mm.
Besides the circuits shown in Figure 5.1, the test chip included an 8-bit counter
143
constructed from an 8-bit adder and 8-bit registers that could serve as the basis of an FIR
decimation filter.
Figure 5.13: Die micrograph of high-temperature sigma-delta test chip.
5.4.2 Test setup
The high-temperature setup shown in Figure 4.35 continued to be used in the tests
of this chip. The follow instruments were used during the test:
•
Agilent E3631A Power Supplies,
144
•
SRS DS-360 Ultra-Low Distortion Function Generator with balanced
output,
•
Agilent 1673G Logic Analyzer,
•
Agilent 4395A Specturm/Network/Imepedance Analyzer,
•
HP 54615B Oscilloscope,
•
Keithley 2001 Multimeter (DVM),
•
Omega HH-306 Thermometer,
•
Omega FGS00321-010 Flexible Heating Tape, and
•
Omega CN2110 Temperature Controller.
The nominal conditions of these tests are VDD = Vref = 5 V, fclk = 2 MHz and OSR
= 256, unless stated otherwise. The modulator clock is generated off-chip using a crystal
oscillator to assure a low-jitter clock source, and the on-chip oscillator was separately
evaluated. The power supply was used as the voltage reference for all the tests.
For each measurement, the logic analyzer collected 64k samples of the1-bit
modulator output, which were further processed using Matlab®. The data was processed
using a Hanning window prior to Fast Fourier Transform (FFT) to reduce spectral
leakage [88], since the test signal generated by DS-360 was not synchronized with the
clock source. The choice of test signal frequency was based on the principle of coherent
sampling [88], discussed in detail in [59]. The nominal test input is a differential
701.904-Hz sinusoidal signal generated by the DS-360.
145
After FFT, the signal power PS is obtained by summing seven bins around the
fundamental bin B0, i.e. B0-3 to B0+3, and the ith harmonic distortion is obtained by
summing five bins around it, i.e. i*B0-2 to i*B0+2. Total distortion PD is the sum of
harmonic distortions within the bandwidth (generally i = 2 to 5). The in-band noise
power PN is the sum of all bins within the bandwidth except the first two bins (DC
component), signal and total distortion. SNR is PS/PN and SNDR is PS/(PN+PD). A
Matlab® program was used to do this processing, and is provided in the appendix.
In all FFT plots，0 dBFS is referred to the rms amplitude of a full-scale
sinusoidal signal, i.e.
VFS
2 2
. The nominal full-scale reference is 5 V, for which 0
dBFS is referenced to 1.7678 Vrms.
One chip of this lot has been tested, and the results are reported in the following
sections.
5.4.3 Sigma-delta modulator
5.4.3.1 Room temperature tests
Figure 5.14 shows a sample spectrum obtained from the stand-alone modulator
with a 701.904-Hz sinusoidal input at -6 dBFS. The extracted SNR and SNDR are 91.8
dB and 90.3 dB, respectively. This result is very close to the 15-bit resolution predicted
in section 5.3.2.2.3. The amplitudes of the second and third harmonics are -102.4 dB and
-97.7 dB below the fundamental, respectively. These harmonics may originate in the
signal generator, which is specified to have a signal-to-distortion ratio of > 105 dB.
146
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
2
10
3
10
4
10
FREQUENCY (Hz)
5
10
6
10
Figure 5.14: Measured spectral content of the sigma-delta modulator for a 701.904Hz, -6-dBFS input tone.
The in-band spectrum (Figure 5.15) shows a small tone near 120 Hz, which may
originate in the power supply. The in-band noise is approximately white, so flicker noise
has clearly been removed by the correlated double sampling. The average in-band noise
is about -112 dB/bin below the fundamental, and the FFT bandwidth is 30.52 Hz for the
2-MHz sampling rate and 216 samples. Therefore, the noise floor is about -132.8
dBFS/sqrt(Hz), very close to the theoretical value for thermal noise from the OPAMP and
switches calculated in section 5.3.2.2.
147
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
Figure 5.15: In-band (4 kHz) spectral content for data of Figure 5.14.
A plot of SNR and SNDR vs. input level is plotted in Figure 5.16. The modulator
achieves a peak SNR of 94.0 dB and a peak SNDR of 90.3 dB corresponding to an
effective number of bits (ENOB) = 14.7. The dynamic range is about 99 dB if maximum
input is considered to be 0 dBFS.
148
110
100
90
SNR
SNDR
80
SNR (dB)
70
60
50
40
Approximate characteristics
30
20
10
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input level (dBFS)
Figure 5.16: Measured SNR and SNDR for 4-kHz bandwidth vs. input level referred
to full scale.
The peak SNR for VDD = 4.5 V, 5 V and 5.3 V is 93.9 dB, 94.0 dB and 92.8 dB,
respectively, while the peak SNDR is 90.9 dB, 90.3 dB and 88.7 dB, respectively. The
modulator performance does not vary much in this range of supply change. But when the
supply voltage is > 5.3 V, non-linearity increases significantly, which may be due to nonlinear behavior of the FDOA in this supply condition. When supply voltage increases,
bias current may increase to a level that causes the transistors in the FDOA go out of
saturation. If this is true, the PSRR of the bias circuit should be improved.
Besides the nominal 2-MHz clock rate, the modulator has been tested using two
other clock frequencies: 1.2288 MHz, and 2.4576 MHz. The peak SNR is 93.3 dB and
84.0 dB, respectively, while the peak SNDR is 89.6 dB and 79.4 dB, respectively. The
149
performance degradation at the higher clock rate may be due to limited slew rate of the
OPAMP.
In the system application, the internal oscillator will be used as the sampling clock
for the modulator. Figure 5.17 shows the output spectrum of the modulator with Vin+ =
Vin- = Vcmo and the internal oscillator. The internal oscillator runs at ~1.53 MHz in this lot
(with GO = 1). The noise floor is indistinguishable from the measurement using the
crystal oscillator.
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
2
10
3
4
10
10
FREQUENCY (Hz)
5
10
Figure 5.17: Measured spectral content of the sigma-delta modulator with zero
signal input, using internal oscillator as sampling clock.
Figure 5.18 shows the frequency response to a -15-dBFS input tone with internal
oscillator as sampling clock. The SNR and SNDR are 82.0 dB and 81.0 dB, respectively.
Compared to the data (Figure 5.16) using the crystal oscillator, there is a degradation of
150
about 4 dB, apparently due to jitter of the internal oscillator. The clock jitter appears to
modulate the signal such that the fundamental of the signal becomes wider, generating
the spurs of Figure 5.18, which are counted as noise. Clock jitter is probably dominantly
by flicker noise and would be reduced by increasing sizing of the device in the oscillator.
Also, a phase locked-loop (PLL) could be used to limit the phase noise bandwidth of the
oscillator [89].
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
2
10
3
4
10
10
FREQUENCY (Hz)
5
10
Figure 5.18: Measured spectral content for a 256.984-Hz, -15-dBFS input tone using
internal oscillator as sampling clock.
5.4.3.2 High temperature test
A comparison of the spectral response of the modulator at 25 °C and 300 °C is
shown in Figure 5.19. The two spectrums are very similar identical except for the larger
third harmonic at higher temperature, which is caused by reduced amplifier output swing
at high temperature. The noise floor at high temperature is slightly larger than for room
151
temperature, as better shown in Figure 5.20. This difference can be caused by an increase
of the thermal noise over temperature. The SNR and SNDR for -6-dBFS input at 300 °C
are 90.4 dB and 83.9 dB, respectively.
0
25 C
300 C
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
2
3
10
10
4
10
FREQUENCY (Hz)
5
6
10
10
Figure 5.19: Measured spectral content of the sigma-delta modulator output for a
701.904-Hz, -6-dBFS input tone at 25 °C and 300 °C.
0
25 C
300 C
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
Figure 5.20: In-band (4 kHz) spectral content for data of Figure 5.19.
152
Figure 5.21 shows a plot of the SNR and SNDR with varying input level at 300
°C. As expected, the SNDR curve overloads at smaller input amplitude compared to the
curve shown in Figure 5.16, due to reduced integrator output swing. The SNR curve is
similar to the result at 25 °C. This result demonstrates that the modulator functions very
well at 300 °C.
100
90
SNR
SNDR
80
SNR (dB)
70
60
50
40
Approximate characterstics
30
20
10
0
-110
-100
-90
-80
-70
-60
-50
-40
Input level (dBFS)
-30
-20
-10
0
Figure 5.21: Measured SNR and SNDR vs. input level at 300 °C.
Measured SNR and SNDR vs. input level for various temperatures are shown in
Figure 5.22 and Figure 5.23, respectively. A plot of peak SNR and SNDR vs.
temperature is shown in Figure 5.24. The peak SNR does not vary much up to 250 °C.
According to the Johnson model, thermal noise increased by about 3 dB from 25 °C to
300 °C. It is possible that the in-band noise at lower temperature is dominated by the
quantization noise, which is stable over temperature.
153
110
100
90
80
SNR (dB)
70
60
50
40
Approximate characterstics
SNR(25 °C)
SNR(100 °C)
SNR(200 °C)
SNR(250 °C)
SNR(300 °C)
30
20
10
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input level (dBFS)
Figure 5.22: Measured SNR vs. input level for various temperatures.
110
100
90
80
SNDR (dB)
70
60
50
40
Approximate characterstics
SNDR(25 °C)
SNDR(100 °C)
SNDR(200 °C)
SNDR(250 °C)
SNDR(300 °C)
30
20
10
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
Input level (dBFS)
Figure 5.23: Measured SNDR vs. input level for various temperatures.
154
0
96
95
94
Peak SNR (dB)
93
92
91
90
89
Peak SNR
Peak SNDR
88
87
86
0
50
100
150
200
250
300
Temperature (°C)
Figure 5.24: Measured peak SNR and SNDR vs. temperature.
As temperature increases, the thermal noise becomes the major noise source that
lowers the SNR at high temperature. The peak SNDR decreases significantly after 150
°C due to integrator saturation, while the overload point of the SNDR curve shifts from
around -4 dBFS to -12 dBFS over this temperature range. The ENOB reduces by 0.5 bit
from 25 °C to 300 °C. In a future version, further reduction of the first integrator gain
may be required to extend the signal range at high temperature and provide better SNDR
stability over temperature. Nonetheless, this result indicates that this modulator has at
least 14-bit of ENOB up to 300 °C with excellent temperature stability.
5.4.4 Sigma-delta modulator with CDS pre-amplifier
Figure 5.25 and Figure 5.26 show the in-band spectrum of the modulator with
CDS pre-amplifier for various gain settings of the pre-amplifier at 25 °C and 300 °C,
respectively. The input level of -42.7 dBV (~7.4 mVrms) is -20 dBFS, -26 dBFS and -32
dBFS referred to the full-scale modulator input of 5 V for GA = 24, 12, and 6,
155
respectively. The noise floor increases as gain is increased, which suggests that the CDS
pre-amplifier noise is dominant. Measured SNR and SNDR at 25 °C for the three preamplifier gain settings, listed in Table 5.2, indicate that for GA = 12 and GA = 24, the
CDS pre-amplifier dominates the in-band noise. Increasing amplifier gain will not
increase the SNR.
0
GA=24
GA=12
GA=6
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
Figure 5.25: In-band (4 kHz) spectral content for a 701.904-Hz, -42.7-dBV input
tone and various pre-amplifier gain settings at 25 °C.
CDS pre-amplifier gain
SNR (dB)
SNDR (dB)
GA = 6
64.0
63.1
GA = 12
68.4
67.9
GA = 24
68.8
68.7
Table 5.2: Measured SNR and SNDR of the sigma-delta modulator with CDS preamplifier vs. gain settings for a 701.904 Hz, -42.7-dBV input at 25 °C.
156
0
GA=24
GA=12
GA=6
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
Figure 5.26: In-band (4 kHz) spectral content for a 701.904-Hz, -42.7-dBV input
tone and various pre-amplifier gain settings at 300 °C.
The extracted gain of the CDS pre-amplifier gain vs. temperature is shown in
Figure 5.27. The pre-amplifier gain is obtained by subtracting the extracted signal power
of the stand-alone modulator from that of the modulator with CDS pre-amplifier for
identical test conditions. The gain stability for several temperature ranges is calculated
and listed in Table 5.3. Compared to Table 4.7, the gain stability shows noticeable
improvement for the highest gain setting. The remaining gain instability may be caused
by amplifier settling error due to the reduction of OPAMP transconductance over
temperature. In these tests, the sampling clock is provided by the stable crystal oscillator.
In the system application, the clock will be provided by the internal oscillator, which is
locked to the gm of the bias circuit and gain stability should improve.
157
28
GA=24
GA=12
GA=6
24
CDS amplifier gain
20
16
12
8
4
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 5.27: Extracted CDS pre-amplifier gain vs. temperature on linear scale for a
701.904-Hz, -42.7-dBV input tone (nominal operating conditions).
Temperature stability (ppm/°C)
Temperature
range (°C)
GA=6
GA=12
GA=24
25 – 250
111
150
176
25 – 275
122
171
198
25 - 300
176
234
270
Table 5.3: CDS pre-amplifier gain stability for several temperature ranges and a
701.904-Hz, -42.7-dBV input tone (nominal operating conditions).
The total offset was calculated, and plotted in Figure 5.28. The offset is obtained
by averaging the samples acquired from the modulator output with zero differential input.
The remaining offset after correlated double-sampling for the architecture used in this
work is VOS,amp/ADC [35], where VOS_amp is the offset of the FDOA and ADC is its DC
158
gain. Increased offset at 300 °C may result from a decrease in OPAMP gain and an
increasing amplifier offset.
0.1
0
Input-referred offset voltage (mV)
0
50
100
150
200
250
300
-0.1
-0.2
-0.3
-0.4
GA=24
GA=12
GA=6
-0.5
-0.6
-0.7
-0.8
-0.9
Temperature (°C)
Figure 5.28: Extracted input-referred offset voltage vs. temperature for zero
differential input (nominal operating conditions).
To further examine the settling issue, the modulator with CDS pre-amplifier was
tested at a reduced clock rate of 1.2288 MHz. The result (Figure 5.29) demonstrates a
significant improvement over the result with faster clock under nominal conditions. The
gain stability is listed in Table 5.4. Thus, the new version of the CDS pre-amplifier
meets the original goal of improving gain stability over temperature. Further increasing
the FDOA bandwidth should allow increased sampling clock frequency. Extracted offset
is less than the higher frequency setting, as shown in Figure 5.30.
159
28
GA=24
GA=12
GA=6
24
CDS amplifier gain
20
16
12
8
4
0
0
50
100
150
200
250
300
Temperature (°C)
Figure 5.29: Extracted CDS pre-amplifier gain vs. temperature on linear scale using
fclk = 1.2288 MHz for a 412.5-Hz, -42.7-dBV input tone.
Temperature stability (ppm/°C)
Temperature
range (°C)
GA=6
GA=12
GA=24
25 – 250
31
30
41
25 – 275
41
41
50
25 - 300
62
66
95
Table 5.4: CDS pre-amplifier gain stability for several temperature ranges and a
421.5-Hz, -42.7-dBV input tone (fclk = 1.2288 MHz).
160
0.2
Input-referred offset voltage (mV)
0
0
50
100
150
200
250
300
-0.2
-0.4
-0.6
-0.8
GA=24
GA=12
GA=6
-1
-1.2
Temperature (°C)
Figure 5.30: Extracted input-referred offset voltage vs. temperature for zero
differential input. (fclk = 1.2288 MHz).
Figure 5.31 and Figure 5.32 show the in-band noise spectrum to a sinusoidal input
of -6 dBFS at the modulator input, 25 °C and 300 °C, respectively. The fundamental
amplitude for different gain settings is approximately the same, but the non-linearity
increases for higher gain. This is probably due to the nature of the narrowband preamplifier which has an effective gain that depends on dv
dt
of the output. The wideband
architecture could be used to improve harmonic distortion [80], which increases at high
temperature due to sigma-delta modulator integrator saturation, reduced CDS preamplifier swing, and lower DC gain of CDS pre-amplifier.
161
0
GA=24
GA=12
GA=6
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
Figure 5.31: In-band (4 kHz) spectral content for a 701.904-Hz input tone and an
input level of -6 dBFS at the modulator input at 25 °C.
0
GA=24
GA=12
GA=6
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
-140
0
500
1000
1500
2000
2500
FREQUENCY (Hz)
3000
3500
4000
Figure 5.32: In-band (4 kHz) spectral content for a 701.904-Hz input tone and an
input level of -6 dBFS at the modulator input at 300 °C.
162
SNR (dB)
CDS pre-amplifier gain
SNDR (dB)
25 °C
300 °C
25 °C
300 °C
GA = 6
86.5
82.5
71.9
61.6
GA = 12
82.1
78.9
73.5
69.3
GA = 24
81.5
79.0
75.0
54.0
Table 5.5: Measured SNR and SNDR vs. gain settings for a 701.904 Hz input and an
input level of -6 dBFS at the modulator input at 25 °C and 300 °C.
The Measured SNR of sigma-delta modulator with CDS pre-amplifier vs. input
level, at 25 °C and 300 °C are shown in Figure 5.33 and Figure 5.34. At 25 °C, the peak
SNR for GA = 6, 12, and 24 is 88.3 dB, 84.1 dB, and 82.9 dB, respectively. Dynamic
range is defined by the input amplitude of peak SNR. At 25 °C, the total dynamic range
of the CDS pre-amplifier and modulator is ~100 dB, while the dynamic range including
the stand-alone modulator is greater than 110 dB. At 300 °C, the SNR of the two largest
gain settings are approximately the same due to increasing thermal noise, but the overall
dynamic is still near 110 dB.
The measured SNDR of the modulator with CDS pre-amplifier vs. input level at
25 °C and 300 °C are shown in Figure 5.35 and Figure 5.36. The peak SNDR of
modulator with CDS pre-amplifier is much less than that of the stand-alone modulator,
presumably due to the non-linearity introduced by the CDS pre-amplifier. The
degradation of SNDR over temperature is also larger, than the stand-alone modulator. At
the highest gain setting, the peak SNDR decreases by about 10 dB from 25 °C to 300 °C.
163
120
110
SNR (GA=24)
SNR (GA=12)
SNR(GA=6)
SNR (sigma-delta only)
Fitted
100
90
SNR (dB)
80
70
60
50
40
30
Dynamic range of sigma-delta modulator with CDS pre-amplifier
20
Dynamic range including the standalone modulator
10
0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input level (dBFS)
Figure 5.33: Measured SNR of sigma-delta modulator with CDS pre-amplifier vs.
input level at 25 °C.
120
110
SNR (GA=24)
SNR (GA=12)
SNR(GA=6)
SNR (sigma-delta only)
Fitted
100
90
SNR (dB)
80
70
60
50
40
30
20
Dynamic range of modulator and CDS pre-amplifier
10
0
-120
Dynamic range including the standalone modulator
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input level (dBFS)
Figure 5.34: Measured SNR of sigma-delta modulator with CDS pre-amplifier vs.
input level at 300 °C.
164
100
90
80
SNDR (dB)
70
SNDR (GA=24)
SNDR (GA=12)
SNDR (GA=6)
SNDR (sigma-delta only)
60
50
40
30
20
10
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input level (dBFS)
Figure 5.35: Measured SNDR of modulator with CDS pre-amplifier vs. input level
at 25 °C.
100
90
80
SNDR (dB)
70
SNDR (GA=24)
SNDR (GA=12)
SNDR (GA=6)
SNDR (sigma-delta only)
60
50
40
30
20
10
0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input level referred (dBFS)
Figure 5.36: Measured SNDR of modulator with CDS pre-amplifier vs. input level
at 300 °C.
165
The output swing of the CDS pre-amplifier was designed to be ±1.25 V that is -6
dBFS. When the amplifier output approaches its maximum, the DC gain reduces and
non-linearity arises. This leads to the significant SNDR reduction when the amplifier
output is near its maximum. At higher temperature, this SNDR overload amplitude
decreases due to lower FDOA gain and smaller output swing. The SNR curves shifts
down slightly due to increasing thermal noise.
Figure 5.37 and Figure 5.38 show the performance of modulator with CDS preamplifier over temperature. Dynamic range is greater than 97 dB for the temperature
ranged from 25 °C to 300 °C. If the stand-alone modulator is included in the calculation,
the dynamic range is greater than 110 dB over this temperature range. At 300 °C, the
peak SNDR for GA = 6, 12 and 24 is 72.4 dB, 72.7 dB and 65.7 dB, respectively,
equivalent to an ENOB of 11.7, 11.8, and 10.8 bits. As shown in Figure 5.24, the peak
SNDR of the stand-alone modulator at 300 °C is 87.2 dB
The CDS pre-amplifier is the limiting factor of the overall noise performance. Its
thermal noise could be reduced by adjusting device sizes of the FDOA and reducing the
bandwidth of the source follower. On the other hand, harmonic distortion could be
reduced by increasing the output swing of the FDOA. Furthermore, the wideband CDS
pre-amplifier architecture could be used to reduce non-linearity, but this would require
duplicating all capacitors, including those in the offset correct DAC.
166
100
95
Peak SNR (dB)
90
85
80
75
70
Peak SNR (Sigma-delta only)
Peak SNR (GA=6)
Peak SNR (GA=12)
Peak SNR (GA=24)
65
60
0
50
100
150
200
250
300
Temperature (°C)
Figure 5.37: Measured peak SNR of modulator with CDS pre-amplifier vs.
temperature.
100
Peak SNDR (dB)
90
80
70
60
Peak SNDR (Sigma-delta only)
Peak SNDR (GA=6)
Peak SNDR (GA=12)
Peak SNDR (GA=24)
50
40
0
50
100
150
200
250
300
Temperature (°C)
Figure 5.38: Measured peak SNDR of the modulator with CDS pre-amplifier vs.
temperature.
167
It is possible to integrate the pre-amplification function into the sigma-delta
modulator by making the ratio of the input capacitor to the reference capacitor
programmable, similar to the instrumentation amplifier. This approach may improve
linearity, but would greatly increase the capacitor area if high amplification is required,
since the input capacitor must be large enough to satisfy thermal noise requirement. For
instance, in [71], the input capacitor, reference capacitor, and integration capacitor for the
largest gain (4) are 24 pF, 12 pF and 48 pF, respectively, but the peak SNDR for this gain
is 70.8 dB only.
168
6 Conclusions
6.1 Achievements
In this research, a monolithic, high-temperature bulk CMOS data acquisition
system for Wheatstone-bridge sensors has been developed. The main design challenges
were 1) excess leakage current, 2) decreased carrier mobility, and 3) unstable threshold
voltage. Design techniques were developed to overcome these high-temperature effects
and allow the bulk CMOS IC to operate at temperatures > 250 °C. Mixed-signal circuit
functions, including an operational amplifier, comparator, oscillator, integrator, current
source and temperature sensor, have been developed using these techniques. These
circuit functions were used to implement more complicated systems, specifically an
instrumentation amplifier and a sigma-delta modulator. Both were fabricated using the
AMI 1.5-μm bulk CMOS process, and characterized at temperatures up to 300 °C.
The Instrumentation Amplifier IC features a fully-differential, adjustable-gain
amplifier with digitally programmable offset cancellation, and features a constant-gm
biasing circuit, a fully monolithic oscillator, internal thermometer circuit and RTD sensor
interface. The thermometer and RTD sensor interface perform well at temperature for T
< 225 °C. The oscillator demonstrates a temperature stability of ~97 ppm/°C for T < 290
°C in the fast clock setting. The instrumentation amplifier shows excellent stability for T
< 300 °C. The best gain stability is achieved when GA = 6 and GD = 8, 128 ppm/°C for
25 °C < T < 300 °C. Within this operating temperature range, the instrumentation
amplifier provides better gain stability than the state of the art [5], and many more
auxiliary functions to facilitate sensor interfacing.
169
A comparison of the instrumentation amplifier to published high-temperature
amplifiers is provided in Table 6.1.
Process
Reported Tmax
(°C)
HighTemperature
Techniques
Performance summary
The instrumentation amplifier achieves a gain
stability of 128 ppm/°C for 25 °C < T < 300
°C for GA=6, GD = 8.
This
work
Bulk
CMOS
300
Constant-gm
biasing, CDS,
locking clock
frequency to
opamp BW
[5]
Bulk
CMOS
300
Dynamic
feedback
The instrumentation amplifier achieves an
average gain error < 25 ppm up to 250 °C and
< 500 ppm at 300 °C.
Continuous-time
auto-zero
The OPAMP achieves an input-referred offset
< 60 μV at 25 °C and < 200 μV at 200 °C, and
a unity-gain bandwidth (CL = 100 pF and RL =
10 kΩ) of 3.3 MHz at 25 °C and 2.2 MHz at
200 °C.
Not reported
One OPAMP achieves a DC gain of 65 dB at
25 °C and 55 dB at 300 °C, and a unity-gain
bandwidth (10 pF load) of ~2 MHz at 25 °C
and 1 MHz at 300 °C; the other OPAMP
achieves a DC gain of 35 dB at 25 °C and 25
dB at 300 °C, and a unity-gain bandwidth (10
pF load) of 100 MHz at 25 °C and ~30 MHz
at 300 °C.
Not reported
The transimpedance amplifier achieves a DC
transimpedance gain of 139 dBΩ at 25 °C and
126 dBΩ at 300 °C, and a pass-band
bandwidth of 1.2 MHz at 25 °C and 400 kHz
at 300 °C.
The OPAMP achieves a DC gain of 44 dB at
25 °C and 30 dB at 225 °C, and a unity-gain
bandwidth (RL = 10 kΩ, CL = 100 pF) of 1
MHz at 25 °C and 2 MHz at 225 °C.
[19]
[7]
[8]
Bulk
CMOS
SOI
200
300
SOI
300
[25]
SOI
225, guaranteed
300, derated
performance
Not reported
[26]
SOI
225
Ping-pong
amplifier with
auto-zero
The OPAMP achieves a DC gain > 114 dB
and a unity-gain bandwidth (RL = 10 kΩ, CL =
20 pF) of 2.2 MHz from 25 °C to 225 °C.
Table 6.1: Comparison of the instrumentation amplifier to published hightemperature amplifiers.
170
The Sigma-Delta IC includes a sigma-delta modulator with CDS pre-amplifier, a
stand-alone sigma-delta modulator, constant-gm biasing circuit, oscillator and internal
thermometer circuit. The CDS pre-amplifier has an adjustable gain and digitally
programmable offset cancellation. The stand-alone sigma-delta modulator has a peak
SNR and SNDR of 94 dB and 90 dB, respectively, at 25 °C, and 94 dB and 87 dB at 300
°C. Theses results far exceed the performance of prior sigma-delta modulators in bulk
CMOS [6].
A comparison of the modulator to published high-temperature ADCs is provided
in Table 6.2.
The gain stability of the CDS pre-amplifier fin the sigma-delta modulator or GA =
6, 12 and 24 is 62, 66 and 95 ppm/°C, respectively, for 25 °C < T < 300 °C, which is a
significant improvement over the version used in the instrumentation amplifier. At 300
°C, the modulator with CDS pre-amplifier achieves a dynamic range of 110 dB including
the stand-alone modulator range. The dynamic range is comparable to the current state of
the art [71], signal bandwidth is lower, but operating temperature range is much wider.
The circuit modules developed in this work can be used to construct other hightemperature mixed-signal systems. Although this research focuses on high-temperature
circuits in bulk CMOS, the techniques and design considerations carried throughout this
work can be used in the designs in SOI, which will result in extended operating
temperature range with stable performance.
171
OSR
Peak
SNR
@25 °C
(dB)
Peak
SNDR
@25 °C
(dB)
Peak
SNR
@Tmax
(dB)
Peak
SNDR
@Tmax
(dB)
Architecture
Process
Reported
Tmax (°C)
This
work
2nd-order
sigma-delta
Bulk
CMOS
300
256
94
90
94
87
[6]
2nd-order
sigma-delta
Bulk
CMOS
255
256
Not
reported
88
Not
reported
80
[6]
3rd-order
(2-1 MASH)
sigma-delta
Bulk
CMOS
255
256
Not
reported
88
Not
reported
80
[28]
1st-order
sigma-delta
SOI
350
128
58
Not
reported
30
Not
reported
[29]
2nd-order
sigma-delta
SOI
350
64
58
Not
reported
30
Not
reported
[30]
2nd-order
sigma-delta
SOI
225
256
95.4
93.9
77.6
72.6
[30]
4th-order
(2-2 MASH)
sigma-delta
SOI
225
256
97.4
94.8
77.6
72.6
[59]
1st-order
sigma-delta
SOI
275
64
54
Not
reported
30
Not
reported
SOI
225,
guaranteed,
300, derated
performance
N/A
[31]
12-bit SAR
12-bit
linearity
12-bit
linearity
Table 6.2: A comparison of the sigma-delta modulator and published hightemperature ADCs.
6.2 Future Work
Most of the circuit blocks function well up to 300 °C, but the performance of the
temperature sensor, RTD interface, and offset cancellation DAC degrades rapidly after
225 °C due to excessive leakage. For these current-mode circuits, a dummy NMOS
transistor can be used to sink the leakage current, as suggested in section 4.5.2.4 and
172
section 4.5.2.5. A differential reference could be used to improve the offset-cancellation
DAC, as discussed in section 4.5.2.6.3.
The improved CDS pre-amplifier used in the Sigma-Delta IC could be used in the
Instrumentation Amplifier to provide better immunity to OPAMP finite gain error, and to
relax the settling requirement for large signals, as discussed in section 4.5.2.7.1.
Potentially, a wideband CDS pre-amplifier could help reduce non-linearity.
The FDOAs can be adjusted to provide better thermal noise performance. The
bias of the FDOA used in the sigma-delta modulator should be adjusted to allow it to
function at higher power supply, and its slew rate can be increased to allow the modulator
to run at higher clock rate. The FDOA of the CDS pre-amplifier could be designed to
have the same large output swing as the one in the sigma-delta modulator, to reduce nonlinearity for large signals.
The gain of the first-stage integrator of the sigma-delta modulator could be further
decreased to relax the output swing requirement, and allow higher overload amplitude.
The temperature stability of the oscillator requires more study. At this time, the
stability of the oscillator with the same design has significant variation from lot to lot.
The designed oscillation frequency for GO = 0 could be lowered to 2 MHz instead of 3
MHz.
In this work, the high-temperature circuit characterization has been performed in
short time periods (~1 hour). Long-term (>1000 hours) tests are needed to further
understand reliability issues in bulk CMOS ICs on rated at high temperatures.
173
7 Appendix
% FFT test program for Prop21 work
% Based on a sample program posted in www.maxim-ic.com
filename='sdout.txt';
fid=fopen(filename,'r');
numpt=2^16; % number of point
fclk=2E6; %2.4576E6;
cycle = 23; %number of signal periods
fsig_in =1/( numpt/cycle/fclk);% expected signal frequency using coherent sampling
sbin_expected = round(fsig_in/fclk*numpt);
%SD ADC - 1-bit data out
numbit=1;
OSR = 256;
bw = fclk/2/OSR;
fb = round(numpt*bw/fclk); %number of baseband bins
%First line is not useful
fgetl(fid);
[v1,count]=fscanf(fid,'%f',[1,numpt]);
fclose(fid);
code=v1';
%Recenter the digital sine wave
Dout=code-(2^numbit-1)/2;
Doutmean= mean(Dout(1:numpt))
%If no window function is used, the input tone must be chosen to be unique and with
%regard to the sampling frequency. To achieve this prime numbers are introduced and
the
%input tone is determined by fIN = fSAMPLE * (Prime Number / Data Record Size).
%To relax this requirement, window functions such as HANNING and HAMING (see
below) can
%be introduced, however the fundamental in the resulting FFT spectrum appears 'sharper'
%without the use of window functions.
w=hanning(numpt,'periodic');
Doutw=Dout.*w;
w1=norm(w,1);
174
%Performing the Fast Fourier Transform
Dout_spect=fft(Doutw);
%Dout_spect= Dout_spect*4*sqrt(2)/numpt; %for dBFSrms or PSD, if for dBFS, should
be multipled by 2*sqrt(2)
Dout_spect=Dout_spect/(w1/2)*2;
Dout_spect(1)=Dout_spect(1)/sqrt(2);
%Recalculate to dB
Dout_dB=20*log10(abs(Dout_spect));
%Find the signal bin number, DC = bin 1
maxdB = max(Dout_dB(sbin_expected-3:sbin_expected+3));
fin=find(Dout_dB(1:fb)==maxdB);
%Display the results in the frequency domain with an FFT plot
figure(99);
maxdB=max(Dout_dB(1:fb));
plot([0:numpt/2-1].*fclk/numpt,Dout_dB(1:numpt/2));
grid on;
%title('FFT PLOT');
xlabel('FREQUENCY (Hz)');
ylabel('AMPLITUDE (dBFS)');
%a1=axis; axis([a1(1) a1(2) -140 a1(4)]);
axis([0 fclk/2 -140 0]);
%Calculate SNR, SINAD, THD and SFDR values
%Span of the input frequency on each side
span = 3;
%Approximate search span for harmonics on each side
spanh=2;
%Determine power spectrum
spectP=(abs(Dout_spect)).*(abs(Dout_spect));
%Find DC offset power
Pdc=sum(spectP(1:2));
%Extract overall signal power
Ps=sum(spectP(fin-span:fin+span));
%Vector/matrix to store both frequency and power of signal and harmonics
Fh=[];
%The 1st element in the vector/matrix represents the signal, the next element represents
%the 2nd harmonic, etc.
Ph=[];
175
%Find harmonic frequencies and power components in the FFT spectrum
for har_num=1:10
%Input tones greater than fSAMPLE are aliased back into the spectrum
tone=rem((har_num*(fin-1)+1)/numpt,1);
if tone>0.5
%Input tones greater than 0.5*fSAMPLE (after aliasing) are reflected
tone=1-tone;
end
Fh=[Fh tone];
%For this procedure to work, ensure the folded back high order harmonics do not overlap
%with DC or signal or lower order harmonics
har_peak=max(spectP(round(tone*numpt)-spanh:round(tone*numpt)+spanh));
har_bin=find(spectP(round(tone*numpt)-spanh:round(tone*numpt)+spanh)==har_peak);
har_bin=har_bin+round(tone*numpt)-spanh-1;
Ph=[Ph sum(spectP(har_bin-1:har_bin+1))];
end
%Determine the total distortion power
Pd=sum(Ph(2:5));
%Determine the noise power
Pn=sum(spectP(1:fb))-Pdc-Ps-Pd;
format;
SNDR=10*log10(Ps/(Pn+Pd))
SNR=10*log10(Ps/Pn)
disp('THD is calculated from 2nd through 5th order harmonics');
THD=10*log10(Pd/Ph(1))
SFDR=10*log10(Ph(1)/max(Ph(2:10)))
disp('Signal & Harmonic Power Components:');
HD=10*log10(Ph(1:10)/Ph(1))
PsigdB = 10*log10(Ps)
176
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