IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991
I568
An Overview of Smart Power Technology
B. Jayant Baliga, Fellow, IEEE
Invited Paper
Abstract-The evolution of smart power technology and its
impact on electronic systems are reviewed. After providing a
definition of smart power technology, the key technological developments in power semiconductor devices; namely, power
MOSFET’s and IGBT’s, are described. These developments
have been the foundation upon which smart power technology
rests. Smart power technology requires the marriage of power
device technology with CMOS logic and bipolar analog circuits.
The technical challenges involved in combining power handling
capability with on-chip regulation of overcurrent, overvoltage,
and overtemperature conditions are described, together with
examples of solutions for telecommunications, motor control,
and switch mode power supplies.
I. INTRODUCTION
HE ROOTS of power semiconductor technology extend before those for integrated circuits. Since the invention of the bipolar transistor and the thyristor, there
has been a strong motivation to increase the power handling capability of these discrete devices in order to extend their applications. The growth in the current and
voltage handling capability of power thyristors over the
last 35 years has been dramatic, as illustrated in Fig. 1.
It is impressive to note that by the 1990’s, a single (monolithic) power thyristor made from a 100-mm-diameter
wafer is commerically available with the ability to block
6500 V in the off-state and conduct over 2000 A in the
on-state. Since each of these devices are fabricated out of
an entire silicon wafer, the growth in the ratings of power
thyristors has been determined by the availability of highresistivity, large-diameter, float-zone, silicon wafers. The
sharp improvement in ratings achieved in the later 1970’s
can be directly linked to the development of neutron
transmutation doping-a new method of doping silicon
very uniformly by converting a silicon isotope to phosphorus by the absorption of thermal neutrons [l].
Over the years, the process technology for bipolar
power devices lagged behind that developed for integrated circuits. These devices continued to be fabricated
using design rules in mil units (25 pm). Further, the junction depths used to fabricate these devices were maintained in the range of 10 to 100 pm to enable high-voltage
operation. Consequently, the process technology for
I
i
T
Manuscript received November 14, 1990; revised February 13, 1991.
This paper is based upon an invited planary session paper given at the 1990
IEEE International Elcctron Devices Meeting.
The author is with the Electrical and Computer Engineering Department,
North Carolina State University, Raleigh, NC 27695-791 1.
IEEE Log Number 9100054.
6500 V
i
-
t
YEAR
(b)
Fig. 1. Progress in power thyristor ratings. (a) Growth in current ratings
of power thyristors. (b) Growth in blocking voltage ratings of power thyristors.
power devices was significantly different from that used
for integrated circuits. This situation changed due to the
introduction of the power MOSFET in the 1970’s and the
advent of MOS/bipolar devices in the 1980’s.
11. MOS POWERDEVICES
The power MOSFET was first introduced commercially
in the 1970’s. When compared with the bipolar transistor,
this device had the advantageous features of a high-input
impedance, high switching speed, ease of paralleling, and
a much superior safe operating area (SOA) [2]. This
makes the power MOSFET attractive for many applications such as computer power supplies and automotive
electronics.
0018-9383/91/0700-1568$01.00
___
--
-~
0 1991 IEEE
~
1569
BALIGA: A N OVERVIEW OF SMART POWER TECHNOLOGY
12.5 m i c r o n s
'
'
Drain Metal
(ai
25 m i c r o n s
Source Metal
N f Subatrate
Drain Metal
(bi
Fig. 2. Comparison of the current flow in a state-of-the-art power MOSFET (b) with a VLSI-based power MOSFET (ai
The current rating of the power MOSFET is determined
by the resistance within the device [2]. The resistance can
be reduced by making the channel length small, especially
in the case of devices with blocking voltages below 100
V. In the commercially available power DMOSFET
structure, the channel length is controlled by adjusting the
relative diffusion depth of the p-base and the nf-source
regions. This allows the fabrication of devices with submicrometer channel lengths without the need to use advanced VLSI processing tools. However, it can be shown
that the current distribution within the cell can be improved by reducing the size of the polysilicon window by
using VLSI technology [3], [4], as illustrated in Fig. 2,
where an optimized state-of-the-art DMOSFET is compared with a VLSI-based DMOSFET. The shaded portion
indicates the area through which the current flows in the
drift region. From this figure, it can be seen that the drift
region is much more effectively used for current transport
when the size of the polysilicon window is reduced by
using VLSI design rules. The impact of this change upon
the specific on-resistance is shown in Fig. 3, where the
polysilicon width has been varied to obtain the minimum
on-resistance for each device. Using VLSI design rules,
it has been found that the specific on-resistance can be
reduced by a factor of 2 X . This theoretical result has also
been experimentally verified [4].
The progress made by the power semiconductor industry in reducing the specific on-resistance can be seen in
Fig. 4.By scaling the DMOSFET geometry, the specific
on-resistance has been reduced from 7 mQ . cm2 in 1970
to only 0.7 m a cm2 in 1990. In addition, the develop-
-
1
0 0018
\
'
\
-
STATE-OF-THE-ART
50 VOLT DMOSFET
v
00014
4\
iJ
U 0.0013
z
3
VI
W
IY
0.0012
0.0011
0.001
0.0009
U 0.0008
-
&
0.0007
W
0.
0.0006
VI
0.0005
+, , ,
11
13
15
17
, , , , ,
19
21
CELL REPEAT SPACING
23
25
27
29
( MICRONS )
Fig. 3. Impact of VLSI technology on 50-V power MOSFET. Comparison
of the specific on-resistance for the state-of-the-art power MOSFET with
the VLSI-based power MOSFET.
ment of power MOSFET's with trench gate structures,
based upon RIE processes used for DRAM'S, have been
explored resulting in devices with specific on-resistances
as low as 0.3 mQ * cm2. The latter value is approaching
the theoretical limit if 0.15 mQ cm2 for a silicon device
with a breakdown voltage of 50 V . For this reason, if
further improvements are to be achieved, it will be necessary to embark upon the development of power devices
based upon other semiconductor materials. As an example, theoretical analysis indicates that the specific on-resistance can be reduced by over 100 times by replacing
silicon with silicon carbide [ 5 ] .
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991
1570
I
Z
7*
6-i
I
50 VOLT POWER MOSFETS
I
I
-
z
-
a
W
::
102
:
z
-
-
v)
a
m
1
o
t
80
UMOSFET
\
THEORETICAL LIMIT
1
i
82
I
84
I
86
88
=-
2>
W
0
-
I-
-
w
z
U
[r
3
90
YEAR
Fig. 4. Progress in reducing the specific on-resistance of power MOSFET’s by technological advances.
5
!
10’
-
3
0
z
-
0
-
-
n
-
$
-
K
Although the power MOSFET is well suited for applications where the blocking voltages are relatively low (less
than 200 V), its on-resistance increases rapidly with the
increase in blocking voltage [2]. Due to this phenomenon,
it has not been possible to economically manufacture highvoltage power MOSFET’s with high current ratings. One
solution to this problem was the invention of the Insulated
Gate Bipolar Transistor (IGBT) [6], [7], whose cross-section is shown in Fig. 5. These devices have the same highinput impedance feature of the power MOSFET and can
operate at a current density of an order of magnitude larger
than the power MOSFET. Since the current transport in
IGBT’s occurs under high-level injection conditions, their
switching speed is limited by minority-carrier recombination. Typical tum-off times range from 0.1 to 10 p s [8].
This makes them suitable for medium-frequency applications where the blocking voltage exceeds 200 V . Examples of such applications are adjustable speed motor
drives, appliance controls, and roboticdnumerical controls.
The availability of the power MOSFET and the IGBT
with their voltage-controlled characteristics resulted in a
tremendous simplification in the control circuit. This in
turn created the opportunity for development of integrated
gate drive circuits. In many applications, the power devices are used in a totem pole configuration. For this reason, the control circuit must be capable of performing
level shifting to high voltages. The development of integrated control circuits also provided the impetus to incorporate protective circuits on the control chips against
overvoltage, overcurrent, and overtemperature conditions. In addition, the need to interface with microprocessors led to the incorporation of logic circuits to provide
encode/decode capability. This heralded the dawn of
smart power technology in the 1990’s.
111. SMARTPOWERTECHNOLOGY
In the broadest sense of the definition, smart power
technology provides the interface between the digital control logic and the power load. In its simplest form, it may
7
-
Ea
E
E
$
100
1
10-1-
0
I
I
1
2
3
4
5
FORWARD VOLTAGE DROP (VOLTS)
6
I
7
Fig. 5 . Impact of reduction in tum-off time on IGBT on-state characteristics. The device structure is shown in the inset. The table gives the turnoff time corresponding to each of the on-state characteristics.
consist of a level shifting and drive circuit that translates
the logic level signals received from a microprocessor to
a voltage and current level sufficient to energize a load.
An example of such a chip would be for display drives,
where the load is usually capacitive in nature but requires
drive voltages much greater than the operating voltage of
logic circuits. On the other extreme, the smart power
technology may be required to perform load monitoring,
diagnostic functions, self-protection, and information
feedback to the microprocessor, in addition to handling
large amounts of power to actuate the load. An example
of this is an automotive multiplexed bus system with distributed smart power modules for control of lights, motors, air-conditioning, etc.
A description of smart power technology can be made
with the aid of Fig. 6. Three fundamental functions that
are performed with this technology are power control,
sensing/protection, and interfacing. The basic components that are needed for the implementation of these
functions are shown in this figure.
Power control is performed by using power devices and
their drive circuits. It is the ability to handle high voltages, high currents, or a combination of both that makes
smart power technology unique. The drive circuits are unusual in that they must be designed to operate at up to 30
V to provide sufficient voltage to the gates of the power
devices. In addition, for totem-pole operation, the drive
1571
BALIGA: AN OVERVIEW OF SMART POWER TECHNOLOGY
BIPOLAR POWER TRANSISTORS
I
POWER MOSFET,
I
r[
I
DMCES
INSUUTED GATE BIPOLAR TRANSISTORS
Ll
D
G
S
G
G
S
1
MOS CONTROLLEU THYRISTORS
I
HIGH SPEED BIPOLAR TRANSISTORS
1
w
E
p:
w
E
I
i"^?&Kq
-
:E;pEl
l
OMR-VOLTAGE/UNDER-VOLTAGE
1
I
OVER-TEMPERATURE
I
L
OVER-CURRENT/NO-LOA0
I
I
Fig. 7 Quasi-vertical power DMOSFET structure and the components of
on-resistance arising from the sinker and buried layer.
- N
5
7
HIGH DENSITY CMOS
-
25
- MOSFET SP.
RESIS.
3 mOHM-CM2
=
,/
I
Fig. 6. Smart power technology functional elements and their implementation.
circuit must be able to perform level shifting to high voltages. The regulation of power flow is performed by a variety of power devices, with the MOS-gated devices being
increasingly favored.
As shown in Fig. 6 , smart power technology usually
incorporates some form of sensor technology together with
local feedback for protection of the IC. In addition to detecting the exceeding of a current, voltage, or temperature
limit, the detection of a no-load or under voltage condition is sometimes implemented. The undervoltage condition is useful to ensure sufficient biasing of the power devices to prevent excessive power dissipation during startup. The current sensing is done with minimum power loss
by partitioning a few cells from the power device and
feeding this current to the control circuit [9]. The protection of the IC is accomplished by using a feedback loop
containing high-frequency bipolar transistors. The response time of the feedback loop is critical to a benign
shutdown because the system current increases at a very
rapid rate during a fault. Consequently, this portion of the
smart power chip requires implementation of high-performance analog circuits.
The interface function in the smart power IC is accomplished by using logic circuits, which perform the encode
and decode operations. The chip must not only respond
to signals received from a microprocessor but must be capable of sending messages regarding operating status,
such as overtemperature shutdown, and information related to load monitoring, such as no-load or short-circuit
condition. This requires integration of high-density
CMOS circuits on the smart power chip. Due to the large
voltage swings and high chip temperatures arising from
self-heating, the design of the CMOS circuits for smart
power chips can be quite challenging to ensure immunity
from latch-up.
IV. PROCESSTECHNOLOGY
Due to the relatively high cost of dielectrically isolated
(DI) silicon wafers, most smart power chips are being
1
~-
&-~-r~-
3
5
7
9
NUMBER OF CELLS
Fig. 8. Optimization of quasi-vertical integrated power DMOSFET on-resistance.
fabricated using junction isolation (JI). If the cost of DI
wafers can be reduced in the future, it is likely that most
smart power chips will be made using DI due to simplification in design by the elimination of parasitics and the
option of integrating multiple, MOS/bipolar power devices. Meanwhile, the challenges faced by designers today are the integration of analog and digital circuits on
the same chip with high-voltage and high-current devices.
This requires the use of a two-level metal process, in addition to the polysilicon gate electrode. A thin metal layer
is used to fabricate the analog and digital circuits and the
thick metal is used for the power devices. The need to bus
high voltages around the chip also requires special metal
crossover design methodology where SIPOS layers are
employed.
For chips designed to operate at relatively low voltages
(up to 100 V), it is possible to implement vertical-power
MOSFET's on the chip with a buried layer as the drain,
as illustrated in Fig. 7 [lo]. The drain current is brought
up to the surface periodically using sinkers. In order to
minimize the size of the power MOSFET, it is essential
to determine the number of DMOS cells that must be located between the sinkers. The specific on-resistance of
the device is a function of the buried layer sheet resistance
and the sinker resistance. This can be seen from an example provided in Fig. 8 for a particular set of values.
This implementation is favorable for many low-voltage
applications,
For applications where the blocking voltages are above
100 V , the vertical device architecture becomes inefficient
because of the large space occupied by the sinker and iso-
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991
1572
CAPTURE
1-11
SYSTEM LEVEL
SIMULATION
(CLOGIC)
U
DEVICE
LAYOUT
(HVDEV)
SIMULATION
(SPICE)
I
STANDARD CELL
PLACE & ROUTE
CELL
LAYOUT
(GDT)
1
CHIP
ASSEMBLY
(ASPICGEN)
LAYOUT
VERIFICATION
(DRACULA)
Fig. 9 . An example o f a CAD tool for application-specific power IC design and simulation
lation regions. In addition, the performance of the logic
and analog circuits deteriorates due to the significant
thickness of the drift region. Since the performance of
these sections of the chips can be maximized by using a
relatively thin epitaxial layer, an approach to making highvoltage lateral power devices in thin epitaxial layers was
conceived [ 111. This approach, called RESURF for reduced surface electric field, has been extensively used to
fabricate high-voltage power IC’s [121, with breakdown
voltages up to 1200 V .
PP
RACTIO
MOTOR
CONTROL
TOOLS
V . COMPUTER-AIDED-DESIGN
Many of the applications of smart power technology are
expected to require application-specific designs. The ability to manufacture such chips requires the availability of
design tools that will allow rapid layout of the circuit,
with a high probability for error-free functional implementation. Excellent interactive CAD tools must be available to maintain a short design cycle time. The tools that
are needed include system and circuit level simulation,
standard cell libraries for components, automated scaling
of power devices with appropriate edge terminations, layout of interconnections with designs for high-voltage
crossover, and final layout verification. An example of
such an integrated software package created by Philips is
shown in Fig. 9, where a number of commerically available tools have been combined using custom-developed
modifications and interfaces.
VI. SMARTPOWERAPPLICATIONS
Smart power chips are expected to have an impact on
all areas in which power semiconductor devices are presently being used. The wide spectrum of voltages and cur-
10
100
1000
10,000
DEVICE BLOCKING VOLTAGE RATING
Fig. 10. Applications of smart power technology.
rents over which power semiconductor devices are now
being utilized is illustrated in Fig. 10. On the one extreme
are display drives that require relatively low currents and
moderate voltages. These applications are already being
served by smart power chips. On the other extreme lie
traction (transportation systems) and high-voltage dc
(HVDC) transmission which demand control of very high
currents and voltages. The development of new MOS/bipolar devices being researched at present could enable the
penetration of smart power technology even to these ap-
1573
BALIGA: AN OVERVIEW OF SMART POWER TECHNOLOGY
plications. Meanwhile, a strong thrust is underway to create smart power chips for motor control, factory automation (robotics), computer power supplies, and
automotive electronics. In many of these cases, application-specific designs will be required putting pressure on
the industry to create computer-aided-design (CAD) tools
that can perform automated layout and mixed-mode circuit simulation at high voltages and currents.
VII. EXAMPLES
OF SMART
POWERIC's
C E U r BOARD PHOTOGRAPH
FUNCTIONS
APPLICATIONS
*3$1500V BJT INVERTER
.MOTOR DRIVES
06 BASE DRIVER
*AC SERVO AMP
OC. OH PROTECTION
One of the fundamental issues that must be addressed
when embarking upon the development of a smart power
technology is the appropriate partitioning of the system.
Although a monolithic implementation is elegant and is
claimed to offer the highest reliability, it is not always the
most cost-effective solution. A multiple-chip implementation needs to be considered with the issues of packaging
cost and interconnect-associated parastics included in the
analysis. Depending upon the chip fabrication and packaging technology available to the manufacturer, the most
cost-effective solution for the same function may be either
multichip or monolithic, and this decision may change
with time.
The first example shown in this paper is a multichip
intelligent power module made by Fuji Electric. This approach, illustrated in Fig. 11, can utilize a variety of
power switches-such as bipolar transistors or IGBT'swith separate driver and level shift circuits. Using this
approach, a full bridge invertor capable of operating at
500 V and over 50 A has been reported [ 131.
An example of a monolithic chip developed by Fuji
Electric for automotive applications as a high side switch
is shown in Fig. 12. This chip contains a prominent power
MOSFET capable of operating at 60 V and 3 A [ 141. Protective circuits for detection of overtemperature, overcurrent, and overvoltage conditions have been integrated on
the chip, together with control logic for interfacing. Since
the power loss in the output device must be very small for
automative applications, a large amount of the chip space
is taken up by the power MOSFET, which has an onresistance of 0.1 R.
An example of a monolithic three-channel driver system for motor and solenoid control applications developed by SGS-Thomson is shown in Fig. 13. This chip
uses the Multipower BCD technology that integrates
quasi-vertical DMOSFET's with CMOS and bipolar circuits. The chip can handle up to 60 V and integrates two
I-A motor drivers, a 3-A solenoid driver. and a 5-V switch
mode power supply [ 151. It has the ability to directly interface with microprocessors and provide thermal protection.
An example of a monolithic three-phase inverter for
fractional horse power motors developed using dielectric
isolation technology is shown in Fig. 14 [16]. The use of
dielectric isolation allows the integration of multiple
IGBT's and Merged p-idSchottky (MPS) rectifiers [ 171
with charge pump drivers and level shift circuits. The use
CIRCUIT DIAGRAM
'AIR CONDITIONER
*SHORT CIRCUIT PROTECTION
Fig. 11. An example of a multichip implementation of a smart power application.
CHIP PHOTOGRAPH
BLOCK D I A G R A M
FUNCTIONS
APPLICATIONS
*HIGH-SIDE SWITCH (6OV-3A)
'DRIVER INTEGRATED
'OH. OC, AND OV PROTECTIONS
*DIAGNOSIS
AUTOMOTIVES
SOLENOID. MOTOR, LAMP
'ELECTRONIC CIRCUITS
POWER SWITCH
'SURGE IMMUNITY
Fig. 12. An example of a smart power chip for automotive applications
illustrating the large area consumed by the power device.
of MPS rectifiers has been reported to be critical to reducing the power losses to within acceptable limits without resorting to lifetime control processes that interfere
with other portions of the chip. The chip is capable of
operating off a rectified 100-V ac line (blocking 250 V)
at 1 A. By extending the operating frequency to 20 kHz,
the acoustic noise associated with motor control can be
reduced.
A final example shown in Fig. 15 is a monolithic dielectrically isolated chip technology developed by AT&T
Bell Laboratories. In this chip, bilateral DMOSFET's are
integrated with high-density CMOS logic and level shift
circuits. It combines an eight-channel shift register with
eight latched switches and is intended for high-voltage
multiplexing or ultrasound imaging applications.
Although many other examples are available in the literature based upon developments at these and other power
semiconductor manufacturers, the above examples were
chosen to illustrate the typical approaches taken and the
diversity of the technologies that are under investigation.
As the chip fabrication technology progresses, a monolithic implementation will become increasingly cost-effective. Consequently, many of the multichip modules
used today, especially at the higher power levels, will be
replaced with single-chip solutions in the future.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. 7, JULY 1991
1574
L 6 2 8 0 (U020)
CIRCUIT DIAGRAM
CHIP FUNCTIONS
APPLICATIONS
TWO 1A MOTOR DRIVERS
PORTABLE TYPEWRITERS
3 A SOLENOID DRIVER
5 V SWITCHMODE SUPPLY
INTERFACE, CONTROL
a
DIAGNOSTICS
Fig 13 An example of a monolithic 5mart power chip implemented u\ing qua\i-verticdl power DMOSFET‘s
CIRCUIT DIAGRAM
;a.i
FEATURES
liOTOR POSITION
SENSING
APPLICATION
25ov ...........................
AClOOV LINE
OFAN MOTOR FOR
1 A .............................
3OW MOTOR
HOME APPLIANCE
1 CHIP ........................
INCLUDE IN MOTOR
Fig. 14. An example of a three-phase invertor for fractional horse power motor control using IGBT‘s and MPS rectifiers achieved
by dielectric isolation technology.
VIII. CONCLUSIONS
Until recently, IC technology has been focussed primarily on chips for signal processing and data storage.
This has resulted in a phenomenal capability for information processing that has led to the “first electronic revolution.” This technology is akin to the brain in the hu-
man body, which assimilates data acquired via the senses
and provides decision making capability. Although this
technology has greatly enriched society, it has been hampered by the fact that in order to perform many functions,
it is necessary to control significant amounts of energy
being delivered to a variety of loads. Using the analogy
BALIGA: A N OVERVIEW OF SMART POWER TECHNOLOGY
Features...........................
Fig. 15. An example of a high-voltage octal switch for multiplexing and
ultrasound applications achieved by dielectric isolation technology.
of the human body, this is equivalent to the need for muscles to perform even the most basic tasks. The advent of
smart power technology promises to create the “second
electronic revolution” by providing the brawn to complement the information processing capability.
REFERENCES
E. Meese, Neutron Transmutation Doping in Semiconductors. New
York: Plenum. 1979.
B. J . Baliga. Modern Pourer Deizices. New York: Wiley. 1987.
D. A. Grant and J . Gowar, Power MOSFETs. New York: Wiley,
1989.
B. J . Baliga. “Impact of VLSI technology on power devices,” in
SSDM Dig., 1990. Abstr. A-1-2. pp. 5-9.
K . Shenai, “Optimally scaled low-voltage vertical power MOSFET’s
for high frequency power conversion,” IEEE Trans. E/rc%-on Deiices. vol. 37, pp. 1141-1 153, 1990.
B. J . Baliga, “Power semiconductor device figure of merit.” IEEE
Electron Device Lett., vol. IO, pp. 455-457, 1989.
1575
[6] B. I. Baliga et al.. “The insulated gate transistor,” in IEEEInt. Electron Devices Meet. Dig.,1982, Abstr. 10.6, pp. 264-267.
[7] J. P. Russel er al., “The COMFET,” IEEE Electron Device Lett.,
vol. EDL-4. pp. 63-65, 1983.
[8] B. J . Baliga, “Switching speed enhancement in IGBT’s by electron
irradiation,“ IEEE Trans. Electron Devices. vol. ED-31, pp. 17901795, 1984.
191 D. A. Grant and R. Pearce, “The dynamic performance of current
sensing power MOSFETs,” Electron. Lett.. vol. 24, pp. 1129-1 131,
1988.
[ I O ] A. Andreini, C. Contiero, and P. Galbiati. “A new integrated silicon
gate technology combining bipolar linear. CMOS logic, and DMOS
power parts,’‘ IEEE Trur7.s. Elcxtron Dei,ices. vol. ED-33, pp. 20252030, 1986.
[ I I ] J . A. Appels, and H . M. J . Vaes. “High voltage thin layer devices
(RESURF),” in IEEE Int. Electron Devices Meet. Dig., 1979, Abstr.
IO. I , pp. 238-241.
[I21 B . J. Baliga, High Voltage htegruted Circuits. New York: IEEE
PRESS, 1988.
B. J . Baliga, Ed., “Special Issue on Power and High-Voltage Integrated Circuits,” IEEE Trans. Electron Deizicrs, vol. ED-33. pp.
1933-2045, Dec. 1986.
1131 H. Shigekane, T. Hosen, N. Terasawa, K . Kuwabara, and Y. Inakoshi, “High power transistor modules with intelligent functions.”
in Proc. I n t . S p p . on Power Semicor~ductorDei7ices und ICs, 1990,
Abstr. 4.2.3., pp. 150-155.
(141 T . Fujihara, N. Kumagai, K . Yoshida, K . Sakurai. S . Fumhata, and
Y. Uchida, “New over-current protection circuit for smart power devices,” in Proc. Sjmp. on High Voltage, arid Smart Powvr ICs. 1989,
pp. 392-399.
[IS] A. Andreini, C . Contiero. and P. Galbiati. “ A new integrated silicon
gate technology combining linear, CMOS logic and DMOS power
parts,’’ IEEE Trans. Electror? Devices, vol. ED-33, pp. 2025-2030,
1986.
[ 161 N. Sakurai, M. Mori, and T. Yatsuo, “High speed. high current capacity LIGBT and diode for output stage of high voltage monolithic
three-phase invertor IC,” in Proc. Int. Symp. on Pow.er Serniconclucf o r Devicrs andICs. 1990. Abstr. 3.2.2, pp. 66-71.
[I71 B. J . Baliga, “Analysis of a high voltage merged PlNiSchottky (MPS)
rectifier,” IEEE Electron Device Lett., vol. EDL-8, pp. 407-409,
1987.