APPLICATION NOTE
SKYA21004: PCB Layout Guidelines
Introduction
PCB layout design is essential to better performance, reliability
and manufacturability. Malfunctions from noise, which may hurt
the system stability, have become an increasing problem, and
may therefore generate more failures and reliability malfunctions
in production lines.
In this document, several considerations and guidelines for
SKYA21004 PCB layout design are presented to improve
performance, reliability, and manufacturability.
Guidelines for Land Pattern and Thermal Vias on
the SKYA21004
The SKYA21004 is a QFN 36L package with a center ground pad
(exposed pad). The PCB center ground pad serves three major
functions: electrical ground, thermal heat sink, and mechanical
support. Ground pad size and soldering quality (such as the
wetting and voids) directly affect the ground pad functions.
Dimensions of the center ground pad are shown in Figure 1. The
center ground pad should be well connected to the terminal
ground pad and the common ground plane of the PCB to optimize
its functions.
Figure 1 shows the recommended land pattern for the
SKYA21004.
Figure 1. Recommended Land Pattern and Thermal Vias for the SKYA21004
(All dimensions are in millimeters)
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APPLICATION NOTE • SKYA21004: PCB LAYOUT GUIDELINES
Electrical and Thermal Performance
To improve thermal and electrical performance of a mounted
SKYA21004, an array of thermal vias placed on the area of the
ground pad should be connected to the internal and bottom
common ground copper planes of the PCB. In general, there is a
direct correlation between the thermal via cross-sectional area
and the heat dissipation rate. However, large and excessive
thermal vias may introduce more voids in the solder joint and
actually reduce overall heat dissipation performance.
Recommended thermal vias are 0.30 mm to 0.33 mm in diameter,
and via barrels should be plated with 1 oz. of copper to plug the
vias. The thermal via array should be arranged evenly with a pitch
of 0.5 mm to 1.0 mm. For the exposed region of the ground pad,
if the plating thickness is not sufficient to effectively plug the
barrel of the via when plated, solder mask should be used to cap
the vias with a minimum dimension equal to the via diameter plus
0.1 mm. This will prevent solder wicking through the thermal via
during the soldering process, resulting in voiding.
In the SKYA21004 layout, it is recommended to arrange 24ea vias
evenly with a pitch 0.6 mm, as shown in Figure 1.
For more detailed information refer to the Skyworks Application
Note #101752I.
Guidelines for the Boost Section for LED
Backlight Driving and LCD Bias Power
The SKYA21004 is divided into two blocks as its operating
purpose. One is a LED Backlight Driving Boost Section and the
other is an LCD Bias Power Boost Section. To prevent interactive
noise between two individual power blocks (LCD Bias Power and
LED Driver), use independent planes for PGND (power ground for
LCD Bias Power) and WPGND (power ground for LED Driver).
Another way to plug thermal vias uses solder mask tenting on the
bottom of the copper plane. Solder mask tenting must completely
cover the vias.
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APPLICATION NOTE • SKYA21004 LAYOUT GUIDELINES
OUT
470 nF
0.1 μF
VIN
LCD Supply Input
0.22 μF
10 μF
8 nF
100 pF
COMP
19
20
FB
21
AGND
VL
IN
22
FB
24 SCL
23
SCL
25
DGND
26
OVP
OUT
BL_EN
28
27 OVP
WEN
WCOMP
18
17
DRVN
GND
FBN
FB
11 kΩ
14
5V
13 VDD
0.1 μF
1 μF
0.22 μF
0.1 μF
BL Supply Input
0.1 μF
00.22 μF
0.22 μF
D1
NC
2.2 μF
2.2 μF
301 kΩ
FBP
10 kΩ
37.4 kΩ
0.22 μF
OVP
NC
6.04 kΩ
OUT (up to 28 V)
1 MΩ
VGH
0.1 μF
4.7 μH
4.7 μF
226 kΩ
NC
15 EN_LCD
VDD
12
11
10
REF
GND
9
WLX
8
WLX
6
7
WPGND
WPGND
NC
2.2 μF 2.2 μF 2.2 μF 2.2 μF
16 FBP
DRVP
5
36
LX
PGND
EN
CS56
1
X
SKYA21004
CS34
PWM
LED3 35
4.7 μH
FBP
4
LED2 34
AVDD
200 kΩ
CS12
GND
22 kΩ
FOSC
PWM 3
LED1 33
SDA
ISET
32
SGND
31
2
34.8 kΩ
29
30 SDA
10 kΩ
0.22 μF
2.2 μF
VGL
45.3 kΩ
AVDD
VDD
Y2380
Figure 2. SKYA21004 LED Driver Boost Section
Layout of LED Driver Boost Section Procedure
1. Connect the inductor and diode as close to the WLX node as
possible.
2. Connect CIN capacitor close to the inductor and COUT capacitor(s)
close to the diode.
3. Connect the COUT ground return and IC WPGND with direct wide
and short trace. If needed, connect the ground return on
multiple layers with multiple vias connected.
4. Make the PCB traces between CIN and inductor, inductor and
WLX pin, WLX pin and diode, diode and COUT as wide and as
short as possible.
5. The trace should be wider than 1.5 mm.
6. Isolate the WPGND return from the AGND, DGND, SGND, and
GND. Connect the WPGND to the system ground near the
system input.
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3
APPLICATION NOTE • SKYA21004: PCB LAYOUT GUIDELINES
OUT
470 nF
0.1 μF
VIN
LCD Supply
pp y Input
p
0.22 μF
10 μF
8 nF
100 pF
COMP
19
20
FB
21
AGND
VL
IN
22
FB
24 SCL
23
SCL
25
DGND
27 OVP
BL_EN
28
26
OUT
18
PGND
17
DRVN
GND
11
FB
11 kΩ
14
5V
13 VDD
0.1 μF
1 μF
0.22 μF
0.1 μF
BL Supply Input
0.1 μF
0.22 μF
0.22 μF
NC
OUT (up to 28 V)
2.2 μF
2.2 μF
301 kΩ
FBP
10 kΩ
37.4 kΩ
0.22 μF
1 MΩ
NC
6.04 kΩ
D1
OVP
VGH
0.1 μF
4.7 μH
4.7 μF
226 kΩ
NC
N
15 EN_LCD
VDD
12
REF
FBN
10
GND
9
WLX
8
7
WLX
6
WPGND
5
WPGND
4
NC
2.2 μF 2.2 μF 2.2 μF 2.2 μF
16 FBP
DRVP
PWM
36
LX
EN
CS56
1
X
SKYA21004
CS34
GND
LED3 35
4.7 μH
FBP
2
LED2 34
2000 kΩ
CS12
PWM 3
22 kΩ
OVP
FOSC
AVDD
WEN
32
LED1 33
WCOMP
ISET
SDA
31
SGND
34.8 kΩ
29
30 SDA
10 kΩ
0.22 μF
2.2 μF
VGL
45.3 kΩ
AVDD
VDD
Y2381
Figure 3. SKYA21004 LCD Bias Power Boost Section and Charge Pump Section
Layout of LCD Driver Boost and Charge Pump Section
Procedure
1. Connect the inductor and diode as close to the LX node as
possible.
2. Connect CIN and COUT capacitor(s) as close to the IC as
possible.
3. Connect the COUT ground return and IC PGND as close as
possible.
4. Make the PCB traces between CIN and inductor, inductor and
LX pin, LX pin and diode, diode and COUT as wide and as
short as possible.
5. Trace should be wider than 1.5 mm. Connect all grounds of the
charge pump to PGND.
6. Isolate the PGND return from the AGND, DGND, SGND, and
GND.
7. Connect the PGND to the system ground near the system input.
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SDA
WCOMP
WEN
OVP
OUT
DGND
SCL
VL
IN
AGND
FB
COMP
30
29
28
27
26
25
24
23
22
21
20
19
APPLICATION NOTE • SKYA21004 LAYOUT GUIDELINES
ISET
31
18
FOSC
32
17
PGND
CS12
33
16
FBP
CS34
34
15
EN
CS56
35
14
DRVP
NC
36
13
VDD
1
2
3
4
5
6
7
8
9
10
11
12
SGND
GND
PWM
WPGND
WPGND
WLX
WLX
GND
REF
FBN
GND
DRVN
EP
LX
t0095
Figure 4. SKYA21004 Pinout
Figure 5. SKYA21004 Layout Example (Boost Section)
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APPLICATION NOTE • SKYA21004: PCB LAYOUT GUIDELINES
Guidelines of Analog and Feedback Section
isolated from the noise of the boost and charge pump section.
Grounds for the analog and feedback sections should be
connected to the plane of AGND, DGND, SGND, and GND.
The Analog and Feedback section is an important block for stable
system operation. For stable operation, these sections should be
OUT
470 nF
0.1 μF
VIN
LCD Supply Input
0.22 μF
10 μF
8 nF
100 pF
20
19
COMP
AGND
FB
21
22
IN
VL
23
FB
24 SCL
SCL
25
26
DGND
OVP
OUT
BL_EN
28
27 OVP
WEN
18
17
DRVN
GND
FBN
FB
11 kΩ
14
5V
13 VDD
0.1 μF
1 μF
0.22 μF
0.1 μF
BL Supply Input
0.1 μF
0.22 μF
0.22 μF
D1
2.2 μF
301 kΩ
FBP
NC
10 kΩ
37.4 kΩ
0.22 μF
OVP
NC
6.04 kΩ
OUT (up to 28 V)
1 MΩ
VGH
0.1 μF
4.7 μH
4.7 μF
226 kΩ
NC
15 EN_LCD
VDD
12
11
10
REF
GND
9
8
WLX
WLX
7
6
WPGND
WPGND
5
NC
2.2 μF 2.2 μF 2.2 μF 2.2 μF
16 FBP
DRVP
PWM
36
LX
PGND
EN
CS56
1
X
SKYA21004
CS34
4
LE
LED3 35
4.7 μH
FBP
GND
LE
LED2 34
AVDD
200 kΩ
CS12
2
22 kΩ
FOSC
PWM 3
LED1 33
LE
WCOMP
ISET
32
SDA
31
SGND
34.8 kΩ
29
30 SDA
10 kΩ
2.2 μF
0.22 μF
2.2 μF
VGL
45.3 kΩ
AVDD
VDD
Y2382
Figure 6. SKYA21004 Analog Section
Layout of Analog Section Procedure
Feedback Layout Design Considerations
1. Connect the resistors and capacitors for IN, OUT, VL, COMP,
WCOMP, ISET, FOSC, and OVP as close to the IC as possible.
 Feedback sensing points – All feedback points including FB,
FBP, FBN, and OVP should be sensed from the output capacitor
for stable and precise output feedback.
2. Connect to DGND ground plane for ground return.
3. Use the same ground plane for AGND, DGND, SGND, and GND.
 Routing of the feedback line – To avoid coupling effects,
sensitive lines should not be routed on top of the digital or
switching signal. Sensitive lines also should not be placed in
parallel with a digital or switching signal.
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APPLICATION NOTE • SKYA21004 LAYOUT GUIDELINES
OUT
470 nF
0.1 μF
VIN
LCD Supply Input
0.22 μF
10 μF
8 nF
100 pF
19
COMP
20
FB
21
AGND
VL
IN
22
FB
24 SCL
23
SCL
OUT
DGND
26
25
BL_EN
28
27 OVP
OVP
18
PGND
17
DRVN
FB
11 kΩ
14
5V
13 VDD
0.1 μF
1 μF
0.22 μF
0.1 μF
BL Supply Input
0.1 μF
0.22 μFF
0.22 μF
D1
NC
22.2 μF
2.2 μF
301 kΩ
FBP
10 kΩ
337.4 kΩ
0.22 μF
OVP
NC
6.04
0 kΩ
OUT (up too 28 V)
1 MΩ
VGH
0.1 μF
4.7 μH
4.7 μF
226 kΩ
NC
C
15 EN_LCD
VDD
12
GND
11
FBN
10
REF
GND
9
8
WLX
WPGND
WLX
7
6
WPGND
5
4
NC
2.2 μF 2.2 μF 2.2 μF 2.2 μF
16 FBP
DRVP
PWM
36
LX
EN
CS56
1
X
SKYA21004
CS34
GND
LED3 35
4.7 μH
FBP
PWM 3
LED2 34
200 kΩ
CS12
SGND
22 kΩ
AVDD
A
AV
DD
WEN
FOSC
LED1 33
WCOMP
ISET
32
SDA
31
2
34.8 kΩ
29
30 SDA
10 kΩ
0.22 μF
2.2 μF
VGL
45.3 kΩ
AVDD
VDD
Y2383
Figure 7. SKYA21004 Feedback Section
Layout of Feedback Section Procedure
1. Connect the OVP resistors to the OUT capacitors with a
dedicated ground shielded trace to avoid interference from
other signals. This trace is used as a feedback for the WLED
boost regulator.
3. To avoid coupling effects, sensitive lines should not be routed
on top of the digital or switching signal.
4. When connecting nodes from the other layer, use at least four
0.4 mm hole diameter, 0.7mm pad diameter vias (conductive
filled via is preferred).
2. Connect the AVDD/VGH/VGL feedback resistors to the OUT
capacitors with a dedicated ground shielded trace.
Figure 8. Example of Routing the Sensitive Line
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SDA
WCOMP
WEN
OVP
OUT
DGND
SCL
VL
IN
AGND
FB
COMP
30
29
28
27
26
25
24
23
22
21
20
19
APPLICATION NOTE • SKYA21004: PCB LAYOUT GUIDELINES
ISET
31
18
LX
FOSC
32
17
PGND
CS12
33
16
FBP
CS34
34
15
EN
CS56
35
14
DRVP
NC
36
13
VDD
1
2
3
4
5
6
7
8
9
10
11
12
SGND
GND
PWM
WPGND
WPGND
WLX
WLX
GND
REF
FBN
GND
DRVN
EP
t0095
Figure 9. SKA21004 Pinout
Figure 10. SKYA21004 Layout Example (Analog and Feedback Section)
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APPLICATION NOTE • SKYA21004 LAYOUT GUIDELINES
Copyright © 2015 Skyworks Solutions, Inc. All Rights Reserved.
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