BOSTON UNIVERSITY COLLEGE OF ENGINEERING
Department of Electrical and Computer Engineering
Syllabus: EC580 – Analog VLSI Circuit Design
Fall Semester 2014
Date/Time/Place: T/R, 4:00-6:00 PM, PHO205
Instructor: Prof. Ronald W. Knepper
Office Hours: Wed. 11AM-12PM, Fri. 3-5 PM, PHO526
e-mail: rknepper@bu.edu, Phone: 353-0223
Course Description:
This course will teach the fundamentals of CMOS and BICMOS analog circuit design techniques
used in today’s advanced mixed-signal integrated-circuit applications. Topics to be covered
include device/process background, IC passives, analog amplifiers, current mirrors, op-amp
design, noise fundamentals, RF design basics, switched capacitor circuits, comparators, A/D and
D/A converters, and other analog circuitry used in today's mixed-signal ICs. The course will
include a laboratory component involving hands-on measurements with high frequency
instruments in the RF Lab in PHO418 as well as the design, layout, and simulation of RF/analog
integrated circuits using IBM 8HP device models and Cadence SpectreRF CAD tools in the
VLSI Lab in PHO305. (4 credits)
Prerequisites: EC412 and/or EC571 (or instructor’s permission)
Texts: Carusone, Johns, and Martin, Analog Integrated Circuit Design, 2nd edition, Wiley, 2012.
T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edition,
Cambridge, 2004
References: 1. Gray, Hurst, Lewis, Meyer, Analysis and Design of Analog Integrated Circuits, 2009
2. Leblebici and Leblebici, Fundamentals of High-Frequency CMOS Analog Integrated
Circuits, Cambridge, 2009
3. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001
4. Allen and Holberg, CMOS Analog Circuit Design, Oxford Univ Press, 2012, 2002
Course Methodology:
The course involves the use of a coordinated set of lectures, labs, homework, and exams to
teach analog/RF/mixed-signal integrated circuit design based on today’s CMOS and BICMOS
technologies. The four simulation labs are designed to introduce the student to the Cadence
SpectreRF CAD design tools, starting with circuit simulation from the schematic, then
physical layout, design rule and logic-versus-schematic checking, and finally circuit
simulation using extracted models based on the layout. Tutorials will be utilized to help
students learn the use of Cadence SpectreRF. An experimental lab will be included using the
RF equipment in PHO418 to measure S-parameters and other RF characteristics of a high
frequency amplifier.
Grading:
Mid-term Exam
Labs
Homework
Final Project & Reading
25%
35%
10%
30%
Schedule of Lectures and Exams:
Dates
9/2
9/4
9/9
?
9/11
9/16
9/18
9/23
9/25
9/30
10/2
10/7
10/9
10/14
10/16
10/21
10/23
10/28
10/30
11/4
11/6
11/11
11/13
11/18
11/20
11/25
11/27
12/2
12/4
12/9
Topic Description
SiGe BICMOS Technology: fabrication, layout, design rules
Review MOS device physics and SiGe NPN device physics
Compact analog/RF circuit models for BICMOS devices
Cadence SpectreRF & 8HP Tutorial (6:20 PM in VLSI Lab)
Passive IC components: capacitor, resistor, inductor, transformer
Passive RLC Networks, Matching Networks
Matching Networks (continued)
Current mirrors and amplifier fundamentals
Frequency response of amplifier circuits
Feedback amplifiers
CMOS Op-amp design
CMOS Op-amp design (continued), Opamp compensation
Op-amp design (continued), Wide-swing current mirrors
No Class (Monday Schedule)
Distributed systems, transmission lines
Smith chart, S-parameters
Noise in Semiconductor Devices
Noise in Semiconductor Devices (cont) , review for Mid-Term
Mid-Term Exam
Go over exam, Estimating bandwidth, risetime, and delay
High frequency amplifier design (shunt peaking, shunt-series)
High freq amp design (tuned amplifiers, cascading)
Comparators
Sample and Hold circuits
Switched capacitor circuits
Data converter fundamentals
No Class (Thanksgiving Recess)
Analog-to-digital converters (ADC)
Analog-to-digital converters (continued)
Digital-to-analog converters (DAC)
Text/Reference
CJ&M Ch 2, 8HP Manual
Lee Ch 5 + RWK notes
Lee Ch 5, CJ&M Ch1 & 8
Cadence Manual
Lee Ch 4
Lee Ch 3
Lee Ch 3
CJ&M Ch 3
CJ&M Ch 4
CJ&M Ch 5
CJ&M Ch 6
CJ&M Ch 6
CJ&M Ch 6
Lee Ch 6
Lee Ch 7
Lee Ch 11
Lee Ch 11
Lee Ch 8
Lee Ch 9
Lee Ch 9
CJ&M Ch 10
CJ&M Ch 11
CJ&M Ch 14
CJ&M Ch 15
CJ&M Ch 17
CJ&M Ch 17
CJ&M Ch 16
Schedule for Labs:
Lab
1a
1b
2
3
4
Assigned
9/9
9/9
10/7
10/21
11/11
Due
9/23
10/7
10/28
11/13
12/2
Project Final Project: Design of an A/D Converter
11/25
12/16
Schedule for Homework:
Assigned
9/2
9/18
9/30
11/6
Due
9/11
10/2
10/17
11/21
11/18
12/9
HW
1
2
3
4
Description
CMOS & NPN Bipolar Device Characteristics (schematic): dc, small-signal ac, fT
CMOS & NPN Bipolar Device Characteristics (layout): dc, small-signal ac, fT
Analog Design: Current Mirror Op-amps in CMOS and BiCMOS
Experimental Lab: S-parameter Measurements of cable, load, & MMIC amplifier
RF Design: High Frequency Amplifier (matching, tuning, S-parameters)
CMOS and Bipolar Devices and Small Signal Models
IC Passives, Matching Networks
Current Mirrors, Operational Amplifier Design
Noise, Estimating Bandwidth, High Freq Amplifiers
Reading Final Reading and Report from IEEE JSSC Literature
Course Policies:
1. Missed Exam – Absence from an exam can be excused only for reasons of illness,
death in a family, or unavoidable travel. In each case, permission of the instructor in
advance is required, as well as a written authorization by a physician (in the case of
illness) or other appropriate authorized signature. The student will be required to take
a makeup exam.
2. Late Homework – Late homework will be accepted up until the date solutions are
made available. A penalty of 5% off per day will be applied. A weekend counts as a
single day.
3. Late Labs – Late labs will be accepted, but with a penalty applied of 5% off per day up
to a maximum of 50% off. It is advantageous for students to complete all the labs.
4. Attendance – Attendance in class is considered essential and required.