M.TECH DEGREE EXAMINATION
Model Question paper
Branch: Electronics and Communication Engineering
Specialization: Advanced Electronics & Communication Engineering
First Semester
MECEC 104 DESIGN OF CMOS VLSI CIRCUITS
(Regular – 2013 Admission Onwards)
Answer all Questions .All questions carry equal marks Time 3hrs Max Marks:100 1.(a) Derive Graphically the dc response of a CMOS inverter.
[10 marks
b) Derive the expressions for propagation delay times of a CMOS inverter using
Capacitance state equation method
[10 marks
(c) A CMOS inverter is built in a process where k’n=100μA/V2, Vtn=+0.7V,
k'p =42 μA/V2 , Vtp=-0.8V, and a power supply of VDD =3.33V is used for its operation
.Find mid point voltage VM if (W/L)n =10 and (W/L)p= 14.
[5 marks
OR
2) .(a) Explain the operation of
BiCMOS inverter? Clearly specify its characteristics.
[8 marks
(b) Explain with neat diagrams ,how the BiCMOS inverter performance can be
improved.
[7 marks
(c) Derive an equation for Ids of an n-channel enhancement MOSFET operating in
saturation region.
[7 marks
(d) Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10; μnCox =
92μA/V2.
[3 marks
3) (a) What is meant by a stick diagram? Draw the stick diagram and layout for a CMOS
inverter.
[10 marks
(b) What are the effects of scaling on Vt ?
[5 marks
(c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing.
[10 marks
OR
4) (a) Draw the following transistors using lambda based design rules
i. NMOS enhancement
ii. NMOS depletion
iii. PMOS enhancement.
[15 marks
(b) Discuss the design rules for wires (both NMOS and CMOS) using lambda based
design rules.
[10 marks
5) (a) Explain the concept of sheet resistance and apply it to compute the ON resistance (VDD to GND) of an NMOS inverter having pull up to pull down ratio of 4:1, If n
channel resistance is Rsn = 104 per square.
[10 marks
(b) Calculate the gate capacitance value of 5μm technology minimum size transistor
with gate to channel capacitance value is 4 × 10−4pF/μm2.
[5 marks]
c) Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit.
[10 marks
OR
6) i) Draw the structure, explain the function and write the applications characteristics of
the following programmable CMOS devices:
[15 marks]
(a) PLA
(b) PAL
(c) FPGA
(d) CPLD.
(ii) Sketch a diagram for two input XOR using PLA and explain its operation with the
help of truth table.
[10 marks]
7.(a) Explain how function of system can be tested.
[9 marks
(b) Explain any one of the method of testing bridge faults.
[8 marks
(c) What type of faults can be reduced by improving layout design?
[8 marks
OR
8).Explain the following with respect to CMOS testing:
(a) ATPG
[8 marks
(b) Fault simulation
[7 marks
(c) Statistical Fault Analysis
[5 marks
(d) Fault Sampling
[5 marks