ELEC301:
Chapter 01:
Introduction to CMOS
VLSI design
Professor Amine Bermak
E-mail:eebermak@ee.ust.hk
Hong Kong University of Science and Technology
Electrical and Electronic Department
(*) The historical development part is based on transparencies by C. Terman at MIT
ELEC301: CMOS VLSI Design
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Outline
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Motivation
Historical development of VLSI design
VLSI design approach.
Design flow.
Circuit and system representation.
Standard Cell versus Full Custom
Hierarchical design
First steps into the CMOS layout
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Why VLSI Design
• Building complex electronic circuits integrated
into a single IC chip.
– Using discrete components is difficult and costly.
• Integrated circuits solved much of the
problems
– Print many small devices on a flat surface.
• VLSI is a relatively new field
– Started early 60’s
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Historical developments
(1.)
(2.)
(3.)
• (1): In 1951, Shockley developped junction transistor.
• In 1954, TI made the first silicon transistor (2.5$).
• (2): In 1961, TI and Fairchild introduced the first claimed
IC chip integrating a dual FF with 4 transistors.
• (3): The first semi custom (Trs organized column wise) chip
marketed by Fairchild in 1967 containing 150 logic
• In 1968, Moore and Noyce left Fairchild to found Intel. No
business plan, only promise to specialize in memory chips.
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Historical development
(4.)
(5.)
(6.)
• (4): The first memory chip marketed by Intel in 1970:
The 1103 IC contained 1K RAM.
• (5): In 1971 Intel introduced the first Microprocessor
designed by Ted Hoff. The 4004 had 2300 tr built in a
10μm process and operates with 4-bit precision at 108KHz.
• (6): An example of nowadays ICs. The circuit is a Video
Codec chip from Lucent Tech, it’s a SOC containing onchip Memory, I/O Video, Host Interface, RISC, SIMD, etc..
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Moore’s Law
• Resolution of the fab process has improved exponentially
– Feature size has been reduced by 0.7 times every 3 years.
– Gordon Moore from Intel predicted in early 80’s that this growth
will continue.
• Cost of the fabrication process has grown modestly
• Cost/function has therefore dropped exponentially.
– At each new generation (3 years) the cost per function is half.
– Cost of manufacturing IC has remain cst but design cost has not.
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Moore’s Law
• Let’s take an example of 0.25μm
technology (late 90’s)
– 18mm on each side, total of 324mm2.
– 0.25 μm is the gate length
– 1 μm wire pitch (18,000 wire pitches)
and 4-5 level metal
• The number of ‘grids’ per chip is
x4 every 3 years
– More functionalities per chip
– More difficult to design
– How to ensure it works?
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Spectacular technological Dev.?
• Many disciplines have contributed to this
spectacular technological development:
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Solid State devices,
Lithography and fab
modeling,
CAD Tools,
- Circuit design and Layout
- Architecture and Algorithms
• EESM301 will focus on some topics:
– Modeling of FET, Digital circuit design and layout,
– CAD Tools (Full-custom and PR tools).
• Other topics will be studied in other courses:
– Analog IC, Semiconductor devices, Digital System
design etc…
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Difficulties in CMOS VLSI Design
• IC design is hard because designers must juggle several different
problems:
• Advanced technologies: More complex chip/ more functionality per
chip
• Multiple levels of abstraction:
• IC designs requires refining an idea through many levels of
detail, specification --> architecture --> logic design --> layout.
• Multiple Conflicting costs:
• Conflicting criteria: speed, area and power.
• Design decisions: improve one at the expense of the other.
• Design is dominated by process of balancing conflicting
constraints.
• Short design times:
• Time is money applies as well for ASIC design companies
• Chips that appear too late may make little or no money because
of competitors.
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ELEC301: CMOS VLSI Design
Manage complexity: Hierarchical and Abstraction
• Two techniques used by designers to eliminate unnecessary details:
• Hierarchical design:
• Divide and conquer: complexity is reduced by recursively
breaking it down into manageable parts.
• Each level of the hierarchy adds complexity by adding
components. Commonly used in programming.
• Design abstraction:
• Complexity is reduced by successively replacing detail with
simplifications at higher levels of abstraction.
• Manage Complexity by the process of:
• Simplify, Abstract, Constrain
• Understand underlying technology
• Determine abstraction and constraints needed
• Determine efficient solutions (in terms of design time, area,
power etc..)
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Hierarchical Design
• Hierarchy involves dividing a module into sub-modules.
• The operation is repeated on the sub-modules until the complexity of
the sub-modules is at an appropriately comprehensible level of
details.
Hierarchy level
cell A
cell D
Level 0
cell B
cell B
cell E
cell C
cell D
cell C
cell E
Level 1
Level 2
cell A
cell1
cell1
• Due to the hierarchy property, when a
cell is modified, all other links are
changed simultaneously.
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ELEC301: CMOS VLSI Design
cell1
cell1
Design Abstraction
• Rather than worrying about precise voltage levels, precise
transistors models, etc…several levels abstractions and
simplifications are introduced:
– Digital Abstraction: Signals are 1 or 0
– Switch Abstraction: MOSFETs are simple switches
– Gate Abstraction: unidirectional element, separable timing.
• Several design levels are introduced in order to simplify
the design process:
– Specification, Architecture, Logic, circuit, device, layout
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Circuit and System representations
Executable
Program, VHDL
Sequential
Machines
Specification
Behavioral Domain
Behavior
Behavioral Domain
Register-transfer
Behavioral Domain
Logic
Gates
Logic
Structural Domain
Transistors
Circuit
Structural Domain
Rectangles
Layout
Physical Domain
Functionality
• Top-Down design methodology: Before drawing the layout (last step) you need to
check the functionality, logic and transistor level description
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ELEC301: CMOS VLSI Design
Circuit and System representations
•Three design domains:
• Behavioral: Specifies what a particular system does
(functionality)
• Structural: Specifies how entities are connected together.
(Block diagram)
• Physical: Specifies how actually build a structure that has the
required connectivity to implement the prescribed behavior.
•Within each domain, there are many levels of abstraction.
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Behavioral representation
• Behavioral:
• Algorithm written in C, behavioral VHDL or behavioral Verilog,
e.g., module Adder ;
•input [0:3]A;
•input [0:3]B;
•output [0:3]Out;
•begin
•OUT=A+B
• end
• Functional simulations would be run to verify the behavior and
compliance with the specification.
• Levels of abstraction include
• Algorithmic (HDLs)
• Register-level transfer: description of specific hardware registers
and the communication between them.
• Boolean equations.
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Structural representation (1)
• Simple behavioral description: x = y + z.
• Structural:
• Structural description of a 1-bit adder:
•Structural Verilog description
•S = A.. + ..C + . .B + A.B.C
•module adder (input[0:3],s,co);
•CO = A.B + A.C + B.C
•iutput input[0:3];
•output s3
•and a1 (input[0], input[1], input2], s1);
•…..
•or a1 (output[0], input[1], input[2], s2);
•…...
•or o1 (s1, s2,s3);
•endmodule;
• Conversion from behavioral to structural domain may be automatic or
manual.
• Simulation would be run to verify compliance with the behavioral
specification.
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Structural representation (2)
• Structural (cont):
• Levels of abstraction include:
•Module level: e.g., cascading of 1-bit adders to form a 4-bit adder.
•Gate level: (see above)
•Switch level: technology dependent since transistor structure is specified.
•Circuit level: SPICE language allows timing behavior to be assessed, e.g.,
• Mname D G S B type-model Length Width AD PD AS PS
•M1 105 107 108 1 pfet L=2.0U W=4.0U
•R5 102 109 139.0
•R6 104 110 195.5
•M2 0 109 110 0 nfet L=2.0U W=4.0U
•R7 104 111 195.5
•R8 106 112 139.0
•M3 111 112 0 0 nfet L=2.0U W=4.0U
•C0 104 0 .01P
•C1 100 0 11F
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Physical representation
• Physical:
• Conversion from structural domain to the physical domain may be
automatic or manual (e.g., using MAGIC).
• ‘and’, ‘or’, ‘not’, etc. gates can be mapped to standard cells.
• Automatic place and route algorithms can be used to construct the
layout from the structural description.
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Physical structure of an IC
• Sandwich of materials:
– Transistors fabricated on silicon substrate.
– Wires on layers of metal separated by insulators.
– The wires connect to transistors.
• Each technology presents a set of design rules.
• Layout is a set of drawings, each layer represented
by a unique color.
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Layout Example
• An Example of a vision sensor designed by A. Bermak including onchip image processing. The chip occupies 15mm2 in 0.35 μm process.
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Layout example
VDD
VDD
A
A
Out
Out
GND
•Layout of a CMOS Inverter
ELEC301: CMOS VLSI Design
Schematic
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Stick Diagram and wiring layers
• Simplified version of the layout
– Abstract view of the layout: wires are just lines and no design rules
are respected.
– Good starting point for the layout
• Wiring layers (different materials) are represented in
different colors:
– Wires on the same layer always connect if they touch.
– Need contacts to connect wires on different layers
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Basic Component of CMOS circuit: Transistor
• Formed when polysilicon [red] crosses a diffusion (n or p
type) [green or yellow]
• The transistor is three terminals device (Drain (D), source
(S), and gate (G))
G
• The current will flow between the drain and source
S
depending on the gate voltage and drain-to-source voltage.
• Two type of transistors: PMOS and NMOS
• NMOS is on when the gate-to-source voltage is larger than a
threshold voltage (Vtn)
• PMOS is on when the gate-to-source voltage is smaller than
a threshold voltage (Vtp)
ELEC301: CMOS VLSI Design
D
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Transistor as a switch
• Treat the transistor as a voltage control on/off
switch
• Structure defines logic functions
– OR constructed using parallel switches
– AND constructed using serial switches
– More complex logical functions can be built.
ON
OFF
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CMOS design: the tools
• Goal
– reduce the design time
• The tools
– Cadence, Synopsys
– Mentor Graphics ,
– Hspice, eldo, spectre, etc.
• Why software are always updated and modified ?
– To cope with new design flow/methodology for new type of
design philosophy for ever-increasing complexity of the chips
– To cope with increasing complexity of analog circuits.
– To satisfy the requirements of a mixed analog-digital design
and mixed mode design methodologies such as Fullcustom;Std cell.
– To cope with advanced new technologies.
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Computer Aided Design (CAD) Tools
• Synthesis tools to synthesis complex circuit from a behavior
description.
• Standard Cell place and route for fast digital semi-customer
design.
• Symbolic layout tools to ease the task of physical design,
mask verification (DRC) to ensure manufacturability.
• Circuit analysis programs predict circuit all the process
corners. Gate level and behavioral simulators help to get it
right the first time.
• Tools to do the repetitive work such as routing or verifying
that the layout and schematic match (LVS).
• The design is usually carried-out following a design flow.
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Different CMOS Design Styles
• SOC (System-on-chip) Design
– Many different views
– SOC is a system in an IC that integrates software and hardware
Intellectual Property (IP) using more than one design
methodology to define/design the functionality and behavior.
• Application-specific IC
– Usually semi-custom design using a lot of automated tools
(automatic synthesis)
• Full custom IC
– High-performance oriented
– Analog or mixed signal
• This course will mainly focus on full-custom design first
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CMOS VLSI Integration Approach: Design Flow
For physical-level design
Specification
Choice of a technology (Bipolar, CMOS, BiCMOS)
Simulation parameters (Simplified equations)
Libraries
Schematic
(Standard Cell)
Simulation.
Physical Layout design. (or/and PR)
Layout Versus Schematics
Simulation of layout.
ELEC301: CMOS VLSI Design
Fabrication.
Test.
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Technological choice
CMOS
•
•
•
•
Higher input impedance
Low power consumption
VLSI and ULSI
Very suitable for digital
circuits
ELEC301: CMOS VLSI Design
Bipolair
•
•
•
•
Better conductance
Higher dynamic
Low offset
Fast
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Post-Layout simulation
Extracted netlist
SPICE3 file created from inverter.ext
• m0 Vdd in out Vdd pfet w=4.8u
l=1.2u
• + ad=14.4p pd=15.6u as=14.4p
ps=15.6u
• m1 out in GND Gnd nfet w=1.8u
l=1.2u
• + ad=6.84p pd=10.8u as=6.84p
ps=10.8u
• C0 Vdd GND 2.3fF
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Simulation
DC Sweep
Verify:
Transfer Voltage Curve
.dc vin 0 5 0.01
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AC simulation
Verify:
Frequency response
.ac dec 10 10
1000M
Transient Analysis
Verify:
Functionality and Timing
.trans 0.01n 4n
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Type of Integration
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Type of integration
• Possibility of automatic
placement and routing
• Need large variety of cells
• Short design time
• Security of the results
• Economical
ELEC301: CMOS VLSI Design
Full Custom
Standard Cell
- For digital-circuit designs, many basic logic gates are used repeatedly.
Thus, to save time, the designers build up a library of logic gates, and
they utilize the logic gate layouts repeatedly. The layouts of the logic
gates inside a design library are called standard cells. -Placement and
routing strategy is then used.
- The standard cells are not optimized since they are realized in order
“to fit” the max of digital application. In order to improve the
performance for a given application, a full-custom approach is preferred
• Possible optimization and
hence more performance
• Total conception
• Time consumming
• Less secure results.
• Costly
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Standard Cell design
•Placement involves finding the most suitable arrangement in the 2D plane
for the cells in the design.
•Routing solves the non-planar interconnection problem created by the
placement.
•From layout, actual transistor sizes and capacitance may be calculated.
Simulations may again be run to confirm behavior at required speed and
estimate power dissipation.
•For each standard cell, the cell height is the same, and this can provide
direct connections for VDD and GND.
VDD
nor2
nor2
inv inv
nor2
reg
nand2
inv
Routing
Channels
nand2
mux
mux
GND
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Full-Custom Layout
NMOS transistor
metal1
poly active
nselect
G
D
S
S
B
D
B
G
pselect
contact
PMOS transistor
metal1 poly active
G
D
S
S
D
B
nselect
G
contact
nwell
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background
pselect
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Background
(p-substrate)
nwell
active
(NMOS)
active
(PMOS)
ohmic
contact
(p-substrate)
ohmic
contact
(nwell)
Step 1: The background is the
p-substrate
Step 2: Draw the N-well
Step 3: Draw the active areas
of PMOS and NMOS
Step 4: Draw the active areas for
the ohmic contact for Nwell and
P-Substrate
Step 5: Draw the nselect to define
the active areas as n-doped regions
nselect
Step 6: Draw the pselect to define
the active areas as p-doped
regions
pselect
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Step 7: Draw the poly for the gates
of the NMOS and PMOS transistors
poly
Step 8: Draw the contact to connect
the doped regions and poly to metal1
contact
Step 9: Draw metal1 for
interconnections
metal1
Interconnections
metal3
B
D
p+
n+
G
S
D
n+
p+
G
S
B
via2
metal2
via
metal1
p+
n+
n-well
contact
p-substrate
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What are we going to
learn in ELEC301??
Technological choice
CMOS Technology
CMOS design tool
CADENCE
Type of integration
Full-Custom
Level of abstraction
Specification, architecture,
logic design, layout design
Hierarchical design
Will be used in the project
Challenges
ELEC301: CMOS VLSI Design
Conflicting objectives,
Short design time
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