Dottorato di Ricerca in Ingegneria Elettronica Informatica e delle
Telecomunicazioni
Short course on
“RF electronics for wireless communication
and remote sensing systems”
Reconfigurable VCOs and Synthesizers
Eleonora Franchi, Antonio Gnudi, Marco Guermandi
DEIS-ARCES - University of Bologna
Viale Risorgimento 2, Bologna, Italy
Outline
• Motivations
• High-tuning range VCO
• Synthesizer for reconfigurable transceivers
• Measurement results
• Conclusions
1
Motivations
Frequency synthesis for multi-standard transceivers
requires:
¾ wide frequency range
¾ versatility in channel spacing
¾ high switching speed
… all this with low phase-noise and low cost !
Available solutions
¾ wide frequency range
• VCO + dividers when possible (multiband)
• switched tanks (L or C) or switched VCOs
• technology boosters (bond-wire inductances or
high CMAX / CMIN ratio capacitors)
• VCOs + mixers for frequency shift (UWB)
¾ versatility in channel spacing & switching speed
• fractional-N PLL
• reconfigurable loop-filter
2
Investigated solutions
¾ wide frequency range
• high-tuning range single-LC VCO
• designed for 0.9-2.4 GHz continuous tuning
¾ versatility in channel spacing & switching speed
• fractional-N PLL with linearization and spurs
cancellation techniques to break the bandwidth
trade-off
Main concept of high-tuning range VCO
α
γ
0.5
0.33
0.2
0.11
3
2
3/2
5/4
1+α
γ
= 1−α
3
Problems with the previous concept
γ = 2 (1 FF), α = 0.33 … too much
for a common LC VCO
• For
• For α = 0.2 (achievable for LC VCO),
γ = 3/2, but what about the duty cycle?
α
γ
0.5
3
0.33
2
0.2
3/2
0.11
5/4
Fvco
Ideal Fvco/(3/2) with
50% duty-cycle
Realistic Fvco/(3/2) with
duty-cycle not good for mixer
More problems
• For I/Q mo-demodulation, both in-phase and inquadrature LO signals are required
• A multiplexer is necessary for the selection of
the output frequency sub-band
A more effective solution is required !!
4
High-tuning range VCO: architecture
0.83-2.5 GHz
2.5-3.75 GHz
(±20%)
High-tuning range VCO: configuration A
0.83-1.25 GHz
2/3 Fvco
Fvco
1/3 Fvco
1/3 Fvco
5
High-tuning range VCO: configuration B
1.25-1.87 GHz
Fvco
Fvco
1/2 Fvco
DC
High-tuning range VCO: configuration C
1.67-2.5 GHz
4/3 Fvco
Fvco
1/3 Fvco
2/3 Fvco
6
Schematic of the core LC-QVCO
ILO
• 5-bit capacitor
array for coarse
tuning
• amplitude control
The quadrature is obtained by two Injection-Locked
Oscillators (ILO) coupled by second harmonic
Some theoretical results on the QVCO
Stability of the solutions:
“low swing” regime:
Is1 Is2 in-phase
Vd1 Vd2 in-phase
“high swing” regime:
Is1 Is2 opp.-in-phase
Vd1 Vd2 in-quadrature
Quadrature oscillation is stable in the “high-swing”
regime, that is also beneficial for low phase noise
7
QVCO explanation (1)
Stable solution
QVCO explanation (2)
Stable solutions: depending on
Is0 two possible regimes
VS and IS opposite in phase:
Quadrature obtained
8
More theoretical results on the QVCO
Phase-noise analysis
QVCO
Single stage ILO
R 1 ω0 r
θ n1 =
⋅ ⋅
⋅ inQ
Vdm Q j 2ωn
r
r
θ n1 =
ω r
R 1
⋅
⋅ 0 ⋅ inQ
Vdm 2Q j 2ωn
The QVCO and the single stage ILO have
the same phase-noise x current product
More theoretical results on the QVCO
Sensitivity to tank mismatches
err =
3Q  I s 0 1   ω01 − ω02 

⋅
+ ⋅
4  I sm 3   ω0 
The quadrature error is proportional to the ratio
of the bias current over the coupling current
and to the quality factor Q
In the proposed scheme the output I/Q signals
are generated by the DIV2
an extremely low
I/Q error is NOT required from the QVCO
9
High tuning VCO: circuit design style
• SCL logic for low
sensitivity to parameter
variations (differential
style)
• Adjustable bias current
across the different
sub-bands
• Differential Gilbert cells
for the SSB mixer.
D-latch used in the MS-FF DIV2
Feedback path: DIV2 and MUX
DIV2
Constant output
Buffer
10
Schematic of the SSB mixer
compensation for
50% duty-cycle
Effect of the duty-cycle compensation
Mixer outputs from
simulations:
w/o compensation
with compensation
11
Chip micrograph
STM 0.13 µm CMOS technology
Summary of measured
high-tuning range VCO performance
Configuration
A (1/3)
B (1/2)
C (2/3)
Freq. range (GHz)
0.83 /1.25
1.25 /1.87
1.67 / 2.5
PN @ 1MHz (dBc/Hz) -130 / -126 -127.5 / -122.5 -126.5 / -120
LC-QVCO curr. (mA) 22.1 / 12.25 22.1 / 12.25
22.1 / 12.25
Reconf. curr. (mA)
Total current (mA)
Quadrature accuracy
9.5
31.5 / 21.7
< 2°
5.3
27.5 / 17.6
< 1°
8
30.1 / 20.2
< 1°
12
Phase-noise measurements
C (2 GHz)
A (1 GHz)
Meas. 0-3 GHz spectrum: configuration A
13
Meas. 0-3 GHz spectrum: configuration B
Meas. 0-3 GHz spectrum: configuration C
14
Possible origin of the subharmonic
spur in configuration C
At the mixer output:
fund. @ 4/3 Fvco + tone @ Fvco (1/3 Fvco offset)
At the divider output:
fund. @ 2/3 Fvco + tone @ 1/3 Fvco (same offset)
Below -35 dBc in worst case over full frequency range
Synthesizer for reconfigurable
transceivers
The classical integer-N architecture …
high-tuning
range VCO
… is not adequate for channel spacing and
switching speed
15
Σ∆ fractional-N synthesizer
N/N+1
high-tuning
range VCO
b(t) = …001110101…
Fractional-N obtained by varying the division ratio
with a proper control sequence (α = <b(t)>):
Fout = Fref x (N+α)
Why fractional synthesis?
• Easier trade off between reference frequency,
loop bandwidth and output frequency resolution.
– The reference frequency can be higher than
channel spacing ⇒ Increase of the loop
bandwidth.
• Fine frequency step.
– The frequency resolution can be much smaller
than the reference (varying α=<b(t)> in very
fine steps)
• Multistandard receivers.
– Reference frequency is independent on
channel spacing
16
First order Σ∆
• Assuming a constant input:
– The output mean is equal to the input
– The quantization noise is high-pass shaped
(see explanation on next slide)
Noise shaping in first order Σ∆
General Σ∆ modulator
Linear model with
injected quantization
noise
N TF ( z ) =
Y ( z)
1
=
E ( z) 1 + H ( z)
N TF ( f ) = 2 sin
πf
fs
First order: H ( z ) =
1
z −1
High-pass noise-shaping
17
Σ∆ of higher order and different type
• Order = number of integrators (accumulators)
• Higher order ⇒ Stronger noise shaping,
Lower Spurs
• Feedback type (single loop): critical stability.
• MASH (Multi Stage noise Shaping):
ƒ Cascade of 1st and/or 2nd order Σ∆.
ƒ Always stable.
ƒ Multibit output.
Σ∆ Noise
18
Problems in fractional synthesis
• PLL bandwidth still limited by Σ∆ quantization
noise.
• High sensitivity to PFD-CP linearity (in band
noise leakage).
• Actually sequences generated by Σ∆ are
periodic: fractional spurs.
Spur compensation concept (1)
current injection related to the phase
error at the input of the PFD,
calculated by the control logic as
 K − M x ( n) 
∆φ (n)= ∆φ (n − 1) + 2π 

 M N+K 
M = 2nbit
x(n) = output
sequence
19
Spur compensation concept (2)
5+1 bits
Quantization noise
shaping also in the DAC
current injection
Multi-modulus divider
Standard CMOS logic
(low-frequency part)
SCL logic prescaler
20
Linearization techniques…
Typical linearity
problems of the
PFD-CP
P-N
mismatch
dead-zone
gain
enhancement
dead-zone
suppression
… in the PFD
buffers to
equalize
loads
Linearization techniques … in the CP
Vbias = low-pass
filtered version of Vout
Matching:
size and bias
21
Alternative linearization technique:
pulse injection
Fixed number
of VCO cycles
In lock conditions the sunk current pulse
forces the PFD-CP to work in the linear part of
its characteristic.
Circuit implementation
• integrated in 0.13 µm CMOS STM technology …
• … with the exception of the Σ∆ modulator, the
control logic block of the compensation scheme and
the largest capacitance of the loop filter
• Σ∆ sequences are computed off-line and passed to
the chip by a pattern generator
• 70 MHz differential mode clock internally divided by
two (35 MHz Fref )
• total area 1.8 x 2.0 mm2
22
Measured settling time
• 75 KHz measured 3-dB closed-loop bandwidth
• 105 µs settling time
Measured phase-noise plus spurs
Conf. C
2.4 GHz
output
same integer
ratio +
fractional
w/o comp.
2 dB decrease @ 10 MHz when
compensation ON (not shown)
integer
division ratio
23
The amount of spur reduction
depends on loop bandwidth
700 kHz BW
200 kHz BW
curve A: integer N
From former STM designs
curve B: same N + fractional
curve C: same N + fractional + spur compensation
Effect of linearization techniques
15 dB
15 dB reduction of the in-band fractional spur
when linearization is turned ON in the PFD-CP
24
Summary of measured performance
Frequency (MHz)
863-2403
3-dB closed loop bandwidth (KHz)
75
Linear settling time (µs)
105
Output frequency resolution (Hz)
11 (A), 16 (B), 22 (C)
In band fractional spur (dBc)
-60
PN @ 1 MHz offset (dBc/Hz)
-126 (A), -120 (B), -114.5 (C)
Power consumption (mW)
88
Conclusions
• integrated fractional synthesizer with
continuous output frequency in the 0.9-2.4 GHz
band
• it combines high-tuning range with high
frequency resolution
• high-tuning range achieved thanks to a suitable
VCO scheme
• spurs compensation + linearization techniques
adopted in the synthesizer
25