IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 9, SEPTEMBER 1999
1369
Short Papers
Highly Accurate and Simple Models
for CML and ECL Gates
M. Alioto and G. Palumbo
Abstract—In this paper simple and accurate models for the propagation
delay of both current mode logic (CML) and emitter-coupled logic (ECL)
gates are proposed. The models start from the small signal model properly
evaluated. This makes it possible to represent propagation delay with
a few terms, providing a better insight into the relationship between
delay and its electrical parameters, which in turn are related to process
parameters. The main difference between accurate and simple models
is that the former need few Spice simulations to properly evaluate the
model parameters.
In order to validate the models, a comparison using both a traditional
and a high-speed bipolar process was carried out under many bias
conditions and output loads. Simple models have typical errors of around
20%. Accurate models have typical errors as low as 2% and 5% for CML
and ECL, respectively, while the worst case error is as low as 5% and
8% for CML and ECL, respectively.
Index Terms— Bipolar digital integrated circuits, bipolar transistor
circuits, circuit modeling, current mode logic, delay estimation, digital circuits, emitter-coupled logic (ECL), high-speed integrated circuits,
integrated circuit modeling.
I. INTRODUCTION
Various different approaches have been proposed in the literature
to determine the delay expression of current mode logic (CML)
and emitter-coupled logic (ECL) circuits. A first one represents
propagation as a linear combination of circuit time constants, properly
weighted with factors determined by sensitivity analysis [1]–[3]. A
drawback in this approach is that propagation delay is expressed as
the sum of N 3 M terms where N and M are half the resistances
and capacitors of the logic gate, respectively (the number is half due
to the symmetry of the circuits). A more accurate model adds further
terms. Thus, the propagation delay of the inverter CML (the simplest
one) has 25 or 26 terms (N = 5 and M = 5). It is clear that a
model with a high number of terms is not useful to really understand
the behavior of the gate and for an initial paper-and-pencil design. A
second drawback is due to the high number of simulations required
by the sensitivity analysis, which is equal to 4 3 N 3 M (100 for a
CML gate). Finally, according to our experience and that of other
authors, this approach is not independent of process parameters; time
constant factors have to be evaluated each time we change technology
(all papers have, in fact, different coefficients). A simplification in the
number of terms resulting from this approach is given in [4], but it
is not significant and must be performed after simulation.
Another approach is based on linearization of the device models
[5]–[7]. Reference [5] gives a delay whose terms have different
expressions which depend on not simple conditions, and, hence, is
difficult to use in a pencil and paper design. In [6] and [7] the
propagation delay of the gate is proportional to the sum of time
constants (as assumed in the sensitivity analysis). This procedure is
Manuscript received December 12, 1997; revised July 10, 1998. This paper
was recommended by Associate Editor Z. Yu.
The authors are with Dipartimento Elettrico Elettronico e Sistemistico
(DEES), Universitá Di Catania, Viale Andrea Doria 6, I-95125 Catania, Italy.
Publisher Item Identifier S 0278-0070(99)06626-9.
easy and fast, and makes it possible to have a good insight into
the behavior of the circuit. Nevertheless, the errors of the linearized
model are too high to implement an accurate CML simulator model.
Moreover, [6] uses the average branch current analysis to evaluate
the delay of ECL gates, and [7] refers only to CML gates.
The average branch current was introduced in [8] and [9]. Following this procedure, differential equations are solved by approximating
currents with their mean value. Although the approach leads to a
simple expression for the emitter follower propagation delay, it does
not take into account the dependence of delay on the bias current.
Other methods have also been presented but they are more complex
than the other ones and less useful for design targets [10].
In this paper we give new models of delay in CML and ECL
which are accurate and simple. The models start from the small signal
model properly evaluated. The high-speed feature of CML and ECL
is due to the emitter-coupled pair working in an almost linear region.
This makes it possible to represent propagation delay with very
few terms, providing a better insight into the relationship between
delay and its electrical parameters, which in turn are related to
process parameters. The accuracy of the model is further improved by
introducing coefficients which minimize the error between analytical
and simulated results. Unlike traditional sensitivity analysis, our
approach only needs a few Spice simulations (five for the CML gate
and ten for the ECL gate).
In order to validate the models, a comparison using both a
traditional and a high-speed bipolar process was carried out under
many bias conditions and output loads. For both processes we found
typical errors of accurate model as low as 2% and 5% for CML and
ECL, respectively, while the worst case error is as low as 5% and
8% for CML and ECL, respectively.
II. CML PROPAGATION DELAY
A. Simplified CML Model
A CML gate is shown in Fig. 1(a). In order to achieve highspeed performance its transistors work in a linear region and can
be represented with a linearized model which is topologically equal
to the Spice small signal model. Moreover, since the circuit is
symmetrical and differential operations are assumed, we can limit our
analysis to the half circuit model in Fig. 1(b). The transconductance
gm and input resistance r are those of the small signal model
ISS =2VT and 2F VT =ISS , respectively, and the resistances rb ,
re , and rc , are resistive parasitics. On the other hand, unlike the
traditional small signal model, we have to properly evaluate the
capacitances as shown in [11], since voltages move rapidly over a
wide range. More specifically, the diffusion capacitance is CD =
2F =RC , where F is the transistor transit time [1]. The junction
capacitances Cj are that in a zero-bias condition Cjo multiplied by
a coefficient Kj evaluated as shown in [11]
Kj
=
m
V 2 0 V1
(
0 V1 )10m 0 ( 0 V2 )10m
10m
10m
where is built-in potential across the junction, m is the grading
coefficient of the junction, and V1 and V2 are the minimum and
maximum direct voltage across the junction, respectively. Moreover,
0278–0070/99$10.00  1999 IEEE
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(a)
(b)
Fig. 1. (a) CML gate and (b) CML half circuit model.
to take into account the distributed effect of the base-collector capacitance Cbc , we have split it into an intrinsic Cbci = Xcjc Cbc , and
extrinsic Cbcx = (1 0 Xcjc )Cbc part, where Xcjc is a technological
parameter in the range 0–1. The base-emitter capacitance Cbe , is due
to the diffusion capacitance CD , and junction capacitance Cje (i.e.,
Cbe = CD + Cje ). Finally, the collector-substrate capacitance, Ccs ,
is only a junction capacitance.
Assuming a dominant pole behavior with a time constant , the
propagation delay P D , is equal to 0.69 [12]. Thus, after simple
approximations in which we neglect the term r , which is higher
than rb + re , we get
P D = 0:69
re + rb
1 + gm re
Cbe + rb Cbci 1 +
gm (rc + RC )
1 + gm re
+(rc + RC )(Cbci + Cbcx + Ccs ) + RC CL :
(1)
The propagation delay is the sum of four main terms which have a
simple circuit meaning. Indeed, these four terms can be evaluated with
pencil and paper. The first term is the contribution made by the baseemitter capacitance, the second is made by the Miller effect on the
intrinsic base-collector capacitance, the third is a contribution which
arises at the inner-collector node (i.e., before parasitic resistance
rc ), and the last is due to the load capacitance at the output node.
It is worth noting that the term gm =(1 + gm re ) is the equivalent
transconductance of the transistor having a resistance re at the emitter
node.
B. Validation of the Simple CML Model
In order to evaluate the accuracy of the simple model, a comparison
between the propagation delay given by (1) and Spice simulations was
carried out. Moreover, to generalize the comparison, two different
technologies were taken into consideration. The first is a BiCMOS
technology whose n-p-n bipolar transistor has a transition frequency
equal to 6 GHz, the second is the HSB2 high-speed bipolar technology (by courtesy of ST Microelectronics) with a n-p-n transition
frequency equal to 20 GHz.
The circuits have a 5-V power supply and a 250-mV logic swing
which determines the junction capacitances reported in Table I. It
also includes the minimum and maximum direct voltages across
the junction, the built-in potential, the grading coefficient, the zerobias capacitance and the resulting K . Other useful technological
parameters are included in Table II, where IF is the high injection
current level.
The error found versus bias current ISS and with a load capacitance
CL equal to zero, 100 fF, and 1 pF, is plotted in Fig. 2(a) and (b)
for the 6- and 20-GHz technology, respectively. Its worst case is
18% and 42%, respectively. Moreover, outside high-level injection
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 9, SEPTEMBER 1999
1371
TABLE I
TABLE II
region (i.e., with a bias current higher than 1.4 and 2.4 mA for the
6- and 20-GHz technology, respectively) we get a respective mean
error equal to 5% and 17%.
The error reduces increasing the load capacitance. This is because
the contribution due to the linear capacitance CL becomes dominant.
Finally, it is worth noting that although the results for high-level
injection bias currents are less significant, the errors are still low.
(a)
C. Improved CML Model
Although the accuracy of the previous model may be adequate
during the design of a CML, it is not sufficient to implement
a simulation model to evaluate the delay of a complex system.
We thus have to improve the accuracy of the model. Since the
critical components are the capacitances which are nonlinear, the
strategy adopted was that of using (1) and evaluating the capacitance
coefficients from a few simulation runs by means of a numerical
procedure. More specifically, representing each junction capacitance
with its zero-bias value and introducing a corrective coefficient for
each capacitance, from (1) we get
PD = 0:69
re + rb
1 + gm re
(Kje Cjeo + KD CD )
+rb Kbci Xcjc Cbco 1 +
(b)
Fig. 2. (a) Errors of the simple CML model for 6-GHz technology and (b)
errors of the simple CML model for 20-GHz technology.
since it requires few simulation runs, is that of minimizing the
functional below0
S (Kbci ; Kbcx ; Kcs ; Kbe ; KD )
n
gm (rc + RC )
1 + gm re
=
+(rc + RC )(Kbci Xcjc Cbco
j =1
0
PDSpice (ISSj ) PD (ISSj )
:
PDSpice (ISSj )
(3)
(2)
In (3), parameter n is itself a variable, but, according to our experience, it can be set to five. Since we consider the load capacitance in
of the many ways to obtain the coefficients K , the most efficient,
0 We do not use root-mean-square formulation to improve the convergence
speed.
+Kbce (1
0 Xcjc)Cbco + Kcs Ccso ) + RC CL
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TABLE III
(a)
the worst condition (i.e., CL = 0), simulation differs only on the bias
current value. Minimization of functional S can be achieved with any
numerical software such as Matchcad, Matlab, etc.
D. Validation of the Improved CML Model
The set of current values in mA used to minimize functional (3)
were [0.1, 0.2, 0.6, 1, 1.4] and [0.1, 0.4, 1.2, 1.6, 2.2] for the 6and 20-GHz technology, respectively. The coefficients K obtained
are reported in Table III for both technologies. By inspection of K
values reported in Table I, it follows that the most difference between
the simple and the improved model is due to the coefficients K of the
capacitances, Ccs and Cje , for the 6 GHz (which differ by a factor
of two) and to the coefficients K of the capacitances, Ccs , for the 20
GHz (which differs by a factor higher than three).
The error found versus bias current ISS and with a load capacitance
of zero, 100 fF, and 1 pF, is plotted in Fig. 3(a) and (b) for the 6- and
20-GHz technology, respectively. It is worth noting that there is no
difference in the accuracy of the model between the two technologies.
The worst case is lower than 5% for both of them, and outside the
high-level injection region, we get a mean error lower than 2%.
In order to compare the accuracy of the proposed model with that
of the model in [5] and [7], the error found versus bias current and
load capacitance for the 6- and 20-GHz technology of models [5]
and [7] is plotted in Figs. 4 and 5, respectively. It is apparent that
the error of those models is higher than that of the accurate model
and has the same order of magnitude of the simple model.
(b)
Fig. 3. (a) Errors of the accurate CML model for 6-GHz technology and (b)
errors of the accurate CML model for 20-GHz technology.
Fig. 6(b), where, in order to simplify the model, the base-collector
parasitic is not split. This assumption is justified since in this case
the base-collector parasitic is not magnified by the Miller effect and
makes a very small contribution.
The transfer function of the circuit in Fig. 6(b) is given by (4),
shown at the bottom of the page, where in the coefficient of the term
s2 the product Cbc (Cbe + CL ) has been neglected with respect to
Cbe CL . Usually, (4) has two complex and conjugate poles which
justify the well-known ringing behavior [8]. Neglecting the zero of
(4) which is at a frequency much higher than that of the poles, the
normalized step response in the time domain is
y (t) = 1
1
1
1 sin
III. ECL PROPAGATION DELAY
A. Simplified ECL Model
0
0
1
2
0!
e
0
t
1
2!
n t + arctg
0
2
(5)
where the pole frequency !n and the damping factor are
An ECL gate, shown in Fig. 6(a), is a symmetrical gate made up
of a CML followed by common-collector (CC) stages. Again, we
assume all transistors to be working in a linear region, therefore
we can consider only half of the circuit and assume the ECL
propagation delay composed by two separated contributions: the CML
propagation delay P D(CML) and the common-collector propagation
delay P D(CC) . The CML propagation delay derives from that
evaluated in the previous section setting CL = 0. The CC propagation
delay must be evaluated by driving the CC stage with the Thevenin
equivalent circuit seen by the output of the CML stage. Therefore,
we have to analyze the linear model of the CC stage depicted in
Vout
Vin
gm
(RC + rb )Cbe CL
!n =
=
1
1
2
r
+
+
RC + rb
gm
(6a)
CL
Cbe
1
(Cbe + CL )2
gm (RC + rb )
Cbe CL
gm (RC + rb )
Cbe
:
CL
(6b)
C
1 + g be s
1+
RC + rb C + Cbe + CL + (R + r )C s + RC + rb (C C )s2
L
C
b
bc
be L
g r
g
g
(4)
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(a)
(a)
(b)
Fig. 4. (a) Errors of the model in [5] for 6-GHz technology and (b) errors
of the model in [5] for 20-GHz technology.
(b)
Fig. 6. (a) ECL gate and (b) ECL half circuit model.
factor. The propagation delay normalized to the inverse of the pole
frequency, PDn , [i.e., y (PDn =!n ) = 0.5] for a common range of
, which is from 0.1–0.8, is quite linear and ranges from 1–1.6. Then,
considering in the following the worst case of PDn = 1.6, from (6a)
we get
PD(cc) =
(a)
PDn
!n
1:6
RC + r b
Cbe CL :
gm
(7)
Our approach to evaluating the propagation delay of the common
collector is much simpler and more general than that proposed in
[8]. It takes into account the dependence of the CC stage on the bias
current (this dependence is small and is reduced by increasing the
bias current since the diffusion capacitance increases).
Following the above discussion, the propagation delay of the ECL
gate can be written as
PD = PD(ECL) + PD(CC)
= 0:69
re + rb
1 + gm1 re
Cbe1 + rb Cbci1 1 +
gm1 (rc + RC )
1 + gm1 re
+(rc + RC )(Cbci1 + Cbcx1 + Ccs1 )
+ 1:6
(b)
Fig. 5. (a) Errors of the model in [7] for 6-GHz technology and (b) errors
of the model in [7] for 20-GHz technology.
The time normalized to the inverse of the pole frequency for a
fixed percentage of the output voltage only depends on the damping
RC + rb
Cbe2 CL
gm2
(8)
where the indexes one and two refer to the CML and the CC,
respectively. It is worth noting that, unlike the CML case, the
minimum and maximum direct voltage across the base-collector
junction are now V1 = 0RC ISS 0 Vbe and V2 = RC ISS 0 Vbe .
Moreover, since the voltage across the base-emitter junction of the
CC can be assumed to be constant, we can use for it the small signal
value.
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(a)
(a)
(b)
Fig. 7. (a) Errors for simple ECL model with 6-GHz technology and CL
= 100 fF and (b) errors for simple ECL model with 6-GHz technology and
CL = 1 pF.
(b)
Fig. 8. (a) Errors for simple ECL model with 20-GHz technology and CL
B. Validation of the Simple ECL Model
In order to evaluate the accuracy of the simple model proposed,
a comparison between propagation delay given by (8) and SPICE
simulations was carried out under many bias conditions and load
capacitors for the 6- and 20-GHz technology. The circuits were
powered with 5 V and a 250-mV logic swing was set. Setting the load
capacitance CL , equal to 100 fF and 1 pF, the errors found with the
6-GHz technology biasing the common collector with 0.4-, 0.8-, and
1-mA current, and with the 20-GHz technology biasing the common
collector current to 0.4-, 1-, and 1.8-mA are plotted in Figs. 7 and
8, respectively.
The worst case errors are much lower than 20% for both 6- and
20-GHz technology, respectively.
= 100 fF and (b) errors for simple ECL model with 20-GHz technology and
CL = 1 pF.
(a)
C. Improved ECL Model
In order to improve the accuracy of the ECL model we adopt a
numerical procedure similar to that used for the CML gate. More
specifically, we represent the propagation delay as
P D = H1 P D(CML)
gm2 F + Cje2 C (R + r )
+ H2
C
b
L
gm2
(9)
where P D(CML) is given by (2) setting CL = 0. The model has
nine unknown coefficients: 1 and 2 which regard only CC terms,
H1 and H2 , which weight the CML and ECL contribution, and the
five coefficients K inside P D(CML) .
To find these coefficients we first have to calculate the values of
Ks as done in the CML case. Then, P D(CML) becomes known and
we have to minimize the functional
= 100 f and (b) errors for accurate ECL model with 6-GHz technology and
CL = 1 pF.
SECL (H1 ; H2 ; 1 ; 2 )
n
P DSpice (ISSj ; Iccj ; CL ) 0 P D (ISSj ; Iccj ; CL )
=
P DSpice (ISSj ; Iccj ; CL )
j =1
Our experience has shown that a good choice of n is ten. Moreover,
the simulations should be run setting = 100 fF and CL = 1 pF,
and properly distributing the bias currents ISS and Icc in the range
outside high-level injection.
(10)
(b)
Fig. 9. (a) Errors for accurate ECL model with 6-GHz technology and CL
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 9, SEPTEMBER 1999
1375
are strongly related to the circuit and, hence, the process parameter.
The main difference between the accurate and the simple models is
that the former need Spice simulations to properly evaluate model
parameters, although the few simulations required are much fewer
than those used with the traditional sensitivity approach.
ACKNOWLEDGMENT
The authors wish to thank ST Microelectronics and in particular
Ing. G. Ferla and Ing. S. Sueri for allowing the use of the Spice
model of the HSB2 technology.
(a)
REFERENCES
(b)
Fig. 10. (a) Errors for accurate ECL model with 20-GHz technology and
CL 100 fF and (b) errors for accurate ECL model with 20-GHz technology
and CL
1 pF.
=
=
D. Validation of the Improved ECL Model
After calculation of the coefficients Ks as done to validate the
accurate CML model, we ran five simulations uniformly covering the
entire region of currents ISS and Icc in which the model is valid (two
with = 100 fF and three with = 1 pF) to determine the coefficients
1 ; 2 ; H1 ; and H2 . The coefficients founds for the technologies
under consideration are reported in Table III. In this model the main
difference between the simple and the improved model is due to the
values of parameters H1 and H2 .
Various simulations were run with different bias current and load
capacitance values to evaluate the error of the accurate ECL model.
The errors found with the 6-GHz technology biasing the common
collector with 0.4-, 0.8-, and 1-mA current, and with the 20-GHz
technology biasing the common collector current to 0.4-, 1-, and 1.8mA are plotted in Figs. 9 and 10, respectively, with CL equal to 100
fF and 1 pF. The worst case error is lower than 10%, while the typical
error is around 5% for both technologies.
IV. CONCLUSIONS
In this paper a simple and an accurate models for the propagation
delay of both CML and ECL gates are proposed. The simple models,
which show typical errors lower than 20%, are suitable for penciland-paper design. The accurate models, which have typical errors
lower than 5%, can be used in simulators to evaluate the time
behavior of complex systems. It is worth noting that simple CML
model accuracy improves by increasing the load capacitance, and
its accuracy is higher (typical errors around 5%) for the traditional
technology. Moreover, the accurate CML model has a lower error
than that of the ECL gate. The typical error of the accurate CML
model is as low as 2% while that of the ECL is around 5%.
Both simple and accurate models have a small number of terms as
compared with those proposed in the literature, and the terms used
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