CHAPTER 15 ADVANCED MOS AND BIPOLAR LOGIC CIRCUITS
Chapter Outline
15.1 Pseudo-NMOS Logic Circuits
15.2 Pass-Transistor Logic Circuits
15.3 Dynamic MOS Logic Circuits
15.4 Emitter-Coupled Logic (ECL)
15.5 BiCMOS Digital Circuits
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15.1 PSEUDO-NMOS LOGIC CIRCUITS
NMOS Inverter Circuits
 A simple inverter circuit is composed of a NMOS and a load
 The load can be realized by a resistor or another NMOS device
Resistive Load
NMOS Inverter
Enhancement Load
NMOS Inverter
Pseudo-NMOS Inverters




Use a PMOS transistor as the load
Does not suffer from body effect
Directly compatible with complementary CMOS circuits
Area and delay penalties arising from the fan-in in
complementary CMOS gate are reduced
Depletion Load
NMOS Inverter
Pseudo-NMOS Inverter
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15.1 PSEUDO-NMOS LOGIC CIRCUITS
Static Characteristics




Load curve represents a much lower saturation current
kn is usually greater than kp by a factor of 4 to 10
A ratioed type logic with r  kn/kp
The logic is typically operated in two extremely cases:
 vI = 0: vO = VOH = VDD
 vI = VDD: vO = VOL > 0 (nonzero VOL for pseudo-NMOS)
 The VTC can be derived based on iDN and iDP:
1
k n (vI  Vt ) 2 for vO  vI  Vt (saturation)
2
1 

 k n (vI  Vt )vO  vO2  for vO  vI  Vt (triode)
2 

1
 k p (VDD  Vt ) 2 for vO  Vt (saturation)
2
1


 k p (VDD  Vt )(VDD  vO )  (VDD  vO ) 2  for vO  Vt (triode)
2


iDN 
iDN
iDP
iDP
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Derivation of the VTC
 Assume Vtn = |Vtp| = Vt for the derivations
 Region I (Segment AB):
vO  VOH  VDD
 Region II (Segment BC):
vO  Vt  (VDD  Vt ) 2  r (vI  Vt ) 2
 Region III (Segment CD):
1
1  


r (vI  Vt )vO  vO2   (VDD  Vt )(VDD  vO )  (VDD  vO ) 2 
2
2  


 Region
R i IV (S
(Segmentt DE)
DE):
1
vO  (vI  Vt )  (vI  Vt ) 2  (VDD  Vt ) 2
r
 Static Characteristics:
VOL  (VDD  Vt )(1  1  k p / k n )
VOH  VDD
VIH  Vt 
2
3k n / k p
(VDD  Vt )
NM H  VOH  VIH
VM  Vt 
VIL  Vt 
VDD  Vt
(k n / k p )(k n / k p  1)
NM L  VIL  VOL
VDD  Vt
kn / k p  1
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Dynamic Operation
 Determine tPLH:
 The analysis is identical to the CMOS inverter and the output capacitance C is charged by PMOS
t PLH 
 pC
k pVDD
 7  V   V 2 
where  p  2 /   3 t    t  
 4  VDD   VDD  
 Determine tPHL:
 The discharge current is iDN  iDP while iDP is typically negligible as r is large
t PHL 
 nC
k nVDD
 3  1   1  V   V  2 
where  n  2 / 1  1     3   t    t  
r  VDD   VDD  
 4  r  

 n  p for a large value of r and tPHL is much larger than tPLH
Design of Pseudo-NMOS Inverter
 Determine ratio r = kn / kp
 The larger the value of r, the lower VOL is
 A larger r increases the asymmetry in the dynamic response
 Usually, r is selected in the range of 4 to 10
 Determine (W/L)n and (W/L)p
 A small (W/L) to keep the gate area and the value of C small
 A small (W/L) to keeps Isat of QP and static power dissipation low
 A large (W/L) to obtain a small propagation delay tP and fast response
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Gate Circuits
 Design of gate circuits refers to a standard pseudo-NMOS inverter
 The approach to determine the PDN is identical to that of a complementary CMOS gate
 The sizing of the PDN has to be taken into account to meet VOL and delay requirement
Concluding Remarks
 In pseudo-NMOS, NOR gates are preferred over NAND gates in order to use minimum-size devices
 Pseudo-NMOS is particularly suited for applications in which the output remains high most of the time
 The static power dissipation can be reasonably low
 The output transitions that matter would presumably be high-to-low ones where the propagation delay
can be made as short as necessary
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15.2 PASS-TRANSISTOR LOGIC CIRCUITS
Design of Pass-Transistor Logic (PTL) Circuits




Using series and parallel combinations of switches
The switches are controlled by input logic variables to connect the input and output nodes
Can be implemented by a single NMOS transistor or CMOS transmission gate
Every circuit node has at all times a low-resistance path to VDD or ground
Y  ABC
Y  A( B  C )
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Operation with NMOS Transistor as the Switch
 Pass-transistor with output high (“poor 1”)
 The output node refers to the source terminal of the NMOS
 Q is in saturation during the charging process and Vt increases with vO due to body effect
 tPLH increases as the charging current reduces by higher Vt due to body effect
 VOH = VDD  Vt leads to a reduction in the gate noise immunity
 Pass-transistor with output low (“good 0”)
 The input node refers to the source terminal of the NMOS
 No body effect
 The output node can be discharged completely  VOL = 0
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Restoring the Output Level
 The circuit-based approach by adding a feedback loop with QR
 The PMOS QR turns on by vO2 (= “0”) to restore the signal loss at vO1 = “1”
 The PMOS QR is turn off by vO2 (= “1”) when vO1 = “0”
 Operation is more involved than it appears due to the positive feedback
 QR has to be a “weak PMOS transistor” in order not to play a major role in the circuit operation
 The alternative approach by process technology
 The signal loss is due to the threshold voltage of the NMOS devices
 Threshold adjustment by ion implantation to during fabrication make zero-threshold devices
 Subthreshold
S bth h ld conduction
d ti becomes
b
significant
i ifi t for
f zero-threshold
th h ld devices
d i
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The Use of CMOS Transmission Gates as Switches





PMOS and NMOS are in parallel with complementary control signals
Both NMOS and PMOS provide charging/discharging current
Good logic level with VOH = VDD and VOL = 0
The complexity, silicon area and load capacitance are increased
Body effect has to be taken into account to evaluate iDN and iDP
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The Equivalent Resistance of the Transmission Gate
 The equivalent resistance of QN:
 For vO  VDD  Vtn:
iDN 
VDD  vO
1
k n (VDD  Vtn  vO ) 2 and RNeq 
1
2
k n (VDD  Vtn  vO ) 2
2
 For vO  VDD  Vtn:
iDN  0 and RNeq  
 The equivalent resistance of QP:
 For vO  |Vtp |:
iDP 
V v
1
d RPeq  1 DD O
k p (VDD  | Vtp |) 2 and
2
k p (VDD  | Vtp |) 2
2
 For vO  |Vtp |:
1


iDP  k p (VDD  | Vtp |)(VDD  vO )  (VDD  vO ) 2  and RPeq 
2


 Empirical formula for the equivalent resistance:
RTG 
VDD  vO
1


k p (VDD  | Vtp |)(VDD  vO )  (VDD  vO ) 2 
2


12.5
(k)
(W / L) n
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Calculation of Propagation Delay in the Signal Path
 The signal path containing multiple transmission gates can be modeled by resistors and capacitors
 The model is in a form of an RC ladder network
 The propagation delay is given by Elmore delay formula as
t P  0.69[(Cout1  CTG1 ) RP1  (CTG 2  Cin 2 )( RP1  RTG )]
 *Elmore delay formula is given by
t P  0.69[C1 R1  C2 ( R1  R2 )  C3 ( R1  R2  R3 )  ...]
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Pass-Transistor Logic Circuit Examples
Final Remarks
 Advantages of CMOS transmission gate over pass-transistor logic with NMOS devices
 Logic level: good “1” and “0”
 No level restoring technique needed
 Disadvantages of CMOS transmission gate over pass-transistor logic with NMOS devices
 Silicon area and complexity: an additional input requires one NMOS and one PMOS devices
 Complementary control signal required
 Propagation delay: more capacitive loading from the MOSFETs
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15.3 DYNAMIC LOGIC CIRCUITS
Principle of Dynamic Logic Circuits
 Rely on the storage of signal voltage on parasitic capacitances at certain circuit nodes
 The circuits need to be periodically refreshed
 Maintain the low device count of pseudo-NMOS while reducing the static power dissipation to zero
Operation of Dynamic Logic Circuits
 Precharge phase: Qp on and Qe off  charge the output node to VDD
 Evaluation phase: Qp off and Qe on  selectively discharge the output node through PDN
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Nonideal Effects
 Noise margin:
 Since VIL ≈ VIH ≈ Vtn , the resulting noise margins are NML ≈ Vtn and NMH ≈ VDD  Vtn
 Asymmetric noise immunity (poor NML)
 Output voltage decay due to leakage effects:
 Leakage current will slowly discharge the output node when PDN is off
 The leakage is from the reversed-biased junctions and possibly the subthreshold conduction
 Charge sharing:
 Some of the internal nodes in PDN will share the charge in CL even the PDN path is off
 Can be solved by adding a permanently turn-on
turn on transistor QL at the cost of static power dissipation
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Domino CMOS Logic
 Problem with cascading dynamic logic gates: errors cuased by undesirable premature discharge
Precharge
Evaluation
Y1
VM
Y2
t
Premature discharge
t
 Domino CMOS logic:
 A dynamic logic with a static CMOS inverter connected to its output
 The output Y is 0 in the precharge phase and at the beginning of the
evaluation phase
 Alleviate the premature discharge problem for the following stages
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 A cascade of Domino CMOS logic:
 Each stage has to wait for the rising edge from the preceding stage
 The rising edge propagates through a cascade of gates
Concluding Remarks
 Advantages of Domino logic: small silicon area, high-speed operation, and zero static power dissipation
 Disadvantages of Domino logic:
 Asymmetric noise margin
 Leakage issue
 Charge sharing
 Dead time: unavailability of output during precharge phase
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15.4 EMITTER-COUPLED LOGIC (ECL)
Basic Principle
 High speed is achieved by operating all transistor out of saturation to avoid storage time delays
 By keeping the logic signal swings relatively small (~0.8V) to reduce the charging/discharging time
 One of the inputs is connected to a reference voltage VR
 When vI is greater than VR by about 4VT  vO1 = VCC  IRC and vO2 = VCC
 When vI is smaller than VR by about 4VT  vO1 = VCC and vO2 = VCC  IRC.
 Important features of ECL:
 The differential nature of the circuit makes it less susceptible to picked-up noise
 The current drawn from the power supply remains constant during switching  no current spikes.
 The output signal levels are both referenced to VCC and can be made particularly stable with VCC = 0V
 Some means has to be provided to make the output signal levels compatible with those at the input
 The availability of complementary output considerably simplifies logic design with ECL
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The Basic Gate Circuit
 Bias network:
 The network generates a reference voltage VR of 1.32V at room temperature
 VR is made to change with T in a predetermined manner so as to keep the noise margins constant
 VR is also made relatively insensitive to variations in the power supply voltage VEE
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 Differential input stage:
 Paralleling input transistors (QA and QB) are used to implement OR and NOR functions
 Current in RE remains approximately constant over the normal range of operation
 Use resistors to connect each input terminal to the negative supply  can leave unused inputs open
 Emitter-follower output stage:
 On-chip loads are not included as the gate drives a transmission line terminated at the other end in
most of high-speed logic
 Emitter followers shift the level by one vBE drop  the shifted levels are centered around VR
 Provide low output resistance and large current driving capability
 Separate power-supply prevents coupling of power-supply spikes from the output to the gate circuit
ECL Families
 ECL 100K: tP ≈ 0.75ns and PD ≈ 40mW  PDP = 30pJ
 ECL 10K: tP ≈ 2ns and PD ≈ 25mW  PDP = 50pJ
 A variant of ECL (current-mode logic) has become popular in VLSI applications
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Voltage Transfer Characteristics
 Definition of unity-gain: QA (or QR) is conducting 1% (or 99%) of IE
 Assuming the vBE = 0.75V at a emitter current of 1 mA for an ECL transistor
OR Transfer Curve
I E |Q R
I E |Q A
 99  VBE |QR VBE |QA  VT ln 99  115mV
VOL  4  0.245  0.75  1.73V
VIL  1.32  0.115  1.435V
VOH  0.88V
VIH  1.32  0.115  1.205V
V  VBE |QR VEE  1.32  0.75  5.2
for vI < VIL: I E  R

 4mA
RE
0.779
NM L  VIL  VOL  1.435  (1.77)  0.335V
NM H  VOH  VIH  0.88  (1.205)  0.325V
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NOR Transfer Curve
I E |Q R
I E |Q A
 99  VBE |QR VBE |QA  VT ln 99  115mV
VIL  1.32  0.115  1.435V
VIH  1.32  0.115  1.205V
for vI < VIL: VOH = 0.88V
for vI = VIH:
VIH  VBE |QA VEE
 1.205  0.75  5.2
 4.17mA
RE
0.779
vO  4.17  0.22  0.75  1.667V
IE 

for vI = VOH:
VOL
VOH  VBE |QA VEE
 0.88  0.75  5.2
 4.58mA
RE
0.779
 4.58  0.22  0.75  1.758V
IE 

NM L  VIL  VOL  1.435  (1.758)  0.323V
NM H  VOH  VIH  0.88  (1.205)  0.325V
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Manufacturers’ Specifications
 VILmax = 1.475 V VIHmin = 1.105 V
 VOLmax = 1.630 V VOHmin = 0.980 V
Fan-Out
 IIL = (1.77+5.2)/50 = 69 A IIH = (0.88+5.2)/50 + 4/101 = 126 A
 Input currents are small and output resistance is small  fan-out of ECL is not limited by logic-level
 The fan-out is limited by considerations of circuit speed
Operating Speed
 The speed
p
is measured by
y the delayy of its basic ggate and by
y the rise and fall times of the output
p waveforms
 Using emitter follower as the output stage, the ECL gate exhibit shorter rise time than its fall time
Signal Transmission
 ECL is particularly sensitive to ringing because the signal levels are so small
 One solution is to keep the wires very “short” with respect to the signal rise/fall time
 the reflections return while the input is still rising/falling
 If greater lengths are needed, then transmission lines must be used
 the reflection is suppressed with proper termination
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Power Dissipation
 Gate power dissipation of unterminated ECL remain relatively constant independent of the logic state
 No current spikes are introduced on the supply line
 The need for supply-line bypassing in ECL is not as great as in TTL
Thermal Effects
 The reference voltage VR is 1.32V at room temperature
 VR is made to change with T in a predetermined manner so as to keep the noise margins almost constant
 A demonstration of the high degree of design optimization of this gate circuit
Wired-OR Capability
p
y
 The emitter follower output stage of the ECL family allows wired-OR for logic design
 The OR function is implemented by wiring the output of several gates in parallel
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15.5 BICMOS DIGITAL CIRCUITS
The BiCMOS Circuits
 BiCMOS Technology combines Bipolar and CMOS Circuits on one IC chip
 CMOS (low-power, high input impedance, wide noise margins) + Bipolar (high current-driving capability)
 Particularly useful for logic with large fan-out (large capacitive load)
The Simple BiCMOS Inverter
 Cascading each of the QN and QP devices of the MCOS inverter with an npn transistor
 Input high:
 QN turns on and the drain current flows into the base of Q2 as the base current
 The initial discharge current ≈ iDN +  iDN  vO drops
 QN in
i deep
d
triode
t i d with
ith iD = 0 as vO drops
d
tto VBEon (≈
( 0.7V)
0 7V)  VOL = VBEon
 Input low:
 QP turns on and the drain current flows into the base of Q1 as the base current
 The initial discharge current ≈ (  iDP  vO increases
 QP in deep triode with iDP=0 as vO drops to VBEon (≈ 0.7V)  VOH = VDD  VBEon
 Q1 and Q2 are operating in nonsaturation mode and will not turn on simultaneously
 Reduced noise margin due to smaller logic swing
 No base discharge path to speed up the turn-off of Q1 and Q2  long turn-off delays.
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BiCMOS Inverter with “Bleeder Resistors”
 Resistor R1 and R2 are added to provide base discharge paths for Q1 and Q2 turn-off
 Input high:
 QN turns on and QP turns off  provides discharging current through QN and Q2
 vO is discharged below VBEon through QN and R2  improved noise margin
 Pulling vO from VBEon to ground is rather slow due to the high impedance path (QN and R2)
 Input low:
 QN turns off and QP turns on  provides charging current through QP and Q1
 A dc current path exist from VDD to ground through QP and R1 when Q1 is off
 vO can only be charged up to VDD  VDS,P
DS P  VBEon
BE by Q1
 R1 and R2 take some of the drain currents of QP and QN away from the bases of Q1 and Q2 and thus slightly
reduce the output charging/discharging currents of the gate
 R1 and R2 are typically implemented by MOSFET QR1 and QR2
 QR1 conducts only when vI is high  R1 to discharge Q1
 QR2 conducts only when vI is low  R2 to discharge Q2
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BiCMOS Inverter “R-circuit”
 R1 is connected to the output node rather than returning to ground:
 The problem of static power dissipation is now solved
 R1 now functions as a pull-up resistor, pulling the output node voltage up to VDD
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Dynamic Operation




The detailed analysis of the dynamic operation is rather complex
The propagation delay is estimated by the time required to charge and discharge a load capacitance C
Such an approximation is justified in cases where C is relatively large
Usually the case for application of BiCMOS inverters
1 W 
2
k p   VDD  | VtP |
2  L P
iR1  VBEon / R1
iD 
iB  iD  iR1
i  (1   )iB  iR1
t PLH 
iD 
CVDD / 2
i
1 W 
2
k n   VDD  VBEon  Vtn 
2  L N
iR2  VBEon / R2
iB  iD  iR2
i   iB  iD
t PHL 
CVDD / 2
i
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BiCMOS Logic Gates
 BiCMOS logic gates can be implemented following the same approach as the inverters
 The bipolar portion simply functions as an output stage
 QN and QP are replaced by pull-down network and pull-up network
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