TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
ADVANCED LinCMOS™ RAIL-TO-RAIL OPERATIONAL AMPLIFIERS
Check for Samples: TLC2272-Q1 , TLC2272A-Q1 , TLC2274-Q1, TLC2274A-Q1
FEATURES
1
•
•
•
•
•
2
•
Qualified for Automotive Applications
Output Swing Includes Both Supply Rails
Low Noise . . . 9 nV/√Hz Typ at f = 1 kHz
Low Input Bias Current . . . 1 pA Typ
Fully Specified for Both Single-Supply and
Split-Supply Operation
Common-Mode Input Voltage Range Includes
Negative Rail
•
•
•
•
•
High-Gain Bandwidth . . . 2.2 MHz Typ
High Slew Rate . . . 3.6 V/μs Typ
Low Input Offset Voltage
950 μV Max at TA = 25°C
Macromodel Included
Performance Upgrades for the TS272, TS274,
TLC272, and TLC274
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
The TLC2272 and TLC2274 are dual and quadruple
operational amplifiers from Texas Instruments. Both
devices exhibit rail-to-rail output performance for
increased dynamic range in single- or split-supply
applications. The TLC227x family offers 2 MHz of
bandwidth and 3 V/μs of slew rate for higher speed
applications. These devices offer comparable ac
performance while having better noise, input offset
voltage, and power dissipation than existing CMOS
operational amplifiers. The TLC227x has a noise
voltage of 9 nV/√Hz, two times lower than competitive
solutions.
The TLC227x, exhibiting high input impedance and
low noise, is excellent for small-signal conditioning for
high-impedance sources, such as piezoelectric
transducers. Because of the micropower dissipation
levels, these devices work well in hand-held
monitoring and remote-sensing applications. In
addition, the rail-to-rail output feature, with single- or
split-supplies, makes this family a great choice when
interfacing with analog-to-digital converters (ADCs).
For precision applications, the TLC227xA family is
available with a maximum input offset voltage of 950
μV. This family is fully characterized at 5 V and ±5 V.
V(OPP)
V
O(PP) − Maximum Peak-to-Peak Output Voltage − V
DESCRIPTION
16
TA = 25°C
14
12
IO = ± 50 µA
10
IO = ± 500 µA
8
6
4
4
6
10
12
8
|VDD ±| − Supply Voltage − V
14
16
The TLC2272/4 also makes great upgrades to the
TLC272/4 or TS272/4 in standard designs. They offer
increased output dynamic range, lower noise voltage,
and lower input offset voltage. This enhanced feature
set allows them to be used in a wider range of
applications. For applications that require higher
output drive and wider input voltage range, see the
TLV2432 and TLV2442 devices.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADVANCED LinCMOS is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2012, Texas Instruments Incorporated
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
TA
VIOmax At 25°C
-40°C to 125°C
-40°C to 125°C
(1)
(2)
PACKAGED DEVICES (1) (2)
SMALL OUTLINE (D)
TSSOP (PW)
950 μV
TLC2272AQDRQ1
TLC2272AQPWRQ1
2.5 mV
TLC2272QDRQ1
TLC2272QPWRQ1
950 μV
TLC2274AQDRQ1
TLC2274AQPWRQ1
2.5 mV
TLC2274QDRQ1
TLC2274QPWRQ1
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Equivalent Schematic (Each Amplifier)
VDD +
Q3
Q6
Q9
Q12
Q14
Q16
IN +
OUT
C1
IN −
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
Q5
R3
R4
Q7
Q8
Q10
Q11
R1
R2
VDD−
2
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Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Actual Device Component Count (1)
COMPONENT
TLC2272
TLC2274
Transistors
38
76
Resistors
26
52
Diodes
9
18
Capacitors
3
6
(1)
Includes both amplifiers and all ESD, bias, and trim circuitry
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
(2)
VALUE
UNIT
VDD+
Supply voltage
8
V
VDD−
Supply voltage (2)
−8
V
VID
Differential input voltage (3)
±16
V
(2)
Any input
VDD− − 0.3 to VDD+
V
Any input
±5
mA
Output current
±50
mA
Total current into VDD+
±50
mA
±50
mA
VI
Input voltage range
II
Input current
IO
Total current out of VDD−
Duration of short-circuit current at (or below) 25°C (4)
unlimited
Continuous total dissipation
See Dissipation Ratings
TA
Operating free-air temperature range
Tstg
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
(4)
-40°C to 125°C
°C
−65 to 150
°C
260
°C
D or PW package
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD −.
Differential voltages are at IN+ with respect to IN −. Excessive current will flow if input is brought below VDD− − 0.3 V.
The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D-8
725 mW
5.8 mW/°C
464 mW
337 mW
145 mW
D-14
950 mW
7.6 mW/°C
608 mW
494 mW
190 mW
D-14
525 mW
4.2 mW/°C
336 mW
273 mW
105 mW
D-14
700 mW
5.6 mW/°C
448 mW
364 mW
-
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VDD±
Supply voltage
±2.2
±8
V
VI
Input voltage
VDD−
VDD+ −1.5
V
VIC
Common-mode input voltage
VDD−
VDD+ −1.5
V
TA
Operating free-air temperature
−40
125
°C
Copyright © 2003–2012, Texas Instruments Incorporated
UNIT
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3
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
TLC2272Q ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
TEST CONDITIONS
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
25°C
VIC = 0 V,
VO = 0 V,
VDD± = ±2.5 V,
RS = 50 Ω
300
RS = 50 Ω
VIC = 2.5 V,
0.002
0.002
μV/m
o
25°C
0.5
60
0.5
800
VIC = 2.5 V,
VO = 1 V to 4 V,
IOL = 5 mA
RL = 10 kΩ (3)
RL = 1 MΩ (3)
60
800
1
1
60
800
0 to 4
−0.3 to
4.2
0 to 4
4.99
25°C
4.85
Full range
4.85
25°C
4.25
Full range
4.25
−0.3 to
4.2
4.85
4.93
4.85
4.65
4.25
V
4.65
4.25
0.01
25°C
0.09
Full range
0.01
0.15
0.09
0.15
0.9
Full range
10
Full range
10
35
0.15
0.15
1.5
0.9
1.5
25°C
pA
4.99
4.93
25°C
25°C
pA
V
0 to
3.5
0 to 3.5
25°C
IOL = 500 μA
μV
25°C
Full range
IOL = 50 μA
950
1600
UNIT
μV/°C
|VIO| ≤ 5 mV
IOH = −200 μA
MAX
2
25°C
VIC = 2.5 V,
Large-signal differential
voltage amplification
2500
TYP
2
25°C
VIC = 2.5 V,
AVD
300
MIN
Full range
IOH = −1 mA
Low-level output voltage
MAX
Full range
High-level output voltage
VOL
TLC2272AQ
TYP
3000
25°C to 125°C
IOH = −20 μA
VOH
TLC2272Q
MIN
Full range
Input offset voltage
long-term drift (2)
IIO
TA (1)
V
1.5
1.5
10
35
10
V/mV
25°C
175
175
rid
Differential input
resistance
25°C
1012
1012
Ω
ri
Common-mode input
resistance
25°C
1012
1012
Ω
ci
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 1 MHz,
AV = 10
25°C
140
140
Ω
CMR
R
Common-mode rejection
ratio
VIC = 0 V to 2.7
V,
VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply voltage rejection
ratio (ΔVDD/ΔVIO)
VDD = 4.4 V to 16 V,
25°C
80
VIC = VDD/2,
No load
Full range
80
IDD
Supply current
VO = 2.5 V,
No load
(1)
(2)
(3)
4
25°C
Full range
75
70
75
dB
70
95
80
95
dB
80
2.2
3
3
2.2
3
3
mA
Full range is −40°C to 125°C for Q level part.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 2.5 V
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Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
TLC2272Q OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
VO =1.25 V to
2.75 V,
RL = 10 kΩ (2)
CL = 100 pF (2)
TLC2272Q
MIN
TYP
25°C
2.3
3.6
Full range
1.7
TLC2272AQ
MAX
MIN
TYP
2.3
3.6
MAX
UNIT
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage
f = 10 Hz
25°C
50
50
f = 1 kHz
25°C
9
9
VN(pp)
Peak-to-peak equivalent
input noise voltage
f = 0.1 to 1 Hz
25°C
1
1
f = 0.1 to 10 Hz
25°C
1.4
1.4
In
Equivalent input noise
current
25°C
0.6
0.6
THD
+N
Total harmonic distortion
plus noise
0.0013
%
0.0013
%
0.004%
0.004%
0.03%
0.03%
25°C
2.18
2.18
MHz
25°C
1
1
MHz
1.5
1.5
2.6
2.6
25°C
50°
50°
25°C
10
10
VO = 0.5V to
2.5V,
RL = 10 kΩ,
f = 20 kHz (2)
AV = 1
25°C
AV = 10
AV = 100
f = 10 kHz,
CL = 100 pF (2)
RL = 10 kΩ
Maximum output-swing
bandwidth
VO(PP) = 2V,
RL = 10 kΩ (2)
AV = 1,
CL = 100 pF (2)
To 0.1%
ts
Settling time
AV = -1,
Step = 0.5V to
2.5V,
RL = 10 kΩ (3)
CL = 100 pF (3)
φm
Phase margin at unity
gain
RL = 10 kΩ (3),
CL = 100 pF (3)
To 0.01%
Gain margin
(1)
(2)
(3)
nV/√
Hz
μV
fA/√H
z
(2)
Gain-bandwidth product
BOM
V/μs
1.7
25°C
μs
dB
Full range is −40°C to 125°C for Q level part.
Referenced to 2.5 V
Referenced to 2.5 V
Copyright © 2003–2012, Texas Instruments Incorporated
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Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
5
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
TLC2272Q ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature
coefficient of input
offset voltage
Input offset voltage
long-term drift (2)
TEST CONDITIONS
25°C
VIC = 0 V,
RS = 50 Ω
IIB
Input bias current
VICR
Common-mode input
RS = 50 Ω
voltage range
VO = 0 V
Large-signal
differential voltage
amplification
0.002
μV/m
o
25°C
0.5
25°C
Full range
60
0.5
800
1
−5 to 4
60
−5.3 to
4.2
1
4.85
Full range
4.85
25°C
4.25
Full range
4.25
VIC = 0 V,
25°C
−4.85
Full range
−4.85
25°C
−3.5
Full range
−3.5
20
Full range
20
pA
V
4.99
4.93
4.85
4.93
4.85
4.65
4.25
V
4.65
4.25
−4.99
25°C
−5.3 to
4.2
pA
−5 to 3.5
4.99
25°C
60
800
−5 to 4
−5 to
3.5
60
800
800
IO = 500
μA
RL = 1 MΩ
μV
0.002
25°C
RL = 10 kΩ
950
1500
UNIT
25°C
IO = 50 μA
VO = ±4 V,
300
MAX
μV/°C
VIC = 0 V,
IO = 5 mA
TYP
2
25°C
IO = −200 μA
VIC = 0 V,
AVD
2500
MIN
2
25°C
IO = −1 mA
Maximum negative
peak output voltage
300
Full range
IO = −20 μA
VOM-
MAX
Full range
|VIO| ≤ 5
mV
TLC2272AQ
TYP
3000
25°C to 125°C
Input offset current
Maximum positive
peak output voltage
TLC2272Q
MIN
Full range
IIO
VOM+
TA (1)
−4.99
−4.91
−4.85
−4.91
−4.85
−4.1
−3.5
V
−4.1
−3.5
50
20
50
20
V/mV
25°C
300
300
rid
Differential input
resistance
25°C
1012
1012
Ω
ri
Common-mode input
resistance
25°C
1012
1012
Ω
ci
Common-mode input f = 10 kHz,
capacitance
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 1 MHz,
AV = 10
25°C
130
130
Ω
CMR
R
Common-mode
rejection ratio
VIC = -5 V to
2.7 V,
VO = 0 V,
RS = 50 Ω
Supply voltage
rejection ratio
(ΔVDD/ΔVIO)
VDD = ±2.2 V to ±8 V,
kSVR
VIC = 0V,
No load
IDD
Supply current
VO = 0 V,
No load
(1)
(2)
6
25°C
75
Full range
75
25°C
80
Full range
80
25°C
Full range
80
75
80
dB
75
95
80
95
dB
80
2.4
3
3
2.4
3
3
mA
Full range is −40°C to 125°C for Q level part.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
TLC2272Q OPERATING CHARACTERISTICS
at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
TLC2272Q
MIN
TYP
25°C
2.3
3.6
Full range
1.7
TLC2272AQ
MAX
MIN
TYP
2.3
3.6
MAX
UNIT
SR
Slew rate at unity
gain
VO = ±2.3 V,
RL = 10 kΩ
Vn
Equivalent input
noise voltage
f = 10 Hz
25°C
50
50
f = 1 kHz
25°C
9
9
Peak-to-peak
equivalent input
noise voltage
f = 0.1 to 1 Hz
25°C
1
1
VN(pp)
f = 0.1 to 10 Hz
25°C
1.4
1.4
In
Equivalent input
noise current
25°C
0.6
0.6
0.0011%
0.0011%
THD
+N
Total harmonic
distortion plus noise
0.004%
0.004%
0.03%
0.03%
25°C
2.25
2.25
MHz
25°C
0.54
0.54
MHz
1.5
1.5
3.2
3.2
25°C
52°
52°
25°C
10
10
BOM
AV = 1
AV = 10
f = 10 kHz,
CL = 100 pF
RL = 10 kΩ
Maximum
output-swing
bandwidth
VO(PP) = 4.6 V,
RL = 10 kΩ
AV = 1,
CL = 100
pF
AV = -1,
Step = -2.3 V to
2.3 V,
RL = 10 kΩ
CL = 100 pF
To 0.1%
Settling time
φm
Phase margin at
unity gain
Gain margin
RL = 10 kΩ,
25°C
AV = 100
Gain-bandwidth
product
ts
(1)
VO = ±2.3 V,
f = 20 kHz,
RL = 10 kΩ
CL = 100
pF
To 0.01%
CL = 100
pF
25°C
1.7
V/μs
nV/√H
z
μV
fA/√H
z
μs
dB
Full range is −40°C to 125°C for Q level part.
Copyright © 2003–2012, Texas Instruments Incorporated
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Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
7
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
TLC2274Q ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
IIB
Input bias current
VICR
Common-mode input
voltage range
VDD± = ±2.5 V,
RS = 50 Ω
RS = 50 Ω
0.002
0.002
μV/m
o
25°C
0.5
60
0.5
800
VIC = 2.5 V,
VIC = 2.5 V,
VO = 1 V to 4
V,
IOL = 500 μA
IOL = 5 mA
RL = 10 kΩ (3)
RL = 1 MΩ (3)
60
800
1
1
60
800
0 to 4
−0.3 to
4.2
0 to 4
4.99
25°C
4.85
Full range
4.85
25°C
4.25
Full range
4.25
−0.3 to
4.2
4.85
4.93
4.85
4.65
4.25
V
4.65
4.25
0.01
25°C
0.09
Full range
0.01
0.15
0.09
0.15
0.9
Full range
10
Full range
10
35
0.15
0.15
1.5
0.9
1.5
25°C
pA
4.99
4.93
25°C
25°C
pA
V
0 to
3.5
0 to 3.5
25°C
IOL = 50 μA
μV
25°C
|VIO| ≤ 5 mV
IOH = −200 μA
950
1600
UNIT
μV/°C
Full range
VIC = 2.5 V,
Large-signal differential
voltage amplification
300
MAX
2
25°C
VIC = 2.5 V,
AVD
TYP
2
25°C
IOH = −1 mA
Low-level output voltage
2500
MIN
Full range
High-level output voltage
VOL
300
Full range
IOH = −20 μA
VOH
MAX
3000
25°C to 125°C
VIC = 0 V,
VO = 0 V,
TLC2274AQ
TYP
Full range
Input offset voltage
long-term drift (2)
Input offset current
TLC2274Q
MIN
25°C
VIO
IIO
TA (1)
V
1.5
1.5
10
35
10
V/mV
25°C
175
175
rid
Differential input
resistance
25°C
1012
1012
Ω
ri
Common-mode input
resistance
25°C
1012
1012
Ω
ci
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 1 MHz,
AV = 10
25°C
140
140
Ω
CMR
R
Common-mode rejection
ratio
VIC = 0 V to 2.7
V,
VO = 2.5 V,
RS = 50 Ω
25°C
70
Full range
70
kSVR
Supply voltage rejection
ratio (ΔVDD/ΔVIO)
VDD = 4.4 V to 16 V,
25°C
80
VIC = VDD/2,
No load
Full range
80
IDD
Supply current
VO = 2.5 V,
No load
(1)
(2)
(3)
8
25°C
Full range
75
70
75
dB
70
95
80
95
dB
80
4.4
6
6
4.4
6
6
mA
Full range is −40°C to 125°C for Q level part.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
Referenced to 2.5 V
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TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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TLC2274Q OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TA (1)
TEST CONDITIONS
VO = 0.5 V to
2.5 V,
RL = 10 kΩ (2)
CL = 100 pF (2)
TLC2274Q
MIN
TYP
25°C
2.3
3.6
Full range
1.7
TLC2274AQ
MAX
MIN
TYP
2.3
3.6
MAX
UNIT
SR
Slew rate at unity gain
Vn
Equivalent input noise
voltage
f = 10 Hz
25°C
50
50
f = 1 kHz
25°C
9
9
VN(pp)
Peak-to-peak equivalent
input noise voltage
f = 0.1 to 1 Hz
25°C
1
1
f = 0.1 to 10 Hz
25°C
1.4
1.4
In
Equivalent input noise
current
25°C
0.6
0.6
THD
+N
Total harmonic distortion
plus noise
0.0013
%
0.0013
%
0.004%
0.004%
0.03%
0.03%
25°C
2.18
2.18
MHz
25°C
1
1
MHz
1.5
1.5
2.6
2.6
25°C
50°
50°
25°C
10
10
VO = 0.5V to
2.5V,
RL = 10 kΩ,
f = 20 kHz (2)
AV = 1
25°C
AV = 10
AV = 100
f = 10 kHz,
CL = 100 pF (2)
RL = 10 kΩ
Maximum output-swing
bandwidth
VO(PP) = 2V,
RL = 10 kΩ (2)
AV = 1,
CL = 100 pF (2)
To 0.1%
ts
Settling time
AV = -1,
Step = 0.5V to
2.5V,
RL = 10 kΩ (3)
CL = 100 pF (3)
φm
Phase margin at unity gain
RL = 10 kΩ (3),
CL = 100 pF (3)
Gain margin
(1)
(2)
(3)
nV/√
Hz
μV
fA/√H
z
(2)
Gain-bandwidth product
BOM
V/μs
1.7
To 0.01%
25°C
μs
dB
Full range is −40°C to 125°C for Q level part.
Referenced to 2.5 V
Referenced to 2.5 V
Copyright © 2003–2012, Texas Instruments Incorporated
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SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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TLC2274Q ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature
coefficient of input
offset voltage
Input offset voltage
long-term drift (2)
TEST CONDITIONS
25°C
VIC = 0 V,
RS = 50 Ω
IIB
Input bias current
VICR
Common-mode input
RS = 50 Ω
voltage range
VO = 0 V
Large-signal
differential voltage
amplification
0.002
μV/m
o
25°C
0.5
25°C
Full range
60
0.5
800
1
−5 to 4
60
−5.3 to
4.2
1
4.85
Full range
4.85
25°C
4.25
Full range
4.25
VIC = 0 V,
25°C
−4.85
Full range
−4.85
25°C
−3.5
Full range
−3.5
20
Full range
20
pA
V
4.99
4.93
4.85
4.93
4.85
4.65
4.25
V
4.65
4.25
−4.99
25°C
−5.3 to
4.2
pA
−5 to 3.5
4.99
25°C
60
800
−5 to 4
−5 to
3.5
60
800
800
IO = 500
μA
RL = 1 MΩ
μV
0.002
25°C
RL = 10 kΩ
950
1500
UNIT
25°C
IO = 50 μA
VO = ±4 V,
300
MAX
μV/°C
VIC = 0 V,
IO = 5 mA
TYP
2
25°C
IO = −200 μA
VIC = 0 V,
AVD
2500
MIN
2
25°C
IO = −1 mA
Maximum negative
peak output voltage
300
Full range
IO = −20 μA
VOM-
MAX
Full range
|VIO| ≤ 5
mV
TLC2274AQ
TYP
3000
25°C to 125°C
Input offset current
Maximum positive
peak output voltage
TLC2274Q
MIN
Full range
IIO
VOM+
TA (1)
−4.99
−4.91
−4.85
−4.91
−4.85
−4.1
−3.5
V
−4.1
−3.5
50
20
50
20
V/mV
25°C
300
300
rid
Differential input
resistance
25°C
1012
1012
Ω
ri
Common-mode input
resistance
25°C
1012
1012
Ω
ci
Common-mode input f = 10 kHz,
capacitance
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 1 MHz,
AV = 10
25°C
130
130
Ω
CMR
R
Common-mode
rejection ratio
VIC = -5 V to
2.7 V,
VO = 0 V,
RS = 50 Ω
Supply voltage
rejection ratio
(ΔVDD/ΔVIO)
VDD = ±2.2 V to ±8 V,
kSVR
VIC = 0V,
No load
IDD
Supply current
VO = 0 V,
No load
(1)
(2)
10
25°C
75
Full range
75
25°C
80
Full range
80
25°C
Full range
80
75
80
dB
75
95
80
95
dB
80
4.4
6
6
4.4
6
6
mA
Full range is −40°C to 125°C for Q level part.
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to
TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
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TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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TLC2274Q OPERATING CHARACTERISTICS
at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
TLC2274Q
MIN
TYP
25°C
2.3
3.6
Full range
1.7
TLC2274AQ
MAX
MIN
TYP
2.3
3.6
MAX
UNIT
SR
Slew rate at unity
gain
VO = ±2.3 V,
RL = 10 kΩ
Vn
Equivalent input
noise voltage
f = 10 Hz
25°C
50
50
f = 1 kHz
25°C
9
9
Peak-to-peak
equivalent input
noise voltage
f = 0.1 to 1 Hz
25°C
1
1
VN(pp)
f = 0.1 to 10 Hz
25°C
1.4
1.4
In
Equivalent input
noise current
25°C
0.6
0.6
0.0011%
0.0011%
THD
+N
Total harmonic
distortion plus noise
0.004%
0.004%
0.03%
0.03%
25°C
2.25
2.25
MHz
25°C
0.54
0.54
MHz
1.5
1.5
3.2
3.2
25°C
52°
52°
25°C
10
10
BOM
AV = 1
AV = 10
f = 10 kHz,
CL = 100 pF
RL = 10 kΩ
Maximum
output-swing
bandwidth
VO(PP) = 4.6 V,
RL = 10 kΩ
AV = 1,
CL = 100
pF
AV = -1,
Step = -2.3 V to
2.3 V,
RL = 10 kΩ
CL = 100 pF
To 0.1%
Settling time
φm
Phase margin at
unity gain
Gain margin
RL = 10 kΩ,
25°C
AV = 100
Gain-bandwidth
product
ts
(1)
VO = ±2.3 V,
f = 20 kHz,
RL = 10 kΩ
CL = 100
pF
To 0.01%
CL = 100
pF
25°C
1.7
V/μs
nV/√H
z
μV
fA/√H
z
μs
dB
Full range is −40°C to 125°C for Q level part.
Copyright © 2003–2012, Texas Instruments Incorporated
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SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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TYPICAL CHARACTERISTICS
Table of Graphs (1)
FIGURE
VIO
αVIO
IIB /IIO
Figure 1, Figure 2,
Figure 3, Figure 4,
Figure 5, Figure 6
Input offset voltage
Distribution vs Common-mode voltage
Input offset voltage temperature coefficient
Distribution
Input bias and input offset current
vs Free-air temperature
Figure 11
vs Supply voltage
Figure 12
vs Free-air temperature
Figure 13
Figure 7,Figure 8,
Figure 9, Figure 10
VI
Input voltage
VOH
High-level output voltage
vs High-level output current
Figure 14
VOL
Low-level output voltage
vs Low-level output current
Figure 15, Figure 16
VOM +
Maximum positive peak output voltage
vs Output current
Figure 17
VOM −
Maximum negative peak output voltage
vs Output current
Figure 18
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
Figure 19
vs Supply voltage
Figure 20
vs Free-air temperature
Figure 21
IOS
Short-circuit output current
VO
Output voltage
vs Differential input voltage
AVD
Large-signal differential voltage amplification
vs Load resistance
Large-signal differential voltage amplification and phase
margin
vs Frequency
Large-signal differential voltage amplification
vs Free-air temperature
Figure 27, Figure 28
Output impedance
vs Frequency
Figure 29, Figure 30
vs Frequency
Figure 31
zo
CMRR
Common-mode rejection ratio
kSVR
Supply-voltage rejection ratio
IDD
Supply current
SR
VO
Figure 24
Figure 25, Figure 26
vs Free-air temperature
vs Frequency
vs Free-air temperature
Figure 36, Figure 37
vs Free-air temperature
Figure 38, Figure 39
vs Free-air temperature
Voltage-follower large-signal pulse response
Figure 44, Figure 45
Inverting small-signal pulse response
Figure 46, Figure 47
Figure 48, Figure 49
vs Frequency
Figure 50, Figure 51
12
Figure 52
Integrated noise voltage
vs Frequency
Figure 53
Total harmonic distortion plus noise
vs Frequency
Figure 54
vs Supply voltage
Figure 55
Gain bandwidth product Gain-bandwidth product
(1)
Figure 41
Figure 42, Figure 43
Noise voltage over a 10-second period
φm
Figure 40
Inverting large-signal pulse response
Equivalent input noise voltage
THD + N
Figure 35
vs Supply voltage
Voltage-follower small-signal pulse response
Vn
Figure 32
Figure 33, Figure 34
vs Load capacitance
Slew rate
Figure 22, Figure 23
vs Free-air temperature
Figure 56
Phase margin
vs Load capacitance
Figure 57
Gain margin
vs Load capacitance
Figure 58
For all graphs where VDD = 5 V, all loads are referenced to 2.5 V.
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TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
DISTRIBUTION OF TLC2272 INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2272 INPUT OFFSET VOLTAGE
Figure 1.
Figure 2.
DISTRIBUTION OF TLC2274 INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2274A INPUT OFFSET VOLTAGE
20
20
992 Amplifiers From
2 Wafer Lots
VDD = ± 5 V
Percentage of Amplifiers − %
Percentage of Amplifiers − %
992 Amplifiers From
2 Wafer Lots
VDD = ± 2.5 V
15
10
5
0
−1.6 −1.2
−0.8
−0.4
0
0.4
0.8
VIO − Input Offset V oltage − mV
Figure 3.
Copyright © 2003–2012, Texas Instruments Incorporated
1.2
1.6
15
10
5
0
−1.6 −1.2
−0.8
−0.4
0
0.4
0.8
1.2
1.6
VIO − Input Offset V oltage − mV
Figure 4.
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
INPUT OFFSET VOLTAGE
vs
COMMON-MODE VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE VOLTAGE
1
VDD = 5 V
TA = 25°C
RS = 50 Ω
VIO − Input Offset V oltage − mV
VIO
VIO
V
IO − Input Offset V oltage − mV
1
0.5
0
−0.5
−1
−1
0
1
2
3
4
5
VIC − Common-Mode V oltage − V
14
VDD = ± 5 V
TA = 25°C
RS = 50 Ω
0.5
0
−0.5
−1
−6 −5 −4 −3 −2
−1
0
1
2
3
4
5
VIC − Common-Mode V oltage − V
Figure 5.
Figure 6.
DISTRIBUTION OF TLC2272
vs
INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC2272
vs
INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT
Figure 7.
Figure 8.
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SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
DISTRIBUTION OF TLC2274A
vs
INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC2274A
vs
INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT
25
25
128 Amplifiers From
2 Wafer Lots
VDD = ± 2.5 V
N Package
TA = 25°C to 125°C
20
Percentage of Amplifiers − %
Percentage of Amplifiers − %
20
15
10
5
0
−5
128 Amplifiers From
2 Wafer Lots
VDD = ± 2.5 V
N Package
TA = 25°C to 125°C
15
10
5
0
−4
−3
−2
−1
0
1
2
3
4
5
−5
−4
−3
−2
−1 0
1
2
3
4
5
α VIO − Temperature Coefficient − µV/°C
Figure 9.
Figure 10.
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
vs
SUPPLY VOLTAGE
35
12
VDD = ± 2.5 V
VIC = 0 V
VO = 0 V
RS = 50 Ω
30
TA = 25°C
RS = 50 Ω
10
8
6
25
20
IIB
15
IIO
10
V I − Input Voltage − V
I IO − Input Bias and Input Offset Currents − pA
IIIB
IB and IIO
α VIO − Temperature Coefficient − µV/°C
4
2
|VIO| ≤ 5 mV
0
−2
−4
−6
5
−8
0
− 10
25
45
65
85
105
TA − Free-Air Temperature − °C
Figure 11.
Copyright © 2003–2012, Texas Instruments Incorporated
125
2
3
4
5
6
7
|VDD ±| − Supply Voltage − V
8
Figure 12.
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
6
VDD = 5 V
VDD = 5 V
VV0H
OH − High-Level Output V oltage − V
V I − Input Voltage − V
4
3
|VIO| ≤ 5mV
2
1
0
−1
−75 − 50
5
4
TA = 125°C
3
TA = 25°C
2
TA = −55°C
1
0
− 25
0
25
50
75
100
125
0
TA − Free-Air Temperature − °C
3
Figure 14.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.4
VOL
VOL − Low-Level Output V oltage − V
VDD = 5 V
TA = 25°C
VOL
VOL − Low-Level Output V oltage − V
2
Figure 13.
1.2
1
VIC = 0 V
0.8
VIC = 1.25 V
0.6
0.4
VIC = 2.5 V
0.2
4
VDD = 5 V
VIC = 2.5 V
1.2
1
TA = 125°C
0.8
TA = 25°C
0.6
TA = −55°C
0.4
0.2
0
0
0
1
2
3
4
IOL − Low-Level Output Current − mA
Figure 15.
16
1
IOH − High-Level Output Current − mA
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5
0
5
1
2
3
4
IOL − Low-Level Output Current − mA
6
Figure 16.
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TLC2272-Q1 , TLC2272A-Q1
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SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
V OM − − Maximum Negative Peak Output V oltage − V
V OM + − Maximum Positive Peak Output V oltage − V
5
VDD ± = ± 5 V
4
TA = −55°C
TA = 25°C
3
TA = 125°C
2
1
0
1
2
3
4
|IO| − Output Current − mA
−3.8
VDD = ± 5 V
VIC = 0 V
−4
TA = 125°C
−4.2
TA = 25°C
−4.4
TA = −55°C
−4.6
−4.8
−5
0
5
1
2
3
4
IO − Output Current − mA
5
Figure 17.
Figure 18.
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
RL = 10 kΩ
TA = 25°C
9
VID = −100 mV
8
7
6
5
VDD = 5 V
4
VDD = ± 5 V
3
2
1
12
8
4
0
VID = 100 mV
−4
VO = 0 V
TA = 25°C
−8
0
10 k
6
16
10
IIOS
OS − Short-Circuit Output Current − mA
V
V(OPP)
O(PP) − Maximum Peak-to-Peak Output V oltage − V
MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
100 k
1M
f − Frequency − Hz
Figure 19.
Copyright © 2003–2012, Texas Instruments Incorporated
10 M
2
3
4
5
6
7
|VDD ±| − Supply Voltage − V
8
Figure 20.
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TLC2272-Q1 , TLC2272A-Q1
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SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 5 V
TA = 25°C
RL = 10 kΩ
VIC = 2.5 V
VID = −100 mV
11
VO − Output V oltage − V
4
7
−3
−1
5
3
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
3
2
1
VID = 100 mV
−5
−75
VO − Output V oltage − V
5
VO = 0 V
VDD = ± 5 V
0
−800
125
800
−400
0
400
VID − Differential Input V oltage − µV
Figure 21.
Figure 22.
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
LOAD RESISTANCE
1200
1000
VDD = ± 5 V
TA = 25°C
RL = 10 kΩ
VIC = 0 V
VO = ± 1 V
TA = 25°C
AVD
A VD − Large-Signal Differential
Voltage Amplification − dB
IIOS
OS − Short-Circuit Output Current − mA
15
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
1
−1
100
VDD = ± 5 V
10
VDD = 5 V
1
−3
−5
0
250 500 750 1000
−1000 −750 −500 −250
VID − Differential Input V oltage − µV
Figure 23.
18
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0.1
0.1
1
10
RL − Load Resistance − k Ω
100
Figure 24.
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
AVD
A VD − Large-Signal Differential
Voltage Amplification − dB
60
180°
80
135°
60
40
90°
20
45°
0
0°
−20
−45°
−40
1k
10 k
100 k
1M
f − Frequency − Hz
−90°
10 M
AVD
A VD − Large-Signal Differential
Voltage Amplification − dB
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
φ
om
m − Phase Margin
80
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
90°
20
45°
0°
0
−20
−45°
−40
1k
10 k
100 k
1M
f − Frequency − Hz
−90°
10 M
Figure 25.
Figure 26.
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
FREE-AIR TEMPERATURE
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1k
VDD = ± 5 V
VIC = 0 V
VO = ± 4 V
AVD
A VD − Large-Signal Differential
Voltage Amplification − V/mV
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
AVD
A VD − Large-Signal Differential
Voltage Amplification − V/mV
135°
40
1k
RL = 1 MΩ
100
RL = 10 kΩ
10
−75
180°
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
φ
om
m − Phase Margin
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 27.
Copyright © 2003–2012, Texas Instruments Incorporated
125
RL = 1 MΩ
100
RL = 10 kΩ
10
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 28.
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19
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
OUTPUT IMPEDANCE
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
1000
VDD = ± 5 V
TA = 25°C
zo − Output Impedance − W
100
AV = 100
10
AV = 10
1
AV = 1
0.1
100
1k
10 k
100 k
CMRR − Common-Mode Rejection Ratio − dB
AV = 10
1
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 29.
Figure 30.
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
90
VDD = ± 5 V
80
VDD = 5 V
60
40
20
100
1k
10 k
100 k
f − Frequency − Hz
Figure 31.
20
10
0.1
100
1M
TA = 25°C
10
AV = 100
f − Frequency − Hz
100
0
100
AV = 1
CMRR − Common-Mode Rejection Ratio − dB
zo − Output Impedance − W
VDD = 5 V
TA = 25°C
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1M
10 M
86
82
VDD = ± 5 V
VIC = −5 V to 2.7 V
78
VDD = 5 V
74
70
−75
VIC = 0 V to 2.7 V
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
Figure 32.
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
100
VDD = 5 V
TA = 25°C
kkSVR
SVR − Supply-V oltage Rejection Ratio − dB
kkSVR
SVR − Supply-V oltage Rejection Ratio − dB
100
80
60
k SVR+
40
k SVR −
20
0
−20
10
100
1k
10 k
100 k
1M
10 M
VDD = ± 5 V
TA = 25°C
80
60
k SVR+
40
k SVR −
20
0
−20
10
100
1k
10 k
100 k
1M
f − Frequency − Hz
f − Frequency − Hz
Figure 33.
Figure 34.
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
TLC2272 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10 M
kkSVR
SVR − Supply V oltage Rejection Ratio − dB
110
VDD ± = ± 2.2 V to ± 8 V
VO = 0 V
105
100
95
90
85
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 35.
Copyright © 2003–2012, Texas Instruments Incorporated
125
Figure 36.
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21
TLC2272-Q1 , TLC2272A-Q1
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SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
TLC2274A SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TLC2272 SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
6
IIDD
DD − Supply Current − mA
VO = 0 V
No Load
4.8
3.6
TA = 25°C
TA = −55°C
2.4
TA = 125°C
1.2
0
0
1
2
3
4
5
6
|VDD ± | − Supply Voltage − V
7
8
Figure 37.
Figure 38.
TLC2274A SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
LOAD CAPACITANCE
6
5
VDD = 5 V
AV = −1
TA = 25°C
VDD = ± 5 V
VO = 0 V
4
SR − Slew Rate − V/ µ s
IIDD
DD − Supply Current − mA
4.8
VDD = 5 V
VO = 2.5 V
3.6
2.4
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 39.
22
3
2
SR +
1
1.2
0
−75
SR −
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125
0
10
100
1k
CL − Load Capacitance − pF
10 k
Figure 40.
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
SLEW RATE
vs
FREE-AIR TEMPERATURE
INVERTING LARGE-SIGNAL PULSE RESPONSE
5
5
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
SR −
4
V
VO
O − Output V oltage − mV
SR +
3
2
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
1
0
−75
−50
−25
0
25
50
75
2
0
125
0
1
2
3
4
5
6
7
8
TA − Free-Air Temperature − °C
t − Time − µs
Figure 41.
Figure 42.
INVERTING LARGE-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE
RESPONSE
5
3
9
5
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
4
V
VO
O − Output V oltage − V
100
3
1
4
VO − Output V oltage − V
VO
SR − Slew Rate − V/ µs
4
2
1
0
−1
−2
−3
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
AV = 1
TA = 25°C
3
2
1
−4
−5
0
1
2
3
4
5
6
7
8
9
0
0
1
2
3
4
5
t − Time − µs
t − Time − µs
Figure 43.
Figure 44.
Copyright © 2003–2012, Texas Instruments Incorporated
6
7
8
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9
23
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE
RESPONSE
5
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
3
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = −1
2.6
VO − Output Voltage − V
4
VO − Output V oltage − V
VO
INVERTING SMALL-SIGNAL PULSE RESPONSE
2.65
2
1
0
−1
−2
−3
2.55
2.5
2.45
−4
−5
0
1
2
3
4
5
6
8
2.4
9
0
0.5
1 1.5
2 2.5 3
3.5 4
4.5
5 5.5
t − Time − µs
t − Time − µs
Figure 45.
Figure 46.
INVERTING SMALL-SIGNAL PULSE RESPONSE
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE
RESPONSE
100
2.65
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
50
2.6
V
VO
O − Output V oltage − V
VO − Output V oltage − mV
VO
7
0
−50
VDD = 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
2.55
2.5
2.45
−100
0
0.5
1
2.5
1.5
2
t − Time − µs
Figure 47.
24
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3
3.5
4
2.4
0
0.5
t − Time − µs
1
1.5
Figure 48.
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE
RESPONSE
50
60
VDD = ± 5 V
RL = 10 kΩ
CL = 100 pF
TA = 25°C
AV = 1
V
Vn
nV/Hz Hz
n − Equivalent Input Noise V oltage − nV
VO − Output V oltage − mV
VO
100
0
−50
VDD = 5 V
TA = 25°C
RS = 20 Ω
50
40
30
20
10
0
−100
0
0.5
t − Time − µs
1
10
1.5
Figure 49.
Figure 50.
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
NOISE VOLTAGE OVER A 10 SECOND PERIOD
60
1000
VDD = ± 5 V
TA = 25°C
RS = 20 Ω
50
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
750
500
Noise Voltage − nV
Vn − Equivalent Input Noise V oltage − nV
Vn
nV/Hz Hz
10 k
100
1k
f − Frequency − Hz
40
30
20
250
0
−250
−500
10
−750
−1000
0
10
100
1k
f − Frequency − Hz
Figure 51.
Copyright © 2003–2012, Texas Instruments Incorporated
10 k
0
2
4
6
8
10
t − Time − s
Figure 52.
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25
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
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Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
FREQUENCY
THD + N − Total Harmonic Distortion Plus Noise − %
µ V RMS
Integrated Noise V oltage − uVRMS
100
Calculated Using
Ideal Pass-Band Filter
Lower Frequency = 1 Hz
TA = 25°C
10
1
0.1
1
10
100
1k
10 k
100 k
1
VDD = 5 V
TA = 25°C
RL = 10 kΩ
0.1
AV = 100
0.01
AV = 10
0.001
0.0001
100
1k
10 k
f − Frequency − Hz
f − Frequency − Hz
Figure 53.
Figure 54.
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
2.5
100 k
3
f = 10 kHz
RL = 10 kΩ
CL = 100 pF
TA = 25°C
2.4
VDD = 5 V
f = 10 kHz
RL = 10 kΩ
CL = 100 pF
2.8
Gain-Bandwidth Product − MHz
Gain-Bandwidth Product − MHz
AV = 1
2.3
2.2
2.1
2.6
2.4
2.2
2
1.8
1.6
2
0
1
6
2
3
4
5
|VDD ±| − Supply Voltage − V
Figure 55.
26
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7
8
1.4
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
Figure 56.
Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TLC2272-Q1 TLC2272A-Q1 TLC2274-Q1 TLC2274A-Q1
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
PHASE MARGIN
vs
LOAD CAPACITANCE
75°
GAIN MARGIN
vs
LOAD CAPACITANCE
15
VDD = ± 5 V
TA = 25°C
VDD = 5 V
AV = 1
RL = 10 kΩ
TA = 25°C
Rnull = 100 Ω
12
Rnull = 50 Ω
Gain Margin − dB
φ
om
m − Phase Margin
60°
45°
Rnull = 20 Ω
30°
9
6
10 kΩ
15°
10 kΩ
3
VDD +
Rnull
Rnull = 0
VI
CL
0°
10
VDD −
Rnull = 10 Ω
100
1000
CL − Load Capacitance − pF
Figure 57.
Copyright © 2003–2012, Texas Instruments Incorporated
10000
0
10
100
1000
CL − Load Capacitance − pF
10000
Figure 58.
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27
TLC2272-Q1 , TLC2272A-Q1
TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
APPLICATION INFORMATION
Macromodel Information
Macromodel information provided was derived using Microsim Parts, the model generation software used with
Microsim PSpice. The Boyle macromodel (2) and subcircuit in Figure 59 are generated using the TLC227x typical
electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following
key parameters can be generated to a tolerance of 20% (in most cases):
(2)
•
•
•
•
•
•
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
99
3
VCC +
9
RSS
92
FB
J1
DP
VC
J2
IN +
11
VAD
DC
12
−
C2
6
DIP
91
+
VIP
−
−
+
VIN
7
+
GCM
GA
VLIM
8
C1
RD1
R2
−
53
+
HLIM
−
+
10
90
RO2
VB
IN −
VCC −
−
+
ISS
RP
2
1
DIN
EGND +
−
RD2
60
+
−
54
−
4
RO1
DE
5
+
VE
.SUBCKT TLC227x 1 2 3 4 5
C1
11
1214E−12
C2
6
760.00E−12
DC
5
53DX
DE
54
5DX
DLP
90
91DX
DLN
92
90DX
DP
4
3DX
EGND
99
0POLY (2) (3,0) (4,) 0 .5 .5
FB
99
0POLY (5) VB VC VE VLP VLN 0
+ 984.9E3 −1E6 1E6 1E6 −1E6
GA
6
011 12 377.0E−6
GCM 0 6 10 99 134E−9
ISS
3
10DC 216.OE−6
HLIM
90
0VLIM 1K
J1
11
210 JX
J2
12
110 JX
R2
6
9100.OE3
OUT
RD1
60
112.653E3
RD2
60
122.653E3
R01
8
550
R02
7
9950
RP
3
44.310E3
RSS
10
99925.9E3
VAD
60
4−.5
VB
9
0DC 0
VC 3 53 DC .78
VE
54
4DC .78
VLIM
7
8DC 0
VLP
91
0DC 1.9
VLN
0
92DC 9.4
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=1.500E−12BETA=1.316E-3
+ VTO=−.270)
.ENDS
Figure 59. Boyle Macromodels and Subcircuit
28
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TLC2274-Q1, TLC2274A-Q1
SGLS007E – FEBRUARY 2003 – REVISED JANUARY 2012
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2009) to Revision E
•
Page
Deleted ESD ratings table .................................................................................................................................................... 3
Copyright © 2003–2012, Texas Instruments Incorporated
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29
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLC2272AQDRG4Q1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272AQ
TLC2272AQDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272AQ
TLC2272AQPWRG4Q1
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272AQ
TLC2272AQPWRQ1
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272AQ
TLC2272QDRG4Q1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272Q1
TLC2272QDRQ1
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272Q1
TLC2272QPWRG4Q1
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272Q1
TLC2272QPWRQ1
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2272Q1
TLC2274AQDRG4Q1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AQ1
TLC2274AQDRQ1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AQ1
TLC2274AQPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AQ1
TLC2274AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274AQ1
TLC2274QDRG4Q1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274Q1
TLC2274QDRQ1
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274Q1
TLC2274QPWRG4Q1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274Q1
TLC2274QPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
2274Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2015
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2272-Q1, TLC2272A-Q1, TLC2274-Q1, TLC2274A-Q1 :
• Catalog: TLC2272, TLC2272A, TLC2274, TLC2274A
• Enhanced Product: TLC2272A-EP, TLC2274-EP, TLC2274A-EP
• Military: TLC2272M, TLC2272AM, TLC2274M, TLC2274AM
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2015
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC2274AQPWRG4Q1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274AQPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274QPWRG4Q1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TLC2274QPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC2274AQPWRG4Q1
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274AQPWRQ1
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274QPWRG4Q1
TSSOP
PW
14
2000
367.0
367.0
35.0
TLC2274QPWRQ1
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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