20 – 40 GHz Amplifier
Technical Data
HMMC-5040
Features
• Large Bandwidth:
20 - 44 GHz Typical
21 - 40 GHz Specified
• High Gain: 22 dB Typical
• Saturated Output Power:
21 dBm Typical
• Supply Bias:
≤ 4.5 volts @ ≤ 300 mA
Description
The HMMC-5040 is a high-gain
broadband MMIC amplifier
designed for both military applications and commercial communication systems. This four stage
amplifier has input and output
matching circuitry for use in
50␣ ohm environments. It is
fabricated using a PHEMT
integrated circuit structure that
provides exceptional broadband
performance. The backside of the
chip is both RF and DC ground.
This helps simplify the assembly
process and reduces assembly
related performance variations
and costs. This MMIC is a cost
effective alternative to hybrid
(discrete-FET) amplifiers that
require complex tuning and
assembly processes.
5965-5444E
Chip Size:
Chip Size Tolerance:
Chip Thickness:
Pad Dimensions:
1720 x 760 µm (67.7 x 29.9 mils)
± 10 µm (± 0.4 mils)
127 ± 15 µm (5.0 ± 0.6 mils)
80 x 80 µm (3.1 x 3.1 mils)
Absolute Maximum Ratings[1]
Symbol
Parameters/Conditions
Units
VD1, 2-3-4
Drain Supply Voltages
V
VG1, 2-3-4
Gate Supply Voltages
V
Min.
Max.
5
-3.0
0.5
IDD
Total Drain Current
mA
400
Pin
RF Input Power
dBm
21
Tch
Channel Temperature[2]
°C
+160
TA
Backside Ambient Temp.
°C
-55
+75
TSTG
Storage Temperature
°C
-65
+165
Tmax
Maximum Assembly Temp.
°C
+300
Note:
1. Absolute maximum ratings for continuous operation unless otherwise noted.
2. Refer to DC Specifications/Physical Properties table for derating information.
6-58
HMMC-5040 DC Specifications/Physical Properties [1]
Symbol
VD1, 2-3-4
ID1
Parameters and Test Conditions
Drain Supply Operating Voltages
Units
V
Min.
2
Typ.
4.5
First Stage Drain Supply Current
(VDD = 4.5 V, VG1 = -0.6 V)
mA
55
ID2-3-4
Total Drain Supply Current for Stages 2, 3, and 4
(VDD = 4.5 V, VGG = -0.6 V)
mA
24.5
VG1, 2, 3-4
Gate Supply Operating Voltages (IDD = 300 mA)
V
-0.6
Pinch-off Voltage (VDD = 4.5 V, IDD ≤ 10 mA)
V
Vp
θch-bs
Tch
Thermal Resistance [2]
(Channel-to-Backside @ Tch = 160°C)
Channel Temperature [3] (TA = 125°C, MTTF > 106 hrs,
VDD = 4.5 V, IDD = 300 mA)
-2
Max.
5
-1.2
°C/W
62
°C
160
-0.8
Notes:
1. Backside ambient operating temperature TA = 25°C unless otherwise noted.
2. Thermal resistance (°C/Watt) at a channel temperature T (°C) can be estimated using the equation:
θ(T) ≅ 62 x [T(°C)+ 273] / [160°C + 273].
3. Derate MTTF by a factor of two for every 8°C above Tch.
HMMC-5040 RF Specifications, TA = 25°C, VDD = 4.5 V, IDD = 300 mA, Z o = 50 Ω
Symbol
Parameters/Conditions
Units
BW
S21
∆ S21
(RLin)MIN
(RLout)MIN
S12
P-1dB
Psat
Operating Bandwidth
Small Signal Gain
Small Signal Gain Flatness
Minimum Input Return Loss
Minimum Output Return Loss
Reverse Isolation
Output Power
(@ 1dB Gain Compression)
Saturated Output Power
@ 3 dB Gain Compression
Broadband
Specifications
Min.
Typ.
Max.
GHz
dB
dB
dB
dB
dB
dBm
21
20
dBm
20
8
8
6-59
20–44
22
± 1.5
10
10
54
18
21
40
Narrow Band
Performance
Typical
21–24
25
±1
9
10
54
18
27–29
23
± 0.75
10
11
54
18
37–40
22
± 0.3
14
12
54
18
21
21
21
HMMC-5040 Applications
The HMMC-5040 broadband
amplifier is designed for both
military (35 GHz) applications
and wireless communication
systems that operate at 23, 28,
and 38 GHz. It is also suitable for
use as a frequency multiplier due
to excellent below-band input
return loss and high gain.
Biasing and Operation
The recommended DC bias
condition is with all drains
connected to single 4.5 volt (or
less) supply and all gates connected to an adjustable negative
voltage supply as shown in Figure
12a. The gate voltage is adjusted
for a total drain supply current of
typically up to 300 mA. Figures 4,
5, 8, and 9 can be used to help
estimate the minimum drain
voltage and current necessary for
a given RF gain and output
power.
The second, third, and fourth
stage DC drain bias lines are
connected internally (Figure 1)
and therefore require only a
single bond wire. An additional
bond wire is needed for the first
stage DC drain bias, VD1.
Only the third and fourth stage
DC gate bias lines are connected
internally. A total of three DC
gate bond wires are required: one
for VG1, one for VG2, and one for
the VG3-to-VG4 connection.
The RF input has matching
circuitry that creates a 50 ohm
DC and RF path to ground. A DC
blocking capacitor should be
used in the RF input transmission
line. Any DC voltage applied to
the RF input must be maintained
below 1 volt. The RF output is
AC-coupled.
No ground wires are needed since
ground connections are made
with plated through-holes to the
backside of the device.
The HMMC-5040 can also be used
to double, triple, or quadruple the
frequency of input signals. Many
bias schemes may be used to
generate and amplify desired
harmonics within the device. The
information given here is
intended to be used by the
customer as a starting point for
such applications. Optimum
conversion efficiency is obtained
with approximately 14 dBm input
drive level.
As a doubler, the device can
multiply an input signal in the
10-20 GHz frequency range up to
20-40 GHz with conversion gain
for output frequencies exceeding
30 GHz. Similarly, 5-10 GHz
signals can be quadrupled to
20-40 GHz with some conversion
loss. Frequency doubling or
quadrupling is accomplished by
operating the first gain stage at
pinch-off (VG1 = VP ≅ -1.2 volts).
Stages 2, 3, and 4 are biased for
normal amplification. The assembly diagram shown in Figure 12b
can be used.
To operate the device as a
frequency tripler the drain
voltage can be reduced to
approximately 2.5 volts and the
gate voltage can be set at about
-0.4␣ volts or adjusted to minimize
second harmonics if needed.
Either of Figures 12a or Figure
12b can be used.
Contact your local HP sales
representative for additional
information concerning multiplier
performance and operating
conditions.
6-60
Assembly Techniques
Solder die attach using a fluxless
gold-tin (AuSn) solder preform is
the recommended assembly
method. A conductive epoxy such
as ABLEBOND® 71-1LM1 or
ABLEBOND® 36-2 may also be
used for die attaching provided
the Absolute Maximum Ratings
are not exceeded. The device
should be attached to an electrically conductive surface to
complete the DC and RF ground
paths. The backside metallization
on the device is gold.
It is recommended that the RF
input and output connections be
made using either 500 lines/inch
(or equivalent) gold wire mesh.
The RF connections should be
kept as short as possible to
minimize inductance. The DC
bias supply wires can be 0.7 mil
diameter gold.
Thermosonic wedge is the
preferred method for wire
bonding to the gold bond pads.
Mesh wires can be attached using
a 2 mil round tacking tool and a
tool force of approximately
22␣ grams with an ultrasonic
power of roughly 55 dB for a
duration of 76 ± 8 msec. A guidedwedge at an ultrasonic power
level of 64 dB can be used for the
0.7 mil wire. The recommended
wire bond stage temperature is
150 ± 2°C.
For more detailed information
see HP application note #999
“GaAs MMIC Assembly and
Handling Guidelines.”
GaAs MMICs are ESD sensitive.
Proper precautions should be used
when handling these devices.
VD1
IN
VG2
VD2
VD3
VD4
MATCHING
OUT
MATCHING
MATCHING
MATCHING
MATCHING
50 Ω
VG3
VG1
VG4
Figure 1. HMMC-5040 Simplified Schematic Diagram.
HMMC-5040 Typical Performance
20
22
30
40
18
Isolation
14
50
60
10
20
24
28
32
36
INPUT RETURN LOSS (dB)
10
Gain
26
0
0
70
40
VDD = 4.5 V, IDD = 300 mA
5
5
10
10
Input
15
25
20
24
300 mA
250 mA
200 mA
150 mA
100 mA
18
12
Spec Range
21 – 40 GHz
26
34
42
50
SMALL-SIGNAL GAIN (dB)
SMALL-SIGNAL GAIN (dB)
30
24
18
36
25
40
VDD = 3 V
Figure 4. Broadband Gain as a
Function of Drain Current vs.
Frequency with VDD = 4.5 V.[1]
300 mA
250 mA
200 mA
150 mA
100 mA
24
18
12
6
0
10
FREQUENCY (GHz)
Note:
1. Wafer-probed measurements
32
Figure 3. Typical Input and Output
Return Loss vs. Frequency.[1]
VDD = 4.5 V
0
10
28
20
FREQUENCY (GHz)
Figure 2. Typical Gain and Isolation
vs. Frequency.[1]
6
15
Output
20
FREQUENCY (GHz)
30
0
OUTPUT RETURN LOSS (dB)
VDD = 4.5 V, IDD = 300 mA
REVERSE ISOLATION (dB)
SMALL-SIGNAL GAIN (dB)
30
Spec Range
21 – 40 GHz
18
26
34
42
FREQUENCY (GHz)
Figure 5. Broadband Gain as a
Function of Drain Current vs
Frequency with VDD = 3 V.[1]
6-61
50
HMMC-5040 Typical Performance, continued
0.06 dB/°C
25
35
30
Gain
25
15
20
10
–60
Power
–30
0
30
15
90
60
16
12
VDD = 4.5 V
IDD = 300 mA
8
VDD = 3.0 V
IDD = 130 mA
4
0
20
24
Figure 6. Small-Signal Gain[3] and
Compressed Power[1] vs. Temperature.
Power
21
19
17
Efficiency
17
13
15
9
5
300
200
23
23 GHz
28 GHz
38 GHz
42 GHz
OUTPUT POWER, PSAT (dBm)
25
13
100
32
36
VDD = 3 V
25
21
21
Power
19
17
Efficiency
17
15
13
100
5
300
200
Figure 8. Output Power[1] and
Efficiency vs. Drain Current with
VDD = 4.5 V.
Figure 9. Output Power[1] and
Efficiency vs. Drain Current with
VDD = 3 V.
Gain
20
25
22
10
18
5
14
10
6
ηadded
10
14
18
22
POWER-ADDED EFFICIENCY (%)
GAIN (dB)
26
OUTPUT POWER, P–1dB AND PSAT (dBm)
TOTAL DRAIN CURRENT, IDD (mA)
VDD = 4.5 V, IDD = 300 mA, f = 40GHz
0
26
30
13
9
TOTAL DRAIN CURRENT, IDD (mA)
30
40
Figure 7. Noise Figure vs. Frequency.
POWER-ADDED EFFECIENCY @ PSAT (%)
OUTPUT POWER, PSAT (dBm)
VDD = 4.5 V
21
28
FREQUENCY (GHz)
OPERATING TEMPERATURE (°C)
23
VDD = 2.0 V
IDD = 170 mA
VDD = 4.5 V, IDD = 300 mA
26 P
SAT
30
Gain
22
26
22
18
18
P–1dB
14
10
20
14
24
28
32
36
10
40
FREQUENCY (GHz)
OUTPUT POWER (dBm)
Figure 10. Gain Compression and
Efficiency Characteristics.[2]
Figure 11. Output Power and Gain vs.
Frequency Characteristics.[2]
Notes:
1. Output power into 50 Ω with 2 dBm input power. Wafer-probed measurements.
2. Wafer-probed measurements.
3. Measurements taken on a device mounted in a connectorized package calibrated at the connector terminals.
6-62
POWER-ADDED EFFECIENCY @ PSAT (%)
20
20
22 GHz
28 GHz
38 GHz
25 GHz
30 GHz
35 GHz
40 GHz
SMALL-SIGNAL GAIN (dB)
30
40
NOISE FIGURE (dB)
VDD = 4.5 V, IDD = 300 mA @ TA = 25°C
COMPRESSED OUTPUT POWER (dBm)
SMALL-SIGNAL GAIN (dB)
35
23 GHz
28 GHz
38 GHz
42 GHz
(≅ 100 pF)
VD1
VG2
(≅ 100 pF)
To VDD DC Drain
Supply Feed
Cb
Gold Plated Shim (Optional)
Cb
VD1
VD2-3-4
RFIN
To VGG DC Gate
Supply Feed
(≅ 100 pF)
RFOUT
VG1
VG3-4
VG2 to VG3 Jumper-Wire
Cb
VD2-3-4
RFIN
RFOUT
VG1
VG2
To VDD DC Drain
Supply Feed
[or use VG2 wire shown in (b)]
Figure 12a. Single drain and single gate supply assembly
for tripler and standard amplifier applications.
To VGG DC Gate
Supply Feed
Cb
(≅ 100 pF)
VG3-4
(≅ 100 pF)
Cb
To VG3-4 DC Gate
Supply Feed
Figure 12b. Separate first-stage gate bias supply for
any multiplier or amplifier application. This diagram
shows an optional variation to the VG2 jumper-wire
bonding scheme presented in (a).
Figure 12. HMMC-5040 Common Assembly Diagrams.
(Note: To assure stable operation, bias supply feeds should be bypassed to ground with a capacitor, Cb > 100 nF typical.)
0
70
330
700
930
1180
1465
760
660
480
300
95
0
0
0
95
710
1200
1640 1720
Figure 13. HMMC-5040 Bonding Pad Locations. (Dimensions in micrometers)
This data sheet contains a variety of typical and guaranteed performance data. The
information supplied should not be interpreted as a complete list of circuit specifications. In this data sheet the term typical refers to the 50th percentile performance. For
additional information contact your local HP sales representative.
6-63