Jitter in High
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ECE 733 Class Notes Jitter in High-Speed I/O Dr. Lei D L i Luo L March 2011 ©2011, Dr. Lei Luo 1 ECE 733 Class Notes Outline Jitter and BER Voltage margin and Time margin Jitter components BER(RJ) Jitter sources in High Speed Links Phase-Locked Loop (PLL) Duty Cycle Distortion (DCD) Power Supply Induced Jitter (PSIJ) Inter-Symbol-Interference (ISI) Cross-Talk and reflections Clocking architectures Clock-Data-Recovery (CDR) Source Synchronous Link Clock embedded with Data Asynchronous link A case study for jitter tracking ©2011, Dr. Lei Luo 2 ECE 733 Class Notes A simple high speed link Sampler p D Transmitter Channel TD-to-Clk Clock To avoid bit error, two factors are important ©2011, Dr. Lei Luo Sampling p gp position ((clock p phase)) Eye opening at sampling position 3 ECE 733 Class Notes Voltage and Time Margin Time margin is constrained by Sampler input swing requirement, which includes sampler sensitivity, sampler mismatch/offset, sampler noise. Eye y diagram g which includes signal swing, edge rate and signal integrity (ISI, crosstalk, reflections, especially at the dotted sensitive area) We will only focus on Time Margin although voltage and time really affects each other. other ©2011, Dr. Lei Luo 4 ECE 733 Class Notes Jitter is Phase Wander The main goal of study Jitter is for BER improvement. Jitter is undesired phase wander of a clock signal or data signal, comparing with an ideal periodic time reference. j affects the BER. Actually, y, it is the jitter j of TD-to-Clk Both data jjitter and clock jitter D to Clk really matters. ©2011, Dr. Lei Luo 5 ECE 733 Class Notes Jitter components Data Uncorrelated Jitter Data Correlated Jitter Total Jitter (TJ) Deterministic Jitter (DJ) (Bounded) Data Dependent Jitter (DDJ) (Bounded) IInter-symbol t b l interference (ISI) (Bounded) Duty-cycle D t l distortion (DCD) (Bounded) Random Jitter (RJ) (Unbounded) Periodic Jitter (PJ) (Bounded) Sub-rate S b t Jitter Jitt (SRJ) (Bounded) Uncorrelated U l t d Bounded Jitter (UBJ) (Bounded) B Bounded/Unbounded d d/U b d d RJ: grows with TIME, following Gaussian distribution DJ: doesn’t grow with TIME Data correlated/uncorrelated ©2011, Dr. Lei Luo 6 ECE 733 Class Notes RJ (Random Jitter) Source of RJ External E t l reference f RJ noise i Internal RJ from PLL, where random voltage noise integrates to random phase noise Concept of Jitter(BER) Jitter is a function of BER, since both ties directly to TIME. BER of 10-12 means one error within a TIME range of consecutive 1012 bits. Jitter (the RJ part) grows with TIME S Specify if a Jitter Jitt without ith t BER is i nott appropriate i t A TJ histogram and Power Spectrum Density (PDF), plot below ©2011, Dr. Lei Luo 7 ECE 733 Class Notes RJPP(BER) PDF Example of BER with RJPP/RJRMS=1 σ=RJRMS BER RJ PP 1 RJ RMS 3 2 0 2 3 x2 1 x2 exp( exp( )dx )dx 2 2 RJ PP 2 RJ RMS 2 RJ RMS RJ RMS 2 2 RJ PP erfc( ) 2 RJ RMS ©2011, Dr. Lei Luo BER RJPP/RJRMS 1.00E-03 6.18 1.00E-04 7.438 1.00E-05 8.53 1.00E-06 9.507 1.00E-07 10.399 1.00E-08 11.224 1.00E-09 11.224 1.00E-10 12.723 1.00E-11 13.412 1.00E-12 14.069 1.00E-13 14.698 1.00E-14 15.301 1.00E-15 15.883 1.00E-16 16.444 8 ECE 733 Class Notes How a BERT measures Jitter(BER) An accurate way y Procedure: 1. Select a sampling point (blue dots) J + TJ2 J 2. TJJ = TJ1 3. Measure the BER bit by bit: BER= incorrect bits/total bits Might take a long time for Low BER. For example: takes more than 3 years to measure BER of 10-18 for a 10Gbps link Measured BER A practical way is to measure the TJ1 TJ2 jitter att hi jitt high h BER and d do d extrapolation (curve fitting) to estimate jitter for lower BER. Extrapolated BER ©2011, Dr. Lei Luo 9 ECE 733 Class Notes Outlines Jitter and BER Voltage margin and Time margin Jitter components Jitter(BER) Jitt sources iin Hi Jitter High h Speed S d Li Links k Phase-Locked Loop (PLL) Power Supply Induced Jitter (PSIJ) Duty Cycle Distortion (DCD) Inter-Symbol-Interference (ISI) Cross-Talk and Reflections Clocking architectures Clock-Data-Recovery (CDR) Source Synchronous Link Clock embedded with Data Asynchronous link A case study for jitter tracking ©2011, Dr. Lei Luo 10 ECE 733 Class Notes Jitter Sources in High Speed Links - PLL PLL: •Ref Clk •PSIJ •Osc O RJ PLL RefClk ©2011, Dr. Lei Luo 11 ECE 733 Class Notes Jitter Sources – Level Shifters Level Shifters: •PSIJ •DCD Level Shifters f PLL RefClk ©2011, Dr. Lei Luo 12 ECE 733 Class Notes Jitter Sources – Clock buffers Clk bufffe rs Clk Buffers: •PSIJ •DCD Level f Shifters PLL RefClk ©2011, Dr. Lei Luo 13 ECE 733 Class Notes Jitter Sources - Channel Sampler Even Data Odd Data Channel: Driver Clk b ufffe rs Clktx •ISI •Reflections Level f Shifters PLL RefClk ©2011, Dr. Lei Luo 14 ECE 733 Class Notes Jitter Sources – Cross-Talk Cross Talk Sampler Driver Sampler Even Data Odd Data Driver Jitter from CrossTalk Clk b ufffe rs Clktx Level f Shifters PLL RefClk ©2011, Dr. Lei Luo 15 ECE 733 Class Notes Jitter Sources – Receiver Clk Sampler Driver Sampler Even Data Odd Data Driver Clktx Clk buff ffe rs Clk b ufffe rs Clkrx Level f Shifters Level Shifters PLL Phase Rotator RefClk Same Clk jitter at Receiver side • Ref Clk Jitter • PSIJ • PLL Osc Jitter • DCD PLL RefClk ©2011, Dr. Lei Luo 16 ECE 733 Class Notes Jitter Sources - CDR Sampler Driver Even Data Odd Data CDR: Sampler Driver Clktx CDR Jitter Jitt due du to t Phase/Freq lag and overshoot Clk b uff ffe rs Clk b ufffe rs Clkrx Level f Shifters Level Shifters PLL Phase Rotator CDR PLL RefClk RefClk ©2011, Dr. Lei Luo 17 ECE 733 Class Notes PLL jitter Noise transfer functions • Low bandwidth desired for noisy input • Jittery Jitt reference f clock l k • High bandwidth required for supply noise rejection Noise trans sfer functions [dB B] PLL noise Transfer Functions 10 from input clock from clock buffer supply 0 -10 -20 from VCO supply -30 5 ©2011, Dr. Lei Luo 10 6 10 7 10 8 10 9 10 10 10 frequency [Hz] 18 ECE 733 Class Notes PSIJ - Clock Buffer Jitter Power supply induced clock jitter falls into DJ Uncorrelated bounded jitter Typical Clock Buffers and tradeoffs Inverters: dynamic power power, full swing swing, smaller area CML: low jitter sensitivity to power supply noise Reduce PSIJJ Circuitry improvements - reduce jitter sensitivity to power supply noise ©2011, Dr. Lei Luo 19 ECE 733 Class Notes What Determines On-chip p Supply pp y Noise? I d Impedance Z(f) Current Profile I(f) V ( f ) I( f )Z( f ) It is the interaction between I(f) and Z(f) that determines the supply noise ©2011, Dr. Lei Luo 20 ECE 733 Class Notes Power Supply Network (PDN) Modeling ((log) Vnoise(f) = ZPDN(f) · Inoise(f) ZPD DN Typical Profile of Supply Impedance Frequency x0 … x00 MHz Vnoise VRM PCB Package (log) ZPDN Inoise(f) On-chip Package inductance separates spectrum into two regions: Low-frequency, o eque cy, add addressed essed by PCB C capac capacitors to s High-frequency, addressed by on-chip capacitors ©2011, Dr. Lei Luo 21 ECE 733 Class Notes Jitter Sensitivity Concept • Linearity Li it assumption: ti • Supply noise induced jitter component at one frequency is a linear function of supply pp y noise component p at the same frequency J( f ) S( f ) [ ps / mV Vpp ] V( f ) • Jitter sensitivity: • Determined only by circuit implementation • Independent of noise or data pattern • A link parameter between data activity (noise) and total jitter impact ©2011, Dr. Lei Luo 22 ECE 733 Class Notes Supply Noiise Amplitu ude (log) ~100MHz z PDN Reso onance ~30MHz PLL Band dwidth Jitter Sensitivity [ps//mV] (log) Noise Spectrum and Jitter Sensitivity Frequency (log) Overlap between both parameters (jitter sensitivity and noise i spectrum) t )d determines t i Amount of supply noise induced jitter Spectrum of jitter (needed for jitter tracking) ©2011, Dr. Lei Luo 23 ECE 733 Class Notes Reduce power supply noise Improve PDN impedance, at critical frequency range; Reduce self-introduced power supply noise, reduce di/dt Use power supply regulator; B d t th Budget the regulator l t noise i source: DC offset due to Limited amp gain Device mismatch AC noise comes from Vref noise Loading impedance change Vdd noise ©2011, Dr. Lei Luo 24 ECE 733 Class Notes Duty Cycle Distortion (DCD) Duty-Cycle-Distortion DCD is the highest g frequency q y jjitter component p Directly affects the timing margin for DDR signaling OUTn DCD mainly comes from Device mismatch V l Voltage l level l shifters hif DCD amplification due to limited BW INp OUTp INn Vbias DCD reduction circuitry example 1: DCD also appears as single-ended common-mode DC offset. A CML high-pass filter reduces the incoming single-ended commonmode d DC offset ff and d thus h reduces d the h DCD at its i output. ©2011, Dr. Lei Luo 25 ECE 733 Class Notes DCD reduction circuitry example 2 LPF LPF FSM The single-ended common-mode is Low-Pass-Filtered and compared. The result is used to correct the DCD The DCD from the CLKin is corrected The DCD introduced in clock buffers is corrected With help from FSM, this detection-correction loop can run Continuously on or P Periodically i di ll or calibrate lib t once att power on. ©2011, Dr. Lei Luo 26 ECE 733 Class Notes ISI - Frequency-dependent Frequency dependent Loss Conductors and dielectrics both lossy Loss in 00.5m 5m of typical FR-4 FR 4 Skin Effect ~ F 1/2 0 -5 Dielectric Loss ~ F -10 Attenuation (dB) A -15 -20 Overall Loss -25 30 -30 -35 0.001 0.01 -40 40 0.1 1 10 Freq enc (GH Frequency (GHz)) •For low-cost PC boards, dielectric loss dominates ©2011, Dr. Lei Luo 27 ECE 733 Class Notes ISI - Why is attenuation bad? Frequency-dependent attenuation in channel produces inter-symbol interference (ISI): Vin Lone 1 in stream of 0 0’s s undetectable Vout • Hurt both voltage margin and timing margin • Equalization required ©2011, Dr. Lei Luo 28 ECE 733 Class Notes ISI - Equalization Channel Equalizing Filter Equalized Channel Frequency Frequency Bit-rate/2 Frequency Bit-rate/2 Bit-rate/2 Filter can go at either end of the channel.. T Tx Tx ©2011, Dr. Lei Luo Filt Filter R Rx Filter Rx 29 ECE 733 Class Notes ISI - TX FIR • De De-emphasis emphasis • Reduce ISI • Increase cross talk noise ©2011, Dr. Lei Luo 30 ECE 733 Class Notes ISI - Tx EQ is effective.. effective Equalization OFF Equalization ON 0.18µ I/O, 1999 3.125Gb/s 50cm FR-4 + conn’s pp -8 dB atten Approx 2-Tap equalizer 210 PRBS pattern 160 mV eye height 150 ps P-P jitter 0.13µ I/O, 2003 6.25Gb/s 73cm FR-4 + conn’s Approx pp -15 dB atten 4-Tap equalizer 210 PRBS pattern 100 mV eye y height g 63 ps P-P jitter ©2011, Dr. Lei Luo 31 ECE 733 Class Notes ISI - Receiver Equalizers • Source degenerated amp popular implementation • About as effective as a 2-tap Tx EQ • Problems: ° Amplifies A lifi hi high-freq hf noise i as well ll as signal i l ° Power-hungry Gain OutOut Out+ In+ 3 dB/octave Min. R 8-10 dB of ‘boost’ In- Max. R R ©2011, Dr. Lei Luo Freq 32 ECE 733 Class Notes ISI - RX DFE (Decision-Feedback-Equalization) (Decision Feedback Equalization) • Non-linear, doesn’t amplify crosstalk! • Power hungry • Tight timing for the 1st loop back • Error E propagation ti ©2011, Dr. Lei Luo 33 ECE 733 Class Notes ISI - 3-Tap pp prDFE (p (partial-response p DFE)) Sampler removed from critical path Solves path through parallelism q offset Eliminates summer, requires Consumes more power ©2011, Dr. Lei Luo 34 ECE 733 Class Notes ISI - ADC & FFE (Andy, (Andy ISSCC08) shift ADC FFE & Crosstalk Cancel “TAP” ADAPTION 16 adc samples MU X > Output O data For very complex BP channel at reasonable data rate ©2011, Dr. Lei Luo 35 ECE 733 Class Notes Cross Talk and Reflections Cross-Talk Connectors and vias introduce reflections, ‘notches’, crosstalk 0 Bare 20” FR4 Trace -5 -10 10 -15 S21 (dB) S -20 -25 20” Backplane Channel -30 -35 -40 -45 0.01 0.1 50 > 100 MHz Flat Channel no attn 1 10 Frequency (GHz) 0.1 - 1 GHz Moderate Attn few dB/octave > 1 GHz Strong Attn > 5 dB/octave Chip-to-chip channels more like bare boards boards, and generally less than 20” 20 ©2011, Dr. Lei Luo 36 ECE 733 Class Notes Outlines Jitter and BER Voltage V lt margin i and d Time Ti margin i Jitter components BER(Jitter) Jitter sources in High Speed Links Phase-Locked Loop (PLL) Duty y Cycle y Distortion ((DCD)) Power Supply Induced Jitter (PSIJ) Inter-Symbol-Interference (ISI) Cross-Talk Cross Talk and reflections Clocking architectures Clock-Data-Recovery (CDR) Source Synchronous Link Clock embedded with Data Asynchronous link A case study d for f jitter ji tracking ki ©2011, Dr. Lei Luo 37 ECE 733 Class Notes Revisit - Jitter is Phase Wander The main goal of study Jitter is for BER improvement. Jitter is undesired phase wander of a clock signal or data signal, comparing with an ideal periodic time reference. j affects the BER. Actually, y, it is the jitter j of TD-to-Clk Both data jjitter and clock jitter D to Clk really matters. ©2011, Dr. Lei Luo 38 ECE 733 Class Notes Clock Recoveryy 1.5GbpsX4 NRZ ERROR Report 1.5GHz CLK IN LFSR PRBS BERT Sampler 1.5GHzX4 CLK Multi-Phase DLL 1.5GHzX8 CLK 6Gbps NRZ RX 1.5GbpsX4 NRZ Clock Recovery Have 6Gbps NRZ data, 1.5GHz 8-phase clks, but clk&NRZ are not aligned Need Align clk at center of NRZ, use this clk to sample NRZ Demux 6Gbps NRZ to 1.5Gbps NRZ ©2011, Dr. Lei Luo 39 ECE 733 Class Notes How to align clk to data? First, need to judge if current clk is early or late If Edge(I) Edge(I)=Edge(I+1) Edge(I+1) then No information If Data(I) Data(I)=Data(I+1) Data(I 1) then No information else if Edge(I)=Data(I-1) then Early else if Data(I)=Edge(I) then Late else if Edge(I)=Data(I) then Late else if Data(I)=Edge(I+1) then Early 6Gbps NRZ D0 D1 D2 D3 1.5GHz CLK Rising edge CLK is aligned Edge0 g Data0 Edge1 g Data1 Edge2 g Data2 Edge3 g Data3 CLK comes early Edge0 Data0 Edge1 Data1 Edge2 Data2 Edge3 Data3 CLK comes late Edge0 Data0 Edge1 Data1 Edge2 Data2 Edge3 Data3 ©2011, Dr. Lei Luo 40 ECE 733 Class Notes How to align clk to data? Second, do majority vote on the 8 Early/Late/No_info judgments Third, do LPF to prevent continuous Early or Late Forth, generate control signal for Selector and Interpolator Fifth, selector clk phases from 8-phase DLL Si th iinterpolate Sixth, t l t and d regenerate t RX side id clock l k which hi h iis aligned li d tto NRZ Clk From 8-phase DLL 0 2 4 6 Sel X8 1 3 5 7 SelectorX4 SelectorX4 ClkX4 LPF InterpolatorX8 FSM E/L/N W X8 E/L/N Vote Judge E/L/N X8 ©2011, Dr. Lei Luo ClkX4 ClkX8 SamplerX8 Data X8 From RX Demuxed out X4 41 ECE 733 Class Notes Selector Design g 18 18 8 8 8 8 A simple 2 to 1 differential selector structure Actually circuit is a 4 to1 selector ©2011, Dr. Lei Luo 42 ECE 733 Class Notes Interpolator p Design g 20 1 1 1 1 A simple 2-bit weight differential interpolator structure IIn actually t ll d design, i 8 8-bit bit weight i ht is i needed d d tto keep k phase h controlling step within 10ps ©2011, Dr. Lei Luo 43 ECE 733 Class Notes Link with CDR (Clock (Clock-Data-Recovery) Data Recovery) The one matters BER is JitterD-to-Clk Jitt sources are from: Jitter f TX side: RefClktx noise; TXPLL; Transmitter; Channel RX side: RefClkrx noise; RXPLL; phase rotator; Jitter reduced: PLL filters out high frequency noise of RefClktx/RefClkrx CDR loop tracks low frequency JitterD-to-Clk noise within its BW Key jitter still matters: JitterD-to-Clk beyond of CDR BW (usually <10MHz) ©2011, Dr. Lei Luo 44 ECE 733 Class Notes Source Synchronous Link Sampler Transmitter Dtx Drx Channel Clktx JitterD-to-Clk PLL Crx RefClktx Channel Clkrx Delay Low and mid frequency jitter sources go away because Drx and Crx jitter moves together, t th assuming i Dtx Dt is i triggered ti d precisely i l b by Clktx. Clkt Remained jitter sources: Any high-frequency high frequency jitter (next slide) Others: Transmitter jitter; Channel difference; PSIJ difference between two chips Constraints: dedicated pin/channel for clock, need to match channels ©2011, Dr. Lei Luo 45 ECE 733 Class Notes Source Synchronous Link • Dtx edge trigged directly from Clktx edge, their jitter dance together. • If “Dtx-Drx delay cycles” matches with “Clktx-Clkrx delay cycles”, JitterD-to-Clk will be perfect. perfect (note, (note clk at center of data is ignored here for simple explain) • The more clk-to-data delay, the more JitterD-to-Clk. ©2011, Dr. Lei Luo 46 ECE 733 Class Notes Source Synchronous Link (N:1) Sampler D3 Transmitter Data Channel 3 Clktx3 JitterD3-to-Clk3 Clkrx3 N data channel share one clock l k channel h l (N=3) (N 3) Challenges Sampler D2 Transmitter Data Channel 2 Clkt 2 Clktx2 JitterD2-to-Clk2 Channel matching Phase adjustment PSIJ difference between TX and RX side Clkrx2 Sampler D1 Transmitter Data Channel 1 Clktx1 JitterD1-to-Clk1 Clk 1 Clkrx1 CLK CLK Channel PLL RefClktx ©2011, Dr. Lei Luo 47 ECE 733 Class Notes Embed the clock with the data Self-Clocked Two-Level Differential signaling methods and apparatus : US patent 7535964 • Source synchronous Link (1:1) • Clock edges embedded with each data channel, no channel matching needed • Compromise voltage margin to improve timing margin ©2011, Dr. Lei Luo 48 ECE 733 Class Notes Outlines Jitter and BER Voltage V lt margin i and d Time Ti margin i Jitter components BER(Jitter) Jitter sources in High Speed Links Phase-Locked Loop (PLL) Duty y Cycle y Distortion ((DCD)) Power Supply Induced Jitter (PSIJ) Inter-Symbol-Interference (ISI) Cross-Talk Cross Talk and reflections Clocking architectures Clock-Data-Recovery (CDR) Source Synchronous Link Clock embedded with Data Asynchronous link A case study d for f jitter ji tracking ki ©2011, Dr. Lei Luo 49 A 5Gb/s Link with Clock Edge Matching and Embedded Common Mode Clock for Low Power Interfaces A 5Gb/s Link with Clock Edge Matching and Embedded Common Mode Clock for Low Power Interfaces Jared Zerbe Zerbe, Barry Daly Daly, Lei Luo, Luo Bill Stonecypher, Wayne Dettloff, John Eble, Teva Stone, Jihong Ren, Brian Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin1 Rambus Inc., Los Altos, CA 1Presently with NVIDIA Corporation 2010 VLSI Circuit Symposium June 16, 2010 Outline • • • • Introduction & motivation Matched source source-synchronous synchronous clocking Common-mode clocking D i Design • • • • Clock distribution & DCDL T Transmitter itt Integrating receiver Noise generation • Measured results • Conclusions C l i 2010 VLSI Circuits Symposium Slide 51 Zerbe : C7P5 Power Beyond y Dynamic: y Turn-on/off Server CPU Utilization • Rarely y at 100% • • Non-zero y y-intercept p power p Building a low-power link system goes beyond low active power link Servers and mobile devices spend a lot of time idle • Proportional power not easy to make 0,0 Fast duty-cycling of burst transactions a good approach pp Speed • 2010 VLSI Circuits Symposium Slide 52 52 Slide time Source: Luiz Barroso & Urs Hölzle, IEEE Computer, December 2007 Zerbe : C7P5 Source-Synchronous y Clocking g D t Data D OMUX CK “1”/”0" CK OMUX D TX Sampler AMP Clock TX AMP • Large Data : Clock ratio for busses • Receive clock buffer gets longer • Often multiple UI of path mismatch • Can lead to anti-tracking in source-jitter & PSIJ • Adds latency to power on/off • Requires R i additional dditi l edges d on state t t transitions t iti 2010 VLSI Circuits Symposium Slide 53 Zerbe : C7P5 Matched Source Synchronous y Clocking-MSSC g • Transmit data DCDL to match Rx clock buffer delay • Switched receiver to windowed integrating sampler 2010 VLSI Circuits Symposium Slide 54 Zerbe : C7P5 MSSC Edge-Timing 2010 VLSI Circuits Symposium Slide 55 Zerbe : C7P5 MSSC Edge-Timing 2010 VLSI Circuits Symposium Slide 56 Zerbe : C7P5 MSSC & PSIJ Source Destination DATA 3 5 DCDL PLL/CLK BUFFER 1 CLK BUFFER 4 FWD CLK 2 • MSSC helps cancel source jitter at (2) but potentially adds PSIJ in DCDL (23) • Low-frequency L f PSIJ will ill track t k with ith destination d ti ti clock buffer (45) • Relative impacts must be studied 2010 VLSI Circuits Symposium Slide 57 Zerbe : C7P5 Common Mode Clocking g (CMC) ( ) • C Can b break k1 1:N N problem bl if we send d clock l k along with data in different mode • Potentially minimizes/eliminates receive distribution clock buffer • Results in multi multi-level level waveform 2010 VLSI Circuits Symposium Slide 58 Zerbe : C7P5 Common-Mode Clocking g Doublets D0 & Clk Dp Dn Dp - Dn = Data D1 & ClkB Dp + Dn = Clock • Complementary clocks over adjacent pairs • Makes CM clock extraction simple • Makes CM noise – in-common • Any CM termination mismatch static phase error (removed during calibration) • Design includes both CM clock and forwarded clock to allow for performance comparisons 2010 VLSI Circuits Symposium Slide 59 Zerbe : C7P5 Outline • • • • Introduction & motivation Matched source source-synchronous synchronous clocking Common-mode clocking D i Design • • • • Clock distribution & DCDL T Transmitter itt Integrating receiver Noise generation • Measured results • Conclusions C l i 2010 VLSI Circuits Symposium Slide 60 Zerbe : C7P5 DCDL : Trellis LSB < 1 Gate Delay y Input d1 = 4 LSB, d2 = 5 LSB 0 4, 5 d1, d2 d1, d2 8, 9, 10 d1 d2 d1, 12 13 12, 13, 14 14,15 15 20-24 d1 24-28 2010 VLSI Circuits Symposium Slide 61 6,7, and 11 Start at 12 16, 17, 18, 19, 20 d1,, d2 d1 Missing 1-3, • Use difference in delay to get resolution < 1 gate dly • CMOS for short / currentstarved inverters for long d l delays Zerbe : C7P5 Transmitter Incorporating g CM Clock • Segmented design • Adjustable between clock and data 2010 VLSI Circuits Symposium Slide 62 Zerbe : C7P5 CMC Transmitter Example DATA CLOCK DATA CLOCK P N P N 2010 VLSI Circuits Symposium Slide 63 Zerbe : C7P5 Integrating/Sampling g g g Receiver Design g Amp/Int switch A Common-gate amplifier dataout Linear Equalizer Integrate or Amplify p y Sampler • Integrator load switchable between cap/resistor • All Allows comparison i off integration/sampling modes • CTLE power efficient way of equalizing for ISI at high-speeds g p 2010 VLSI Circuits Symposium Slide 64 Zerbe : C7P5 PS Noise Generation Effect on output eye Noise measured at sense off on • Adjustable Vdd-Vss Clamp • • ‘noiseclk’ driving shorting clamp – observable at sense lines Set frequency to insight highest PSN from package/pwr package/pwr-gnd gnd network 300/305MHz @ 30mV used for testing 2010 VLSI Circuits Symposium Slide 65 Zerbe : C7P5 Outline • • • • Introduction & motivation Matched source source-synchronous synchronous clocking Common-mode clocking D i Design • • • • Clock distribution & DCDL T Transmitter itt Integrating receiver Noise generation • Measured results • Conclusions C l i 2010 VLSI Circuits Symposium Slide 66 Zerbe : C7P5 Two Device MSSC SJ & PSIJ Testing g • Configurations SER • 6 Bi-directional links/device Tx Freq gen for PSIJ Tx VER 16 M SAMP Rx DES • 3 Bi-directional clocks/device BERT w/SJ* • Devices fi d in i configured parallel loopback for data generation 2010 VLSI Circuits Symposium Slide 67 Tx Clk VER T Tx Tx VER SERVC 16 Clock With Jitter PRBS M PRBS *SJ 300MHz Equipment limit Rx SAMP DES Zerbe : C7P5 DCDL Delay y vs. Code & Filtering g Raw results vs. simulation Results after code filtering • Raw DNL/INL not as critical as code filtered INL • DCDL code only updated during re-calibration 2010 VLSI Circuits Symposium Slide 68 Zerbe : C7P5 Integrating g g / Sampling g Rx Sensitivity y Sampling Integrating (variable window) 0.87 UI 0.90 UI 0 93 UI 0.93 BER PRBS7 Input Eye Opening (mVpp) • Integrating I t ti receiver i is i superior, i with ith proper windowing i d i 2010 VLSI Circuits Symposium Slide 69 Zerbe : C7P5 MSSC & SJ Measured Results @ 5Gbps Integrating Sampling 1E+00 BER R 1E-03 1E-06 1E-09 50 100 150 200 250 50 Time (ps) Sample BER Integrate BER No SJ, no MSSC (91/110ps) 100 150 200 250 650 Time (ps) Sample BER Integrate BER 300MHz 0.3UI SJ, no MSSC 700 750 800 850 Time (ps) Sample BER Integrate BER 300MHz 0.3UI SJ, with MSSC (47/45ps) MSSC shows ~2× improvement 2010 VLSI Circuits Symposium Slide 70 (94/113ps) Integrating g g shows 20% improvement Zerbe : C7P5 Sampled Rx : SJ & PSIJ @ 5Gbps No SJ or PSIJ 1E+0 With SJ With SJ Big MSSC benefit (SJ & no SJ ~identical) (SJ & no SJ identical) 1E‐3 1E‐6 1E‐9 1E+0 0 200 400 600 800 200 400 600 800 200 400 600 800 1E 3 1E‐3 1E‐6 1E‐9 1E+0 0 1E‐3 1E‐6 1E‐9 1E 9 0 2010 VLSI Circuits Symposium Slide 71 With PSIJ DCDL PSIJ sensitivity is not huge With both SJ & PSIJ With SJ & PSIJ, With SJ & PSIJ MSSC is required to open the eye to open the eye Delay (ps) 300mUI SJ, 30mV PSIJ Zerbe : C7P5 Integrating g g Rx : SJ & PSIJ @ 5Gbps No SJ or PSIJ 1E+0 With SJ Strong MSSC jjitter benefit 1E 3 1E‐3 1E‐6 1E‐9 BER 1E+0 0 200 400 600 800 With PSIJ Moderate PSIJ margin impact 1E 3 1E‐3 1E‐6 1E‐9 1E+0 0 200 400 600 800 200 400 600 800 1E‐3 1E‐6 1E‐9 1E 9 0 2010 VLSI Circuits Symposium Slide 72 Delay (ps) With both SJ & PSIJ MSSC net win w/both MSSC net win 80ps margin vs. 10ps IntRx 30% more 30% more margin than sampled Zerbe : C7P5 300mUI SJ, 30mV PSIJ CM Clocking g : Modal Conversion (3Gbps) ( ) No CMCLK With CMCLK Data Jitter: only 38mUI increase for CM clocking No PRBS7 With PRBS7 Clock Jitter*: only 15.4mUI 15 4mUI increase in jitter when running PRBS7 2010 VLSI Circuits Symposium Slide 73 *As measured on looped back clock output Zerbe : C7P5 CMC Margins @ 4Gbps 1E+00 BER 1E-03 1E-06 1E-09 10 60 110 160 Time (ps) 210 No MSSC, MSSC with SJ + PSIJ 54ps 2010 VLSI Circuits Symposium Slide 74 260 490 540 590 640 Time (ps) 690 740 With MSSC, MSSC with SJ + PSIJ 106ps Zerbe : C7P5 Low Power : Enabling g Duty-Cycling y y g Improved DCDL vs. PhaseMixer @6.4Gbps PhMix • Neither MSSC or CMC save power themselves… and are not too expensive • • • • DCDL vs. Phase-Mixer : similar in many y ways, y , can be more efficient at lower codes • • • They enable Th bl more effective ff ti architectures hit t with ith power duty-cycling d t li in i low-power l li k links CM Clocking enables fine-grain (2 bit) enabling / disabling Current test silicon @ 5mW/Gbps due primarily to many un-optimized test options With MSSC no longer need phase mixer for pin-pin variation Opportunities for sharing DCDL delay between pins CMClk • CM-clocking of 2:1 (1 CM doublet vs. forwarded clock) : ~ equal power at 2:1 ratio 2010 VLSI Circuits Symposium Slide 75 Zerbe : C7P5 Conclusions • Matched Source-Synchronous Clocking (MSSC) has promise for high-source-jitter high source jitter environments • Especially with Integrating Receiver • With PSIJ & SJ only MSSC passes @ 5Gbps • Common-Mode Clocking shows promise Systems S t where h additional dditi l pin i costt is i prohibitive hibiti • F Future low-power l li k will links ill need d to consider multiple clocking approaches to achieve hi low l power and d fast f t duty-cycling d t li 2010 VLSI Circuits Symposium Slide 76 Zerbe : C7P5 ECE 733 Class Notes References 1. 2 2. 3. 4. 5. 6. 7 7. 8. 9. 10 10. 11. 12. 13. 14. 15. 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G Gary S Steven M Murdock, d k “Self-Clocked “S lf Cl k d T Two-Level L l Differential Diff i l signaling i li methods h d and d apparatus”, US patent 7535964 B2. Ali Hajimiri and Thomas H. Lee, The Design of Low Noise Oscillators, Springer, 1999. Behzad Razavi, Design of Analog CMOS Integrated Circuits, MCGrawHill, 2001. Behzad Razavi, Razavi Monolithic Phase-Locked Phase Locked Loops and Clock Recovery Circuits: Theory and Design, Wiley-IEEE Press, 1996. Behzad Razavi, Phase-Locking in High-Performance Systems: From Devices to Architectures, Wiley-IEEE Press, 2003. Floyd y M. Gardner,, Phaselock Techniques, q , 3rd Edition,, Wiley, y, 2005. Introduction to Jitter: http://www.analogzone.com/nett0927.pdf Jitter center on Agilent: http://www.home.agilent.com/agilent/industry.jspx?nid=536900074.0.00&cc=US&lc=eng Dual-Dirac Model htt // http://www2.tek.com/cmswpt/tidetails.lotr?ct=TI&cs=wpp&ci=12838&lc=EN 2t k / t/tid t il l t ? t TI& & i 12838&l EN ©2011, Dr. Lei Luo 77
