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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 3, MARCH 2004
Enhanced Tuning Efficiency in Tunable Laser Diodes
Using Type-II Superlattices
G. Rösel, T. Jacke, M. Grau, R. Meyer, and M.-C. Amann, Senior Member, IEEE
Abstract—We propose a type-II AlGaAsSb–AlGaInAs heterostructure superlattice for improved electronically tunable laser
diodes exploiting the free-carrier plasma effect. In electronically
tunable laser diodes, commonly type-I heterostructure diodes
(e.g., GaInAsP–InP) are used as tuning region; however, at equal
tuning, the type-II heterostructure superlattices provide the
advantage of significantly smaller recombination rates due to
the spatial separation of electrons and holes. As a consequence,
the required tuning currents can be reduced and the maximum
achievable carrier density in an optimized type-II diode can be
enhanced by about a factor of two.
Index Terms—Charge carrier lifetime, semiconductor lasers,
semiconductor superlattices, tuning.
Fig. 1. Schematic band diagram of the type-II diode.
TABLE I
DETAILS OF THE TYPE-II MBE-GROWN LAYER STRUCTURE
I. INTRODUCTION
E
XPLOITING the free-carrier plasma effect, carrier injection is extensively used to electronically change the refractive index of a waveguide and, thus, for the wavelength tuning
of 1.55- m tunable laser diodes [1]. Generally, a p-i-n type-I
double heterostructure junction forms a waveguide, where carriers are injected into the intrinsic region. These injected carriers cause a refractive index reduction proportional to the excess carrier density. However, with increasing injection current
the recombination rate is also increased and, therefore, the excess carrier density saturates at high injection [2]. Furthermore,
a sustained current is needed for the carrier injection and an undesired heat generation occurs with the carrier recombination.
This additional temperature increase causes a refractive index
change, which counteracts the one induced by the free carriers
[3]. Important laser characteristics like the threshold current
and the optical power output also suffer from tuning-induced
heating. Thus, the tuning efficiency as well as the overall laser
performance can be considerably improved by a suppression of
the recombination of the electron-hole pairs in the tuning region.
Previously, it has been suggested [4] that the application of a
spatially indirect semiconductor in the tuning region could effectively reduce the recombination rate and, consequently, the
tuning current for a given carrier density. This spatially indirect
semiconductor could be realized by a type-II superlattice composed of AlGaAsSb–AlGaInAs layers [5].
For a comparative study of type-I and type-II diodes, we have
employed the impedance measurements [6] to determine accurately the recombination rate via the differential carrier lifetime
as a function of the tuning current.
Manuscript received November 12, 2003; revised November 22, 2003. This
work was supported by the Deutsche Forschungsgemeinschaft.
The authors are with the Walter Schottky Institute, Technical University of
Munich, D-85748 Garching, Germany (e-mail: roesel@wsi.tum.de).
Digital Object Identifier 10.1109/LPT.2004.823753
TABLE II
PARAMETERS
II. DEVICE STRUCTURE
The energy band diagram of the InP-based type-II diode is
schematically shown in Fig. 1. A detailed description of the
layer sequence grown by a solid-source molecular beam epitaxy
(MBE) is given in Table I. Since due to the lower mass, mainly
the electrons tunnel into the barrier and recombine therein with
the holes [7], a larger offset in the conduction band is preferred
for an efficient suppression of recombination. Therefore, the
bandgap of the AlGaInAs layer (1.19 eV) was chosen to be
smaller than the bandgap of the AlGaAsSb (1.3 eV). The type-II
was found to be 0.89 eV. Then, the band
emission energy
can be estimated by the expression
offset
(1)
where
and
are the ground subband level of the
electrons and holes, respectively. A similar equation holds for
. Using the material parameters described in Table II, a
conduction band offset of 455 meV and a valence band offset
of 345 meV were derived. Additionally, a standard type-I diode
was grown by chemical beam epitaxy consisting of intrinsic
eV). The detailed layer sequence is listed
GaInAsP (
in Table III.
1041-1135/04$20.00 © 2004 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004
311
GaAs-MISFETs With Insulating Gate Films Formed
by Direct Oxidation and by Oxinitridation of
Recessed GaAs Surfaces
Masahide Takebe, Kazuki Nakamura, Narayan Chandra Paul, Koichi Iiyama, Member, IEEE, and Saburo Takamiya
Abstract—Direct oxidation by an ultraviolet (UV) and ozone
process and oxinitridation (plasma nitridation after oxidation) of
GaAs surfaces were used to form nanometer-scale gate insulating
layers for depletion-type recessed gate GaAs-MISFETs. The drain
current–drain voltage characteristics of the oxide gate devices exhibit lower transconductance (max. 40 mS/mm), lower breakdown
voltage and smaller gate capacitance than the oxinitrided gate devices. The presence of hysteresis in the oxide gate devices is also
apparent. The maximum transconductance of the oxinitrided gate
devices is 110 mS/mm and they have a sharper pinch-off, compared
to the oxide gate devices. In addition, no hysteresis is observed in
their current voltage curves. The current gain cutoff frequency of
1.4 m gate-length FETs for both types is 6 GHz. These results correspond well with results obtained from characterization of these
insulating films.
Index Terms—Field-effect transistors (FET), GaAs, metal–insulator–semiconductor (MIS), nitridation, oxidation.
I. INTRODUCTION
I
T IS WELL known that for the gate structure of a field-effect
transistor (FET), a metal–oxide–semiconductor (MOS) or
metal-insulator-semiconductor (MIS) is essentially superior to a
Schottky barrier. The availability of enhancement-type devices,
the fact that they can be operated using a single source of power,
the possibility of high temperature operation and the attribute of
scalability, etc. are all features which maintain this superiority.
However, due to complex and unsolved surface/interface related
problems, compound semiconductor MIS gate devices have not
yet been realized commercially. Deposition of insulator materials and the conversion of semiconductor surfaces into insulating layers have been studied by many researchers in order
to realize a reliable MIS gate compound semiconductor device
with good performance. As for the deposition method, Ga O
[1], Ga O (Gd O ) [2], wet chemical SiO [3], Si N after the
formation of a Si interface control layer [4], etc. have been reported. These form 10–40-nm-thick insulating layers and good
electrical performance has been reported. In this paper, we have
studied the conversion method, because this method utilizes the
inherent properties of the mother material, and therefore gives
rise to the possibility of realizing an essentially reproducible
process, once an appropriate combination of semiconductor maManuscript received Sept. 17, 2003; revised December 15, 2003. This work
was supported under a grant from the Ministry of Public Management, Home
Affairs, Posts and Telecommunication. The review of this paper was arranged
by Editor C.-P. Lee.
The authors are with Kanazawa University, Kanazawa, Japan.
Digital Object Identifier 10.1109/TED.2003.823049
terials, gases and process conditions have been found that gives
an insulator with a good insulator/semiconductor (I/S) interface and good performance. However, the flexibility in material
choice and the applicable process techniques of this method are
very limited.
We have reported that an ultraviolet radiation and ozone (UV
and ozone) process forms a nanometer scale GaAs oxide layer
that can suppress leakage current [5]. The thickness of this layer
is proportional to square root of the process period. We also reported that GaAs-MOSFETs and InAlAs/InGaAs-MOSHEMTs
with such oxide layers could be operated even beyond their flatband voltage [6]–[8], although dips in transconductance and the
hysteresis were apparent in their current–voltage (I–V) curves.
In order to overcome these problems, we studied the effect of
nitridation upon bare and oxidized GaAs wafers from the points
of view of the crystallographic structure near the interface and
the electrical and photoluminescence performance. Hara et al.
reported improved capacitance–voltage (C–V) characteristics of
an oxidized GaAs-MIS diode by subjecting it to a helicon-waveexcited N plasma treatment [9], although Trivedi et al. reported
on N plasma damage of an AlGaAs–InGaAs–GaAs system
[10]. Our experimental results demonstrate that N plasma nitridation after the UV and ozone oxidation forms a good quality
GaAs-insulator interface with very little crystallographic disorder and improves both the electrical and the photoluminescence performance [11]–[13]. In order to check whether the beneficial effect of the N plasma nitridation is reproduced in a device fabrication process, we simultaneously fabricated GaAsMOSFETs (oxidation by UV and ozone only) and GaAs-MISFETs (N plasma after the UV and ozone oxidation) and compared their performance.
Firstly, in this paper, the effects of nitridation upon oxidized
(100) GaAs surfaces are briefly reviewed, then the structure,
fabrication process, ant the dc and RF characteristics of
GaAs-MISFETs are described and compared with GaAs-MOSFETs.
II. EFFECTS OF NITROGEN PLASMA
Nitrogen plasma severely damages the surface properties
when it is applied to a bare GaAs surface, but it improves the
interface properties when applied to an oxidized GaAs surface
(becoming an nitrided oxide surface). The details of this are
described in our previous papers [11]–[13].
Fig. 1 shows a cross-sectional transelectron microscope
(TEM) image at the interface of oxinitrided GaAs, observed
0018-9383/04$20.00 © 2004 IEEE
312
Fig. 1. TEM image of an oxinitrided GaAs/(100)n-GaAs structure observed
from the h110i direction.
Fig. 2. (a) Measured 1=C –V characteristics of MIS diodes with insulating
layers formed by oxidation for 8 h and (b) nitridation for 4 h after 8 h oxidation
.
from
direction. This was formed by nitridation for 8
h in a N plasma (RF power 250 W, N flow rate 10 sccm)
after oxidation for 8 h by an UV and ozone process at room
temperature. The insulating layer thickness is about 8 nm.
Very little crystallographic disorder and good interface flatness are observed. These characteristics are very effective in
preventing the development of disorder related interface states
and reducing electron scattering at the interface. The flatness
is mainly realized by the long oxidation time rather than by
the effect of nitridation. The oxidized GaAs layer is composed
of Ga-oxide (mainly Ga O ) which contains an amount of
As-oxide (mainly As O ). The nitridation process drives out
the As and incorporates N in the GaAs-oxide layer changing
it into a GaON layer with GaN especially near the interface.
Moreover, the crystallographic order of the GaAs surface
improves suggesting a decrease in the density of defects near
the I/S interface. This accords well with the increased photoluminescence intensity of the oxinitrided surface compared to
a simply oxidized surface. In nitridation of an oxidized GaAs
layer, the N plasma energy probably has an effect similar to
annealing on the GaAs layer beneath the interface. The reverse
leakage current of a MIS diode decreases with nitridation.
Nitridation also improves the - characteristics of the diodes
in two respects. As these are directly related to a description
of the dc and RF performance of the GaAs-MISFETs, they are
shown in Fig. 2.
–V relationship is generally used to find the barThe
rier height of a Schottky junction rather than a MIS junction.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004
Fig. 3. Nitridation period dependence of flatband voltage obtained from
1=C –V characteristics.
However, as the insulator of our sample is very thin and negligibly small, compared to the depletion layer in reverse bias,
the relationship holds even for a MIS diode and can be applied
to obtain the flatband voltage. This is found by extrapolating
–V curve and finding the point
the linear portion of the
at which this intercepts the voltage axis. The curve of a simply
V and the
oxidized sample has two bends, one at around
other at around
V. On the basis of the first bend the barrier height or flatband voltage of the oxidized sample is low (0.5
V). After 4 h of nitridation, the first bend completely disappears
V, which is similar to
and the flatband voltage increases to
previously reported values (0.8–1.1 eV) of Ni/n-GaAs Schottky
barrier heights, suggesting a decrease in the positive I/S interface charge by nitridation. The dependence of flatband voltage
on the nitridation time is shown in Fig. 3. This suggests that the
cm
oxidized samples initially have positive charge (
in the oxide or
cm at the interface [13]) which
is neutralized by nitridation. The second bend, after nitridation,
becomes sharper and shows a somewhat increased capacitance
even at higher frequencies. This reflects the improvement of the
I/S interface as explained by Passlack et al. [1]. The increase of
the capacitance at high frequencies looks insufficient. However,
as Xie et al. have demonstrated theoretically [14], even if the
high frequency capacitance is increased sufficiently, this may
mm, in our MIS diode
be due to a parasitic effect of an area (
samples) between a broad Ohmic contact and the MIS junction
(0.32 mm diameter).
III. STRUCTURE AND FABRICATION
GaAs-MISFETs were fabricated on n-/S.I GaAs (100)
wafers, of which the epitaxial layer thickness was 0.4 m
cm . After ultrasonic
and the donor density was
cleaning with acetone, the native oxide layer was removed by
etching in buffered hydrofluoric acid. The epitaxial layer was
etched down to 0.3 m in order that the step height of the
mesas in the later stages of the process would be reduced. The
samples were then rinsed in de-ionized water. Drain and the
source electrodes were formed by evaporating AuGe and Ni,
followed by sintering at 360 C for 2 min in N . After etching
,
the mesas in a GaAs etchant
the wafer was coated with photo-resist which was patterned to
define the gate areas. These areas were thinned to 0.18 m.
The etchant used to etch this recess was the same as that used
for the mesa etch. Oxidation of the sample was done by an
TAKEBE et al.: GaAs-MISFETs WITH INSULATING GATE FILMS FORMED BY DIRECT OXIDATION
313
Fig. 4. Cross-sectional structure of the a GaAs-MISFET.
Fig. 6. Measured
GaAs-MISFETs.
I –V
characteristics between the gate and source of
Fig. 5. Surface image of the fabricated GaAs-MISFET. (a) The whole area and
(b) the gate portion.
UV and ozone process at 100 C (SAMCO: UV and Ozone
Cleaner UV-1) and the nitridation was done in an N plasma
at room temperature (SANYU: SHR-708). The plasma system
was conditioned such that the RF power was 50 W and the N
flow rate was 10 sccm. Consequently, the oxinitrided layer was
formed only in the recessed region. The oxidation period was
fixed at 4 h and various nitridation periods of 0 h (hereafter
denoted as the 4-0h sample), 1 h (4-1h sample) and 2 h (4-2h
sample) were carried out depending on the wafers. Al was
deposited and the unwanted parts removed by lift-off to leave
only the gate electrodes. The cross-sectional structure of a
fabricated GaAs-MISFET is shown in Fig. 4 and photographs
of the surface are shown in Fig. 5. The gate width is 80 m (40
m 2) and the gate length is 1 m (designed).
In the above process, the photoresist for the gate pattern was
used to define the area for four successive process steps; these
were the recess etch, the oxidation, the nitridation and the gate
electrode. This minimizes the possibility of contamination, automatically restricts the influence of the oxinitridation to within
the recessed portion and self-aligns the electrode to the insulator
as shown in Fig. 4. Both of the UV and ozone process and the
N plasma process ashes and thins the photo-resist. This, on the
one hand implies that these are clean processes, but on the other
restricts the operating conditions of the oxidation and nitridation
systems so that the resist remains usable for the lift-off process.
The RF power (50 W) of the treatment is much lower than that
(250 W) used in our previous experiment [13].
IV. DC CHARACTERISTICS
The MIS diode characteristics between the gate and the
source of GaAs MISFETs with different nitridation periods
are shown in Fig. 6. The thickness of the insulating layer was
estimated to be 6–8 nm from the oxidation time dependence
of the oxide thickness [5], and it is not significantly altered by
nitridation. The leakage current in the low reverse bias region
is decreased depending on the nitridation time. The leakage
Fig. 7. Normalized dc characteristics of 1 m GaAs-MISFETs for the (a) 4-0h
and (b) 4-2h samples.
currents of nitrided samples were suppressed by up to three
orders of magnitude compared to ones with simple oxide gates.
The higher gradient of the reverse leakage current of the 4-2h
sample in the high negative voltage region suggests generation
of an inversion layer due to an improved barrier effect against
holes. On the other hand, the small change in the low forward
voltage region suggests that the barrier height of GaON against
conduction band electrons is not so high. In the high forward
voltage region, the 1h-nitridation sample exhibits a smaller
current than the 2h-nitridation sample. This may be due to
poorer Ohmic contact.
Fig. 7 shows the drain current versus drain voltage ( – )
characteristics of the 1- m gate length (a) 4-0h and (b) 4-2h
samples measured using a semiconductor parameter analyzer
(Hewlett Packard: HP 4156A). The gate bias was changed from
to
V in 0.5 V steps. In the (a) 4-0h sample , the pinchoff
is not good and a slight decrease in the transconductance is observed around the flatband voltage, similar to the GaAs MOSFETs, which we reported in 2002 [8], implying the existence of
interface states. However, in the (b) 4-2h sample, the pinchoff
is improved and a higher transconductance is realized. This indicates that the interface states are significantly reduced by 2 h
of nitridation. Moreover, the drain-source resistance and the saturation voltage are decreased, suggesting that the gate voltage
dependence of the depletion layer is increased partly due to recovery of the damaged layer.
–
characteristics of 1- m gate length
Fig. 8 shows
GaAs-MISFETs (different samples from those shown in Fig. 7)
during the drain voltage swing-up and swing-down processes.
The simply oxidized sample has large hysteresis loops. In the
negative gate bias region, the change in the gate voltage by
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004
Fig. 8. Hysteresis curves of 1-m GaAs-MISFETs for the (a) 4-0h and (b)
4-2h samples.
Fig. 10.
Fig. 9. Measured breakdown drain voltages of 3-m gate length
GaAs-MISFET at V = 2 V.
Fig. 11. RF characteristics of 1-m GaAs-MISFETs for the (a) 4-0h and (b)
4-2h samples.
hysteresis is comparable to the flatband voltage improvement
of 0.6 V by nitridation (Fig. 3). This results in an inaccurate
transconductance when it is taken from the dc curves such as
those in Fig. 7(a). On the other hand, the nitrided sample shows
no hysteresis loops. This also implies that the former has a
high density of traps and/or mobile ions near the interface or
in the oxide layer, and that these are drastically reduced by
nitridation.
Fig. 9 shows the measured drain breakdown voltages of 3- m
V. The breakgate length GaAs-MISFETs at a gate bias of
down voltage of the 4-0h sample is about 6 V and that of the
4-2h sample is 10 V. This improvement may also be due to the
reduced crystallographic disorder brought about by nitridation.
The gate voltage dependence of the transconductance of the 1
m GaAs-MISFETs with different nitridation times, at a drain
voltage
of 5 V are shown in Fig. 10. It is quite obvious that
the peak value of the transconductance increases with nitridation and that the pinch-off voltage is clear. One h of nitridation
is insufficient and 2 h is not quite sufficient to minimize the interface problem. This agrees well with the previous experiment
(Fig. 3) in spite of the different radio frequency (RF) powers.
The simply oxidized sample has a maximum transconductance
of 60 mS/mm, however this is not an accurate measurement due
to the above mentioned hysteresis, and the data suggests that the
actual transconductance is about 40 mS/mm with the base line
shifted up by about 20 mS/mm due to hysteresis. The sample
nitrided for 2 h has a peak transconductance of 110 mS/mm at
of 1.1 V, which coincides with the flatband
a gate voltage
voltage obtained in Fig. 3. This coincidence is very important,
because it implies that the device has no extra charge, neither in
the insulator nor at the interface. On this point, the 4-2h sample
has an ideal I/S interface.
0
Measured transconductances of 1-m gate length GaAs-MISFETs at
V = 5 V with different nitridation times after 4 h oxidation.
V. RF CHARACTERISTICS
parameters of the samples from 500 MHz to 40 GHz were
measured with a network analyzer (Hewlett Packard: 8722D).
The frequency dependence of the maximum available gain
(MAG), the maximum stable gain (MSG), the unilateral gain
and the stability
(U), the square of the absolute value of
parameters, are shown in
factor K, all obtained from the
V,
V. The
Fig. 11. The bias voltages are
and the maximum oscillation
current gain cutoff frequency
frequency
are estimated to be
GHz,
GHz for both samples. The gate voltage dependence of
and
the transconductance of the 1- m gate length (measured value
1.4 m) GaAs-MISFET 4-2h sample are shown in Fig. 12. The
maximum
is observed at the peak transconductance.
The 4-0h and the 4-2h samples showed nearly equal RF performance despite the increase in the transconductance after nitridation. This suggests that nitridation causes an increase in the
capacitance, because the current gain cutoff frequency is given
and the gate-to-source
by the transconductance divided by
capacitance. The capacitances calculated from measured
parameters at 10 GHz with the bias condition of
V
are shown in Fig. 13. The 4-2h sample has 2–3 times larger capacitance than the 4-0h sample. This is in contrast to the results
shown in Fig. 2, where the capacitance of the nitrided MIS diode
is nearly equal to that of the simply oxidized MIS diode in the
high-frequency region (1 MHz). However, this contradiction is
TAKEBE et al.: GaAs-MISFETs WITH INSULATING GATE FILMS FORMED BY DIRECT OXIDATION
Fig. 12. Gate voltage dependence of f and g
MISFET for the 4-2h sample.
315
of the 1-m gate length GaAs
Fig. 14. (a) Equivalent MIS capacitance with an oxidized interface and (b) an
oxinitrided interface.
Fig. 13. Gate voltage dependence of the capacitances of 1-m gate length
GaAs-MISFETs from the S parameters.
explained by the theory developed by Xie et al. [14]; the parasitic effect of the area between the MIS junction and the Ohmic
contact of the MISFET is very small compared to that of the
mm), and thus the increase in capacitance by
MIS diode (
nitridation is observed directly in the FET. Nitridation increases
reboth the transconductance and the capacitance, but the
mains unchanged. As shown in Fig. 14(a), the total capacitance
of the gate MIS junction of the 4-0h sample consists of the insulator capacitance , the depletion layer capacitance , the
and the interface state capacdeteriorated layer capacitance
itance , where the resistance , in combination with , determines the time constant of the charge/discharge process of
the interface states.
Fig. 15 shows an energy band diagram across the MIS portion of the 4-0h sample. The deteriorated layer may be like an
O doped semi-insulating semiconductor and contains positive
– curves
charges as suggested by the first bend in the
[13]. The increase in drain current in the positive gate voltage
region far beyond the flatband voltage [Fig. 7(a)] suggests the
existence of a high potential energy layer beneath the gate insulator only, outside of which the whole n-layer is normal. Obviously, the latter limits the maximum available drain current.
Remarkably, although not perfectly, nitridation converts the de, but deteriorated layer into a normal layer and increases
and
as shown in Fig. 14(b). This is the main
creases
reason for the increased capacitance as well as the increase in
the transconductance. An additional reason may be the increase
in the dielectric constant of the insulator. Nitridation increases
by changing the GaAs-oxide into GaON, a similar effect to
to Si N
in silicon
that of changing SiO
Fig. 15.
sample.
Energy band diagram across the MIS portion of the simply oxidized
does not respond at microwave frequentechnology. Since
and
are observed in
. Thus,
cies, only the changes of
the capacitance at 10 GHz, especially in the forward bias region,
and .
is increased by nitridation, reflecting the increase of
VI. CONCLUSION
We have demonstrated GaAs-MISFETs with an oxinitrided
gate insulating layer formed by a combination of UV and
ozone oxidation process and a N plasma nitridation process in
order to solve the problems associated with GaAs-MOSFETs
reported in [8]. The oxinitrided gate device (GaAs-MISFET)
exhibited smaller leakage current than the simple oxide gate
device. Furthermore, it showed good pinch-off, no hysteresis,
higher breakdown voltage and higher transconductance (110
mS/mm) with no dip at the flatband voltage, suggesting the
existence of very little interface charge. This concurs with
previous investigates of the structural and electrical properties
of the oxinitrided n-GaAs layers. However, the GaAs-MISFET
and GaAs-MOSFET showed a nearly equal current gain cutoff
frequency of 6 GHz and a maximum oscillation frequency of
10 GHz. This is due to the increased capacitance.
In this experiment, in order to minimize thinning of the photoresist, an RF power of 50 W was used for exciting the N plasma,
which is much lower than that used in our previous experiment
[13]. The authors have not yet found the optimum nitridation
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 3, MARCH 2004
period under such low power conditions. However, the coincidence between the gate voltage for the maximum transconductance (Fig. 10) and the flatband voltage suggests that a period of
2 h is not far from the optimum. When a plasma is applied to a
wafer that is covered with a thin insulator, the insulator buffers
the radical bombarding effect of the plasma and partly changes
the effect into an annealing effect. The former causes deterioration of a semiconductor surface, but the latter possibly improves
it. This deterioration/improvement ratio may depend on the insulator thickness and the plasma power; i.e., a lower power is
preferable for the case of a thin insulator.
[12] N. C. Paul, D. Tezuka, T. Inokuma, K. Iiyama, and S. Takamiya, “Effect
of oxidation and/or nitridation of (100) n-GaAs surface,” in Proc. Workshop on Fundamentals and Applications of Advanced Semiconductor
Devices, 2002, p. 253.
[13] N. C. Paul, K. Nakamura, M. Takebe, A. Takemoto, T. Inokuma, K.
Iiyama, S. Takamiya, K. Higashimine, N. Ohtsuka, and Y. Yonezawa,
“Structural and electrical characterization of oxidated, nitridated and
oxi-nitridated (100) GaAs surfaces,” Jpn. J. Appl. Phys., vol. 42, pp.
4264–4272, 2003.
[14] Y. G. Xie, K. Takahashi, H. Takahashi, J. Chao, S. Kasai, and H.
Hasegawa, “Surface passivation of epitaxial multi-layer structures for
InP-based high speed devices by an ultrathin silicon layer,” in IEICE
Tech. Dig., vol. J84-C, 2001, p. 872.
ACKNOWLEDGMENT
The authors would like to thank Prof. N. Ohtsuka and K. Higashimine, JAIST for the TEM images.
Masahide Takebe was born in Toyama, Japan, in 1980. He received the B.E.
degree in electrical and computer engineering from Kanazawa University,
Kanazawa, Japan, in 2003.
His current research interest is the development of MISFETs/MISHEMTs.
REFERENCES
[1] M. Passlack, M. Hong, E. F. Schubert, G. J. Zydzik, J. P. Mannaerts, W.
S. Hobson, and T. D. Harris, “Advancing metal-oxide-semiconductor,
theory: Steady-state nonequilibrium condtions,” J. Appl. Pys., vol. 81,
no. 11, pp. 7647–7661, 1997.
[2] F. Ren, M. Hong, W. S. Hobson, J. M. Kuo, J. R. Lothian, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, “Demonstration of enhancement-mode p- and n-channel GaAs MOSFETs with
Ga O (Gd O ) as gate oxide,” Solid-State Electron., vol. 41, no. 11,
pp. 1751–1753, 1997.
[3] M. P. Houng, Y. H. Wang, C. J. Houang, S. P. Huang, and J. H. Houng,
“Quality optimization of liquid phase deposition SiO films on gallium
arsenide,” Solid-State Electron., vol. 44, pp. 1917–1923, 2000.
[4] Y. G. Xie, S. Kasai, H. Takahashi, C. Jiang, and H. Hasegawa, “A novel
InGaAs/InAlAs insulated gate pseudomorphic HEMT with a silicon
interface controllayer showing high, DC- and RF-performance,” IEEE
Electron Device Lett., vol. 22, pp. 312–314, July 2001.
[5] T. Sugimura, T. Tsuzuku, T. Katsui, Y. Kasai, T. Inokuma, S. Hashimoto,
K. Iiyama, and S. Takamiya, “A preliminary study of MIS diodes
with nm-thin GaAs-oxide layers,” Solid-State Electron., vol. 43, pp.
1571–1576, 1999.
[6] Y. Kita, Y. Ohta, N. C. Paul, K. Iiyama, and S. Takamiya, “Depletion
and accumulation mode operation of GaAs MISFETs with nm-thin gate
insulating layers formed by UV & ozone,” in Proc. Int. Symp. Compound
Semicond., Tokyo, Japan, 2001, p. 56.
[7] M. Nasuno, K. Nakamura, Y. Yamamura, K. Iiyama, and S. Takamiya,
“Enhancement and accumulation mode operation of GaAs MISFETs
and InAlAs/InGaAs MISHEMTs with nm-thin gate oxide layers,” in
Proc. Int. Conf. on Solid-State Devices and Materials, Nagoya, Japan,
2002, p. 506.
[8] K. Iiyama, Y. Kita, Y. Ohta, M. Nasuno, S. Takamiya, K. Higashimine,
and N. Ohtsuka, “Fabrication of GaAs MISFET with nm-thin oxidized
layer formed by UV & ozone process,” IEEE Trans. Electron Devices,
vol. 49, pp. 1856–1862, Nov. 2002.
[9] A. Hara, F. Kasahara, S. Wada, and H. Ikoma, “Effects of helicon-wave
excited N plasma treatment on fermi-level pinning,” J. Appl. Phys., vol.
85, no. 6, pp. 3234–3240, 1999.
[10] V. P. Trivedi, C. H. Hsu, B. Luo, X. Cao, J. R. Lorach, F. Ren, S. J.
Pearton, C. R. Abernathy, E. Lambers, M. Hoppe, C. S. Wu, J. Sasserath,
J. W. Lee, and K. Mackenzie, “The effect of N plasuma damage on AlGaAs/InGaAs/GaAs high electron mobility transistorts. I. dc characteristics,” Solid-State Electron., vol. 44, pp. 2101–2108, 2000.
[11] N. C. Paul, Y. Ohta, D. Tezuka, M. Nasuno, Y. Yamamura, T.
Inokuma, K. Iiyama, and S. Takamiya, “Quality improvement of
oxidized-GaAs/n-GaAs structure by nitrogen plasma treatment,” in
Proc. Indiurn Phosphide and Related Materials Conf., Stockholm,
Sweden, 2002, p. 217.
Kazuki Nakamura was born in Shiga, Japan, in 1978. He received the B.E.
degree in electrical and computer engineering from Kanazawa University,
Kanazawa, Japan, in 2002. He is currently pursing the M.E. degree in
electronics at Kanazawa University.
His research interest is the development of MISFETs/MISHEMTs.
Narayan Chandra Paul was born in South Tripura, Tripura, India, on April
14, 1973. He received the B.E. degree from Tripura University in 1996, and the
M.E. degree in electronics and computer science from Kanazawa University,
Kanazawa, Japan, in 2003, where he is currently pursuing the Ph.D. degree in
applied science.
Koichi Iiyama (M’95) was born in Fukui, Japan, on March 19, 1963. He received the B.E., M.E., and D.E. degrees in electronics from Kanazawa University, Kanazawa, Japan, in 1985, 1987, and 1993, respectively.
From 1987 to 1988, he was with Yokogawa Hewlett-Packard Ltd., Yokogawa,
Japan. Since 1988, he has been with the Faculty of Engineering, Kanazawa University, and now is an Associate Professor in the Department of Electrical and
Electronic Engineering. From 2001 to 2002, he was a Guest Scientist in Heinrich-Hertz-Institut für Nachrichtentechnik Berlin GmbH, Berlin, Germany. He
is now working in research on optical fiber science, high-speed photoreceivers,
and high-speed compound semiconductor devices.
Dr. Iiyama is a menber of the IEICE and the Japan Society of Applied Physics.
Saburo Takamiya was born in Tokyo, Japan, on March 1, 1943. He received the
B.E. degree in 1965 and the D.E. degree in 1977, both from the Tokyo Institute
of Technology.
From 1965 to 1996, he had been with Mitsubishi Electric Corporation, Itami,
Japan. From 1965 to 1967, he was a Visiting Research Scientist at the Semiconductor Research Institute of the Semiconductor Research Foundation, Sendai,
Japan.His main experiences are the development and production of optoelectronic and microwave semiconductor devices such as laser diode, photo detectors, microwave diodes, and microwave transistors. Since 1997, he has been a
Professor at Kanazawa University, Kanazawa, Japan.
Dr. Takamiya received the Yonezawa Memorial Young Engineer Award in
1975 and the Best Paper Award in 1976, both from the IEICE. He is a member
of the IEICE and the Japan Society of Applied Physics.
158
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 1, JANUARY 2004
TABLE III
THE DEVICE RF AND POWER CHARACTERISTICS COMPARISONS OF THE Al Ga
exhibits the same trend with their gate diode characteristics, where
the higher Al content devices present the lower gate leakage current,
and all leakage currents are increased by increasing the input rf
powers.
IV. CONCLUSION
In summary, the Alx Ga10x As=InGaAs (x = 0.3, 0.5, 0.7, 1)
DCFETs on GaAs substrates were fabricated and characterized. Based
on the experimental evaluations, we conclude that for the aluminum
content of Al0:5 Ga0:5 As, i.e. x = 0:5, is the best composition
to realize DCFETs in terms of device dc and RF characteristics.
Although higher Al content devices ( x = 0.7, 1) can further enhance
the Schottky diode performance; however, due to the inferior material
quality and higher parasitic resistance, the device characteristics
degrade. The dc peak extrinsic gm of Al0:5 Ga0:5 As/In0:15 Ga0:85 As
DCFETs is 272 mS/mm, together with an fT of 13 GHz and an fmax
of 25 GHz. As to the power performance at 2.4 GHz, it demonstrates
a 15-dBm saturated output power, a 16.5—dB linear power gain and
a 20% efficiency.
REFERENCES
[1] M. Kudo, M. Miyazaki, M. Mori, H. Ono, A. Terano, and Y. Umemoto,
“Pseudomorphic power HEMT with 53.5% power-added efficiency for
1.9 GHz PHS standard,” in Proc. Int. Microwave Symp. Tech. Dig., 1996,
pp. 547–550.
[2] J. L. Lee, H. Kim, J. K. Mun, H. G. Lee, and H. M. Park, “2.9 V operation
GaAs power MESFET with 31.5 dBm output power and 64% poweradded efficiency,” IEEE Electron Device Lett., vol. 15, pp. 324–326,
Sept. 1994.
[3] H. C. Chiu, S. C. Yang, and Y. J. Chan, “AlGaAs/InGaAs heterostructure doped-channel FETs exhibiting good electrical performance at high
temperatures,” IEEE Trans. Electron Devices, vol. 48, pp. 2210–2215,
Oct. 2001.
[4] B. Yang, Z. G Wang, Y. H Cheng, J. B Liang, L. Y. Lin, Z. P. Zhu, B. Xu,
and W. Li, “Influence of DX centers in the Al Ga
As barrier on the
low-temperature density and mobility of the two-dimensional electron
gas in GaAs/AlGaAs modulation-doped heterostructure,” Appl. Phys.
Lett, vol. 66, no. 11, pp. 1406–1409, 1995.
[5] Y. Bito, T. Kato, and N. Iwata, “Enhancement-mode power heterostructure FET utilizing Al Ga As barrier layer with negligible operation
gate current for digital cellular phones,” IEEE Trans. Electron Devices,
vol. 48, pp. 1503–1509, Aug. 2001.
[6] M. T. Yang and Y. J. Chan, “Device linearity comparisons between
doped-channel and modulation-doped designs in pseudomorphic
Al Ga As/In Ga As heterostructures,” IEEE Trans. Electron
Devices, vol. 43, pp. 1174–1180, Aug. 1996.
As=InGaAs DCFETs
Design of 50-nm Vertical MOSFET Incorporating a
Dielectric Pocket
D. Donaghy, S. Hall, C. H. de Groot, V. D. Kunz, and P. Ashburn
Abstract—A new architecture for a vertical MOS transistor is proposed
that incorporates a so-called dielectric pocket (DP) for suppression of shortchannel effects and bulk punch-through. We outline the advantages that
the DP brings and propose a basic fabrication process to realize the device.
The design issues of a 50-nm channel device are addressed by numerical
simulation. The gate delay of an associated CMOS inverter is assessed in
the context of the International Technology Roadmap for Semiconductors
and the vertical transistor is seen to offer considerable advantages down
to the 100-nm node and beyond due to the dual channels and the ability to
produce a 50-nm channel length with more relaxed lithography.
Index Terms—Dielectric pocket, short-channel effects (SCEs), Si devices,
vertical MOSFET.
I. INTRODUCTION
It is recognized that vertical transistors can overcome scaling problems due to lithography resolution, whereby decananometer channels
can be realized with relaxed lithography as the channel length is determined by the accuracy of ion-implantation or epitaxial growth. Vertical
transistors also allow double gate or gate all-around structures thus increasing current drive albeit at the expense of increased device capacitance. The architectures are however compact and hence give a high
drive with reduced footprint compared to an equivalent lateral architecture, as demonstrated in [1]. Much of the work reported previously
is concerned with discrete device fabrication often using fabrication
techniques that could not be easily integrated into an advanced CMOS
process [2]–[5]. We report here on a novel vertical transistor architecture incorporating a so-called dielectric pocket (DP) [6], [7] for control
of short-channel effects (SCEs). This concept was first demonstrated
successfully within a lateral architecture [8], but implementation in a
vertical architecture is considerably simpler. The structure is compatible with strategies reported previously to reduce parasitic capacitances
Manuscript received April 21, 2003; revised August 13, 2003. The work was
supported by U.K. EPSRC and the EU SIGMOS project. This review of this
paper was arranged by Editor R. Shrivastava.
D. Donaghy and S. Hall are with the Department of Electrical Engineering
and Electronics, University of Liverpool, Brownlow Hill, Liverpool, L69 3GJ,
U.K. (e-mail: s.hall@liv.ac.uk).
C. H. de Grott, V. D. Kunz, and P. Ashburn are with the Department of
Electronics and Computer Science, University of Southampton, Highfield,
Southampton, SO17 1BJ, U.K.
Digital Object Identifier 10.1109/TED.2003.821378
0018-9383/04$20.00 © 2004 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 1, JANUARY 2004
159
Fig. 1. Cross section showing the concept of the dielectric pocket vertical
MOST.
in the device [7], [9]. The objective of this communication is to demonstrate the use of a dielectric pocket to suppress short channel effects in
a vertical MOSFET, rather than other strategies such as pocket implantation. Furthermore, we demonstrate how the device could be designed
and made and assess its potential performance in the context of the International Technology Roadmap for Semiconductors (ITRS).
Fig. 2. Threshold voltage and offstate leakage current versus body doping
for 50 nm vertical MOSTs with and without dielectric pocket. The gate oxide
thickness was 2 nm.
II. DEVICE DESIGN AND PERFORMANCE APPRAISAL
The basic structure of the vMOST device concept is shown in Fig. 1.
The pocket serves a number of functions; it greatly reduces the influence of the large area parasitic bipolar transistor in the vertical structure, and also prevents encroachment of the doping from the extrinsic
drain, so reducing electrical bulk punchthrough effects. Furthermore, it
reduces charge sharing effects associated with the reverse biased drain
and so improves threshold control.
Referring again to Fig. 1, a basic process to realize such a device
could be as follows. Body regions are implanted for pMOS and nMOS
followed by growth of an oxide layer to form the DP. A layer of polysilicon is then deposited to form the extrinsic drain contact. This layer is
partly silicided to reduce drain resistance. The pillar is then etched with
overetching of the DP layer to undercut the poly-Si drain contact. A
blanket silicon epitaxial layer is then grown with continuity over the DP
edge realized because the epi can seed on the Si region under the DP
and also on the extrinsic drain poly-Si layer, because of the undercut
profile. This process is similar to that used in SiGe HBTs [10], where a
graft base is formed on the bottom face of an exposed polysilicon layer.
The gate oxide is then grown followed by gate electrode formation by
deposition of poly-Si followed by appropriate implant. Care is required
with the thermal budget to ensure that only slight out-diffusion occurs
from the extrinsic drain contact such that there is no encroachment of
drain dopant below the DP into the channel region. Such encroachment
would remove the electrostatic influence of the DP on the channel and
so mitigate its influence on the SCE. Note that dual channel operation is
achieved by the gate poly-contact running over the pillar width, which is
set to the minimum feature size to reduce drain/gate overlap capacitance.
The ISE device simulator was used to obtain electrical characteristics
for the DP vMOST. The Van Dort quantum correction model, hydrodynamic model, avalanche and band-to-band tunnelling were all switched
on to provide selfconsistent data for short-channel, highly doped
devices. The dielectric pocket thickness was set at 15 nm to minimize its
parasitic capacitance [7]. The gate oxide thickness was set at a conservative value of 2 nm. The body doping was then varied to produce electrical
characteristics for the pMOS with and without the DP, as summarized
in Fig. 2. Note that the threshold voltage VT was determined by linear
extrapolation of transconductance gm (VGS ) to zero [11] and the offstate
leakage current was taken as the current measured at VDS = 01 V
and VGS = 0 V. The leakage current is seen to be a minimum for a
(a)
(b)
Fig. 3. (a) Effect of the contact width W on the threshold voltage for
= 1 m, N
varied from
a p-channel vMOST, L = 50 nm, W
1 10 cm to 4 10 cm , V
= 1.0 V. (b) Effect of the contact
and I
for a p-channel vMOST, L = 50 nm, W =
width W on I
1 m, N
varied from 1 10 cm to 4 10 cm , V
= 1.0 V.
2
2
2
0
2
0
body doping of 3.0 21018 cm03 ; band-to-band tunnelling becomes
increasingly dominant beyond the minimum whereas punchthrough
causes the increase in leakage for lower doping levels. A body doping
of 2.4 21018 cm03 results in a threshold voltage of 00.28 V and a
leakage current of 1.5 nAm at a drain to source voltage of 01 V.
A further set of simulations was undertaken to investigate the influence of the spacing between the pocket and the gate oxide, referred
to as the contact region width WC on the threshold voltage and results are shown in Fig. 3. The DP serves to increase the magnitude of
160
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 1, JANUARY 2004
(a)
Fig. 5. Delay for DP vMOST versus technology node, compared to ITRS
roadmap values. Channel width for all devices = 1 m. vMOS channel
length = 50 nm. Circles are for ITRS and triangles show vMOS performance.
The arrows show the effect of adding a 5-fF load capacitor.
(b)
Fig. 4. Simulated vMOST dc characteristics for a p-channel DP = vMOST,
= 50 nm, W = 1 m, N
= 2:4 10 cm . (a) Transfer
characteristics, for V
= 0.1 V and 1.0 V. (b) Output characteristics.
L
0
0
2
threshold voltage because it inhibits charge sharing by the drain. For
WC = 50 nm, the VT equals that of the non-DP device indicating that
the DP no longer exerts electrostatic influence as WC is comparable to
the depletion width under the gate. Fig. 3(b) shows that decreasing WC
results in significant reduction in IOFF with little reduction in ION . For
example, for a substrate doping of 2 21018 cm03 and a pocket width
of 30 nm, the reduction in IOFF compared with no pocket is a factor
of 10 but the reduction in ION is only 5%. Thus the ION =IOFF ratio
is improved by a factor of 5. The slight reduction in ION arises from
the increase in VT because of the reduced charge sharing. The much
greater and beneficial reduction in IOFF arises from the suppression of
both drain induced barrier lowering and tunnelling as is also clearly evident on Fig. 2. Fig. 4 shows the simulated transistor characteristics and
a DIBL of 80 mV is apparent for a body doping of 2.4 21018 cm03 .
Repeating the simulations with a gate oxide thickness of 1.2 nm results
in a DIBL of 30 mV, IOFF = 1:5 nA= m, ION = 1:3 mA= m.
The vMOST inverter performance with 2 nm gate oxide was compared to equivalent minimum sized lateral CMOS inverters deduced
from ITRS 2001. The width of the pMOST, Wp was set to 2Wn . Parameters extracted from ITRS were Idd (saturation current), Cgate and
Cparasitic (intrinsic gate and overlap capacitances), equivalent electrical oxide thickness, and supply voltage, VDD . The delay was then
calculated using CT VDD =Idd where CT = Cgate + Cparasitic . For
the vMOST, the gate oxide was scaled, as was CT and VT using the
models of [7], [12], respectively. The simulation results of the 50-nm
channel device allowed for some calibration and selfconsistency.
It’s worth noting that the source and drain resistances of the vMOST
(extracted from ISE simulation) are three to four times smaller than
the ITRS values and this represents a further significant advantage
of the vMOST architecture. This advantage arises because the dielectric pocket precludes the need for pockets or extensions. These resistances do not significantly increase when the device is scaled. Fig. 5
serves to make the comparison with the roadmap using the delay metric
CT VDD =ION . The vMOS shows a clear advantage down to the 90-nm
node (note that the channel length of the vMOS is not scaled). Thereafter the performance deteriorates largely because of the reduced VDD .
The effect of maintaining VDD for the vMOST is shown also. It should
be noted that although CT is higher for the vMOST, the ability to
realize a 50-nm channel at coarser technology nodes produces a significant advantage over conventional lateral architectures. Beyond the
100-nm node, we can say that load capacitance due to interconnections will have a very dominant role and so the additional drive capability of the vMOS should continue to offer considerable advantage.
We demonstrate this by including a fixed load capacitance of 5 fF in the
calculation of delay. In this context, the smaller relative degradation in
performance of the vMOST compared with the ITRS roadmap demonstrates the potential of the latter device. Finally, it is worth noting that
we envisage no serious problem in scaling the device to 20-nm channel
length.
III. CONCLUSION
We have proposed and presented design details of a novel vertical
transistor architecture that offers good short channel control and drive
capability together with low off current. The off current can be reduced
without seriously compromising on current. The device can easily be
scaled without incurring high series parasitic resistances. Fabrication
would still be realized with existing tools. The use of a DP within a
vertical architecture therefore opens up a new design space for these
vertical transistors and allows greater flexibility than is afforded by
simple scaling of lateral MOSFETs.
REFERENCES
[1] T. Schulz, W. Rosner, L. Risch, A. Korbel, and U. Langmann, “Short
channel vertical sidewall MOSFETs,” IEEE Trans. Electron Devices,
vol. 48, pp. 1783–1788, Aug. 2001.
[2] V. R. Rao, F. Wittmann, H. Gossner, and I. Eisele, “Hysteresis behavior
in 85-mm channel length n-MOSFETs grown by MBE,” IEEE Trans.
Electron Devices, vol. 43, pp. 973–976, June 1996.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 1, JANUARY 2004
161
[3] J. Moers, D. Klaes, A. Tonnesmann, L. Vescan, S. Wickenhauseer,
M. Marso, P. Kordos, and H. Luth, “19 GHz vertical Si p-channel
MOSFET,” IEE Electron. Lett., vol. 35, pp. 239–240, 1999.
[4] J. M. Hergenrother et al., “The vertical replacement-gate (VRG)
MOSFET: A 50 nm MOSFET with lithography-independent gate
length,” in IEDM Tech. Dig., 1999, pp. 75–78.
[5] K. C. Liu, T. Chin, Q. Z. Lui, T. Nakamura, P. Yu, and P. Asbeck, “A deep
submicron Si/sub 1-x/Ge/sub/sub x/Si vertical PMOSFET fabricated by
Ge ion implantation,” IEEE Electron Device Lett., vol. 19, pp. 13–15,
Jan. 1998.
[6] A. C. Lamb, L. S. Riley, S. Hall, V. D. Kunz, C. H. de Groot, and P.
Ashburn, “A 50 nm vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket,” in Proc. ESSDERC, 2000, pp.
347–350.
[7] D. Donaghy, S. Hall, V. D. Kunz, C. H. de Groot, and P. Ashburn, “Investigating 50 nm channel length vertical MOSFETS containing a dielectric pocket in a circuit environment,” in Proc. ESSDERC, 2002, pp.
499–503.
[8] M. Jurczak, T. Skotniki, R. Gwoziecki, M. Paoli, B. Tormen, P. Ribot,
D. Dutartre, S. Monfay, and J. Galvier, “Dielectric pockets—A new concept of the junctions for deca-nanometric CMOS device,” IEEE Trans.
Electron Devices, vol. 48, pp. 1770–1774, Aug. 2001.
[9] V. D. Kunz, T. Uchino, C. H. de Groot, P. Ashburn, D. C. Donaghy,
S. Hall, Y. Wang, and P. Hemment, “Reduction of parasitic capacitance
in vertical MOSFETs by fillet local oxidation (FILOX),” IEEE Trans.
Electron Devices, vol. 50, pp. 1480–1487, June 2003.
[10] F. Sato, T. Hashimoto, and T. Tashiro, “Sub-20 ps ECL circuits with
high performance super self-aligned selectively grown SiGe base bipolar
transistors,” IEEE Trans. Electron Devices, vol. 42, pp. 483–488, Mar.
1995.
[11] M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch,
and M. Hirose, “Physically-based threshold voltage determination for
MOSFETs of all gate lengths,” IEEE Trans. Electron Devices, vol. 46,
pp. 1429–1434, July 1999.
[12] T. Skotniki, “Heading for decananometer CMOS—Is navigation among
icebergs still a viable strategy?,” in Proc. ESSDERC, 2000, pp. 19–33.
1514
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
High Sensitive and Wide Detecting Range MOS
Tunneling Temperature Sensors for On-Chip
Temperature Detection
Yen-Hao Shih, Shian-Ru Lin, Tsung-Miau Wang, and Jenn-Gwo Hwu, Senior Member, IEEE
Abstract—This paper examined the feasibility of applying a
highly sensitive metal–oxide–semiconductor (MOS) tunneling
temperature sensor, which was compatible with current CMOS
technology. As the sensor was biased positively at a constant
voltage, the gate current increased more than 500 times when
the sensor was heated from 20 C to 110 C. However, when the
sensor was biased at a constant-current situation, its gate voltage
magnitude changed significantly with substrate temperature,
with a sensitivity exceeding 2 V
C. The improvement of
temperature sensitivity in this paper is one thousand times over
the sensitivity of a conventional p-n junction, i.e., namely, about
2 mV C. Regarding a temperature sensor array, this paper
proposes a method using gate current gain, rather than absolute
gate current, to eliminate the gate current discrepancy among
sensors. For constant current operation, a sensitivity exceeding 10
V C can be obtained if the current level is suitable. Finally, this
paper demonstrates a real temperature distribution for on-chip
detection. With such a high temperature-sensitive sensor, accurate
temperature detection can be incorporated into common CMOS
circuits.
Index Terms—Metal–oxide–semiconductor (MOS) device, temperature sensor, ultrathin oxide.
I. INTRODUCTION
D
ECREASING feature sizes and increasing packaging densities have increased power densities in integrated circuits
(ICs), and decreased the reliability of these systems. Early detection of possible overheating problems can prevent system
malfunctioning due to irreversible damage caused by the increased temperatures. Thermal monitoring is extremely important in the case of safety-critical IC. Circuits used for the control of railway systems, space, aeronautics, and automotive critical functions require concurrent error detection for both tranManuscript received October 15, 2003; revised April 5, 2004. This work was
supported by the National Science Council, Taiwan, R.O.C., under Contract
NSC 92–2120-E-002–005. The review of this paper was arranged by Editor K.
Najafi.
Y.-H. Shih is with Emerging Central Lab, Macronix International Company,
Ltd., Hsinchu, Taiwan, R.O.C.
S.-R. Lin is with Realtek Semiconductor Corporation, Hsinchu, Taiwan,
R.O.C.
T.-M. Wang is with the Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan,
R.O.C.
J.-G. Hwu is with the Department of Electrical Engineering/Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan,
R.O.C. He is also with the Department of Electronics Engineering/Department
of Electrical Engineering, National United University, Miaoli, Taiwan, R.O.C.
(e-mail: hwu@cc.ee.ntu.edu.tw).
Digital Object Identifier 10.1109/TED.2004.833571
sient and permanent faults; a goal that can be achieved only by
making the circuits self-checking.
IC designers usually do not consider the thermal system in
detail when designing an electrical circuit. In numerous cases,
the effects of the thermal system are negligible. However, as
technology downscaling causes greater power and package densities, thermal effects become significant in increasing numbers
of designs. Facing thermal problems is a new challenge for electronic engineers. Until recently, electronic engineers generally
left these problems to mechanical engineers, who applied external cooling to the warming packages or sometimes directly
to the chips. It was reported that even a 1 C increase could
increase IC failure rate by 2%–4% [1]. Without an appropriate
thermal solution [2], chips are easily burnt out in seconds.
An ideal thermal solution includes: 1) chip temperature
detection, and 2) methods for chip cooling. Using an on-chip
temperature sensor is known to further enhance precision and
accuracy. For example, a transistor [3]–[6] or a p-n junction
diode [7]–[9] is preferred, owing to its easy fabrication and
well-known physics. However, the conventional temperature
sensors generally have a lower temperature sensitivity. For
example, the temperature sensitivity in a p-n junction is around
mV C; that is, when the temperature increases by 1 C,
the extra junction voltage must reduce by about 2 mV to
maintain the same current magnitude. Circuit designers usually
use the emitter-to-base voltage of a biploar junction transistor
to detect temperature. Additionally, the temperature also could
be detected by measuring the threshold voltage ( ) of an
is within the range
MOSFET. The temperature sensitivity of
of
to
mV C. Our recent paper demonstrated that
a simple metal-oxide-semiconductor (MOS) capacitor with
of around 2 nm could be suitable for
an oxide thickness
adoption as an on-chip temperature sensor [10]. Moreover, the
on-chip temperature sensors can be integrated into the circuit
V C. The improvement of
with an improved sensitivity of
temperature sensitivity was exceeded three orders of magnitude
compared with that of a p-n junction. This paper gives the
detailed considerations involved in biasing the MOS temperature sensors, including constant voltage and constant current
operations, and also gives fabrication notices. The current gain
method and multipoints mapping technologies are introduced
particularly show the applicability of using MOS diodes as
temperature sensors. This low-cost and high-performance
sensor can be adopted by any system wishing to detect the
temperature.
0018-9383/04$20.00 © 2004 IEEE
SHIH et al.: HIGH SENSITIVE AND WIDE DETECTING RANGE MOS TUNNELING TEMPERATURE SENSORS
1515
Fig. 1. Schematic band diagrams for an MOS tunneling diode biased (a) at
accumulation and (b) at inversion.
II. PRINCIPLE AND EXPERIMENTS
The principles behind an MOS tunneling temperature sensor
are simple ones. The properties of an MOS capacitor fabricated
on a low-doped p-type substrate has a strongly oxide thickexceeds 4 nm,
ness-dependent. In the accumulation region, if
charge transport is dominated by Fowler–Nordheim (F–N) tunneling which is temperature-independent. For a thin oxide (for
nm), direct tunneling dominates the gate curexample,
rent transportation at the low voltage regime [11]. However, at
the inversion region, the gate current is not only limited by the
oxide thickness but is also by the minority carrier generation.
The inversion gate current saturates if the minority carrier generation rate is below the tunneling rate. Since minority carriers
are temperature-sensitive, the saturation inversion gate current
) changes with the substrate temperature. This charac(
teristic is applied to on-chip temperature detection.
Fig. 1 illustrates the current mechanisms of an MOS (P) tunneling diode biased at both accumulation and inversion. Similar
to a forward-biased p-n diode, gate current at accumulation is
dominated by electron direct tunneling under the low field or by
F–N tunneling under the high field from the metal gate (EM)
[12]. Since neither the hole concentration on the silicon surface
and the gate electron concentration are substrate temperature
)-dependent,
is only dependent on
. At inversion,
(
is controlled by the total amount of electrons directly tunneling from the silicon conduction band (ECB) [13]. Raising
increases the electron concentration on the silicon surface
increases with
.
conduction band, and
Experimental results indicated no inversion oxide breakdown
cm, and p-type silicon wafers were
since low-doped, 1–5
used. Triggering inversion oxide breakdown on such kind of
MOS diode is hard, and does occur until silicon breakdown [14].
The silicon breakdown voltage (
) is defined by
(1)
where
, ,
, and
denote silicon permittivity, electron charge, doping density, and silicon breakdown field (0.3
below 15
MV/cm), respectively [15]. For the samples with
2
Fig. 2. (a) J –V curves of a 150 150 m MOS tunneling temperature
sensor measured at various temperatures. While the gate voltage is positive, the
current delimited by minority carrier (electron) generation rate is changed with
T . (b) J
–T
data of the sensor in (a). Empirical parabolic curve fits
the data points well.
V, the maximum E-field on the silicon surface is far below the
silicon breakdown field. Since the gate current characteristics
nm) resemble those of p-n diodes,
of MOS capacitors (
they are sometimes called MOS tunneling diodes.
For all experiment samples, the oxides were first grown in
a rapid thermal processor and then nitrogen annealed. Oxide
thickness was determined using an ellipsometer with a fixed re. Following aluminum evaporation,
fractive index of
devices with 150 150 m and 2500 2500 m gate areas
were patterned via photolithography and wet etching. The large
area devices are required for the possible direct application of
a constant current to an MOS sensor in this paper. When the
sensors are integrated into circuits, the area is very small. Following by back oxide stripping, aluminum was evaporated again
on the back of the wafer. Some devices were post-metallization
annealed to reduce the effect of the interface state on the current.
Temperature responses of the MOS tunneling diodes are described using current density versus voltage ( – ) curves,
current density versus time ( – ) curves and voltage versus
time ( – ) curves by measuring samples on a hot chuck. The
chuck temperature treated as the substrate temperature ranges
from 20 C to 110 C. As a certain constant current is applied
to the sensor, the gate voltage ( ) must change rapidly with
the substrate temperature to maintain the same current quantity. This paper applies both of the constant–voltage and constant–current characteristics to on-chip temperature detection.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
III. RESULTS AND DISCUSSIONS
A. Temperature Responses of MOS Tunneling Sensors Under
Constant–Voltage Operation
Fig. 2(a) displays typical – curves of an MOS tunneling
nm) at different substrate temtemperature sensor (
peratures. When such a sensor is biased at accumulation,
is
dependent. On the other hand,
changes significantly
at inversion. A 10 C increase in
almost douwith
, and
increases more than 500X when
bles
is raised from 20 C to 110 C. We take
at
V
) as a temperature indicator.
–
relation(
ship is manifested in Fig. 2(b). An empirical parabolic function,
i.e., that is
(2)
data well, and
can be easily obtained
fits the
by (3), shown at the bottom of the page. Notably, the value
of constant in (2) can vary from device to device among deregularly and continuously meavices. This paper changed
of one MOS temperature sensor. The sensor
sured the
was heated and cooled twice. Each cycle including seven states
lasts for 5000 s. Each of the states was separated by 10 C.
The
- curve is illustrated in Fig. 3(a). Since the heater
used here is a proportional-integral- derivative-controlled, gate
current damping occurs in each state, particularly in the initial
is stable,
duration of each state. However, once
remains constant. Between states,
increases with in. Notably, the values of
in the first and
creasing
. An
the second cycles are almost identical at the same
MOS temperature sensor is reliable even though it suffers stress
data
at high temperatures. Fig. 3(b) illustrates stable
at each stage and a fitted parabolic curve. A curve identical to
that in Fig. 2(b) is also shown in Fig. 3(b) to provide a comparison. These two curves have the same coefficients except for
the constant term. The discrepancy involving the constant term
implies that the gate current of an MOS tunneling temperature
sensor could differ among samples, but that their temperature
responses are similar. The discrepancy results from the variations in oxide thickness, defect density, and interface traps. This
finding indicates that composing numerous MOS temperature
sensors into a temperature sensor array was very difficult if the
differences among sensors could not be eliminated. In a later
section i.e., namely, Section III–C, a method of indirect temperature converting via gate current gains ( ) is demonstrated
that solves this problem.
B. Temperature Responses of MOS Tunneling Sensors Under
Constant–Current Operation
Fig. 4 illustrates the
perature sensor (
-
characteristics of an MOS temnm) with an area of 2500 2500
Fig. 3. (a) J
–t record of a practical MOS tunneling temperature
sensor biased under constant voltage. The record contains two heating-up and
cooling-down cycles. In each cycle, there are seven stages separated by 10 C.
data from each stage follow the same temperature response
(b) Stable J
curve as shown in Fig. 2(b), except the constant term.
2
Fig. 4. I –V curves of a 2500 2500 m MOS tunneling temperature
sensor measured at various temperatures. A constant current of 3.64 10 A
is plotted for demonstrating the possible voltage detection under various
temperatures.
2
m measured at different substrate temperatures. As a certain
constant current is applied to the sensor (solid line in Fig. 4), the
C
(3)
SHIH et al.: HIGH SENSITIVE AND WIDE DETECTING RANGE MOS TUNNELING TEMPERATURE SENSORS
1517
Fig. 6. Voltage levels in the heating-up and cooling-down cycles of an MOS
tunneling temperature sensor under constant current bias operation. The gate
voltage levels are identical at the same chuck temperature.
Fig. 5. (a) Variations of temperature ranging from a 40
43 C through
0.3 C=step increment setting. The dotted line is the temperature programmed
by controller and the solid line is real temperature measured in chuck. (b) Gate
voltage (V ) varies step by step with time when a 0.3 C step is applied to the
sensor under constant current bias operation.
sustained
across the device must change rapidly with substrate temperature to maintain the same current. Under such a
constant current bias, flatter current–voltage (I–V) curves owing
to temperature variation in the inversion region have larger gate
voltage changes. The sensors under the constant-current operation could always achieve a temperature sensitivity exceeding
V C.
Fig. 5 shows a schematic assessment of a practical MOS tunneling temperature sensor. The figure illustrates the
versus
time for this temperature sensor under constant–current operation. The bias current magnitude of this sensor is around 46.25
nA. The chuck temperature was treated as the same temperature of substrate at ranges from 40 C to 43 C. The dotted line
in Fig. 5(a) illustrates the temperature programmed by the controller, and the solid line denotes the real temperature measured
in the chuck. The sensor was heated from 40 C to 43 C and
varies
stabilized using a 0.3 C gap. Fig. 5(b) reveals that the
in a stepwise fashion with time when a 0.3 C step is applied to
the sensor. The continuous gate voltage clearly determines the
substrate temperature. A 1 C increment (from 40 C to 41 C)
by around 5.5 V (from 11.8 to 6.3 V); that is,
reduced the
the temperature sensitivity is around
V C. The temperature sensitivity decreases with increasing substrate temperature.
C
C), this sensor
With limiting the detection range (
V C. A
could achieve temperature sensitivity exceeding
high sensitive MOS tunneling temperature sensor always faces
the problem of low detecting range because the voltage drops
rapidly. This problem can be overcome by changing the constant-current biasing level to enlarge the detection voltage range.
Fig. 6 illustrates the voltage levels in the heating and cooling
cycles. The temperature sensor was heated from 60 C to 69 C
and stabilized using a 3 C gap. The sensor then was cooled
from 69 C to 60 C and stabilized using the same gap. The
controller, heating, and cooling cycles then were repeated. The
gate voltage levels are identical at the same chuck temperature.
A one-to-one relation exists between the output gate voltage and
the substrate temperature. The high sensitivity MOS tunneling
temperature sensor thus has good uniformity. From the previous
is smaller than 15 V, the maximum E-field
discussion, while
on the silicon surface is far below the silicon breakdown field
(0.3 MV/cm). The entire operating voltage range in the present
experiments is below 12 V, and thus, the operation of the proposed temperature sensor is unaffected by such gate voltage.
This figure shows that uniformity of an MOS temperature sensor
could be maintained despite being subjected to high voltage
stress (up to 11 V). Moreover, the I–V curve of this temperature
sensor is identical to before a high voltage stress. Consequently,
although the device was high voltage stressed, it is believed to
be reliable.
C. Indirect Temperature Conversion Method for a
Temperature Sensor Array
A big challenge in creating a temperature sensor array based
on numerous temperature sensors is that saturation current may
differ among sensors. Oxide thickness variation, defect densities, and interface traps all may contribute to gate current discrepancies. This paper proposes a new method of using current
gain to solve this problem. Using current gain as the detecting
parameter can reduce the variations in current levels owing to
oxide thickness nonuniformity, and different gate area.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
Fig. 7. Temperature responses of 40 MOS temperature sensors under constant
voltage bias operation represented by gate current density and by current gain.
The huge discrepancies among the sensors can be reduced by current gain
method.
Fig. 8.
I–V curves fitted by second-order polynomials.
Fig. 7 shows the
distribution of 40 MOS temperanm) in an array.
varies over
ture sensors (
an order. That is, if only a
converter handles currents
coming from the 40 sensors, the current variation will demonstrate an unacceptable error of 40 C. The same figure demonat 50 C
strates gate current gains ( ) of the sensors.
serves as the reference. Moreover, the
distribution in the
logarithm scale is described using a parabolic fitting curve. If
distribution is used for
detection, the error can be significantly suppressed from 40 C to 5 C. At high temperature
(
C), a temperature difference is expected between
the silicon surface and the hot chuck for the stretch-out data.
The unique fitting curve in Fig. 7 indicates an indirect temperature conversion method for a sensor array. Before measuring
, each sensor should be individually calibrated at a specific
), and its gate current (
) is then recorded
temperature (
for future temperature calculation. Equation (2) displays the exas follows:
pression of
Fig. 9. Gate current gain versus the gate voltage curves that will be fitted by
second-order polynomials.
(4)
Notably,
denotes the gate current density when the substrate
. Then
is obtainable by solving (4). Fabtemperature is
rication processes may slightly alter the coefficients in (2), but
can be experimentally determined. Equation (4) gives a general
solution for such kinds of an MOS temperature sensor array, and
the solution is much easier for an array to embody.
(
V
V), the two curves are almost overlapping. That
is, the proposed model provides a perfect fit. From previous
discussion, the gate current gain, rather than the absolute gate
current, was used for assessing the temperature. The gate
current gain algorithm could overcome the process variation.
The gate current gain fitted using second-order polynomials
can be expressed as
(6)
D. Model for MOS Devices Biased at Inversion Region
The model used to fit the gate current can be expressed as
(5)
where the values , , , , and
are constants. Fig. 8
shows I–V curves fitted by second-order polynomials. The
dotted lines denote the measured gate currents under different
substrate temperatures while the solid lines are the fitted
gate currents based on (5). Within the sensor operating range
where the values
,
,
,
, and
are constants and
is the gate current when the substrate temperature is
30 C. Fig. 9 illustrates the gate current gain versus the gate
voltage curves fitted by second-order polynomials. The proposed model is quite simple. Fig. 9 shows the measured and
calculated curves, which reveal a perfect fit. Since different sensors share the same coefficients in this model, the current gain
algorithm is believed to be useful for temperature detection.
SHIH et al.: HIGH SENSITIVE AND WIDE DETECTING RANGE MOS TUNNELING TEMPERATURE SENSORS
1519
E. Analysis of Temperature Sensors’ Sensitivity
Differentiating the equation as proposed above can obtain the
following:
(7)
Rearranging (7) leads to
(8)
) causes lower gate current
Lower substrate temperature (
( ). The above equation reveals that larger substrate tempera) will be produced by the first term, which
ture deviation (
implies that the temperature sensors have a lower sensitivity
is deterunder low temperature situations. Additionally,
mined based on the detecting circuit’s resolution. Higher resolution produces lower substrate temperature deviation, and improves the sensitivity of the temperature sensor. The second term
derives from the usage of the voltage information of the gate.
term is also determined based on the detecting circuit
The
resolution. The detecting circuit forces the second term to elim, resulting in a
inate the first term by producing a suitable
smaller substrate temperature deviation and improvement in the
sensitivity of the temperature sensor. Correspondingly, a higher
resolution produces better eliminating effect, thus a higher temperature sensitivity can be obtained.
Fig. 10(a) and (b) illustrates the gate voltage and the variation of temperature sensitivity with the substrate temperature,
respectively. The sensitivities were determined by the semi-experiment approach based on the I–V curve data measured under
different temperatures. Both the gate voltage and the temperature sensitivity decrease with increasing substrate temperature
in region 1 (from 36.9 C to 37.4 C). Moreover, the gate voltage
reaches the lower limit (5 V), as the temperature equals 37.4 C.
The bias level of the constant current source must change to
prevent the sensor from operating out of the detection range
V). Different regions have different bias current levels.
(
Moreover, this change in bias current always keeps the temperature sensitivity above 10 V C in our paper theoretically.
On the other hand, the experimental approach is also used
to realize the temperature sensors except the above semi-experimental way. Fig. 11 shows that the measured gate voltages
varied with the substrate temperature for one temperature
sensor. Moreover, the resolution of the sensor under the conV C. However, the
stant current operation is at least
resolution reduces with decreasing gate voltage, and making
the noise consideration] more important. To avoid this noise
effect, the sensors should be biased to operate under an appropriate voltage range. For example, the current level was
cm to 1.82
cm ,
changed from 1.69
as illustrated in Fig. 11 to maintain the voltage range within
when the temperature changes from 35 C to
37 C. Bias current levels differ among regions. This device is
clearly observed to have high sensitivity.
F. Temperature Distribution Detection
This study demonstrated the real-time temperature distribution for on-chip detection. Multi-points on the wafer are mea-
Fig. 10. (a) Variations of the gate voltage and (b) the temperature sensitivity
as a function of the substrate temperature according to the fitted polynomials
under three different constant current biases operation.
Fig. 11. Experimental observation of the variations of gate voltage as a
function of the substrate temperature for an MOS sensor measured at three
different constant current biases operation.
sured, and the current gain method is used. The temperature distribution on the wafer can also be pictured. The currents of three
dies are measured at 30 C, and serve as current references.
Fig. 12(a) illustrates the current densities of the three points
versus time. The currents rapidly rise when the heat source approaches the chip. The current discrepancies can be taken away
using the current gain method, as shown in Fig. 12(b). The ratio
can indicate the temperature situation. When the
of
currents of multi-points are measured already, the temperature
1520
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
V C. Such sensitivity
temperature sensitivity exceeding
is one thousand times larger than that of conventional systems.
As for a temperature sensor array, this paper proposes a method
using gate current gain, rather than absolute gate current, to obtain temperature. The proposed method eliminates gate current
discrepancy among sensors. This paper also demonstrates the
possible application of detecting the multi-points temperatures
on a wafer. The proposed low-cost and high-performance sensor
is useful for on-chip temperature detection application.
REFERENCES
Fig. 12. Simultaneous responses of (a) the current densities and (b) the
current gains and the corresponding interpreted real time temperature for three
temperature sensors on a wafer.
distribution on the chip will be decided. Notably, under the bias
,
, and
terms in (6) can be igof 2 V, the
nored. Consequently, the model used here to fit the temperature
distribution can be simplified as follows:
(9)
where and are constants. Fig. 12(b) also shows the interpreted temperature distribution on the wafer versus the real time.
With further improvement in the stability and reliability, the integration of temperature sensors on a chip is expected to detect
the entire real time temperature distribution on the wafer.
[1] C. N. Liao, C. Chen, and K. N. Tu, “Thermoelectric characterization of
Si thin films in silicon-on-insulator wafer,” J. Appl. Phys., vol. 86, no. 8,
pp. 3204–3208, Sept. 1999.
[2] H. Sanchez, B. Kuttanna, T. Olson, M. Alexander, G. Georosa, R. Philip,
and J. Alvarez, “Thermal management system for high performance
power PC microprocessors,” in Proc. Compcon, 1997, pp. 325–330.
[3] A. Syal, V. Lee, A. Ivanov, and J. Altet, “CMOS differential and absolute thermal sensors,” in Proc. On-Line Testing Workshop, 2001, pp.
127–132.
[4] V. Szekely, C. Marta, Z. Kohari, and M. Rencz, “CMOS sensors for
on-line thermal monitoring of VLSI circuits,” IEEE Trans. VLSI Syst.,
vol. 5, pp. 270–276, Sept. 1997.
[5] J. Altet, A. Rubio, S. Dilhaire, E. Schaub, and W. Claeys, “BiCMOS
thermal sensor circuit for built-in test purposes,” Electron. Lett., vol. 34,
pp. 1307–1309, June 1998.
[6] A. Bakker and J. H. Huijsing, “Micropower CMOS temperature sensor
with digital output,” IEEE Trans. Solid-State Circuits, vol. 31, pp.
933–937, July 1996.
[7] G. Fisher, J. C. Daly, C. W. Recksiek, and K. D. Friedland, “A programmable temperature monitoring device for tagging small fish: A prototype chip development,” IEEE Trans. VLSI Syst., vol. 5, pp. 401–407,
Dec. 1997.
[8] J. L. Merino, S. A. Bota, A. Herms, E. Cabruja, X. Jorda, A. Ferre,
J. Bigorra, J. Samitier, M. Vellvehi, and J. Bausells, “Smart temperature sensor for on-line monitoring in automotive applications,” in Proc.
On-Line Testing Workshop, 2001, pp. 122–126.
[9] V. F. Mitin, V. V. Kholevchuk, R. V. Konakova, and N. S. Boltovet, “Temperature microsensors,” in Proc. Semiconductor Conf., vol. 2, 1999, pp.
495–498.
[10] Y. H. Shih and J. G. Hwu, “An on-chip temperature sensor by utilizing
a MOS tunneling diode,” IEEE Electron Device Lett., vol. 22, pp.
299–301, June 2001.
[11] T. P. Chen, S. Li, S. Fung, and K. F. Lo, “Interface generation by FN injection under dynamic oxide field stress,” IEEE Trans. Electron Devices,
vol. 45, pp. 1920–1926, Sept. 1998.
[12] A. Yassine, H. E. Nariman, and K. Olasupo, “Field and temperature dependence of TDDB of ultrathin gate oxide,” IEEE Electron Device Lett.,
vol. 20, pp. 390–392, Aug. 1999.
[13] W. C. Lee and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” in Symp. VLSI
Tech. Dig., June 2000, pp. 198–199.
[14] C. G. Fonstad, Microelectronic Devices And Circuits. New York: McGraw-Hill, 1994, p. 153.
[15] S. M. Sze, VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988,
p. 656.
IV. CONCLUSION
A high sensitivity temperature sensor that used an MOS tunneling diode structure was designed in this paper. It has the
advantage of being CMOS technology compatible. Since the
sensor is biased at constant-voltage, the gate current was increased over 500 times when the sensor was heated from 20
C to 110 C. Additionally, since the sensor operates in a constant-current situation and with limiting output voltage range,
the proposed MOS tunneling temperature sensor could achieve
Yen-Hao Shih was born in Changhua City, Taiwan,
R.O.C., in 1974. He received the B.S. and the
Ph.D. degrees in electron engineering from National
Taiwan University, Taipei, in 1997 and 2002, respectively.
In 2002, he joined Emerging Central Lab,
Macronix International Company, Ltd., Hsinchu,
Taiwan. His research fields are ultrathin gate oxide,
nitride thin films, reliability, and nitride storage flash
memories.
SHIH et al.: HIGH SENSITIVE AND WIDE DETECTING RANGE MOS TUNNELING TEMPERATURE SENSORS
Shian-Ru Lin was born in Nantou, Taiwan, R.O.C.,
in 1978. He received the B.S. degree in electronic
engineering from National Taiwan University (NTU)
of Science and Technology, Taipei, in 2000, and the
M.S. degree in electronic engineering from NTU, in
2003.
He joined Realtek Semiconductor Corporation,
Hsinchu, Taiwan, in 2003. His research interests include the MOS device, on-chip temperature sensors,
and high-speed ADCs.
Tsung-Miau Wang was born in Changhua, Taiwan,
R.O.C., in 1980. He received the B.S. degree in electronic engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2002. After his graduation, he pursued the M.S. degree in electronic engineering in National Taiwan University, Taipei, for
one year and he was then qualified to enter the Ph.D.
program in 2003.
His research major is MOS devices, especially
on-chip temperature sensors.
1521
Jenn-Gwo Hwu (SM’99) was born in Taiwan,
R.O.C., on August 29, 1955. He received the B.S.
degree in electronic engineering from National
Chiao-Tung University, Hsinchu, Taiwan, in 1977
and the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU),
Taipei, in 1979 and 1985, respectively.
He joined the faculty of NTU in 1981, where he
is presently a Professor with the Department of Electrical Engineering and with the Graduate Institute of
Electronics Engineering. From 1997 to 1998, he was
the vice chairman of the Department of Electrical Engineering. From February
1, 2004, he was invited to be the Dean of the College of Electrical Engineering
and Computer Science, National United University, Miaoli, Taiwan. His research is mainly on the preparation of reliable ultrathin gate oxide and the related
MOS devices. He has experience in teaching the courses of circuits, electronics,
solid-state electronics, semiconductor engineering, MOS capacitor devices, radiation effects on MOS systems, and special topics on oxide reliability.
Dr. Hwu was a recipient of the 1986, 1998, 1999, 2000, and 2002 Excellent
Teaching Award sponsored by NTU. From 1988 to 1991, and 1993, he was a
recipient of the Excellent Teaching Award sponsored by the College of Engineering, NTU. In 1991, he was also a recipient of the Outstanding Teaching
Award sponsored by the Ministry of Education, R.O.C., and in 1987 and 2003
by the NTU. In 1999, he was the recipient of Jan Ten-You Paper Award by The
Chinese Institute of Engineering, R.O.C.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
253
A Novel Multibridge-Channel MOSFET (MBCFET):
Fabrication Technologies and Characteristics
Sung-Young Lee, Sung-Min Kim, Eun-Jung Yoon, Chang-Woo Oh, Ilsub Chung, Donggun Park, and
Kinam Kim, Fellow, IEEE
Abstract—We have demonstrated a novel three-dimensional
multibridge-channel metal–oxide–semiconductor field-effect
transistor (MBCFET). This transistor was successfully fabricated
using a conventional complementary metal–oxide–semiconductor
process. We introduce the fabrication technologies and electrical
characteristics of MBCFET in comparison with a conventional
planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability
than a planar MOSFET. This is due to the vertically stacked
multibridge channels. The subthreshold swing of MBCFET is
61 mV/dec, which is almost an ideal value due to the thin body
surrounded by gate. Based on a simulation result, we show that
the MBCFET will have a large on–off state current ratio at short
channel transistors.
Index Terms—Multibridge-channel metal–oxide–semiconductor field-effect transistor (MBCFET), vertically stacked
multibridge channels.
I. INTRODUCTION
T
O ACHIEVE THE high-density device with high performance and low power dissipation, the transistor has been
scaled down aggressively in its size and operating voltage. International Technology Roadmap for Semiconductor (ITRS) 2002
predicts that the transistor gate length is expected to be reduced
by 15% every year, while the current drivability requirement
remains the same for the reduced operating voltage.
Since improving the performance and scaling down the gate
length of the transistor have faced many technological barriers
to overcome, many alternative solutions have been investigated.
One of the solutions is a novel process technology, such as
the damascene process [1], which overcomes the lithography
limit. Another solution is using the new gate electrodes and
dielectrics to reduce the gate poly depletion and gate leakage
current. Recently, three-dimensional (3-D) transistor structures
such as FinFET, double-gate ultra-thin body (UTB) FET, and
gate-all-around (GAA) FET have been proposed and extensively studied [2]–[5] as a promising solution to reduce short
channel effect (SCE) and performance degradation. Alternative
materials will be the long-term solutions to circumventing
the scaling issues because of their integration difficulties
Manuscript received July 17, 2003; revised August 15, 2003. This work was
presented in part at the Silicon Nanoelectronics Workshop, Kyoto, Japan, June
2003.
S.-Y. Lee, S.-M. Kim, E.-J. Yoon, C.-W. Oh, D. Park, and K. Kim are with
the Samsung Electronics Company, Kyungki-Do 449-711, Korea (e-mail:
afc.lee@samsung.com).
I. Chung is with the School of Information and Computer Engineering,
SungKyunKwan University, Kyungki-Do 440-746, Korea.
Digital Object Identifier 10.1109/TNANO.2003.820777
and reliabilities. However, the combinations of new process
technology and novel transistor structure with complementary
metal–oxide–semiconductor (CMOS) compatibility can be
both short-term and long-term solutions to proceed with the
CMOS scaling.
So, several researchers have reported and presented transistor performance improvements, thanks to the 3-D transistor
structures [2]–[5]. However, their fabrication processes were
very difficult to manufacture and it is hard to control the
process parameters. Also, further performance improvements
are required in their characteristics such as current drivability,
off-state leakage current, and so on.
Therefore, in this paper, we propose a novel and manufacturable multibridge-channel metal–oxide–semiconductor fieldeffect transistor (MBCFET) structure fabricated on bulk Si substrate. And we describe the detailed processes to fabricate the
MBCFET, including epitaxial growth of the SiGe/Si multilayer.
Transistor characteristics and simulation results are also presented.
II. TRANSISTOR FABRICATION TECHNOLOGIES
The MBCFET fabrication processes are schematically illustrated in Fig. 1. To prevent the parasitic transistor operation
at the bulk Si substrate, channel isolation ion implantation is
applied before the epitaxial growth of multiple Si Ge and
Si layers [Fig. 1(a)]. With the UTB silicon-on-insulator (SOI)
wafers, this process can be eliminated and simplified. Besides,
the additional UTB transistor can be formed on the bulk Si.
The epitaxial layer thickness of Si Ge , alternately grown
with Si on (100) Si substrate, should be controlled below a critical thickness that starts to generate defects such as misfit dislocations or other crystal defects. If we control the number of
SiGe/Si alternating epitaxial layers, we can control the number
of channels, i.e., the inversion charges that determine the current drivability of MOSFETs.
An oxide dummy gate is used as a hard mask to etch the epitaxial layers at the source/drain (S/D) region. After etching the
S/D region, a thin source drain extension (SDE) layer is formed
by Si selective epitaxial growth (SEG) as shown in Fig. 1(d) and
Fig. 2. The SDE layer is doped by tilted ion implantation.
After a poly-Si deposition to fill the S/D region, chemical
mechanical polishing (CMP) and etchback of poly-Si are performed to planarize the S/D poly-Si, as shown in Fig. 1(e). Then,
thick SiN is deposited and planarized by CMP. After the removal of dummy gate, the multibridge channel (MBC) region is
implanted with multiple energy to adjust the threshold voltage
1536-125X/03$17.00 © 2003 IEEE
254
Fig. 1.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
Schematic diagrams for MBCFET fabrication.
Fig. 2. Scanning electron microscope photograph after Si SEG of Fig. 1(d).
Fig. 3.
Fig. 4. Highly selective etching profile of SiGe over Si has been successfully
achieved.
Bird’s-eye view of Fig. 1(g).
Fig. 5. Final profile of MBCFET. Si body (channel) thickness is 32 nm.
, as shown in Fig. 1(f). We anisotropically etched the oxide
of shallow trench isolation (STI) using SiN and Si hard masks,
which is followed by the selective Si Ge removal to form
the structure of Fig. 1(g). Fig. 3 shows the bird’s-eye view after
the completion of this process.
One of the key technologies to form this MBCFET is highly
selective Si Ge removal over Si. As shown in Fig. 4, the
Si Ge layers were selectively removed against Si with the
selectivity higher than 300 : 1 [6].
Gate oxidation 2.5 nm thick, using N O, N + doped poly-Si
deposition, CMP, and SiN strip, are successively performed to
form the gate of -channel MBCFET. Thereafter, conventional
CMOS processes are applied to finish the transistor fabrication.
Fig. 5 shows the final profile of the MBCFET. Floating Si body
thickness is 32 nm.
The implantation processes of a planar MOSFET are the
same as those of the MBCFET, except for channel-isolation
LEE et al.: NOVEL MULTIBRIDGE-CHANNEL MOSFET (MBCFET): FABRICATION TECHNOLOGIES AND CHARACTERISTICS
0
Fig. 6. I
V characteristics of MBCFET. The I of MBCFET is
38 A=m at V = V = 1 V , while the planar MOSFET shows the I
of 2.9 A=m.
0
Fig. 7. I
V characteristics of MBCFET. V of MBCFET is lowered due
to the thin body surrounded by gate as well as the lightly doped channel.
implantation and SDE implantation. Both a planar MOSFET
and the MBCFET have no halo implantation in fabrication, but
a planar MOSFET only has a halo implantation process in case
of simulation.
III. TRANSISTOR CHARACTERISTICS AND DISCUSSION
Figs. 6 and 7 show the
and the
characterm, W
m
istics of the -channel MBCFET with L
comparing with those of the -channel planar MOSFET.
of MBCFET is 0.1 V, while the
The threshold voltage
of planar MOSFET is 0.45 V. The current drivability of
at
, while planar
MBCFET is 38
. MBCFET shows 13 times larger
MOSFET shows 2.9
current drivability than planar MOSFET. When we consider
difference between MBCFET and planar MOSFET,
the
the MBCFET shows a 4.6 times larger current drivability than
that of planar MOSFET, according to the simple mathematical
calculations of current drivability. Although the actual transistor
width was increased four times due to the vertically stacked
multiple channels of the MBCFET, mobility enhancement
thanks to the thin-body double-gate structure of the MBCFET
resulted in a 4.6 times larger current drivability in comparison with that of planar MOSFET. Since depletion charge is
small enough in thin-body MBCFET, carriers in the inversion
255
Fig. 8. Since the channels are all floating and surrounded by gate, no body-bias
effects are observed in the MBCFET.
Fig. 9.
Simulation result of I
=I
of MBCFET and planar MOSFET.
layer encounter a smaller vertical electric field in thin-body
MBCFET than in planar bulk MOSFET with relatively heavy
channel doping. This reduction in vertical field is expected to
improve carrier mobility [7].
of MBCFET is due to thin body
We think that the low
surrounded by gate. The subthreshold swing of MBCFET is
61 mV/dec, that is, almost ideal value, while planar MOSFET
shows 87 mV/dec, as shown in Fig. 7. Even though both transistors have low subthreshold swing because of long channel, the
ideal value of MBCFET is remarkable. We think that this comes
from the thin body surrounded by gate as well as lightly doped
channel.
In Fig. 8, we show that MBCFET has no body-bias dependency. It means that MBCs of MBCFET are electrically all
floating and fully depleted by the surrounding gate. It can be
a clear evidence for current flow in the floating channels of
MBCFET, not body.
Fig. 9 shows the simulation result of on–off current characteristics for planar MOSFET and MBCFET. From that result,
we know that MBCFET has much less off-state current at the
same on-state current. The kink in planar MOSFET shown in
due to halo imFig. 9 is due to halo implantation. High
plantation in planar MOSFET reduces off-leakage currents with
decreasing gate length for a few points in Fig. 9. When we
compare on–off current characteristics between MBCFETs, the
256
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
MBCFET having a thin Si body shows superior characteristics
to another one. Therefore, if we are thinning down the epitaxial
Si layers surrounded by gate, we can maximize the on–off state
current ratio. The simulation result in Fig. 9 also shows the benefits of MBCFET with short channel transistors that we are focusing as a further study.
Sung-Min Kim received the B.S. degree in 1998 and
the M.S. degree in 2000 from Kyung Hee University,
Seoul, Korea.
Since 2000, he has been with the Semiconductor
R&D Center, Samsung Electronics Company, Ltd.,
Kyungki-Do, Korea, where he is an Engineer with the
Technology Development Team.
IV. CONCLUSIONS
Eun-Jung Yoon received the B.S. degree in chemical
engineering from Yonsei University, Seoul, Korea, in
2001.
Since 2001, she has been with the Samsung
Electronics Company, Ltd., Kyungki-Do, Korea. Her
research interests include nano-CMOS structure and
technology, and memory devices.
We proposed a novel 3-D MOSFET, MBCFET, and successfully fabricated it using a conventional CMOS process. The
MBCFET shows a 4.6 times larger current drivability than a
conventional planar MOSFET at the same threshold voltage,
due to the vertically stacked double-bridge channels. The subthreshold swing of MBCFET is 61 mV/dec, that is, almost ideal
value, due to a thin body surrounded by gate. Since the number
of channels can be controlled by a simple process modification,
we expect that the MBCFET will be a promising candidate transistor for the future nanoscale CMOS technology era.
Chang-Woo Oh was born in Youngyang, Kyungpook, Korea, on January 27, 1971. He received the
B.S. degree in electronics from Kyungpook National
University, Kyungpook, Korea, in 1996 and the M.S.
and Ph. D. degrees in electrical engineering from
Seoul National University, Seoul, Korea, in 1998
and 2002, respectively.
Since 2002, he has been a Senior Engineer with
Samsung Electronics Company, Ltd., Kyungki-Do,
Korea. His research interests include nano-CMOS
structure and technology, memory devices, and field
REFERENCES
[1] C.-W. Oh, S.-H. Kim, C.-S. Lee, J.-D. Choe, S.-A. Lee, S.-Y. Lee, K.-H.
Yeo, H.-J. Jo, E.-J. Yoon, S.-J. Hyun, D. Park, and K. Kim, “Highly manufacturable sub-50 nm high-performance CMOSFET using real damascene gate process,” in Symp. VLSI Technology, 2003, p. 147.
[2] Y. K. Choi, T.-J. King, and C. Hu, “Nanoscale CMOS spacer FinFET for
the terabit era,” IEEE Electron Device Lett., vol. 23, p. 25, Jan. 2002.
[3] S. Monfray and T. Skotnick et al., “50 nm-gate all around (GAA)-silicon on nothing (SON) devices: A simple way to co-integration of GAA
transistors within bulk MOSFET process,” VLSI Technol., p. 108, 2002.
[4] M. Kumar, H. Liu, and J. K. O. Sin, “A high-performance five-channel
NMOSFET using selective epitaxial growth and lateral solid phase epitaxy,” IEEE Electron Device Lett., vol. 23, p. 261, May 2002.
[5] S. Cristoloveanu, F. Allibert, and A. Zaslavsky, “Double-gate MOSFETs: performance and technology options,” in Proc. Semiconductor
Device Research Symp., 2001, p. 459.
[6] S. M. Kim, C.-W. Oh, J.-D. Choe, C.-S. Lee, and D. Park, “A study
etch using polysilicon etchant diluted by H2O
on selective Si Ge
for three-dimensional Si structure application,” presented at the Proc.
Electrochemical Society Meeting, Paris, France, Apr. 2003.
[7] L. Chang, K. J. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu,
“Direct-tunneling gate leakage current in double-gate and ultrathin body
MOSFETs,” IEEE Trans. Electron Devices, vol. 49, pp. 2288–2295,
Dec. 2002.
Sung-Young Lee received the B.S. and M.S. degrees
in materials science and engineering from Korea University, Seoul, Korea, in 1990 and 1992, respectively.
He is currently working towards the Ph.D. degree in
electrical engineering at SungKyunKwan University,
Kyungki-Do, Korea.
Since 1993, he has been with Samsung Electronics
Company, Ltd., Kyungki-Do, Korea. His research
interests include nano-CMOS structure and technology, memory devices, and nanocharacterization
using scanning probe microscopy.
emission display.
Ilsub Chung was born in Jinju, Korea, in 1957. He
received the B.S. degree in electronic engineering
from SungKyunKwan University, Kyungki-Do,
Korea, in 1981, and the M.S. and Ph.D. degrees
in electrical and computer engineering from the
University of Texas at Austin in 1988 and 1992,
respectively.
In 1993, he joined the FRAM project team of
the Samsung Advanced Institute of Technology,
Giheung, Korea. In 2001, he joined SungKyunKwan
University, where he is currently an Associate
Professor in the School of Electrical and Computer Engineering, In addition,
he currently serves as a secretary of TC47/IEC. His main research area is
the characterization of nonvolatile memories such as FRAM, MRAM, and
SONOS.
Donggun Park received the B.S. and M.S. degrees
from Sogang University, Seoul, Korea, and the Ph.D.
degree from the University of California, Berkeley
(UC Berkeley), all in electrical engineering. His
Ph.D. study involved plasma charging damage and
reliability of thin gate oxides.
Since he joined Samsung Electronics Company,
Ltd., Kyungki-Do, Korea, in 1983, he has been
involved in the diffusion process development of 64
K and 256 K DRAM, and process integration of 1
Mega, 4 Mega, and 16 Mega DRAM development
until 1993. After his Ph.D. study at UC Berkeley, in 1998, he rejoined Samsung
Electronics, where he is now a Vice President of the R&D Center. After the
successful development of 0.15 m and 0.13 m 256M DRAMs, 90 nm NAND
Flash, and 100 nm high-speed 72 M SRAM, in 1999, 2001, 2002, and 2003,
respectively, he is leading the development projects of nano-CMOS transistor,
memory cell transistors, and the advanced technologies for mobile/graphic
DRAMs.
LEE et al.: NOVEL MULTIBRIDGE-CHANNEL MOSFET (MBCFET): FABRICATION TECHNOLOGIES AND CHARACTERISTICS
Kinam Kim (S’90–M’97–SM’01–F’03) received
the B.Sc. degree in electronic engineering in 1981
from Seoul National University, Seoul, Korea, the
M.Sc. degree in electrical engineering from the
Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1983, and the Ph.D.
degree in electrical engineering from the University
of California, Los Angeles, in 1994.
In 1983, he joined Samsung Electronics Company, Ltd., Kyungki-Do, Korea, where he has been
involved in the development of DRAMs, ranging
from 64 Kb to l Gb densities. Currently, he is a Vice President responsible
for the research and development of future memory technologies for DRAM,
nonvolatile memory, SRAM, and emerging new memories. His current major
activity is focused on the development of technologies for low power and high
performance multi-gigabit density DRAMs. He serves as a committee member
of the international electron device meeting (IEDM), and he is a member of the
editorial advisory board of Microelectronics Reliability.
Dr. Kim is listed in Who’s Who in the World and nominated for IBC’s 21st
Century Award for Achievement. He will be listed in The Asia 500-Leaders for
the New Century. He is a recipient of ISI’s Citation Award for a highly cited
paper.
257
1322
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 5, MAY 2003
An Ultrathin Vertical Channel MOSFET for
Sub-100-nm Applications
Haitao Liu, Student Member, IEEE, Zhibin Xiong, and Johnny K. O. Sin, Senior Member, IEEE
Abstract—An ultrathin vertical channel (UTVC) MOSFET with
an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was
obtained using the cost-effective solid phase epitaxy, and the borondoped poly-Si0 5 Ge0 5 gate was adopted to adjust the threshold
voltage. The fabricated NMOSFET offers high-current drive due
to the lightly doped ( 1 1015 cm 3 ) channel, which suppresses
the electron mobility degradation. Moreover, an asymmetric gateoverlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as
compared to the conventional symmetrical LDD. The on-current
drive, offstate leakage current, subthreshold slope, and DIBL for
the fabricated 50-nm devices are 325 A m, 8 10 9 A m,
87 mV/V, and 95 mV/dec, respectively.
Index Terms—Asymmetric LDD, solid phase epitaxy, ultrathin
channel, vertical MOSFET.
I. INTRODUCTION
O
VER THE past two decades, channel length of the CMOS
transistors has been halved at intervals of approximately
two years, due to the increasing needs for higher packing density
and higher device speed. However, conventional scaling beyond
100 nm requires the support of more complex lithography technology and a precisely adjusted doping profile in the channel region [1]. Thus, alternatives to further scale down the MOSFET
channel is of great importance. One of the most promising architectures is the vertical MOSFET due to the following advantages [2]–[4]. First, the channel length has no dependence on
the critical lithography. Second, vertical MOSFET can double
the channel width per transistor area, and this leads to an increase of packing density as compared to the planar MOSFET.
Third, a fully depleted vertical MOSFET provides almost ideal
subthreshold slope and excellent short-channel effects immunity, which makes it suitable for high-density, low-voltage, and
low-power DRAM, SRAM, and conventional CMOS applications.
There are mainly two ways to fabricate the vertical MOSFETs. One way is to use the expensive epitaxial growth (e.g.,
MBE, RT-CVD, SEG) to define the short-channel length
[5]–[7], and a channel length down to 25 nm was obtained
[8]. However, it is not flexible to make CMOS with this
approach due to the different dopants needed in the NMOS
and PMOS. The other way is to etch silicon pillars and then
Manuscript received November 20, 2002; revised March 10, 2003. This
work was supported by the RGC Competitive Earmarked Research Grant
HKUST6021/02E. The review of this paper was arranged by Editor J. Vasi.
The authors are with the Department of Electrical and Electronic Engineering,
The Hong Kong University of Science and Technology, Clear Water Bay, Hong
Kong (e-mail: eesin@ust.hk).
Digital Object Identifier 10.1109/TED.2003.813243
Fig. 1. (a) Cross section and (b) layout of the UTVC MOSFET.
diffuse the implanted dopants to obtain a short channel [9],
[10]. However, the minimum channel length that can be
reached in this way is limited by the thermal budget during
device fabrication. The biggest problem of all these reported
devices is that the high-body doping concentration required
to suppress the short-channel effects produces unacceptably
high-threshold voltage for the 50-nm devices. This high-body
doping concentration also leads to large leakage current and
degrades the electron and hole mobilities in the channel region;
is reduced significantly. In addition,
thus, the ratio of
the floating body effect, which is the cause of the kink effect
in silicon-on-insulator (SOI) devices, is also a big problem in
those reported structures. To address these problems, a novel
ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is proposed
and implemented [11]. The device structure and fabrication
process will be described in Sections II and III, and the device
characteristics will be discussed in Section IV.
II. DEVICE STRUCTURE AND DESIGN
The cross section of the proposed structure is shown in Fig. 1.
It looks similar to the conventional vertical MOSFET but with a
layer of oxide supporting the channel and separating the source
and the drain. This oxide layer effectively blocks the subsurface
leakage between the source and the drain. The lightly doped ultrathin channel, which was obtained using solid phase epitaxy
(SPE) [12], can suppress the effective mobility degradation and
the short-channel effects significantly [13]. The proposed structure has inherent thick source/drain regions, which can reduce
the contact resistance. In addition, since the channel is lightly
doped, the body depletion charge has a negligible contribution to
the threshold voltage so that the threshold voltage variation due
to random fluctuations in the dopant density and position can be
greatly reduced. The threshold voltage can be controlled by the
work function of the boron-doped poly-Si Ge gate [14]. A
0018-9383/03$17.00 © 2003 IEEE
LIU et al.: ULTRATHIN VERTICAL CHANNEL MOSFET FOR SUB-100-nm APPLICATIONS
1323
Fig. 2. Comparison of the electric field on the drain side for the UTVC
MOSFETs with and without the asymmetric gate-overlapped LDD.
typical layout of the fabricated vertical MOSFET is shown in
Fig. 1(b), which is similar to the planar MOSFET except that
the effective channel width of the vertical MOSFET is doubled
with the same active area.
Although devices without the LDD provide the highest
current drive, those devices are not useful due to the unac1 A m and very poor
ceptable offstate leakage current
short-channel effects. To keep the high-current drive while
suppressing the leakage current, an asymmetric gate-overlapped LDD can be used. The asymmetric gate-overlapped
LDD provides the following advantages. First, it reduces
the series resistance on the source side as compared to the
conventional symmetric LDD [15]. The series resistance on the
source side has a more adverse effect on the current drive than
that on the drain side. This is because the source resistance
not only increases the total resistance, but also reduces the
. The second advantage is that
effective gate drive
the LDD in the proposed structure is fully overlapped with the
poly-SiGe gate. This significantly reduces the series resistance
on the drain side, thus improves the current drive. However,
the parasitic capacitances between the S/D and gate become
larger due to the gate overlap on the S/D and LDD regions,
and this is expected to adversely impact the device speed and
power consumption. Therefore, a tradeoff does exist between
the series resistance and the gate overlap capacitances. The
overlap capacitances can be extracted using the method based
on S-parameter measurement as proposed by Korbel et al. [16].
The third advantage of the asymmetric LDD is the reduction
of the electric field on the drain side; thus, the offstate leakage
current is suppressed effectively and the hot carrier reliability
is also improved [17]. The simulated electric field along the
channel for the device with the asymmetric gate-overlapped
LDD and the device without the LDD is shown in Fig. 2. It can
be seen that the peak electric field in the device without the
LDD is approximately two times larger than that of the device
with the asymmetric gate-overlapped LDD at the offstate
V and
V).
(
Unlike all other vertical devices, the proposed UTVC
MOSFET has less junction capacitance because the source
and drain regions are isolated by a SiO layer. However, this
advantage was partially offset by the high-overlap capacitances
made between the polysilicon gate and the S/D and LDD re-
Fig. 3. Major fabrication steps of the UTVC MOSFET. (a) Depositing oxide,
PSG, and phosphorus-doped polysilicon, etching for the ploysilicon/PSG/oxide
pillars, implanting arsenic for the source. (b) Depositing 15-nm amorphous
silicon, implanting high-dose Si ions, and furnace annealing at 590 C for 10 h.
(c) Deposit 15-nm oxide, dry etching the oxide and amorphous silicon to form
the oxide and silicon spacer on the sidewall. (d) Removing the oxide spacer,
A gate oxide, depositing poly-Si Ge and etching it to form
growing 33 the gate spacer, RTA to form the asymmetric LDD through the out-diffusion
of the PSG.
gions. This restricts the RF capability and high-speed operation
of the transistor, and an improved structure with less parasitic
capacitances and a self-aligned gate is preferred in future work.
III. FABRICATION PROCESS
The major process steps of the UTVC MOSFET are shown
in Fig. 3. The fabrication started with the deposition of the
undoped oxide, PSG, and phosphorus-doped polysilicon. The
channel length is determined by the thickness of the undoped
oxide film rather than the photolithography. The deposited layer
was then etched to form the pillar and followed by the arsenic
implantation for the source region in the substrate [Fig. 3(a)].
After a 15-nm lightly doped amorphous silicon film with
good conformity was deposited, a high-dose Si implantation
was carried out with tilt angle to break the interfacial oxide
[Fig. 3(b)]. Otherwise, this interfacial oxide will prevent the
silicon crystallization. The samples were then loaded into the
furnace and annealed at 590 C for 10 h to make sure the amorphous silicon on the sidewall becomes single crystal. It is worth
pointing out that some mechanical stress will exist between
the -Si and the sidewall oxide due to the different expansion
coefficients. Anisotropic dry etching was then carried out to
remove the ultrathin lightly doped silicon on the source/drain
regions [Fig. 3(c)] to provide low-contact resistance. It should
be noted that a thin deposited oxide film was needed to protect
the silicon on the sidewall before the anisotropic dry etching is
carried out. After removing the thin protecting oxide, a 3.3-nm
gate oxide was grown at 750 C by dry thermal oxidation and a
150 nm in situ boron-doped poly-Si Ge was deposited and
etched to form the gate spacer [Fig. 3(d)]. Low-temperature
oxide (LTO) was then deposited to cover the device, and rapid
thermal annealing (RTA) was implemented to form the LDD
through the out-diffusion of the PSG. On the other hand, the
1324
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 5, MAY 2003
Fig. 4. SEM micrographs of (a) the cross section and (b) the top view of the fabricated UTVC MOSFET.
dopants in the S/D also diffused into the channel region, and the
final channel length was determined by the difference between
the undoped oxide thickness and the S/D lateral diffusion,
which was less than 25 nm on each side. The rest of the process
such as contact opening, metal defining, and metal annealing
was carried out. An SEM micrograph of the cross section of
the fabricated UTVC MOSFET is shown in Fig. 4(a), in which
the oxide and PSG were etched in BOE (1:6) for 45 s to obtain
good contrast. It can also be seen that the conformity of the
amorphous silicon film deposited in the LPCVD system is
very good. A top view of the fabricated UTVC MOSFET is
shown in Fig. 4(b), and the source regions on both sides were
connected by metal.
IV. DEVICE CHARACTERIZATION
The
and
characteristics of the devices with 100-nm effective channel length are shown in
Fig. 5, and the current is normalized to the effective channel
W
. The devices have large on-curwidth
rent drive (210 A m, defined as the drain current at
V), low-leakage current (3 10
A m),
and steep subthreshold slope (76 mV/dec). The peak effecV is
tive mobility extracted at low drain bias
approximately 302 cm V s. The low-leakage current and
high-effective mobility indicate that the crystallized silicon film
is of good quality. The improved on-current drive is mainly due
cm
channel in the device.
to the lightly doped 1
Another reason is that the LDD in the device is asymmetric
and is fully overlapped with the poly-SiGe gate; thus, the series
resistance is smaller as compared to the conventional symmetric
LDD. However, the on-current drive is only approximately
half the saturation current reported in the roadmap [2]. This is
mainly attributed to the lack of the silicidation of the contacts,
the relatively thick gate oxide (3.3 nm), and the nonperfect
quality of the crystallized silicon. According to the scaling
rules, the appropriate gate oxide thickness for the devices with
100-nm channel length should be 2 nm, which will lead to a
higher current drive and better short-channel effects immunity.
In addition, the quality of the gate oxide grown on the crystallized silicon is very critical to obtain good device performance.
0
0
Fig. 5. (a) I
V and (b) I
V characteristics of the UTVC MOSFET
with an effective channel length of 100 nm.
If the gate oxide were not of good quality, the gate leakage
current of the device would be degraded significantly and the
poor Si/SiO interface would also be a cause for the reduction
of the on-current drive. In the experiment, the gate leakage
current of the gate oxide was measured to be approximately
A/cm , 5 10 A/cm , and 1 10
A/cm at
2 10
V, 2 V, and 3 V, respectively.
characteristics of the UTVC MOSFET with
The basic
50-nm effective channel length were reported elsewhere [11],
LIU et al.: ULTRATHIN VERTICAL CHANNEL MOSFET FOR SUB-100-nm APPLICATIONS
1325
0
Fig. 6. I
V characteristics of the UTVC MOSFET with an effective
channel length of 50 nm.
and the
characteristics are shown in Fig. 6. It can be
seen that the devices with 50-nm channel length still provide
good performance. The on-current drive, offstate leakage current, and subthreshold slope are 325 A m, 8 10 A m,
and 87 mV/dec, respectively. The threshold voltage is approximately 0.35 V, which is controlled by the work function of
the boron-doped poly-Si Ge gate. Compared to the devices
with 100-nm channel length, most of the device parameters, except the on-current drive, have degraded significantly because
of the short-channel effects. The parameter degradation can be
alleviated effectively by using a thinner channel and thinner gate
oxide. According to the roadmap, the appropriate gate oxide
thickness for the devices with 50-nm channel length is 1 nm;
however, the gate tunnelling current for 1 nm SiO is unacceptable. In order to continue scaling down the MOSFET while
keeping the good performance, high-k dielectrics (e.g., HfO
and ZrO ) may be used.
The threshold voltage rolloff characteristics of the UTVC
MOSFETs are shown in Fig. 7(a). The threshold voltage remains almost the same when the channel length is larger than
80 nm. But, it decreases rapidly when the channel length is
scaled down to 50 nm due to the short-channel effects. In addition, the threshold voltage in the saturation region is smaller
than that in the linear region because of the drain-induced barrier
lowering (DIBL) effect. Fig. 7(b) shows the dependence of the
threshold voltage on the drain voltage for the devices with different channel lengths. It can be clearly seen that the threshold
voltage decreases gradually as the drain voltage increases. It can
be explained as follows. When the drain voltage increases, a
larger electric field is coupled to the back gate through the back
oxide. Thus, the body potential is affected by the higher electric
field, and the back channel is turned on even though the gate
voltage is still at zero or negative bias. This is the reason why
and the leakage current
the threshold voltage variation
become larger as the drain voltage increases. The shorter the
channel length, the more the threshold voltage variation. For example, DIBL (defined as
V
V ) for
the 100 and 50 nm devices is 90 and 175 mV/V, respectively.
Dependence of the subthreshold slope of the UTVC MOSFETs on the effective channel length is shown in Fig. 8. For the
devices with 15-nm channel thickness, the subthreshold slope
Fig. 7. (a) Threshold voltage rolloff characteristics and (b) DIBL effect of the
UTVC MOSFET.
Fig. 8. Dependence of the subthreshold slope of the UTVC MOSFET on the
effective channel length (T is the channel thickness).
increases gradually from 75 to 95 mV/dec when the channel
length scales from 150 to 50 nm. However, for the devices
with 20-nm channel thickness, the subthreshold slope increases
rapidly when the channel length is less than 100 nm, and the
subthreshold slope for the 50-nm devices is approximately 125
mV/dec. This is because the gate controllability at the bottom
of the channel becomes weaker as the channel becomes thicker,
and the high-electric field coupled from the drain to the body
and the back channel has a larger effect. These degrade the
subthreshold slope and increase the offstate leakage current.
1326
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 5, MAY 2003
Fig. 9. I versus I for the UTVC MOSFET with different channel lengths
(I is measured at V
1:5 V, V = 0 V, and I is measured at V =
= 1:5 V).
V
=
Therefore, reducing the channel thickness is an effective way to
improve the short-channel effects of the UTVC MOSFETs. The
characteristics are summarized in Fig. 9. An on-current of 325 A m was obtained at a leakage current of 8 nA
for the 50-nm devices, and the smaller current drive compared
to the reported value (900 A m) in the ITRS roadmap [2]
might be due to the nonsilicidation of the source/drain contacts,
thicker gate oxide, and nonperfect quality of the crystallized
silicon film. The leakage current increases rapidly due to the
short-channel effects when the channel length is scaled down to
100 nm and beyond. It should be noted that the leakage current
also increases rapidly when the channel length becomes larger
than 250 nm. This is because the crystallized silicon layer is not
long enough, and the quality of the crystallized silicon layer
0.4 m . One way
begins to degrade after a certain length
to improve the maximum SPE length is to increase the initial
thickness of the deposited amorphous film such as using a
stacked layer of thick -Si/thin -SiGe/thin -Si. A maximum
SPE length of 2.5 m was obtained [18], and the thick -Si/thin
-SiGe layer on top of the thin -Si layer can be removed
using KOH KCr O H O and NH OH H O H O before
device fabrication.
Uniformity of the device performance is another important
issue for the devices fabricated on the crystallized SPE layer,
and it can be evaluated by measuring the statistical variation
of the device parameters. If the quality of the SPE layer degrades over a certain length or the MOSFET is too large, the
device performance and the uniformity of the performance will
characteristics of
become poor. Fig. 10 compares the
the 100-nm devices with 2- m (Device A) and 20- m (Device
B) channel widths. It can be seen that at negative gate bias, the
A m) is approxleakage current of Device B (6.5 10
imately one order of magnitude larger than that of Device A
A m). In addition, the subthreshold slope of De(5 10
vice B is also larger than that of Device A. All of these indicate that some defects exist in the crystallized channel region,
and this becomes more serious in the devices with wider channels. When the channel width increases, the probability for the
channel to encounter a dislocation becomes larger. Thus, the
leakage current increases as the channel width becomes larger.
0
Fig. 10. Comparison of I
with different channel widths.
V
characteristics of the 100-nm UTVC devices
Fig. 11. Schematic diagram of the proposed dislocation formation process.
Fig. 11 shows a proposed dislocation formation process in the
SPE layer. In the figure, the residual SiO is assumed to exist
even though high-dose Si implantation is used to break the interfacial oxide. During furnace annealing, the SPE starts at the
cleaned -Si/Si substrate interface. The crystallized silicon regions merge together on top of the residual oxide, and the merge
is not necessarily coherent in terms of lattice matching. Thus,
lattice mismatch and vertical dislocations occur. To reduce these
dislocations and obtain high-quality crystallized silicon film, the
native oxide has to be carefully removed before the amorphous
silicon deposition.
V. CONCLUSION
A high-performance UTVC MOSFET was experimentally demonstrated and characterized. The ultrathin channel
was obtained using solid phase epitaxy, and a boron-doped
gate was used to tune the threshold voltage.
poly-Si Ge
The asymmetric gate-overlapped LDD reduces the series resistance in both the source and drain regions, and it also reduces
the electric field at the drain. Thus the offstate leakage current
is suppressed. The channel thickness has been demonstrated
to have significant influence on the short-channel effects,
and the results show that reducing the channel thickness
of the UTVC MOSFET is an effective way to suppress the
LIU et al.: ULTRATHIN VERTICAL CHANNEL MOSFET FOR SUB-100-nm APPLICATIONS
short-channel effects. A channel length of 50 nm was achieved
with 15-nm-channel thickness in the experiment, and a channel
length of 15 nm should also be attainable if a 5-nm-channel
thickness is used. The experimental characterization of the
UTVC MOSFET indicates that it is promising for sub-100-nm
CMOS applications.
ACKNOWLEDGMENT
The authors would like to thank the fabrication staffs of the
Microelectronics Fabrication Facility (MFF) at the HKUST for
their help in the processing and their constant support.
REFERENCES
[1] H. S. P. Wong, D. J. Frank, P. M. Solomon, C. J. Wann, and F. J. Welser,
“Nanosacale CMOS,” Proc. IEEE, vol. 87, pp. 537–569, Apr. 1999.
[2] International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2001.
[3] C. K. Date and J. D. Plummer, “Suppression of the floating-body effect
using SiGe layers in vertical surrounding-gate MOSFETs,” IEEE Trans.
Electron Devices, vol. 48, pp. 2684–2689, 2001.
[4] H. Okada, Y. Uchida, M. Arai, S. Oda, and M. Matsumura, “Vertical-type amorphous silicon MOSFET ICs,” in Extended Abstracts
19th Conf. Solid State Devices and Materials, 1987, pp. 51–54.
[5] L. Risch, W. H. Krautschneider, F. Hofmann, H. Schafer, T. Aeugle, and
W. Rosner, “Vertical MOS transistor with 70 nm channel length,” IEEE
Trans. Electron Devices, vol. 43, pp. 1495–1498, Sept. 1996.
[6] C. Fink, J. Schulze, I. Eisele, W. Hansch, and W. Kanert, “Vertical power
MOSFETs with local channel doping,” in IEDM Tech. Dig., 2000, pp.
71–74.
[7] J. M. Hergenrother et al., “The vertical replacement-gate (VRG)
MOSFET: A 50-nm vertical MOSFET with lithography-independent
gate length,” in IEDM Tech. Dig., 1999, pp. 75–78.
[8] M. Yang, C. L. Chang, M. Carroll, and J. C. Sturm, “25 nm p-channel
vertical MOSFETs with SiGeC source-drain,” IEEE Electron Device
Lett., vol. 20, pp. 301–303, June 1999.
[9] K. C. Liu, S. K. Ray, S. K. Oswal, and S. K. Banerjee, “A deep submicron SiGe/Si vertical PMOSFET fabricated by Ge implantation,” IEEE
Electron Device Lett., vol. 19, pp. 13–15, Jan. 1998.
[10] T. Schulz, W. Rosner, L. Risch, A. Korbel, and U. Langmann, “Shortchannel vertical sidewall MOSFETs,” IEEE Trans. Electron Devices,
vol. 48, pp. 1783–1788, Aug. 2001.
[11] H. Liu, Z. Xiong, and J. K. O. Sin, “A novel ultra-thin vertical channel
NMOSFET with asymmetric fully overlapped LDD,” IEEE Electron
Device Lett., vol. 24, Feb. 2003.
[12] H. Liu, M. Kumar, and J. K. O. Sin, “A novel 3-D BiCMOS technology
using selective epitaxial growth and lateral solid-phase epitaxy,” IEEE
Electron Device Lett., vol. 23, pp. 151–153, Mar. 2002.
[13] Y. K. Choi, K. Asano, N. Lindert, V. Subramanian, T. J. King, J. B.
Bokor, and C. Hu, “Ultra-thin body SOI MOSFET for deep-sub-tenth
micron era,” in IEDM Tech. Dig., 1999, pp. 919–922.
[14] T. J. King, J. P. Mcvittie, K. C. Saraswat, and J. R. Pfiester, “Electrical
properties of heavily doped polycrystalline silicon-germanium films,”
IEEE Trans. Electron Devices, vol. 41, pp. 228–232, Feb. 1994.
[15] T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, “An asymmetric
sidewall process for higher performance LDD MOSFETs,” IEEE Trans.
Electron Devices, vol. 41, pp. 186–189, Feb. 1994.
[16] A. Korbel, T. Schulz, S. Mecking, and U. Langmann, “Extraction of
extended BSIM3v3.2.2 model card of vertical 130 nm Si p-MOSFET
for circuit simulation,” Proc. Inst. Elec. Eng. Circuits, Devices, Syst.,
vol. 149, no. 4, pp. 264–270, 2002.
[17] J. F. Chen, J. Tao, P. Fang, and C. Hu, “Performance and reliability comparison between asymmetric and symmetric LDD devices and logic,”
IEEE J. Solid-State Circuits, vol. 34, pp. 367–370, 1999.
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[18] B. J. Greene, J. Valentino, J. L. Hoyt, and J. F. Gibbons, “Thin single
crystal silicon on oxide by lateral solid phase epitaxy of amorphous
silicon and silicon germanium,” Mat. Res. Soc. Symp. A, vol. 609, pp.
9.3.1–6, 2000.
Haitao Liu received the B.S. and M.S. degrees from
Zhejiang University in 1996 and 1999, respectively.
He is currently pursuing the Ph.D. degree from Hong
Kong University of Science and Technology, Hong
Kong.
His research interests include semiconductor
devices and fabrication processes, high-frequency
semiconductor devices and RFIC design, and RF
MEMS systems.
Zhibin Xiong was born in Hengshan, China, in
1974. He received the B.S. and M.S. degrees from
Huazhong University of Science and Technology,
Wuhan, China, in 1995 and 1998, respectively. He is
currently pursuing the Ph.D. degree from Hong Kong
University of Science and Technology, Hong Kong.
From 1998 to 2000, he was with the ASIC Design
Department, Huawei, Corp., Shenzhen, as a Project
Manager, working on mixed signal ASIC design.
His research interests include thin-film transistors
and high-k materials.
Johnny K. O. Sin (S’80–M’81–SM’96) was born in
Hong Kong. He received the B.A.Sc., M.A.Sc., and
Ph.D. degrees, all in electrical engineering, from the
University of Toronto, Toronto, ON, Canada, in 1981,
1983, and 1988, respectively.
He joined Philips Laboratories, Briarcliff Manor,
NY, upon the completion of his Ph.D. studies, and
was a Senior Member of Research Staff there from
1988 to 1991. He joined the Department of Electrical
and Electronic Engineering, Hong Kong University
of Science and Technology (HKUST), Hong Kong,
in August 1991, and is currently a Professor. He is one of the founding members
of the Department, and has been serving as the Director of the Undergraduate
Studies Program in the department since Fall 1998. His research interests are
in the general area of microelectronic devices and fabrication technology. In
particular, he has been working in the areas of integrated microsystem-on-a-chip
using power semiconductor devices, thin-film transistors, silicon-on-insulator,
and RF devices, and integrated gas sensors for many years. He holds seven U.S.
patents and has published over 170 papers in technical journals and refereed
conferences in the aforementioned areas.
Prof. Sin is an Editor of IEEE ELECTRON DEVICE LETTERS. He is an
elected member of the EDS Administrative Committee and a member of the
EDS Power Devices and ICs Technical Committee. He served as Technical
Committee Member of the International Conference on Microelectronics
Test Structures (ICMTS). He is also a Technical Committee Member of the
International Symposium on Power Semiconductor Devices and ICs (ISPSD).
He was made an Honorary Visiting Professor of the Dalian University of
Technology, Dalian, China, in 1996. In Fall 1998, he was awarded the Teaching
Excellence Appreciation Award by the School of Engineering, HKUST.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
1401
SODEL FET: Novel Channel and Source/Drain
Profile Engineering Schemes by Selective
Si Epitaxial Growth Technology
Satoshi Inaba, Member, IEEE, Kiyotaka Miyano, Hajime Nagano, Akira Hokazono, Member, IEEE,
Kazuya Ohuchi, Member, IEEE, Ichiro Mizushima, Hisato Oyamatsu, Member, IEEE, Yoshitaka Tsunashima,
Kazunari Ishimaru, Member, IEEE, Yoshiaki Toyoshima, Member, IEEE, and Hidemi Ishiuchi, Member, IEEE
Abstract—In this paper, novel channel and source/drain profile
engineering schemes are proposed for sub-50-nm bulk CMOS
applications. This device, referred to as the silicon-on-depletion
layer FET (SODEL FET), has the depletion layer beneath the
channel region, which works as an insulator like a buried oxide in
a silicon-on-insulator MOSFET. Thanks to this channel structure,
junction capacitance ( ) has been reduced in SODEL FET,
(area) was
0 73 fF m2 both in SODEL nFET and
i.e.,
pFET at Vbias = 0 0 V. The body effect coefficient
is also
reduced to less than 0.02 V1 2 . Nevertheless, current drives of
886 A m ( o = 15 nA m) in nFET and 320 A m
( o = 10 nA m) in pFET have been achieved in 70-nm gate
length SODEL CMOS with dd = 1 2 V.
New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination
of SODEL FETs and bulk FETs on the same chip for 90-nm-node
generation and beyond.
Index Terms—Body effect, CMOS device, epitaxial growth,
floating-body effect (FBE), junction capacitance, logic circuits,
MOS devices, p-n junction, silicon-on-insulator (SOI) technology.
the history effect, wafer quality and cost, self-heating, and additional body contact area. If desirable SOI device characteristics were realized using conventional bulk CMOS technology, a
better solution would be available for high-performance CMOS
applications.
In this paper, the concepts of novel channel and source/drain
(S/D) impurity profile engineering are proposed for high-performance and low-power bulk CMOS devices to realize the benefits of PD-SOI CMOS. This transistor has an artificial depletion layer beneath the channel region, which electrically divides
the channel region from the substrate region, and it works as an
insulator similar to a buried oxide (BOX) in SOI. This device
is, therefore, referred to as the silicon-on-depletion layer FET
(SODEL FET) from the viewpoint of its structural property.
In the following, the characteristics of SODEL FET are
demonstrated based on both simulation and fabricated hardware results. New circuit design schemes using the combination
of SODEL CMOS and conventional bulk CMOS are proposed
for high-performance and low-power logic circuit applications.
I. INTRODUCTION
R
ECENTLY, partially depleted silicon-on-insulator (SOI)
(PD-SOI) CMOS has emerged as one of the promising
solutions for high-performance CMOS applications, offering
many advantages compared to the conventional bulk CMOS; it
due to the floating-body effect (FBE), smaller
has larger
junction capacitance ( ), and less body effect with substrate
bias voltage than bulk CMOS [1]. However, there are many disadvantages to be overcome for PD-SOI CMOS devices, such as
Manuscript received February 11, 2004 and revised April 26, 2004. The review of this paper was arranged by Editor C.-Y. Lu.
S. Inaba, A. Hokazono, K. Ohuchi, K. Ishimaru, and H. Ishiuchi are with the
SoC Research and Development Center, Toshiba Corporation Semiconductor
Company, Yokohama 235-8522 Japan (e-mail: satoshi1.inaba@toshiba.co.jp).
K. Miyano, H. Nagano, I. Mizushima, and Y. Tsunashima are with the Process
and Manufacturing Engineering Center, Toshiba Corporation Semiconductor
Company, Yokohama 235-8522 Japan.
H. Oyamatsu was with the SoC Research and Development Center, Toshiba
Corporation Semiconductor Company, Yokohama 235-8522 Japan. He is now
with the System LSI Division I, Toshiba Corporation Semiconductor Company,
Yokohama 235-8522 Japan.
Y. Toyoshima was with the SoC Research and Development Center, Toshiba
Corporation Semiconductor Company, Yokohama 235-8522 Japan. He is now
with the Toshiba-IBM Research and Development Center, Toshiba America
Electronic Components, Inc., Hopewell Junction, NY 12533 USA.
Digital Object Identifier 10.1109/TED.2004.833573
II. DEVICE STRUCTURE AND FABRICATION OF SODEL FETS
The basic idea of SODEL FETs is similar to shallow junction
well transistors (SJETs) [2], [3], pseudo-SOI [4], or Fermi
threshold transistors [5], which have a special p-n junction
region beneath the channel region in the substrate. As far as
we know, almost all such devices are intended to achieve fully
depleted (FD)-channel CMOS operation. The reduction of a
vertical electric field was expected in such MOSFETs by extending the channel depletion layer into the substrate. However,
could not be controlled arbitrarily
in view of the structure,
by channel doping, and sometimes metal gate electrodes were
used in such FETs, because fully depleted channel operation
required low impurity concentration in the channel region.
In addition, the depth and the distribution of impurity for the
channel and well region could not be precisely controlled
by the ion implant process only, because both the projection
) of the implanted ions are
range ( ) and the deviation (
functions of the implant energy, and they cannot be controlled
independently. Previously proposed devices, unfortunately,
did not realize enough thin body regions nor thin depletion
layer regions to prevent punch-through even for sub-0.25- m
generation CMOS. Therefore, further structural improvement is
required for high-performance sub-50-nm CMOS applications.
0018-9383/04$20.00 © 2004 IEEE
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Fig. 1. (a) Schematic illustration of a SODEL nFET and (b) simulated vertical
impurity profiles in the channel region in a SODEL nFET. SODEL pFET has the
same structure with anticonductive doped layers. The depletion layer is formed
beneath the channel region by Arsenic implant. An epitaxial channel silicon
layer is used to control the depth of the implanted arsenic region.
TABLE I
COMPARISON OF SODEL FETS AND PREVIOUSLY PROPOSED DEVICES
On the other hand, SODEL FET has further improved the
channel profile to achieve higher performance and higher
punch-through immunity for 90-nm-node CMOS and beyond
[6]. Fig. 1(a) is the schematic illustration of the concepts of
SODEL nFETs. Basically, a SODEL FET is formed on a bulk
Si substrate. The structural key features of SODEL FETs are as
follows.
1) A relatively thinner channel (body) region with higher
can be adjusted by the
channel impurity concentration.
channel implant condition.
2) An artificial depletion layer region formed by the p-n
junctions, which exists beneath the channel region ( body
region).
The body region is electrically isolated from the substrate
region by this artificial depletion layer, as in the case of the
BOX region in SOI. That is why this device is referred to as
SODEL FET. The differences between SODEL FETs and previously proposed devices are summarized in Table I.
Regarding the MOSFET device design, the process and
device simulations were carried out with in-house simulators
(TOPAZV2 and DSStation) to seek the optimal channel profiles, including the optimization of the depth and the width in
the vertical direction of the artificial depletion layer for SODEL
CMOS operation. An example of simulated channel impurity
profiles in SODEL nFETs is shown in Fig. 1(b). The artificial
depletion layer is formed by the stack of p/n / p-type layers
Fig. 2. Simulated vertical potential profiles with and without substrate bias
voltage in a SODEL nFET. At the surface channel region, both profiles are
application.
almost similar in spite of V
in nFET and n/p / n-type layers in pFET, respectively. The
impurity concentration of counter-type dopant layers (i.e., n
layer in nFET and p layer in pFET) should be sufficiently low
to be depleted by the built-in potential between the channel
region and the counter-doped region. In contrast to SJET [2],
[3] or pseudo-SOI [4], the impurity concentration of the surface
channel region in a SODEL FET is larger than that of the substrate region to adjust and to suppress surface punch-through.
This device should work like a partially depleted channel SOI
MOSFET.
Fig. 2 shows the simulated vertical potential profiles with or
without substrate bias voltage. The potential profiles in the surface channel region are almost the same, even in the case of
application. These simulated results suggest that the artificial depletion layer in a SODEL FET should work as well as a
BOX in a PD-SOI MOSFET. Therefore, we have expected that
device characteristics similar to those of PD-SOI CMOS could
be realized in SODEL CMOS.
Regarding the device fabrication, both n-type and p-type
SODEL FETs were fabricated on bulk Si (100) substrates
with 90-nm-node CMOS technology and a selective Si epitaxial growth technique. The process sequence is shown in
Fig. 3(a)–(e). After the device isolation and well ion implant to
the substrate [Fig. 3(a)], the counter-type dopant was implanted
to form a depletion layer region beneath the channel region
[Fig. 3(b)]. Then, an undoped selective Si epitaxial growth
process was applied at the channel region to control the depth
of the artificial depletion layer region. If there is no epi-Si layer,
we have to use much higher implant energy for counter doping,
in the artificial depletion
which should result in larger
layer region. The thickness of the undoped epi-Si layer was
sufficiently small (30–60 nm) to suppress SCE. An ion implant
adjustment was applied to the channel epi-Si region
for
[Fig. 3(c)].
Fig. 4 shows a transmission electron microscopy (TEM) photograph of the cross section ofa SODEL FET at the gate edge,
where the crystal defect has not been observed at the interface
between the channel region and the substrate. After the S/D
extension implant and gate sidewall spacer formation, a very
slightly raised S/D structure [7] was formed in some samples as
INABA et al.: SODEL FET: NOVEL CHANNEL AND SOURCE/DRAIN PROFILE ENGINEERING SCHEMES
1403
Fig. 5. Measured junction capacitance characteristics in a 90-nm-node
conventional bulk nFET and SODEL nFET. Less than half of C (conventional
bulk has been realized in the SODEL nFET.
SUMMARY
OF
TABLE II
MEASURED JUNCTION CAPACITANCES
CMOS DEVICES
IN
SODEL
III. DC CHARACTERISTICS IN SODEL CMOS DEVICES
Fig. 3.
Fabrication sequence of SODEL FET.
Fig. 4. TEM photograph of a cross section in an SODEL FET at the gate edge.
Almost no crystal defect has been observed at the interface between the epitaxial
Si channel and the substrate.
an option [Fig. 3(d)]. However, we have not seen a major impact of raised S/D on dc characteristics in this experiment. The
silicidation has been done with CoSi [Fig. 3(e)].
One of the important device characteristics in SODEL FETs
is the reduction of the parasitic capacitance. Fig. 5 shows the
and bias voltage both in SODEL nFET and
relationships of
the conventional bulk nFET, respectively. The referred conventional bulk nFET and pFET were fabricated with 90-nm-node
technology, similar to that in [8], but the details are not the same
as the latest generic 90-nm-node CMOS. Thanks to a special
in SODEL FET has been reduced, i.e.,
channel structure,
(area) was
fF m at Vbias
V both in nFET
(area) in
and pFET. As far as we know, this is the smallest
90-nm-node CMOS reported to date [9]. We have also found
were also reduced at the
that the perimeter components of
results, including the pFET case,
gate edge. Other measured
are summarized in Table II.
Another important device characteristic in SODEL FETs is
the smaller body effect than in conventional bulk MOSFETs.
characteristics at the triode region in
Fig. 6 shows –
SODEL nFETs and conventional bulk nFETs with different
and
V step),
substrate bias voltage (
shift has been observed in the
respectively. Apparently, less
– curve in SODEL nFETs by
application. –
relationships in SODEL CMOS and the conventional bulk
CMOS are compared in Fig. 7, where the body effect coeffiboth in SODEL nFETs
cient is reduced to less than 0.02
and pFETs, respectively. These results suggest that there is a
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
Fig. 6. Measured V
dependence of I –V characteristics in 90-nm-node
was
conventional bulk nFETs and SODEL nFETs in a triode region. V
changed from 0.0 V to 1:0 V with 0:5 V step. There is less V
dependence
in I characteristics in SODEL nFETs.
0
0
Fig. 8. Measured n+/p and p+/n junction leakage current characteristics in
SODEL nFETs and pFETs.
j
j
Fig. 7. Comparison of V shift versus sqrt( V
). The body effect
both in SODEL nFET and pFET.
coefficient was less than 0.02 V
floating body region in the SODEL FET structure; therefore,
the body effect is much smaller than that in the conventional
bulk CMOS, as expected from the simulation results shown
in Fig. 2. Leakage current at the S/D deep junction is also
improved in SODEL FETs, because the counter doped region
extends the depletion layer edge in p-n junction into a much
deeper portion of the substrate, and the electric field should be
weakened inthe p-n junction (Fig. 8).
roll-offs in both SODEL nFETs, and pFETs are shown in
Fig. 9, which shows the reasonable short-channel effects even
nm region. The scaling limit of these devices is
in a
not known at this moment. Further improvement of roll-offs
may be possible if the process parameters are e optimized, such
as the shallow doping profiles in the substrate or halo implant
optimization. We are now trying to miniaturize SODEL CMOS
in gate length, and the details will be discussed elsewhere. The
– characteristics of a 70-nm gate length SODEL CMOS
m with
are shown in Fig. 10, where current drives of 886
nA m and
m with
nA m
have been achieved at 1.2-V operation. The current drive in the
SODEL nFET is as high as that in the conventional 90-nm-node
nFET [8]. – characteristics in SODEL nFETs and pFETs
are shown in Fig. 11, where there is almost no kink in the curves.
The differences between SODEL FETs and PD-SOI FETs
are interesting and important. Fig. 12(a) shows the simulated
vertical potential distribution in the SODEL nFET again, where
stacked p/n / p-type layers compose a kind of bipolar transistor.
If energetic holes are generated by the impact ionization at the
channel region, they will be swept away into the substrate due to
this structure. Fig. 12(b) shows the simulated hole current density in the SODEL nFET, which supports this assumption. In
in the SODEL nFET
fact, as shown in Fig. 13, measured
was comparable to that in the conventional bulk nFET, though
at
V in the SODEL nFET has been
slightly higher
observed, and it may be due to some kind of bipolar action. This
phenomenon would be improved by the drain engineering or
by the reduction of operating voltage. The kink effect in –
characteristics, which is normally observed in PD-SOI FETs,
can be reasonably suppressed in SODEL FETs by hole current
flowing into a substrate, while the body region is almost floating.
Thanks to the bulk Si-based MOSFET structure, SODEL FETs
should ameliorate other disadvantages of SOI CMOS, such as
self-heating and the requirement of special design for body contacts, while the main advantage in PD-SOIs should be reproduced in SODEL CMOS as well.
DC characteristics of PD-SOI CMOS and SODEL CMOS are
compared in Table III. Again, SODEL FETs show better performance than conventional bulk CMOS without having disadvantages in PD-SOI CMOS.
IV. SODEL CMOS APPLICATIONS FOR OPTIMAL STATIC AND
DYNAMIC LOGIC CIRCUIT DESIGN
In this section, the impacts of SODEL CMOS on logic circuit performance are discussed. The figure-of-merits (FOMs)
inverters are calculated both for conventional bulk
for F/O
CMOS and SODEL CMOS [10]. The result shows that SODEL
faster switching speed than the convenCMOS has
tional bulk CMOS (Fig. 14), thanks to the reduction of parasitic
capacitances.
In general, PD-SOI CMOS is preferable for the multistacked
gate in static logic circuits because of the absence of body effect [11] and no current degradation by the substrate bias effect.
However, special care should be taken for the parasitic bipolar
leakage current and noise immunity for SOI CMOS. As described in the previous section, SODEL FETs have less body
effect than bulk MOSFETs, and they can also be applied to both
INABA et al.: SODEL FET: NOVEL CHANNEL AND SOURCE/DRAIN PROFILE ENGINEERING SCHEMES
Fig. 9.
1405
(a) V roll-off characteristics in SODEL nFETs and (b) pFETs.
Fig. 10. Measured I –V characteristics of SODEL nFET and pFET. Gate
length L was about 70 nm. At 1.2-V operation, current drives were 886 A=m
(I = 15 nA=m) in nFET and 320 A=m (I = 10 nA=m) in pFET,
respectively.
Fig. 12. (a) Simulated potential profile, and hole current in vertical direction
and (b) the distribution of hole current density in a SODEL nFET. Energetic
holes generated by impact ionization will be swept away into the substrate.
Therefore, less kink effect in I –V characteristics will be expected in a SODEL
nFET, even though the body region is almost floating.
Fig. 11. Measured I –V characteristics in SODEL nFET and pFET at 1.2 V
(0.1–V step). Gate length L was about 70 nm. Almost no kink has been observed
in SODEL nFETs.
Fig. 13. Measured I –V characteristics of SODEL nFET and conventional
in the SODEL nFET suggests that the harmful hole
bulk nFET. Measured I
accumulation is suppressed in the body region of the SODEL nFET. Slightly
higher I
at V = 1:2 V in the SODEL nFET may be due to some kind of
bipolar action.
static and dynamic logic circuits without having some of the disadvantages of an SOI MOSFET.
It is apparent that if some additional mask and implant
processes are used, SODEL CMOS and bulk CMOS can be
easily combined on the same chip; such a combination cannot
be easily realized in SOI CMOS using a conventional approach.
This combination, called “hybrid SODEL CMOS,” will realize
many advantages in logic circuit design. For example, in static
NAND logic circuits, SODEL FETs should be used for stacked
nFET portions for faster switching without body effects, and
bulk pFETs should be used for a load transistor to have a higher
noise margin as shown in Fig. 15 [11]. Instead of conventional
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COMPARISON
OF
TABLE III
DC CHARACTERISTICS IN PD-SOI CMOS
AND SODEL CMOS
Fig. 16. Example of hybrid SODEL CMOS for dynamic domino circuit. A
higher noise margin and less charge-sharing loss are expected in SODEL CMOS
than in PD-SOI CMOS.
ADVANTAGES
Fig. 14. Calculated FOM for conventional bulk CMOS and SODEL CMOS
based on the measured parameters. SODEL CMOS shows about
shorter delay time at the same technology node.
10 15%
Fig. 15. Example of hybrid SODEL CMOS for a static NAND circuit. SODEL
CMOS is suitable for high-speed multistacked logic, because it has less body
effect. Bulk pFETs are used in this circuit to realize a wide noise margin. For
high-speed CMOS applications, SODEL pFETs can be used in a pFET portion
with a slightly less noise margin.
bulk pFETs, SODEL pFETs are also applicable for high-speed
NAND logic applications with slightly less noise margin.
In dynamic domino circuits, SODEL FETs are suitable for
and the absence of body efinput gates because of smaller
fects. Bulk FETs should be combined in a precharge switch and
keeper transistor to realize stable operation without a dynamic
FBE, as shown in Fig. 16. SODEL nFETs can be also used for
clocked nFETs for low operating power applications, because
AND
TABLE IV
DISADVANTAGES OF THE PERFORMANCE
EACH CMOS DEVICE
FOR
the active power in SODEL nFETs should be smaller than that
in conventional bulk nFETs. Such a dynamic circuit with hybrid
SODEL CMOS should realize a higher noise margin than SOI
than
CMOS and less charge-sharing loss [11] with smaller
conventional bulk CMOS.
The advantages and disadvantages of each CMOS type
are summarized in Table IV, where the optimized hybrid
SODEL CMOS should show the best circuit performance for
silicon-on-a-chip (SoC) by combining the advantages of bulk
CMOS technology and PD-SOI CMOS technology. Hybrid
SODEL CMOS will also provide another solution for future
embedded memory applications like an eDRAM on a hybrid
bulk/SOI substrate [12], because SODEL CMOS can be easily
combined with conventional memory cell technology.
V. CONCLUSION
We have proposed a SODEL FET structure with new channel
and S/D profile engineering schemes, fabricated by a selective
Si epitaxial growth technique. It is demonstrated that SODEL
CMOS realizes unique characteristics, such as high current
, and small junction
drive, very small body effects, small
leakage current. The advantages of PD-SOI CMOS are reproduced in this bulk substrate-based SODEL FET without having
the disadvantages in PD-SOI CMOS.
Therefore, SODEL FET will provide a potential solution for
high-speed and low-power SoC applications in 90-nm-node
bulk CMOS generations and beyond.
INABA et al.: SODEL FET: NOVEL CHANNEL AND SOURCE/DRAIN PROFILE ENGINEERING SCHEMES
ACKNOWLEDGMENT
The authors would like to thank N. Aoki, H. Enda, H.
Tanimoto, and the personnel of the Advanced ULSI Wafer Processing Section, Advanced Microelectronics Center, Toshiba
Corporation Semiconductor Company, for useful discussions
and support. The authors are also grateful to Prof. T. Hiramoto
of the University of Tokyo, Prof. K. Shibahara of Hiroshima
University, Dr. H. Wakabayashi and Dr. K. Imai of NEC Corporation, and Prof. T. J. King of UC Berkeley for their useful
comments and suggestions.
REFERENCES
[1] D. H. Allen, A. G. Aipperspach, D. T. Cox, N. V. Phan, and S. N. Storino,
“A 0.2 m 1.8 V SOI 550 MHz 64 b PowerPC microprocessor with
copper interconnects,” in ISSCC Tech. Dig., 1999, pp. 438–439.
[2] T. Mizuno, Y. Asao, and J. Koga, “High-performance shallow junction
well transistor (SJET),” in Symp. VLSI Tech. Dig., 1991, pp. 109–110.
[3] H. Yoshimura, F. Matsuoka, and M. Kakumu, “New CMOS shallow
junction well FET structure (CMOS-SJET) for low power-supply
voltage,” in IEDM Tech. Dig., 1992, pp. 909–912.
[4] M. Miyamoto, R. Nagai, and T. Nagano, “Pseudo-SOI: P-N-P channeldoped bulk MOSFET for low-voltage high-speed applications,” IEEE
Trans. Electron Devices, vol. 48, pp. 2856–2860, Dec. 2001.
[5] A. W. Vinal, “Fermi threshold field effect transistor,” U. S. Patent 4 984
043, Jan. 8, 1991.
[6] S. Inaba, K. Miyano, A. Hokazono, K. Ohuchi, I. Mizushima, H. Oyamatsu, Y. Tsunashima, Y. Toyoshima, and H. Ishiuchi, “Silicon on depletion layer FET (SODEL FET) for sub-50 nm high performance CMOS
applications : Novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology,” in IEDM Tech. Dig., 2002, pp.
659–662.
[7] A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima,
and Y. Toyoshima, “Source/drain engineering for sub-100 nm CMOS
using selective epitaxial growth technique,” in IEDM Tech. Dig., 2000,
pp. 243–246.
[8] K. Miyashita, T. Nakayama, A. Oishi, R. Hasumi, M. Owada, S. Aota,
Y. Okayama, M. Matsumoto, H. Igarashi, T. Yoshida, K. Kasai, T.
Yoshitomi, Y. Fukaura, H. Kawasaki, K. Ishimaru, K. Adachi, M.
Fujiwara, K. Ohuchi, M. Takayanagi, H. Oyamatsu, F. Matsuoka, T.
Noguchi, and M. Kakumu, “A high performance 100 nm generation
SOC technology [CMOSIV] for high density embedded memory and
mixed signal LSIs,” in Symp. VLSI Tech. Dig., 2001, pp. 11–12.
[9] G. C-F. Yeap, J. Chen, P. Grudowski, Y. Jeon, Y. Shiho, W. Qi, S.
Jallepalli, N. Ramani, K. Hellig, L. Vishnubhotla, T. Luo, H. Tseng, Y.
Du, S. Lim, P. Abramowitz, C. Reddy, S. Parihar, R. Singh, M. Wright,
K. Petterson, N. Benavides, D. Bonser, T. V. Gompel, J. Conner, J. J.
Lee, M. Rendon, D. Hall, A. Nghiem, R. Stout, K. Weidemann, A.
Duvallet, J. Alvis, D. Dyer, D. Burnett, P. Ingersoll, K. Wimmer, S.
Veera-raghavan, M. Foisy, M. Hall, J. Pellerin, D. Wristers, M. Woo,
and C. Lage, “A 100 nm copper/low- bulk CMOS technology with
multi-V and multigate oxide integrated transistors for low standby
power, high performance and RF/analog system on chip applications,”
in Symp. VLSI Tech. Dig., 2002, pp. 16–17.
[10] A. Chatterjee, M. Rodder, and I.-C. Chen, “A transistor performance
figure-of-merit including the effect of gate resistance and its application to scaling to sub-0.25-mm CMOS logic technologies,” IEEE Trans.
Electron Devices, vol. 45, pp. 1246–1252, June 1998.
[11] K. Bernstein and N. J. Rohrer, SOI Circuit Design Concepts. Norwell,
MA: Kluwer, 2000, ch. 4 and 5.
[12] T. Yamada, K. Takahashi, H. Oyamatsu, H. Nagano, T. Sato, I.
Mizushima, S. Nitta, T. Hojo, K. Kokubun, K. Yasumoto, Y. Matsubara, T. Yoshida, S. Yamada, Y. Tsunashima, Y. Saito, S. Nadahara,
Y. Katsumata, M. Yoshimi, and H. Ishiuchi, “An embedded DRAM
technology on SOI/bulk hybrid substrate formed with SEG process
for high-end SOC application,” in Symp. VLSI Tech. Dig., 2002, pp.
112–113.
1407
Satoshi Inaba (M’98) was born in Kanagawa, Japan, in 1964. He received the
B.S. degree in applied physics in 1988 and the M.S. degree in physics in 1990,
both from Waseda University, Tokyo, Japan.
In 1990, he joined the ULSI Research Center, Toshiba Corporation,
Kawasaki, Japan, where he has been engaged in the research and development of 0.10-m gate length CMOS. In October 1994, he moved to the
Semiconductor Device Engineering Laboratory, and then to the ULSI Device
Engineering Laboratory, Microelectronics Engineering Laboratory, Toshiba
Corporation, Yokohama, Japan, from 1996 to 1998. From 1998 to 2000, he was
with the IBM-Siemens (now Infineon)-Toshiba 256-Mbit DRAM Development
Alliance, Hopewell Junction, NY, and was working on both the for 0.175-m
and 0.15-m DRAM support devices. He is currently a member of SoC
Research and Development Center, Toshiba Corporation Semiconductor Company, Yokohama Japan. His current research interests are the device physics and
fabrication technology of the high-speed and low-power dissipation sub-50-nm
gate length CMOS devices. He is also interested in the physics of electron
transport phenomena in very small Si-based electron devices.
Mr. Inaba has served as a Technical Subcommittee Member of the International Electron Devices Meeting from 2003 to 2004 and the International Conference on Solid State Devices and Materials from 2002 to 2004. He is a member
of the Physical Society of Japan and the Japan Society of Applied Physics.
Kiyotaka Miyano was born in Tokyo, Japan, in 1969. He received the B.E.
degree in applied physics from the University of Tokyo.
In 1994, he joined the Research and Development Center of Toshiba Corporation, Kawasaki, Japan, where he engaged in the metallization of ULSI. Since
2000, he has been with the Process and Manufacturing Engineering Center,
Toshiba Corporation Semiconductor Company, Yokohama, Japan. He is now
working on the research and development of advanced FEOL processes.
Hajime Nagano was born in Hyogo, Japan, in 1972. He received the B.S. and
M.S. degrees in electrical and electronics engineering from Chiba University,
Chiba, Japan in 1996 and 1998, respectively.
He joined the Microelectronics Center, Toshiba Corporation, where he engaged in the research and development of semiconductor substrates for ULSI.
He joined the Advanced Microelectronics Center, Toshiba Corporation Semiconductor Company, Yokohama, Japan, where he has been researching and developing the growth of single-crystal, poly-crystalline, and amorphous silicon
and silicon–germanium.
Akira Hokazono (M’00) was born in Kanagawa, Japan, in 1971. He received
the B.S. and M.S. degrees in electronics, information, and communication engineering from Waseda University, Tokyo, Japan, in 1994 and 1996, respectively.
In 1996, he joined ULSI Device Engineering Laboratory, Microelectronics
Engineering Laboratory, Toshiba Semiconductor Company Corporation, Yokohama, Japan, where he has been working on the research and development of a
scaled CMOS device.
Kazuya Ohuchi (M’96) received the B.S. degree in applied physics from the
University of Tokyo, Tokyo, Japan, in 1990.
He joined the Toshiba Research and Development Center, Toshiba Corporation, Kawasaki, Japan in 1990 and dealt with 100-nm MOSFETs device physics.
He moved to the Toshiba Semiconductor Device Engineering Laboratories in
1995 and developed Ti and Co Salicide technologies. He is currently a Specialist
in advanced CMOS technology development, SoC Research and Development
Center, Toshiba Semiconductor Company Corporation, Yokohama, Japan. His
current research interests are centered on the development of novel source/drain
technologies including ultrashallow junction, elevated source/drain and Salicide
technologies for high-performance sub-50-nm MOSFETs.
Mr. Ohuchi is a member of the IEEE Electron Device Society and Materials
Research Society.
1408
Ichiro Mizushima was born in Tokyo, Japan, in 1962. He received B.S., M.S.,
and Ph.D. degrees in electrical engineering from Keio University, Yokohama,
Japan, in 1984, 1986, and 1989, respectively. His Ph.D. work involved the solidphase crystallization of amorphous silicon.
He joined the ULSI Research Center, Toshiba Corporation, Kawasaki, Japan,
in 1990, where he was engaged in the research of doping technologies of silicon
and epitaxial growth. He is currently with the Process and Manufacturing Engineering Center, Toshiba Semiconductor Company Corporation, Yokohama, and
has been engaged in the research and development for front-end process technology of advanced LSI.
Dr. Mizushima is a member of the Japan Society of Applied Physics, the
Institute of Electronics, Information, and Communication Engineers, and the
Surface Science Society of Japan.
Hisato Oyamatsu (M’96) was with the SoC Research and Development Center,
Yokohama, Japan, and is now with Advanced Logic Technology Department,
System LSI Division I, Toshiba Corporation Semiconductor Company, Yokohama, Japan.
Yoshitaka Tsunashima was born in Tokyo, Japan, in 1956. He received the
B.S. degree in metallurgical engineering and M.S. degree in materials science
from Tokyo Institute of Technology, in 1980 and 1982, respectively.
In 1982, he joined Research and Development Laboratory, Toshiba Corporation, Kawasaki, Japan, where he worked on the research and development of
process technologies for VLSIs. In 1993, he participated in the 256-M DRAM
joint development project at the Advanced Semiconductor Technology Center,
IBM Corporation, Hopewell Junction, NY. In 1996, he joined the Microelectronics Engineering Laboratory, Toshiba Corporation Semiconductor Company,
Yokohama, Japan, and has been engaged in research and development of fabrication process of memory and logic LSIs. Since 2000, he has been a manager of
the front end of the line process development group. He is currently involved in
the area of high- gate dielectric/metal gate electrode, silicon epitaxy, surface
migration process, and all kinds of advanced hot and wet processes.
Mr. Tsunashima is a member of the IEEE Electron Devices Society and the
Japan Society of Applied Physics.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 9, SEPTEMBER 2004
Kazunari Ishimaru (M’96) received the B.S. degree in electronics and communication engineering from the Musashi Institute of Technology, Tokyo, Japan,
in 1986 and M.S. degree in electrical engineering from the Waseda University,
Tokyo, in 1988.
He joined Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan, in 1988, where he worked on BiCMOS technology
and developed high-speed cache SRAM. He also worked on development of
high-density 6T SRAM with shallow trench isolation technology. From 1997
to 1998, he was a Visiting Industrial Fellow at the University of California,
Berkeley. His research topics were future MOSFET model prediction by
BSIM3, sub-1-V device operation, and hot-carrier reliability. Now he is a
manager of the Advanced CMOS Technology Department, SoC Research and
Development Center, Toshiba Corporation Semiconductor Company, Yokohama, Japan. He is currently involved with CMOS technology development for
45-nm-node and beyond.
Mr. Ishimaru has served as a technical subcommittee member of the International Electron Devices Meeting from 2001 to 2004, and the International
Conference on Solid State Devices and Materials from 1999 to 2001. He is a
member of the IEEE Electron Device Society and the Institute of Electronics,
Information, and Communication Engineers.
Yoshiaki Toyoshima (M’91) was born in Chiba, Japan, in 1958. He received the
B.S. degree in electronics and communications in 1981 from Waseda University, Tokyo, JapanIn 1984, he joined Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan, where he has been engaged in the
development of ULSI device engineering. In 1994, He moved to the Semiconductor Division to develop and produce 64-bit Risc microprocessors. In 1997,
he moved to the ULSI Device Engineering Laboratory, Microelectronics Engineering Laboratory, Toshiba Corporation, Yokohama, Japan. For more than five
years, he worked on advanced CMOS device technologies. In August 2002, he
joined IBM-Sony-TOSHIBA SOI technology Development Alliance, Hopewell
Junction NY, as a director from Toshiba. His current research interests are the
high-speed CMOS device/process technology.
Mr. Toyoshima is a member of the IEEE Electron Devices Society.
Hidemi Ishiuchi (M’86) received the B.S. and M.S. degrees in physics at the
University of Tokyo, Tokyo, Japan, in 1978 and 1980, respectively.
He joined the Advanced CMOS Technology Department, SoC Research
and Development Center, Toshiba Corporation Semiconductor Company,
Yokohama, Japan, in 1980, working on DRAM development. From 1988 to
1989, he was with Stanford University, Stanford, CA, as a Visiting Scholar
to study BiCMOS technologies. From 1993 to 1995, he was with IBM, East
Fishkill, NY, as a Member of the 256-Mbit DRAM joint development project
among IBM, Siemens, and Toshiba. Since 1996, he has been working on the
development of advanced CMOS technologies including SOI MOSFETs, RF
mixed-signal CMOS technology, embedded DRAM technology, TCAD, etc.
Mr. Ishiuchi is a member of the Physical Society of Japan.
IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 9, SEPTEMBER 2004
661
A Stacked CMOS Technology on SOI Substrate
Shengdong Zhang, Ruqi Han, Xinnan Lin, Xusheng Wu, and Mansun Chan
Abstract—A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on
the SOI film and the n-MOSFET on the bulk substrate is
demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2)
self-aligned double-gate p-MOSFET with thick source/drain and
thin channel regions; 3) self-aligned channel region of n-MOSFET
to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and
loading. Experimental results show that the fabricated double-gate
p-MOSFET has a nearly ideal subthreshold swing and almost the
same current drive as the n-MOSFET with the same lateral width,
resulting in a highly compact and completely overlap stacked
CMOS inverter.
Index Terms—Double-gate, self-alignment, SOI CMOS, 3-D
integration.
I. INTRODUCTION
S
EMICONDUCTOR-on-insulator (SOI) technology has
been extensively studied due to its inherent merits such as
high-density, low-parasitic capacitance, and simple fabrication
process [1], [2]. All SOI CMOS technologies reported in the
literature have the devices and circuits fabricated on the silicon
films of the SOI wafers, whereas the high-quality single-crystal
bulk substrate is only used as a solid support. The availability of
silicon through the bulk substrate has not been utilized. On the
other hand, three-dimensional (3-D) integration technology is
also one of the most promising candidates for ULSI application
due to its high density and short interconnection [3], [4]. The
circuit architecture and material quality of the upper layers to
form 3-D structures are two major challenges.
In this work, a novel and very compact high-performance SOI
CMOS technology is demonstrated, in which both the silicon
film and the silicon base of the SOI wafer are utilized for device
and circuit formation. In an inverter structure, the p-MOSFET
is perfectly stacked on the n-MOSFET. Unlike other approaches
to form 3-D circuits that relies on recrystallized or laterally epitaxial active layers [5]–[7], the technology has the stacked devices formed using the in situ single-crystal silicon film and bulk
substrate of SOI wafers. The fabrication process is described in
detail in this paper. The transistor and inverter characteristics are
also presented and discussed.
Manuscript received March 15, 2004; revised June 14, 2004. This work is
sponsored by the Chinese Special funds for Major State Basic Research Projects
(Contract G20000365) and an Earmarked Grant HKUST 6190/01E from the
Research Grant Council of Hong Kong. The review of this letter was arranged
by Editor T.-J. King.
S. Zhang and R. Han are with the Institute of Microelectronics, Peking University, Beijing 100871, China (e-mail: zsd@ime.pku.edu.cn).
X. Lin, X. Wu, and M. Chan are with the Hong Kong University of Science
and Technology, Clear Water Bay, Kowloon, Hong Kong.
Digital Object Identifier 10.1109/LED.2004.834735
Fig. 1. Schematic diagram of the proposed 3-D SOI CMOS technology.
(a) Conventional SOI wafer as starting substrate. (b) CMOS inverter with
double-gate p-MOSFET stacked on bulk n-MOSFET.
II. CMOS ARCHITECTURE AND FABRICATION PROCESS
The proposed stacked architecture is shown in Fig. 1. A typical CMOS circuit is formed on a conventional SOI wafer with
the p-MOSFET on the in situ single-crystal silicon film and
the n-MOSFET on the bulk-silicon substrate. The p-MOSFET
has a double-gate structure and stacked perfectly on top the
n-MOSFET, allowing a very compact circuit. Over 60% area
saving is observed when compared with a conventional planar
CMOS technology.
The key processing steps to fabricate the stacked 3-D CMOS
circuit are schematically illustrated in Fig. 2. The starting material of is a SOI wafer with 200-nm buried-oxide film. The top
silicon film is first thinned down to 60 nm. A modified shallow
trench isolation (STI) process is used to define the active area.
After growing 15 nm of oxide and depositing 20 nm of nitride, a shallow trench with a total depth of 400 nm is etched as
shown in Fig. 2(a). The trench is refilled by depositing a 400-nm
LTO film, followed by planarization with chemical–mechanical
polishing (CMP) with the nitride as polish stop layer. The nitride is then removed and a 200-nm LTO is deposited as shown
in Fig. 2(b). A 12-nm nitride is then deposited right after patterning of the LTO/silicon/oxide stack as a spacer for the deep
source/drain region formation as shown in Fig. 2(c). As+ is implanted to form the source/drain region of the n-MOSFET on the
bulk substrate of the SOI wafer. A via hole is opened at the drain
region to connect the drain of the n-MOSFET to the drain of the
p-MOSFET in the formation of a CMOS inverter. 500 nm of
poly-Si is then deposited and planarized using CMP with the top
nitride as a stop layer. The poly-Si is then thinned to about 100
nm in TMAH and the exposed nitride is removed in hot H PO
as shown in Fig. 2(d). After that, a 150 nm a-Si is deposited
and the elevated part is removed by CMP as shown in Fig. 2(e).
Next, a B+ implantation is performed to dope the source/drain
regions of the p-MOSFET and the LTO on the top is removed in
buffered oxide etch (BOE). The active area of the p-MOSFET is
defined by patterning the polysilicon. The exposed oxide at the
bottom is subsequently removed in BOE as shown in Fig. 2(f).
0741-3106/04$20.00 © 2004 IEEE
662
IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 9, SEPTEMBER 2004
Fig. 2. Key fabrication steps of the 3-D CMOS devices and inverter.
Fig. 3.
(b) I
Note that a trench on the top of the silicon film and a tunnel beneath it are formed to define the dimension of the three channels
(two for the p-MOSFET and one for the n-MOSFET). The gate
oxides of both the n-MOSFET and the p-MOSFET are grown
together with thermal oxidation as shown in Fig. 2(g), followed
by a conformal deposition of 200-nm in situ doped poly-Si and
patterning to form the gate electrode as shown in Fig. 2(h). The
thermal oxidation step is also used for the activation of the implanted dopants in the source/drain regions.
The fabrication is completed with conventional back-end
processes including passive layer deposition, contact opening
and metallization as shown in Fig. 2(i). The final cross section from SEM is shown in Fig. 2(j). It is shown that the
fabricated 3-D CMOS architecture has following preferable
features: 1) self-aligned double-gate and thick source/drain
of p-MOSFET; 2) 2 channel width of p-MOSFET due to
the dual channels in spite of the same real estate; 3) perfectly
stacked p-MOSFET and n-MOSFET; and 4) short interconnect
distance between devices.
III. RESULTS AND DISCUSSION
The gate transfer and output characteristics of the fabricated
p-MOSFET and n-MOSFET are shown in Fig. 3. The gate
length, channel width and gate oxide thickness of the devices
are 0.22 m, 0.46 m and 8 nm, respectively. The effective
mobility is 526 cm V-s for the n-MOSFET and 274 cm V-s
for the p-MOSFET. The subthreshold slope is measured to
I–V characteristics of a fabricated CMOS devices. (a) I
.
V
V .
be 61.4 mV/dec for the p-MOSFET and 73.2 mV/dec for the
n-MOSFET. The nearly ideal subthreshold characteristics in
the p-MOSFET are attributed to the double-gate structure and
the high-quality single-crystal channel, whereas the slightly
compromised subthreshold swing in the n-MOSFET is due
are
to the bulk substrate used. The threshold voltages
measured to be 0.76 V for the p-MOSFET and 0.21 V for the
in the p-MOSFET is due
n-MOSFET. The relatively high
can be tuned using
to the use of the n+ poly-Si gate. The
body doping in principle. An undoped or lightly doped body is
variation caused by dopant
usually required to minimize the
fluctuation for extremely scaled device and to maintain a high
carrier mobility. The preferable solution to tuning and matching
is to use the metal-gate with proper work-function. The
the
metal gate can be used in the proposed technology since no
high temperature process is performed after the gate formation.
It is also observed in Fig. 3(b) that the double-gate
p-MOSFET has almost the same current drive as the
n-MOSFET with the same lateral width. As a result, the
p-MOSFET can be perfectly stacked on top of the n-MOSFET
to form a very compact and symmetric inverter. Furthermore,
the thick source/drain of the p-MOSFET also provides reasonable reduction in series resistance, thereby the overall
source/drain resistance is comparable to that of the n-MOSFET
formed on bulk silicon. Fig. 4 illustrates the voltage transfer
characteristics of the fabricated 3-D CMOS inverter. Good
ZHANG et al.: STACKED CMOS TECHNOLOGY ON SOI SUBSTRATE
663
is proposed and demonstrated. The technology allows perfect
stacking of p-MOSFET on-MOSFET to form a very compact
and symmetric inverter. The resulting p-MOSFET has a selfaligned double-gate and thick source/drain structure. The excellent characteristics of the fabricated devices and inverter confirm
the feasibility of the technology.
REFERENCES
Fig. 4. Voltage transfer characteristics of a fabricated 3-D stacked CMOS
inverter.
transfer characteristics with abrupt transition at both high and
low power supply are observed.
IV. CONCLUSION
A novel 3-D SOI CMOS technology utilizing both silicon
film and substrate of SOI wafers for device and circuit formation
[1] J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI.
Dordrecht, The Netherlands: Kluwer, 1991.
[2] G. G. Shahidi, “SOI technology for the GHz era,” IBM J. Res. Develop.,
vol. 46, no. 2/3, pp. 121–131, 2002.
[3] K. Banerjee, S. J. Souri, and K. C. Saraswat, “3-D ICs: a novel chip design for improving deep submicron interconnect performance and systems-on-chip integration,” Proc. IEEE, vol. 89, pp. 602–603, May 2001.
[4] K. C. Saraswat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W.
Wang, “Novel 3-D structures,” in Proc. 1999 IEEE Int. SOI Conf., 1999,
pp. 54–55.
[5] R. Zingg and B. Hofflinger, “Stacked CMOS inverter with symmetric
device performance,” in IEDM Tech. Dig., 1989, pp. 909–912.
[6] S. Pae, T. C. Su, J. P. Denton, and G. W. Neudeck, “Multiple layers of
silicon-on-insulator islands fabrication by selective epitaxial growth,”
IEEE Electron Device Lett., vol. 20, pp. 194–196, May 1999.
[7] V. W. C. Chan, P. C. H. Chan, and M. Chan, “Three dimensional CMOS
integrated circuits on large grain polysilicon films,” in IEDM Tech. Dig.,
2000, pp. 161–164.
IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 7, JULY 2004
453
AlGaN–GaN HEMTs on Si With Power Density
Performance of 1.9 W/mm at 10 GHz
A. Minko, V. Hoël, E. Morvan, B. Grimbert, A. Soltani, E. Delos, D. Ducatteau, C. Gaquière, D. Théron,
J. C. De Jaeger, H. Lahreche, L. Wedzikowski, R. Langer, and P. Bove
Abstract—AlGaN–GaN high electron mobility transistors
(HEMTs) on silicon substrate are fabricated. The device with
a gate length of 0.3- m and a total gate periphery of 300 m,
exhibits a maximum drain current density of 925 mA/mm at
GS = 0 V and DS = 5 V with an extrinsic transconductance
( ) of about 250 mS/mm. At 10 GHz, an output power density
of 1.9 W/mm associated to a power-added efficiency of 18% and
a linear gain of 16 dB are achieved at a drain bias of 30 V. To
our knowledge, these power results represent the highest output
power density ever reported at this frequency on GaN HEMT
grown on silicon substrates.
TABLE I
POWER DENSITY STATE-OF-THE-ART OF AlGaN–GaN HEMT
ON SILICON SUBSTRATES
Index Terms—AlGaN, amplification, GaN, high-electron mobility transistors (HEMTs), power, Si(111).
I. INTRODUCTION
HE AlGaN–GaN-based device technology is an attractive
solution for the high-power operations at high-frequencies
for next–generation microwave power amplifiers. GaN-based
high-electron mobility transistors (HEMTs) are excellent candidates for these applications at high temperatures with minimal cooling, because of their superior physical properties such
as a wide bandgap (3.4 eV), leading to high breakdown fields
V/cm and high saturation electron drift velocity
cm/s). The capability to achieve high output power densities at X-band up to Ka-band [1], [2] makes the AlGaN–GaN
HEMTs very interesting for the commercial and the military
power applications. Nowadays, GaAs– and InP-based HEMTs
are commonly used in front ends of microwave systems such
as telecommunications, but there is an increasing interest to use
the advantages of AlGaN–GaN HEMTs for these kind of applications in X-band. Recently several authors presented power
performances regarding AlGaN–GaN HEMTs on silicon substrates at different frequencies (Table I). In this contribution, a
record power density of 1.9 W/mm for a 0.3- m gate-length
AlGaN–GaN HEMTs on Si(111) at 10 GHz is reported. This
device also exhibits a power-added efficiency (PAE) of 18%, a
T
Manuscript received March 15, 2004; revised April 16, 2004. This work was
supported in part by the Ministry Of Defence (MOD) Délégation Générale de
l’Armement (DGA) under Contract 01.34.050, in part by the French Ministry
of Research, and in part by the European Community (EC) under the European
sources of Nitrides Materials (EURONIM) project The review of this letter was
arranged by Editor T. Mizutani.
A. Minko, V. Hoël, E. Morvan, B. Grimbert, A. Soltani, E. Delos, D. Ducatteau, C. Gaquière, D. Théron, and J. C. De Jaeger are with the Thales Institut
d’Electronique de Microéletronique et de Nanotechnologie (IEMN) Thalès
IEMN GaN Electronics Research (TIGER), Lille University, IEMN, Villeneuve
d’Ascq Cedex 59652, France (e-mail: auxence.minko@iemn.univ-lille1.fr).
H. Lahreche, L. Wedzikowski, R. Langer, and P. Bove are with the Picogiga
International, Courtaboeuf Cedex 91971, France.
Digital Object Identifier 10.1109/LED.2004.830272
linear gain of 16 dB, a current density of 925 mA/mm, a high
unity current gain cutoff frequency
of 30 GHz, and a maxof 72 GHz. The extrinsic
imum frequency of oscillation
transconductance is about 250 mS/mm. AlGaN–GaN HEMTs
on Si(111) substrate present the advantages of the large scale
and the availability of low cost silicon substrates. Nitride layers
grown on silicon have a strong tendency for cracking due to the
tensile strain which appears during the cooling of the samples
after growth. Hence, it is obviously a critical issue in order to
fabricate nitride based transistors. Recently, great progress was
obtained in the material quality [3]–[5] and processing for the
fabrication of AlGaN–GaN HEMTs based on Si(111).
II. GROWTH PROCESS AND DEVICE PROCESSING
The devices used in this letter are grown on silicon (111)
substrate by molecular beam epitaxy. The resistivity of the
cm. The epilayer contains a
Si substrate is about 2
40-nm-thick AlN nucleation layer, a 250-nm-thick GaN layer,
a 250-nm-thick AlN layer, a 2.5- m-thick of unintentionally
doped GaN buffer, a 25-nm-thick Al Ga N barrier, and a
1-nm-thick unintentionally doped GaN cap layer. This scheme
reduces the extensive stress appearing during the cooling of
the sample, and it allows the crack-free 2.5- m-thick GaN
buffer layer to be grown. The principle of the process used by
Picogiga International is described elsewhere [6]. It is based
on development work conducted CRHEA. Hall measurement
cm , an electron
shows a sheet-carrier density of
mobility of 1480 cm V s, a sheet square resistance of about
0741-3106/04$20.00 © 2004 IEEE
454
IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 7, JULY 2004
Fig. 2.
HEMT power characteristics against P , at V
= 30 V, V
=
AlGaN–GaN HEMT on Si(111).
03 V and f = 10 GHz for a 300 2 0:3 m
Fig. 1. (a) Typical dc (I–V) characteristics and (b) dc transfert characteristics
of a 300 0:3 m AlGaN–GaN HEMT (gate to drain spacing of 1.5 m).
2
340
at room temperature, and the density of dislocation is
cm to
cm .
about
The mesa isolation is defined by reactive ion etching using
8 sccm of SiCl gas, an RF power of 200 W, and a pressure of
40 mtorr. This results in an etch rate of 20 nm/min. The source
and drain ohmic contacts are formed using a rapid thermal
annealing (RTA) of evaporated Ti–Al–Ni–Au (12–200–40–100
nm) metallization at 900 C during 30 s under nitrogen
mm as
atmosphere. The ohmic contact resistance is 0.7
measured by the transmission line method. A T-shaped gate
based on Pt–Ti–Pt–Au (25–25–25–300 nm) metallization is
defined by electron-beam lithography using a bilayer resist
scheme. The two fingers devices are a 300- m gate width with
a drain–source spacing from 2.8 to 5.3 m and a gate–source
from 0.3 to 0.8
spacing of 1 m. Different gate lengths
m are available. In this letter, devices are unpassivated.
III. MEASUREMENT RESULTS
Devices selected for measurement have a gate length
- m and a source-drain distance
- m. The dc
characteristics measured on an HP4142B modular source and
monitor, show good static drain currents. Typical output characteristics of a 300- m AlGaN–GaN HEMT on Si(111) is shown
sweeping from 0 to 4 V. A maximum
in Fig. 1(a) with
mA/mm is obtained at a gate bias
drain current
of 0 V and at a drain bias of 5 V. The transfer characteristics
of the same device are shown in Fig. 1(b). An extrinsic peak
of approximately 250 mS/mm is meatransconductance
sured at a gate bias of 3.25 V for a drain bias of 10 V. The
V close to
breakdown voltage is about 100 V at
the pinchoff voltage. At the maximum output power, the maximum gate leakage current is 600 A. Furthermore, the insulating properties of the buffer grown on silicon substrate result
in a good pinchoff behavior as shown in Fig. 1(b).
Small signal gain measurements are achieved on the device.
The device calibration is performed by using on-wafer TRL
method. The S-parameters are measured using a HP8510C network analyzer connected to Picoprobe probes in the 0.5 to 50
GHz frequency range. The value of the unity current gain cutoff
frequency
is determined by the extrapolation of the
.
is determined
The maximum frequency of oscillation
and
values are,
from the Mason’s gain. The extrinsic
respectively, 30 and 72 GHz at
V for a 0.3- m
ratio of 2.4 is obtained.
gate length device. A good
This good RF performance associated to the high output power
(Table I) is attributed to the optimized device processing and
also to the high material quality.
Large signal power measurements are also performed at
10 GHz, by on wafer load-pull, using an automated load-pull
station with computer controlled mechanical tuners from focus
V and
V
microwaves. At the bias point
under class AB operation, selected devices show good perfor- m is
mance. A 300- m HEMT power sweep with
plotted in Fig. 2. It shows that an output power density of 1.9
W/mm, a maximum PAE of 18%, a linear gain of about 16 dB
and a power gain of 10 dB are achieved at the maximum output
power. To our knowledge, these are the best output power
density and PAE obtained for AlGaN–GaN HEMTs on silicon
substrates at 10 GHz.
IV. CONCLUSION
AlGaN–GaN HEMTs grown on silicon (111) substrate using
molecular beam epitaxy techniques are fabricated. At 10 GHz,
a record output power density as high as 1.9 W/mm is obtained.
MINKO et al.: AlGaN–GaN HEMTs ON Si WITH POWER DENSITY PERFORMANCE
This result shows the capability of AlGaN–GaN HEMTs on
Si(111) substrate for the power applications. This constitutes
an interesting alternative to devices grown on silicon carbide
substrates, including the advantage of making low cost devices.
silicon substrates MMICs can be also investigated for the fabrication of power amplifiers working in Ka-band. So, GaN-based
HEMTs on silicon substrate appear very interesting for future
high-power electronic applications. Continuous improvements
in the layer structure combined with advances in processing
should lead to the progress in power measurements of our
AlGaN–GaN Si(111) devices.
REFERENCES
[1] Y. F. Wu, B. P. Keller, S. Keller, D. Kapolnek, S. P. Denbaars, and U. K.
Mishra, “Very-high power density AlGaN–GaN HEMTs,” IEEE Electron Device Lett., vol. 48, pp. 586–590, Aug. 2001.
[2] C. Lee, H. Wang, J. Yang, L. Witkowski, M. Muir, M. A. Khan, and
P. Saunier, “State-of-art CW power density achieved at 26 GHz by
AlGaN–GaN HEMTs,” Electron. Lett., vol. 38, pp. 924–925, 2002.
[3] Y. Cordier, F. Semond, P. Lorenzini, N. Granjean, F. Natali, B. Damilano,
J. Massies, V. Hoel, A. Minko, N. Vellas, C. Gaquière, J. C. Dejaeger,
B. Dessertene, S. Cassette, M. Surrugue, D. Adam, J.-C. Grattepain, R.
Aubry, and S. L. Delage, “MBE growth of AlGaN–GaN HEMTs on resistive Si(111) substrate with RF small signal and power performances,”
J. Cryst. Growth, vol. 251, no. 1–4, pp. 811–815, 2003.
455
[4] J.-D. Brown, R. Borges, E. Piner, A. Vescan, S. Singhal, and R. Therrien, “AlGaN–GaN HFETs fabricated on 100-nm GaN on silicon (111)
substrates,” Solid State Electron., vol. 46, no. 10, pp. 1535–1539, 2002.
[5] P. Javorka, A. Alam, M. Marso, M. Wolter, A. Fox, M. Heukens, and
P. Kordos, “Fabrication and performance of AlGaN–GaN HEMTs on Si
(111) substrates,” Phys. Stat. Sol., A, vol. 194, no. 2, pp. 472–475, 2002.
[6] J. M. Berthoux, P. Vennéguès, F. Natali, E. Feltin, O. Tottereau, G. Nataf,
P. De Mierry, and F. Semond, “Growth of high-quality crack-free AlGaN
films on GaN templates using plastic relaxation through buried craks,”
J. Appl. Phys., vol. 94, no. 10, pp. 6499–6506, 2003.
[7] R. Behtash, H. Tobler, M. Neuburger, A. Schurr, H. Leier, Y. Cordier, F.
Semond, F. Natali, and J. Massies, “AlGaN–GaN HEMTs on Si (111)
with 6.6 W/mm output power density,” Electron. Lett., vol. 39, no. 7, pp.
626–628, Apr. 2003.
[8] R. Borges, J. Brown, A. Hanson, S. Singhal, A. Vescan, and P. Williams,
“GaN HFETs on silicon target wireless infrastructure market,” Comput.
Semicond., pp. 22–24, Aug. 2003.
[9] E. M. Chumbes, A. T. Schremer, A. J. Smart, Y. Wang, N. C. MacDonald, D. Hogue, J. J. Komiak, S. J. Lichwalla, R. E. Leoni, and J.
R. Shealy, “AlGaN–GaN high electron mobility transistors on Si (111)
substrates,” IEEE Trans. Electron Devices, vol. 48, pp. 420–425, Mar.
2001.
[10] W. E. Sutton, D. Pavlidis, H. Lahrèche, B. Damilano, and R. Langer,
“Large signal properties of AlGaN–GaN HEMTs on high resistivity silicon substrates grown by MBE,” in Proc. GAAS Symp., Munich, Germany, 2003.
244
IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004
A New InP–InGaAs HBT With a
Superlattice-Collector Structure
Jing-Yuh Chen, Der-Feng Guo, Member, IEEE, Shiou-Ying Cheng, Member, IEEE, Kuan-Ming Lee,
Chun-Yuan Chen, Hung-Ming Chuang, Ssu-Yi Fu, and Wen-Chau Liu, Senior Member, IEEE
TABLE I
STRUCTURES FOR DEVICE A AND DEVICE B
Abstract—The dc characteristics of an interesting InP–InGaAs
heterojunction bipolar transistor (HBT) with a superlattice (SL)
structure incorporated in the base–collector (B–C) junction
are demonstrated. In the SL structure, holes injected from
the collector collide with holes confined in the SL and impact
them out of the SL across the valence-band discontinuities.
With a collector–emitter (C–E) voltage CE less than the C–E
breakdown voltage
CE0 , the current gain can be increased
at base–current inputs because the released holes from the SL
inject into the base to cause the emitter–base junction operating
under more forward-biased condition. An ac current gain up to
204 is obtained. At base–emitter voltage BE inputs, the released
holes travel to the base terminal to decrease the base current. The
studied HBT exhibits common–emitter current gains exceeding 47
at low current levels and useful gains spreading over seven orders
of magnitude of collector current.
BV
Index Terms—Breakdown voltage (BV), impact ionization, multiple-quantum-well (MQW), superlattice (SL).
I. INTRODUCTION
ETEROJUNCTION bipolar transistors (HBTs) are attractive devices for driving optical-electrical sources due to
their high current gains and high output currents. By introducing
the impact ionization into the base–collector (B–C) junction,
the current gains and output currents can further be enhanced
[1]. Superlattice (SL) or multiple-quantum-well (MQW) structures with band discontinuities at the heterojunction interfaces
have been proposed as ones of the impact-ionization structures
[2]–[4]. In this letter, dc characteristics of an interesting InP–InGaAs based HBT wherein a SL structure is incorporated in the
B–C junction are studied and demonstrated. In the SL structure,
carriers confined in the SL are excited across the band discontinuities by impact ionization. Because the valance-band disis less than the conduction-band discontinuity
continuity
, the confinement effect of holes is weaker than that of
electrons in the SL structure. As a consequence, holes can be
released more easily than electrons from the SL structure. The
released holes inject into the base to increase the emitter–base
H
Manuscript received January 7, 2004; revised February 20, 2004. This work
was supported in part by the National Science Council of Taiwan, R.O.C., under
Contract NSC-92-2218-E006-032. The review of this letter was arranged by
Editor T. Mizutani.
J.-Y. Chen, K.-M. Lee, C.-Y. Chen, H.-M. Chuang, S.-Y. Fu, and W.-C. Liu
are with the Department of Electrical Engineering, Institute of Microelectronics, National Cheng-Kung University, Tainan 70101, Taiwan, R.O.C.
(e-mail: wcliu@mail.ncku.edu.tw).
D.-F. Guo is with the Department of Electronic Engineering, Chinese Air
Force Academy, Kang-shan, Taiwan, R.O.C.
S.-Y. Cheng is with the Department of Electronic Engineering, National I-Lan
University, I-Lan 26041, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LED.2004.826978
(E–B) forward-biased condition at base–current inputs. At B–E
inputs, the released holes travel to the base terminal
voltage
to decrease the base current. The current gain can, therefore, be
improved. With the bipolar structure serving as a high-gain controller and the SL structure as a gain promoter, the studied HBT
exhibits current gains exceeding 47 at low current levels and
useful gains spreading over a wide collector current range at a
less than the C–E breakcollector–emitter (C–E) voltage
down voltage
.
II. EXPERIMENT
As compared with GaAs-based HBTs, InP–InGaAs HBTs
have shown excellent high-frequency performances and are
promising candidates for high-speed applications. These
advantages of InP–InGaAs HBTs over GaAs-based HBTs
are attributed to the high electron ballistic velocity and high
electron mobility in the InGaAs base [5]–[8]. The studied
InP–InGaAs HBTs were grown by metal–organic chemical
vapor deposition (MOCVD) on semi-insulating InP substrates.
The unintentionally doped layer grown by this MOCVD
system exhibited the background donor concentration of
cm . In order to study the influence
of the impact ionization on the HBT characteristics, two
devices, denoted device A and B, were fabricated. Structures of device A and B are shown in Table I. Both devices
have similar structures. However, a five-period SL structure
was incorporated in the B–C junction of device A, whereas
-In Ga Al As
the SL was replaced by a 750layer in device B. The SL of device A was composed of
0741-3106/04$20.00 © 2004 IEEE
CHEN et al.: NEW InP–InGaAs HETEROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH A SUPERLATTICE-COLLECTOR STRUCTURE
Fig. 2.
Fig. 1. Base–collector junction band diagram of device A.
five-period 70- undoped In Al As barriers and 60undoped In Ga Al As wells. The constitutions of
-In Ga Al
As graded layers were linearly changed
between In Ga As and In Al As for device A, and
between In Ga As and In Ga Al As for device
B. Based on the previous related capacitance–voltage measurement, it is known that the additional incorporation effect
of impurity in SL region of the device A is negligible. After
finishing the growth, mesa-type devices were formed by utilizing photolithography, vacuum evaporation, liftoff, alloying,
and selective etching techniques. The etching was achieved by
employing H PO :H O :H O and H PO :HCl solutions to
remove the In(Ga)(Al)As and InP layers, respectively. AuGeNi
alloy was used for the emitter and collector Ohmic contacts,
and AuZn for the base Ohmic contact, respectively. An emitter
area of 50 50 m of the studied devices was used in this
letter.
III. RESULTS AND DISCUSSION
Many reports have been made on the impact ionization of SL
or MQW structures. The ionization mechanism of SL or MQW
structures mainly includes the band-to-band carrier ionization
and ionization across the band discontinuity [2]–[4], [9]. It is
known that the band-to-band carrier ionization dominates in the
SL structures whose well thicknesses exceed the threshold value
[10], [11].
of two impact ionization mean free paths
In device A, the ionization across the band discontinuity is dominant because the thickness of each well in the SL is only 60 .
Carriers confined in the SL are excited across the band discontinuity during the impact ionization. The electrical characteristics of device A may be understood with the aid of energy
band diagrams. Fig. 1 shows the B–C junction band diagram of
device A. In the B–C junction, the SL structure is sandwiched
between two 900- –graded i-InGaAlAs structures. Due to the
thermal generation of electrons and holes in the wells of the SL
structure, relatively large amounts of electrons and holes can be
stored in the wells. Based on the presence of 900- -graded i-InGaAlAs structures on both sides of the SL structure to minimize
tunneling effect, electrons and holes are confined in the wells
even under a strong electric field. The -InGaAlAs graded layer
245
Room-temperature Gummel plots of device A and B.
near the collector serves as a transit layer to accelerate holes injecting from the collector toward energy levels higher than the
barrier of the SL structure. When accelerated holes enter the
wells of the SL with sufficient energies, they can impact and
ionize bound holes out of the wells across the valence-band dis. Electrons injected into the SL from the base
continuity
may also impact and ionize electrons out of the wells across the
. Since the
is about
conduction-band discontinuity
two times of magnitude larger than the
for the SL structure, the impact ionization rate of electron is smaller than that
of hole [9]. Nevertheless, confined electrons in the wells can
if their energies are greater than
also jump across the
. The impact-ionized holes from the valence-band wells
will inject into the base to forward-bias the E–B junction at a
certain base–current input. The released electrons from the conduction-band wells will travel to the collector to contribute the
collector current. The current gain of the device can, therefore,
be improved.
Fig. 2 shows room-temperature Gummel plots of device A
V which is less than the
V of both
and B at
devices. The base current
of device A is smaller than that of
voltage, i.e.,
device B, which is more pronounced at low
voltage. This relatively small
in device A is mainly
high
attributed to the introduction of impact-ionized holes from the
SL structure. Because the hole current from the base to emitter
voltage, these impact-ionized holes will
is limited by the
travel to the base terminal. Therefore, the base current of device
of device A in low
A is smaller. The smaller collector current
regime may be resulted from the wider average energy gap
regime, the larger
of the B–C junction in device A. At high
of device A is principally due to the impact-ionized electrons
from the SL by high-energy electrons injected from the emitter.
and base current
The ideality factors of collector current
of device A are 1.19 and 1.35, respectively, from
to
0.8 V. The collector current is a portion of the emitter current that
is not lost in recombination when electrons are traveling to colis mostly determined by the electron
lector. Therefore, the
value
injection across the E–B junction. The difference of
from unity is attributed to the contribution of tunneling current
value is larger than
through the abrupt B–E junction. The
by 0.16. The departure of the
from
is mainly due to the
recombination in the space-charge region and the neutral base.
and
are nearly equal, the neutral base recomSince the
bination is the dominant component of the whole base current.
246
IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004
higher gain in device A is mainly caused by the injection of impact-ionized holes from the SL into the E–B junction and the
high-energy electrons jumping out of the SL to increase the collector current, as mentioned previous.
IV. CONCLUSION
Fig. 3. Room-temperature current gain as a function of collector current I
of device A and B.
A new InP–InGaAs HBT with a SL structure incorporated in
the B–C junction is fabricated and demonstrated. Impact-ionized holes from the valence-band wells of the SL inject into the
base to forward-bias the E–B junction, or reduce the base current. In addition, released electrons from the conduction-band
wells travel to the collector to contribute to the collector current. The current gain of the device can, therefore, be improved.
Common–emitter current gains greater than 47 for more than
seven orders of magnitude of collector current are obtained.
Also, an ac current gain up to 204 is observed.
REFERENCES
Fig. 4. Common–emitter I–V characteristics of device A and B at room
temperature.
Fig. 3 shows the common–emitter current gain as a function
for both devices at room temperature.
of collector current
Device A shows considerably higher current gains than device
B. The of device A is greater than 47 for more than 7 orders of
to
mA, and reaches
magnitude of , i.e., from
a maximum value of 220 around 20 mA. The of device A is
larger than 47 at low
regime. In addition, useful gains over
a wide collector range are obtained. The degradation of current
20 mA may be caused by the relatively long time
gain at
of holes to refill the quantum wells in the SL [9]. The detailed
mechanism is under studied.
In the measurement of common–base current–voltage (I–V)
characteristics of device A and B, the degradation of turnon
characteristics is not observed. Thus, due to the employment
of i-InGaAs spacer and i-InGaAlAs graded layers in the B–C
junction, the potential spike and blocking effect are almost eliminated. The corresponding common–emitter I–V characteristics
for both devices at room temperature are shown in Fig. 4. The
A/step. AC current gains of
applied base current is
204 and 40 are obtained for device A and B, respectively. The
[1] P. K. Bhattacharya, A. Chin, and K. S. Seo, “A controlled-avalanche
superlattice transistor,” IEEE Electron Device Lett., vol. EDL-8, pp.
19–21, Jan. 1987.
[2] R. Chin, N. Holonyak, G. E. Stillman, J. Y. Tang, and K. Hess, “Impact
ionization in multilayered heterojunction structures,” Electron. Lett.,
vol. 16, pp. 467–469, 1980.
[3] M. Tsuji, K. Makita, L. Watanabe, and K. Taguchi, “InAlGaAs impact ionization rates in bulk, superlattice, and sawtooth band structures,”
Appl. Phys. Lett., vol. 65, pp. 3248–3250, 1994.
[4] P. K. Bhattacharya, Y. Zebda, and J. Singh, “Electron and hole impact
Ga
As/Al Ga As coupled
ionization coefficients in GaAs/Al
well systems,” Appl. Phys. Lett., vol. 58, pp. 2791–2793, 1991.
[5] Y. Z. Xiong, G. I. Ng, H. Wang, and J. S. Fu, “DC and microwave noise
transient behavior of InP–InGaAs double heterojunction bipolar transistor (DHBT) with polyimide passivation,” IEEE Trans. Electron Devices, vol. 48, pp. 2192–2197, Dec. 2001.
[6] B. Willen, M. Rohner, V. Schwarz, and H. Jackel, “Experimental evaluation of the InP-InGaAs-HBT power-gain resonance,” IEEE Electron
Device Lett., vol. 23, pp. 579–581, June 2002.
[7] W. C. Wang, H. J. Pan, K. B. Thei, K. W. Lin, K. H. Yu, C. C. Cheng,
L. W. Laih, S. Y. Cheng, and W. C. Liu, “Observation of resonant tunneling effect and temperature dependent characteristics of an InP–InGaAs heterojunction bipolar transistor,” Semicond. Sci. Technol., vol.
15, pp. 935–940, 2000.
[8] W. C. Liu, H. J. Pan, W. C. Wang, K. B. Thei, K. W. Lin, K. H. Yu,
and C. C. Cheng, “Temperature-dependent study of a lattice-matched
InP–InGaAlAs heterojunction bipolar transistor,” IEEE Electron Device
Lett., vol. 21, pp. 524–527, June 2000.
[9] F. Capasso, J. Allam, A. Y. Cho, K. Mohammed, R. J. Malik, A. L.
Hutchinson, and D. Sivco, “New avalanche multiplication phenomenon
in quantum well superlattices: evidence of impact ionization across the
band-edge discontinuity,” Appl. Phys. Lett., vol. 48, pp. 1294–1296,
1986.
[10] K. Brennan, T. Wang, and K. Hess, “Theory of electron impact ionization including a potential step: Application to GaAs-AlGaAs,” IEEE
Electron Device Lett., vol. EDL-6, pp. 199–201, 1985.
[11] K. Mohammed, F. Capasso, J. Allam, A. Y. Cho, and A. L. Hutchinson,
In
As/Ga
In
As
“New high-speed long-wavelength Al
multiquantum well avalanche photodiodes,” Appl. Phys. Lett., vol. 47,
pp. 597–599, 1985.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
2631
InP/GaAsSb/InP Double HBTs: A New Alternative
for InP-Based DHBTs
C. R. Bolognesi, Member, IEEE, N. Matine, Martin W. Dvorak, Student Member, IEEE, P. Yeo, X. G. Xu, and
Simon P. Watkins, Member, IEEE
Abstract—We report on the physical operation and performance
of MOCVD-grown abrupt heterojunction InP/GaAs0 51 Sb0 49 /
InP double heterojunction bipolar transistors (DHBTs). In particular, the effect of the InP collector thickness on the breakdown
voltage and on the current gain cutoff frequency is assessed and
a T of 106 GHz is reported for a DHBT with a 400 Å base
and a 2000 Å InP collector with a
CEO of 8 V. We show that
InP/GaAsSb/InP DHBTs are characterized by a weak variation
of T as a function of temperature. Finally, we also demonstrate
that high maximum oscillation frequencies MAX
T can
be achieved in scaled high-speed InP/GaAsSb/InP DHBTs, and
provide estimates of the maximum cutoff frequencies achievable
for this emergent but promising material system. Recent results
on improved structures validate our performance predictions with
cutoff frequencies well beyond 200 GHz.
Index Terms—Heterojunction bipolar transistors (HBTs), millimeter wave bipolar transistors.
Fig. 1. Equilibrium band diagram for an InP/GaAs
Sb
/InP DHBT.
I. INTRODUCTION
I
nP/GaInAs-BASED heterojunction bipolar transistors
(HBTs) have demonstrated good cutoff frequencies but
suffer from low breakdown voltages because of the narrow
Ga In As collector energy gap of 0.75 eV [1], [2]. The
use of an Al In As or InP collector in double heterojunction bipolar transistors (DHBTs) enhances breakdown
voltages by reducing impact ionization in the collector layer,
but the latter improvement comes at the cost of a collector
current blocking effect caused by the positive conduction
band discontinuity between the GaInAs base and the wider
gap collector [3], [4]. The blocking effect increases carrier
, enhances
storage in the base and dramatically reduces
neutral base recombination, and by the same token reduces the
transistor current gain. Collector blocking can be alleviated by
doping and/or compositional grading schemes which however
complicate transistor design and impose stringent uniformity
and repeatability requirements on the epitaxial growth [3]–[5].
Although impressive laboratory results have been reported in
Manuscript received August 16, 1999; revised February 21, 2001. This work
was supported by the Canadian NSERC Strategic Research Project Program and
by Hewlett-Packard Research and Equipment Grants. The review of this paper
was arranged by Editors P. Asbeck and T. Nakamura.
C. R. Bolognesi is with the Compound Semiconductor Device Laboratory
(CSDL), School of Engineering Science, and the Department of Physics, Simon
Fraser University, Burnaby, BC V5A 1S6, Canada (e-mail: colombo@ieee.org).
N. Matine and M. W. Dvorak are with the Compound Semiconductor Device
Laboratory (CSDL), School of Engineering Science, Simon Fraser University,
Burnaby, BC V5A 1S6, Canada.
P. Yeo, X. G. Xu, and S. P. Watkins are with the Department of Physics, Simon
Fraser University, Burnaby, BC V5A 1S6, Canada.
Publisher Item Identifier S 0018-9383(01)09074-8.
such conventional DHBT structures, devices based on doping
and/or grading of the base-collector heterojunction have not yet
matured into products as of writing time. This calls attention
to the inherent challenges associated with the large scale
production of conventional DHBTs in the InP/GaInAs system.
The InP/GaAsSb heterojunction system is an attractive alternative to InP/GaInAs for DHBT implementation. At 300 K,
conduction band edge lies up 0.15 eV
the GaAs Sb
above that of InP [6], [7], thus enabling the implementation
of abrupt base-collector (B/C) heterojunctions, which do not
suffer from the collector blocking effect that plagues GaAsand InP-based DHBTs. As seen in Fig. 1, this advantageous
band lineup eliminates the collector blocking effect caused
by compositional changes at the base-collector junction and
instead launches electrons into the collector with a high initial electron velocity. The effect of the initial injection energy
into the collector remains to be clarified. On the one hand, an
initial velocity overshoot domain near the base reduces the collector signal delay, but on the other hand, launching electrons
with a significant initial energy may accelerate their transfer
to satellite valleys and thus reduce the overall electron transit
velocity through the InP collector. The measured energy gap
at 300 K is 0.72 eV [6], [8] and leads to
of GaAs Sb
eV with
a massive valence band discontinuity
InP. InP can thus also be used as a high-efficiency emitter
material with negligible hole back-injection when used in conbase. In addition, the small enjunction with a GaAs Sb
results in low emitter-base turn-on
ergy gap of GaAs Sb
voltages, which make these devices attractive for low-power
long-talk-time wireless communication systems. Along these
0018–9383/01$10.00 © 2001 IEEE
2632
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
lines, we recently demonstrated high-quality MOCVD-grown
lattice-matched NpN InP/GaAs Sb /InP DHBTs characterized by near ideal Gummel characteristics, collector offset
voltages as low as 14 mV, emitter turn-on voltages of 0.4 V,
high collector breakdown voltages, and a low output conductance [9], [10]. As pointed out in [10], the fundamental benefit
of this new system is that DHBTs can be implemented without
compositional grading and with nominally abrupt interfaces.
Turn-on voltages are then determined by the band lineups,
doping levels, and junction areas. They are not affected by the
effectiveness or lack thereof, of compositional grading and/or
pulse-doping schemes that are intended to overcome conduction band spikes and barriers. The DHBTs of [10] displayed a
GHz but suffered from
current gain cutoff frequency
20–25 GHz,
a low maximum oscillation frequency
which was largely due to the high base sheet resistance of the
) and the use of a wide
p-type GaAsSb base layer (1400
12 m . MOCVD-grown InP/GaAsSb
emitter stripe of 4
DHBTs were first reported by Bhat et al. and McDermott et
al. [11], [12], who showed devices with generally poor junction idealities and low current gains. McDermott et al. however, made the particularly important discovery that a GaAsSb
base layer eliminates the hydrogen passivation problem encountered in MOCVD-grown C-doped HBTs (thus removing
the requirement for postgrowth annealing cycles) and achieved
hole concentrations of 1.3 10 cm in as-grown material
[12]. On the other hand, [12] also reported that the hole mobility in GaAsSb was roughly 50–60% of that in GaInAs for
a given concentration. The latter finding appears to have deterred further development efforts with GaAsSb-based HBTs
on InP.
In the present article, we study several aspects of the operation and performance of high-speed InP/GaAsSb/InP DHBTs.
We examine the role of the InP collector thickness and its effects
and
and report on the temperature dependence
on
devices
of . W also describe the first high- and highachieved by appropriately scaling the junction areas. Finally, we
provide some tentative estimates of the potential ultimate cutoff
frequencies achievable in InP/GaAsSb/InP DHBTs. The paper
is organized in the following manner: Section II describes the
MOCVD growth and fabrication of our DHBTs, Section III focuses on the static properties of the transistors, and Section IV is
concerned with the microwave performance of the devices. Section IV has been augmented to reflect some more recent results
to account for the rapid evolution of InP/GaAsSb DHBTs since
the writing time of the original manuscript in the summer of
1999. In each section, we attempt to outline both the advantages
and drawbacks associated with InP/GaAsSb DHBTs as gauged
from our current understanding of this emergent but promising
material system. Potential avenues for further improvements of
device performance are also suggested where appropriate.
II. DEVICE GROWTH AND FABRICATION
Our InP/GaAs Sb
/InP DHBTs structures were grown
, unless specified otherwise) on exactly-oriented
(
(001) InP : Fe SUMITOMO substrates in a horizontal quartz
tube MOCVD system at a pressure of 100 torr. The precursors
Fig. 2. High-resolution SIMS profile around the base region in a MOCVDgrown InP/GaAsSb/InP DHBT. Carbon base doping shown on the left axis, all
other ion counts shown on the right axis. Measurements by Charles Evans and
Associates.
were TMIn, TEGa, TMSb, TBAs, and TBP, and the carrier
gas was Pd-diffused H . H S and CCl were the n- and p-type
dopant sources. CBr was also used as an alternate carbon
source in other experiments but we have not detected any
noticeable difference in transistor gain or base-sheet resistance
when compared to devices grown with CCl . All results reported here were achieved on CCl -doped layers. The susceptor
temperature was maintained at 560 C during the GaAsSb
growth and the V/III flux ratio was 2. The growth rate for
both InP and GaAsSb was 1.0 m/h. Device layers typically
consist of a 3000 Å GaInAs subcollector (S: 2 10 cm ),
an InP collector (S 10 cm , nominally undoped), a 400 Å
10 cm , a
GaAsSb base layer doped with carbon at 4
1500 Å InP emitter (S: 3 10 cm ), a 500 Å InP layer (S:
3 10 cm ), and a 2000 Å GaInAs Ohmic contact layer (S:
2 10 cm ). More details on the growth of these structures
can be found in [13].
Fig. 2 shows a high-resolution SIMS profile (measured
at Charles Evans and Associates) of the base region of an
InP/GaAsSb/InP DHBT test layer grown under conditions similar to those described previously. The apparent lack of mixing
or long range interface grading confirms the high-quality of
the epitaxial layers. Note that interfaces between the C-doped
GaAsSb base and the InP emitter and collector layers are quite
abrupt despite the fact that no element is conserved across
the InP–GaAsSb interface. For example, the Sb-ion counts
decay by an order of magnitude in a scan depth of 12–16 Å
or less around the interfaces. Beyond the apparent interface
abruptness and the good electrical quality (as seen below) of
our InP–GaAsSb heterojunctions, little is known about their detailed atomic configuration. The system is inherently interesting
because no one possible anion-cation bonding configuration
across the interface (i.e., In–As, In–Sb, or Ga–P bonds) is
lattice-matched to InP. We have so far determined that good
morphology (as determined by X-ray diffraction and atomic
force microscopy) and electrical and optical characteristics are
obtained by avoiding long soak times at the interfaces and that
little difference between various gas switching schemes in our
reactor as long as transition times are kept short.
BOLOGNESI et al.: InP/GaAsSb/InP DOUBLE HBTs
Fig. 3. Room temperature hole mobility in C-doped MOCVD-grown
Sb layers. The rapid drop in mobility near endpoints is attributed to
GaAs
a strong alloy scattering contribution in the GaAsSb ternary compound.
The previous growth conditions for GaAs Sb
result
in high base sheet resistances in comparison to those currently
achieved in state-of-the-art GaAs- and GaInAs-based HBTs
with similar base width and doping levels. Typically, base
are measured by the TLM
sheet resistances 1300–1900
method on a 400 Å base doped with C at 4 10 cm ,
in good agreement with Hall effect data, which reveal a hole
20–30 cm /Vs at room temperature. In
mobility of
comparison, similarly doped GaAs and Ga In As layers
exhibit mobilities of 120 cm /Vs and 40–50 cm /Vs [14]. The
reduced hole mobilities for GaInAs and GaAsSb in comparison
to GaAs are accounted for by the additional contribution of
alloy scattering in the ternary compounds. In this context, one
would expect the lowest mobility to be observed in GaAsSb:
in III–V compounds the valence band wavefunction is mainly
determined by the anion species, and compositional fluctuations in a mixed-group V alloy mostly perturb the valence
appears in
band edge position (that is, a larger fraction of
than in
for the GaAs : GaSb pair). In comparison,
GaInAs also suffers from alloy scattering, but its valence
band wavefunction experiences a weaker scattering potential
because the GaAs : InAs fluctuations occur on the cation (group
III) sublattice. Fig. 3 shows the measured variation of room
Sb as a function of the mole
temperature mobility in GaAs
for material grown in our MOCVD reactor with
fraction
C-doping at 2–6 10 cm . The rapid drop in hole mobility
with respect to the binary compounds certainly supports an
depenalloy scattering limited transport with a
dence of the scattering rate upon alloy composition. The issue
of hole transport and conductivity optimization in C-doped
GaAsSb base layers extends beyond the scope of the present
article and was examined in a separate publication focusing on
the effect of growth conditions and C-doping species [15].
Fully self-aligned DHBTs were fabricated by contact
lithography and wet etching as described in [16]. Conventional
Pt/Ti/Pt/Au and Ti/Pt/Au multilayers were electron beam evaporated to form the base and emitter/collector Ohmic contacts.
The emitter contact was annealed at 300 C while the base and
collector contacts were simultaneously annealed at 215 C.
2633
Fig. 4. Forward-mode collector current I (V ) and reverse-mode emitter
current I (V ). The overlap for low to intermediate currents confirms the
electrical symmetry of the E/B and C/B heterojunctions. The discrepancy at
higher currents is caused by the higher series resistance in the lightly doped InP
collector.
Base contact resistances of 1
10
-cm are extracted
from TLM pattern measurements with a sheet resistance of
1400
with TLM gaps accurately determined by SEM
measurements. In comparison, the same process on similarly
doped GaInAs base layers yields similar minimum contact re-cm (after annealing at 300 C) in our
sistances 1 10
laboratory. In principle at least, superior base Ohmic contacts
should be possible on GaAsSb because of the low Schottky
for holes on antimony-containing compounds.
barrier
Although we are not aware of any reported barrier heights on
GaAs Sb , chemical trends have long been known for
III–V compounds:. In general, the surface Fermi level pinning
energy progressively approaches the valence band maximum
As
Sb” anion series [17]. For example, GaAs
for the “P
0.5–0.6 eV, while GaSb is characterized
features
0.15–0.20 eV. In comparison, the surface Fermi level pinning
energy for Ga In As is 0.45 eV [18] above the valence
band maximum. The low base contact specific resistance
achievable on GaAsSb is an important potential technological
advantage for the fabrication of deep submicrometer emitter
HBTs where the specific base contact resistance can eventually
. Work is currently under
dominate the total base resistance
way to optimize the base contact process on GaAsSb.
III. DC CHARACTERISTICS
The symmetry of the InP/GaAsSb heterojunctions can be
verified by plotting the collector current in forward mode
(electrons injected down from the emitter) and the emitter
(electrons injected up from the
current in the reverse mode
collector and collected by the top emitter contact). According
and
should overlap if the
to the Moll–Ross relation,
E/B and C/B junctions are equivalent and if base transport
dominates transistor behavior as it does in a homojunction
bipolar transistor (i.e., when transport across the E/B and C/B
junctions does not dominate device behavior). Fig. 4 shows
that this is indeed the case in our InP/GaAsSb/InP DHBTs.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
Fig. 5. Common-base characteristics for a large area InP/GaAsSb/InP DHBT
V
with a 5000 Å InP collector. The near vertical turn-on at V
indicates there is no collector current blocking effect at the B/C heterojunction.
V.
The breakdown voltage is BV
= 17
01
Fig. 6. Common-emitter characteristics for the device of Fig. 6. The commonV, and the collector offset voltage
emitter breakdown voltage is BV
is V
mV.
1
= 50
= 15
The apparent equivalence between the E/B and C/B junctions
is further supported by the very low collector offset voltages
(14 mV) achievable InP/GaAsSb DHBTs, as already discussed
in [9]. The structural symmetry suggests that the co-integration
of emitter-up and collector-up DHBTs should prove more
straightforward in the InP/GaAsSb/InP system than in the
AlGaAs/GaAs or InP/GaInAs systems.
The absence of collector current blocking in our
InP/GaAsSb/InP DHBTs can be verified by examining
their common-base – characteristics. Fig. 5 shows the
characteristics of a large area transistor with a 5000 Å InP
collector layer. The transistors are clearly free of collector
1 V is
current blocking because the turn-on near
abrupt and the collector current is very nearly independent
in the turn-on region. Smaller area devices feature a
of
similar behavior at higher current densities. In common-base,
V.
the devices feature a breakdown voltage of
The corresponding common-emitter characteristics are shown
V and a low
in Fig. 6. The transistor displays a
Fig. 7. Common-emitter characteristics for a large area MBE-grown
InP/GaInAs SHBT with a 750 Å base (Be-doped) and a 7500 Å GaInAs
collector. The current scale (y -axis) is the same as in Fig. 6 to facilitate
comparison. Note the much-compressed voltage range of the GaInAs device.
Fig. 8. Comparison of Gummel characteristics for large area InP/GaAsSb/InP
DHBTs and InP/GaInAs SHBTs. The GaAsSb devices show lower turn-on
:
voltages and current ideality factors. The collector ideality factor n
indicates that electron injection in the GaAsSb base is thermal.
= 1 00
collector offset voltage which also indicates that no blocking
takes place at the base-collector junction, as expected from the
device band diagram. The relatively large
ratio shown here is routinely observed for our devices, but its
cause remains to be clarified. It may be pertinent to note that
ratio increases
it has been asserted that the
when nonlocal impact ionization effects occur in the collector
region of bipolar transistors [19].
–
characterFor comparison, Fig. 7 shows the
istics obtained for an MBE-grown abrupt heterojunction
InP/GaInAs SHBT (750 Å base, 7500 Å GaInAs collector
doped at 10 cm ) also fabricated in our laboratory using
the same fabrication technology. Clearly, the InP/GaAsSb/InP
DHBTs provide higher breakdown voltages, lower output
conductances, and smaller offset voltages. Fig. 8 contrasts the
measured Gummel characteristics. The GaInAs devices feature
(because
a collector current ideality factor of
of the thermionic contribution to electron injection across
BOLOGNESI et al.: InP/GaAsSb/InP DOUBLE HBTs
2635
Fig. 9. Current gain cutoff frequency dependence on current density for
1:5 V. Thicker
various InP collector designs in 4 12 m devices at V
undoped collectors display a dramatic Kirk-like effect.
2
=
the InP/GaInAs heterojunction) while the GaAsSb device is
characterized by collector current ideality factors
and a lower emitter turn-on voltage. The unity collector current
ideality factor indicates that electrons are injected into the
base thermally in contrast to the nonequilibGaAs Sb
rium injection that commonly takes place in abrupt InP/GaInAs
[20] or (Al,Ga,In)As/GaInAs HBTs.
IV. MICROWAVE CHARACTERIZATION
The present section first focuses on the room temperature microwave performance of InP/GaAsSb/InP DHBTs with various
is
InP collector thicknesses. The temperature dependence of
then characterized between 40 C and 100 C for a 3000 Å
InP collector thickness. These measurements are first performed
on larger area self-aligned devices (typically with 4 12 m
emitter contacts), which yield lower
values but have the
advantage of being implemented with a reduced process comtranplexity. We then report on the performance of high
sistors implemented by appropriately scaling the junction areas
to compensate the base resistance limitation of GaAsSb and thus
values.
yield high
A. Wide Emitter Stripe Devices (4
12 m )
The 300 K on-wafer microwave performance of InP/GaAsSb/
InP DHBTs was measured between DC and 40 GHz with an
HP8510 network analyzer equipped with GGB PicoProbe 40 A
extractions from the measured
coplanar probes. Preliminary
-parameter data were carried out for collector thicknesses of
2000 Å, 3000 Å, and 5000 Å on 4 12 m emitter devices with
voltages of 8, 10, and 15 V, respectively.
breakdown
dependence for devices with different
Fig. 9 shows the
InP collector thicknesses for devices with nominally undoped
collectors. The figure also shows that a higher collector doping
current
level of 10 cm can be used to increase the peak
density and the maximum cutoff frequency as well. Fig. 9 shows
value (106 GHz) is achieved with a 2000 Å collector
the best
layer.
Fig. 10. Current gain cutoff frequency dependence on current density with the
temperature as a parameter for a 4 12 m device.
2
The temperature dependence of
with a 3000 Å InP
collector was measured at Nortel Networks, Ottawa, ON,
between 40 C and 100 C by performing -parameter
measurements on a temperature-controlled Cascade probing
for
station. Fig. 10 shows the temperature variation of
a 4 12 m device. The InP/GaAsSb/InP transistors appear
very stable between 40 C and 50 C, and suffer only a
at 100 C ( 12.5%, over a 140 C
small decrease in peak
drop from
range). In comparison, Ahmari et al. reported an
61 GHz to 42 GHz ( 31%) over the temperature range ranging
from 20 C to 100 C for GaInP/GaAs HBTs with a 3 10 m
emitter and 3000 Å GaAs collector [21]. The AlInAs/GaInAs
from
SHBTs of Hafizi et al. showed a decrease in peak
145 GHz to 115 GHz ( 21%) between 25 C and 100 C,
and a 10% decrease between room temperature and 125 C
[22], which was attributed to the strong temperature dependence of electron transport in the Ga In As collector
layer. InP/GaAsSb/InP, DHBTs exhibit a superior temperature
stability that should prove attractive for applications requiring
stability over broad temperature excursions such as wireless
communication systems.
B. Scaled Devices (1
24 m )
where
(and
is the base sheet resisand
are the emitter contact width and
tance and
length) shows that the maximum oscillation frequency of
InP/GaAsSb/InP DHBTs can be significantly improved by
using narrower emitter stripes to reduce the base spreading
and by appropriately scaling the base contacts to
resistance
. We have therefore
reduce the base-collector capacitance
developed a more aggressively scaled self-aligned process
24 m emitter contact strip and a 2
24 m
with a 1
collector-base junction area implemented by controlled undercutting of the InP collector under the base contact by wet
etching. The process is based on optical contact lithography
and exclusively relies on selective wet etching. Fig. 11 shows
and the current gain
the extracted unilateral power gain
as a function of frequency for a 3000 Å InP collector.
The relation
2636
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
Fig. 11. Unilateral power gain and current gain as a function of frequency for a
1:5 V. Extrapolation at 20 dB/dec
1 24 m emitter device biased at V
yields f
= 90 GHz and f = 80 GHz for a 3000 Å InP collector.
2
=
0
Extrapolation at 20 dB/dec yields
GHz and
GHz. This is the first demonstration of a high
value (
) in a high-speed InP/GaAsSb/InP
DHBT, and superior performances could still be anticipated
from a stepper-based process allowing a tighter registration
between the emitter and base Ohmic contacts. The high base
sheet resistance represents a major challenge for GaAsSb
DHBTs because it necessitates the use of smaller geometry
values in InP/GaAsSb/InP
devices to achieve higher
DHBTs. Our laboratory is currently investigating a number of
design alternatives intended to reduce the base sheet resistance
such as the use of higher base C-doping levels to reduce
(without significant reductions in
the base sheet resistance
current gain), and the potential use of compressively-strained
GaAsSb bases which show mobilities comparable to those
achieved in GaInAs (see Fig. 3).
as a function of the inFig. 12 plots the total transit time
verse collector current density. The minimum transit time obis approximately equal
tained by extrapolation to
1.4–1.5 ps. The transit time is seen to increase
to
sharply at higher currents unless a higher reverse bias is applied to the base-collector junction. This indicates that the traveling electron space charge in the lightly-doped InP collector
in agreecan effectively limit the peak cutoff frequency
ment with the findings of Fig. 9, which shows that peak s
are reached at progressively lower current densities as the InP
collector thickness is increased unless a higher doping level is
employed. The increased transit time at high current densities
cannot be caused by a classical Kirk effect accompanied by
hole injection (i.e., base widening) into the InP collector besuppresses hole injection,
cause even a relatively small
as shown by Tiwari and Frank for AlGaAs/GaAs DHBTs [23].
Clearly, the classical base widening mechanism is even less
eV at the
a consideration with the very large
InP/GaAsSb heterojunction. The retarding alloy potential effect
[23], [24] that limits the high-current performance of conventional GaAs- and InP-based DHBTs cannot explain the rise in
seen in Fig. 12 either because the staggered InP/GaAsSb heterojunction is free of any opposing quasielectric field that could
Fig. 12. Transit time = 1=2f plotted versus inverse collector current
density for collector biases ranging from 1.0 V to 2.0 V. A minimum transit time
0.
of 1.4–1.6 ps is extrapolated to 1=J
!
be revealed by a large traveling electron space charge. The band
lineup of InP/GaAsSb/InP DHBTs therefore forces the conclusion that the high-current behavior of these devices is limited by
a Kirk-like effect akin to that already described by Cottrell and
Yu for SiGe HBTs [25] or by a suppression of the electric field
at the base/collector junction at high current densities.
C. Potential High-Speed Performance
The rapid improvement in the microwave performance of
InP/GaAsSb/InP DHBTs raises the question of the ultimate
potential frequency performance in this material system. At
this point, not enough information is available regarding the
electron transport properties in GaAsSb to provide an accurate
answer. Exploratory arguments must nonetheless be made to
provide some estimates of potential performances to come in
the InP/GaAsSb system.
As discussed above, electrons are thermally injected from the
InP emitter into the GaAsSb base which they cross by diffusion,
without the benefit of nonequilibrium transport. Both considerations place GaAsSb-based DHBTs at a disadvantage with respect to GaInAs-based devices in terms of base transit time. Two
mutually compatible options are then available to attempt to enhance the cutoff frequency by reducing the base transit time.
a) Incorporate a hot electron launcher emitter with a positive
with respect to the GaAsSb base.
b) Use a graded gap base layer to reduce the base transit time.
The first solution can be implemented with an Al In As
eV with respect
emitter which should provide
to the GaAsSb conduction band edge, assuming band offset
transitivity. Alternately, a Ga-rich strained GaInP emitter might
be considered, but our estimates based on the model-solid
theory [26] suggest the required Ga-mole fraction to overcome
eV at the InP–GaAsSb heterojunction
the
by incorporating Ga-to InP will likely result in excessive
amounts of tensile strain for high-quality epitaxy. The effects
of nonequilibrium base transport on the transit time through a
GaAsSb base still remain to be experimentally quantified.
BOLOGNESI et al.: InP/GaAsSb/InP DOUBLE HBTs
2637
The effect of energy gap grading in the base can be estimated if some tentative assumptions are first made. The minority electron mobility has not yet been determined for p-type
GaAs Sb . In the following considerations, we therefore
from the average collector saturation current values
estimate
measured on several large area emitter devices. As mentioned
earlier, our devices display a collector current ideality factor of
which indicates thermal injection into the base and
diffusive transport across the base. The collector current density
is then described by the relation
The average saturation current density can then be used to estimate the minority electron mobility (or diffusivity) from the
1.7
10 cm
(estimated
previous equation with
from the measured electron effective mass in GaAsSb [27] and
from the effective valence band densities of states in GaAs and
GaSb). For example, this procedure yields an electron mobility
cm /Vs for the structure of Fig. 2 with a base
of
10 cm , while it yields a value of
doping of 2
540–770 cm /Vs for a base doping of 4 10 cm for several
nominally identical growth runs. These findings suggest that the
GaAsSb could increase with
minority electron mobility in
increasing hole concentration as it does in GaInAs [28]–[30]
(and GaAs, to a lesser extent [29]). We note that these values
are comparable to the majority electron mobilities of McDermott et al. [12] who reported a mobility of 750 cm /Vs in n-type
GaAsSb (Te-doped, 10 cm ). The estimated minority electron mobility in the GaAsSb base is thus comparable to what is
found in heavily doped silicon, and is roughly four to five times
lower than similarly doped GaInAs layers, which are characterized by a minority electron mobility of 3000 cm /Vs [28],
[30]. The low electron mobility in the GaAsSb base layer represents another significant limitation if transport across the base is
purely diffusive. In the following, we make use of a drift/diffusion model of transport through a graded base [31] to estimate
the effect of grading on the base transit time. Fig. 13, which ascm /Vs, shows that even a modest amount
sumes
of grading across a 400 Å base region significantly reduces .
eV reduces the estiA base bandgap grading of
mated base transit time from 0.48 ps down to 0.18 ps. The necessary base bandgap grading can easily be implemented through
the incorporation of as little as a 10% Al-mole fraction near the
graded base layer latemitter to form an (Al,Ga)As Sb
tice-matched to InP. It should be emphasized that the above conwith
siderations do not account for the possible increase of
the base doping due to bandgap narrowing [32]. This may have
to a degree determined
caused us to somewhat overestimate
in GaAsSb around the doping
by the rate of change of
levels employed here.
We now turn to transport through the collector. Brennan and
Hess studied the high-field transport properties of GaAs, InP,
and InAs [33]. Their work is particularly relevant to the present
devices because they accounted for the effect of the initial electron injection energy. This aspect must be considered in the context of InP/GaAsSb/InP DHBTs because electrons are injected
Fig. 13. Effect of base gap grading on the base transit time for gradings of
E
, 50, and 100 meV based on an estimated minority electron mobility
cm /Vs.
of 1
=0
= 650
from the base into the InP collector with 0.15 eV with the
conduction band discontinuity at the GaAsSb–InP heterojunction. The simulations of [33] show that the nonzero initial injection energy can sometimes lead to longer transit times in high
electric fields because of the enhanced electron transfer to the
satellite valleys. Interestingly, Brennan and Hess also report that
initial injection energies 0.1 eV can cause significant ballistic
transport over a length scale of 1000–1500 Å, and their results
ps should be posshow that a collector signal delay
sible for a 2000 Å collector. Note that we extrapolate a minimum
, thus
transit time of 1.0 ps with a 2000 Å collector for
leaving some 0.8 ps to be made up by the sum of the base transit
time , and the collector charging delay
(the latter turns out to be 0.2 ps in the structures considered so
far). The remaining base transit time estimated in this fashion is
in general agreement with the base diffusion estimate of Fig. 13
given the range of .
ps with a 100 meV
Assuming a base transit time
ps for a 2000 Å InP
base grading, a collector delay
collector, and the current emitter charging delay of 0.5 ps, we
estimate a total transit time
ps or
GHz. It should in principle be possible
to reduce the emitter charging delay by optimizing the emitter
design (reduce the InP emitter thickness to minimize its series
resistance) and increasing the collector doping density to push
to a higher current density to yield maximum s
the peak
approaching 200 GHz for a 400 Å graded base and a 2000 Å
values of
InP collector. Such devices should maintain
approximately 8 V.
D. Recent Developments: Ultrahigh-Speed DHBTs
Progress in the high-speed performance of InP/GaAsSb
DHBTs has been swift since the writing time of our original
manuscript (summer of 1999). We have successfully pursued
the development of ultrahigh speed devices by incorporating
the following changes to the general structure discussed in
Section II.
1) The base layer was thinned to 200 Å to reduce the base
transit time, and the base C-doping level was increased
2638
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 11, NOVEMBER 2001
the large valence band discontinuity at the GaAsSb/InP junction
suppresses hole injection into the InP collector layer. These recent results lend support to the physical picture of InP/GaAsSb
DHBT operation presented above: the
GHz is particularly satisfying because of the equivalence of base transit times
for a uniform 200 Å base and the 400 Å base with a 100 meV
grade predicted in Fig. 13. A more aggressive exploitation of the
above trends coupled with significant process technology improvements have permitted the realization of an unprecedented
250 GHz DHBT performance [34]: these results will be discussed in a separate publication.
ACKNOWLEDGMENT
Fig. 14. Microwave performance of a 200 Å base InP/GaAsSb/InP DHBT with
210 GHz
a 1 12 m emitter contact: extrapolation at 6 dB/oct yields f
and f
200 GHz. The device BV
was 6 V due to the higher collector
doping.
2
0
=
The authors would like to thank Dr. N. Moll from the Hewlett
Packard Research Laboratories (now Agilent Laboratories),
Palo Alto, CA, for his encouragement, support, and stimulating
discussions on HBT physics. They would also like to thank
T. W. MacElwee, Nortel Networks, Ottawa, ON, Canada, for
temperature dependent measurements (Fig. 10).
REFERENCES
Fig. 15. Minimum transistor delay as a function of collector bias. Delays
corresponding to f s of 160 and 200 GHz are also shown for reference.
to 8 10 cm by taking advantage of the affinity of
) for C as an acceptor impurity.
GaAsSb (
2) The lightly-doped portion of the InP emitter was thinned
from 1500 Å to 750 Å to reduce the emitter series resistance.
3) A doping level of 2–3 10 cm was used in our 2000
Å InP collector layers to enable operation and higher current densities for lower emitter dynamic resistances.
Fig. 14 shows the current gain and relevant power gains extracted from on-wafer scattering parameter measurements on a
typical device with a 1 12 m emitter contact characterized
V: extrapolation from the
by a breakdown voltage
measured data with a 20 dB/dec roll-off results in
GHz and
195–220 GHz. Note that the base sheet resistance for this heavily doped 200 Å base layer was 1400
and that the emitter contact is undercut by about 0.4 m. Fig. 15
dependence of the minimum transistor delay (exshows the
. It
trapolated to infinite emitter current level, or
is important to note that very short delay times are maintained
even for operation in the saturation mode of operation because
[1] Y. K. Chen, R. N. Nottenburg, M. B. Panish, R. A. Hamm, and D. A.
Humphrey, “Subpicosecond InP/InGaAs heterostructure bipolar transistors,” IEEE Electron Device Lett., vol. 10, pp. 267–269, 1989.
[2] Q. Lee, B. Agarwal, D. Mensa, R. Pullela, J. Guthrie, L. Samoska, and
transferred-substrate heterojuncM. J. W. Rodwell, “A >400 GHz f
tion bipolar transistor IC technology,” IEEE Electron Device Lett., vol.
19, pp. 77–79, 1998.
[3] K. Kurishima, H. Nakajima, T. Kobayashi, Y. Matsuoka, and T.
Ishibashi, “High-speed InP/InGaAs double-heterostructure bipolar
transistors with suppressed collector current blocking,” Appl. Phys.
Lett., vol. 62, pp. 2372–2374, 1993.
[4] E. F. Chor and C. J. Peng, “Composite step-graded collector of InP/InGaAs/InP DHBT for minimized carrier blocking,” Electron. Lett., vol.
32, pp. 1409–1410, 1996.
[5] C. Nguyen, T. Liu, M. Chen, H.-C. Sun, and D. Rensch,
“AlInAs/GaInAs/InP double heterojunction bipolar transistor with a
novel base-collector design for power applications,” IEEE Electron
Devices Lett., vol. 17, pp. 133–135, 1996.
[6] J. Hu, X. G. Xu, J. A. H. Stotz, S. P. Watkins, A. E. Curzon, M. L. W.
Thewalt, N. Matine, and C. R. Bolognesi, “Type II photoluminescence
and conduction band offsets of GaAsSb/InGaAs and GaAsSb/InP heterostructures grown by metalorganic vapor phase epitaxy,” Appl. Phys.
Lett., vol. 73, pp. 2799–2801, 1998.
[7] M. Peter, N. Herres, F. Fuchs, K. Winkler, K.-H. Bachem, and J. Wagner,
“Band gaps and band offsets in strained GaAs
Sb on InP grown by
metalorganic chemical vapor deposition,” Appl. Phys. Lett., vol. 74, pp.
410–412, 1999.
[8] J. Klem, D. Huang, H. Morkoç, Y. E. Ihm, and N. Otsuka, “Molecular
beam epitaxial growth and low-temperature optical characterization of
GaAs Sb on InP,” Appl. Phys. Lett., vol. 550, pp. 1364–1367, 1989.
[9] N. Matine, M. W. Dvorak, C. R. Bolognesi, X. Xu, J. Hu, S. P. Watkins,
and M. L. W. Thewalt, “Nearly ideal InP/GaAsSb/InP double heterojunction bipolar transistors with ballistically launched collector electrons,” Electron. Lett., vol. 34, pp. 1700–1702, 1998.
[10] C. R. Bolognesi, N. Matine, M. W. Dvorak, X. G. Xu, J. Hu, and S. P.
Watkins, “Non-blocking collector InP/GaAsSb/InP double heterojunction bipolar transistors with a staggered lineup base–collector junction,”
IEEE Electron Device Lett., vol. 20, pp. 155–157, 1999.
[11] R. Bhat, W. P. Hong, C. Caneau, M. A. Koza, C. K. Nguyen, and
S. Goswami, “InP/GaAsSb/InP and InP/GaAsSb/InGaAsP double
heterojunction bipolar transistors with a carbon-doped base grown by
organometallic chemical vapor deposition,” Appl. Phys. Lett., vol. 68,
pp. 985–987, 1996.
[12] B. T. McDermott, E. R. Gertner, S. Pittman, C. W. Seabury, and M.
F. Chang, “Growth and doping of GaAsSb via metalorganic chemical
vapor deposition for InP heterojunction bipolar transistors,” Appl. Phys.
Lett., vol. 68, pp. 1386–1388, 1996.
BOLOGNESI et al.: InP/GaAsSb/InP DOUBLE HBTs
2639
[13] X. G. Xu, J. Hu, S. P. Watkins, N. Matine, M. W. Dvorak, and C.
R. Bolognesi, “Metalorganic vapor phase epitaxy of high-quality
GaAs Sb and its application to heterostructure bipolar transistors,”
Appl. Phys. Lett., vol. 74, pp. 976–978, 1999.
[14] R. A. Hamm, R. Malik, D. Humphrey, R. Ryan, S. Chandrasekhar, L.
In
As using carLunardi, and M. Geva, “Carbon doping of Ga
bontetrabromide by metalorganic molecular beam epitaxy for InP-based
heterostructure bipolar transistor devices,” Appl. Phys. Lett., vol. 67, pp.
2226–2228, 1995.
[15] S. P. Watkins, O. J. Pitts, C. Dale, X. G. Xu, M. W. Dvorak, N. Matine,
and C. R. Bolognesi, “Heavily carbon-doped GaAsSb grown on InP for
HBT applications,” J. Cryst. Growth, vol. 221, pp. 59–65, 2000.
[16] N. Matine, M. W. Dvorak, J. L. Pelouard, F. Pardo, and C. R. Bolognesi,
“Fabrication and characterization of InP heterojunction bipolar transistors with emitter edges parallel to [001] and [010] crystal orientations,”
Jpn. J. Appl. Phys., vol. 38, pp. 1200–1203, 1999.
[17] K. W. Böer, Survey of Semiconductor Physics. New York: Van Nostrand Reinhold, 1992, vol. II.
[18] E. H. Rhoderick and R. H. Williams, Metal–Semiconductor Contacts,
2nd ed. Oxford, U.K.: Clarendon Press, 1988, vol. 19.
[19] M. J. Kumar and D. J. Roulston, “Miller’s approximation in advanced
bipolar transistors under nonlocal impact ionization conditions,” IEEE
Trans. Electron Devices, vol. 41, pp. 2471–2473, 1994.
[20] R. Teissier, J. L. Pelouard, and F. Mollot, “Direct measurement of ballistic electron distribution and relaxation length in InP-based heterojunction bipolar transistors using electroluminescence spectroscopy,” Appl.
Phys. Lett., vol. 72, pp. 2730–2732, 1998.
[21] D. A. Ahmari, G. Raghavan, Q. J. Hartmann, M. L. Hattendorf, and G.
E. Stillman, “Temperature dependence of InGaP/GaAs heterojunction
bipolar transistor DC and small-signal behavior,” IEEE Trans. Electron
Devices, vol. 46, pp. 634–640, 1999.
[22] M. Hafizi, W. E. Stanchina, R. A. Metzger, P. A. Macdonald, and F.
Williams, “Temperature dependence of DC and RF characteristics
of AlInAs/GaInAs HBTs,” IEEE Electron Device Lett., vol. 40, pp.
1583–1588, 1993.
[23] S. Tiwari and D. J. Frank, “Analysis of the operation of GaAlAs/GaAs
HBTs,” IEEE Trans. Electron Devices, vol. 36, pp. 2105–2121, 1989.
[24] S. Tiwari, “A new effect at high currents in heterostructure bipolar transistors,” IEEE Electron Device Lett., vol. 9, pp. 142–144, 1988.
[25] P. E. Cottrell and Z. Yu, “Velocity saturation in the collector of
/Si HBTs,” IEEE Electron Device Lett., vol. 11, p. 431,
Si/Ge Si
1990.
[26] C. G. Van de Walle, “Band lineups and deformation potentials in the
model-solid theory,” Phys. Rev. B, vol. 39, pp. 1871–1883, 1989.
[27] P. Devlin, H. M. Heravi, and J. C. Woolley, “Electron effective mass
alloys,” Can. J. Phys., vol. 59, pp. 939–944,
values in GaAs Sb
1981.
[28] E. S. Harmon, M. L. Lovejoy, M. R. Melloch, M. S. Lundstrom, D.
Ritter, and R. A. Hamm, “Minority-carrier mobility enhancement in p
InGaAs lattice matched to InP,” Appl. Phys. Lett., vol. 63, pp. 636–638,
1993.
[29] T. Kaneto, K. W. Kim, and M. A. Littlejohn, “A comparison of minority
Ga
As and GaAs,” Appl. Phys. Lett., vol.
electron transport in In
63, pp. 48–50, 1993.
[30] Y. Betser, D. Ritter, G. Bahir, S. Cohen, and J. Sperling, “Measurement
of the minority carrier mobility in the base of heterojunction bipolar
transistors using a magnetotransport method,” Appl. Phys. Lett., vol. 67,
pp. 1883–1884, 1995.
[31] M. J. W. Rodwell, private communication, 1999.
[32] M. S. Lundstrom, M. E. Klausmeier-Brown, and M. R. Melloch,
“Device-related material properties of heavily doped gallium arsenide,”
Solid State Electron., vol. 33, pp. 693–704, 1990.
[33] K. Brennan and K. Hess, “High field transport in GaAs, InP and InAs,”
Solid State Electron., vol. 27, pp. 347–357, 1984.
[34] M. W. Dvorak, O. J. Pitts, S. P. Watkins, and C. R. Bolognesi, “Abrupt
junction InP/GaAsSb/InP double heterojunction bipolar transistors with
as high as 250 GHz and
V,” in IEDM Tech. Dig., San
Francisco, 2000, pp. 178–181.
+
F
BV
>6
C. R. Bolognesi (S’84–M’94) was born in St-Lambert, QC, Canada. He received the B.Eng. degree from McGill University, Montréal, QC, in 1987, the
M.Eng. degree from Carleton University, Ottawa, ON, Canada, in 1989, and the
Ph.D. degree from the University of California, Santa Barbara, in 1994, all in
electrical engineering, focusing his Ph.D. research on the physics and fabrication of InAs/AlSb-based HFETs and the development of a high-yield process
for these devices.
In 1994, he joined Northern Telecom’s Semiconductor Components Group,
Ottawa, as a BiCMOS Process Integration Engineer and was responsible for a
new generation of high-performance single-polysilicon emitter BJTs with selectively implanted pedestal collectors and studied the effects of fluorine incorporation on poly-emitter BJTs. In 1995, he joined Simon Fraser University (SFU), Burnaby, BC, as an Assistant Professor with a joint appointment
between the Engineering Science and Physics Departments to launch and direct SFU’s Compound Semiconductor Device Fabrication Laboratory (CSDL).
He was promoted to the rank of Associate Professor in 1998 and to the rank
of Professor in 2001. His current research interests focus on the development
of high-speed transistors (HBTs and HEMTs) and optoelectronic components
based on new materials (InP/GaAsSb, GaInP/GaInAs, and AlGaN/GaN) and
processes for high-performance electronic and optoelectronic devices.
Dr. Bolognesi was the recipient of the IEEE 1999 GaAs IC Symposium Best
Paper Award.
N. Matine received the M.S. degree in electronics from the Université Pierre et
Marie Currie, Paris, France, and the Ph.D. degree in electrical engineering from
the University of Paris Sud, Orsay, France, in 1996.
He was with the Compound Semiconductor Device Laboratory, Simon Fraser
University, Burnaby, BC, Canada, in March 1997, where he worked on development of InP/GaAsSb/InP and InP/InGaAs HBTs as a Postdoctoral Fellow.
In 1999, he joined the Platform Technology Division, Conexant Systems Inc.,
where he is presently conducting research and development on advanced HBTbased power amplifiers and digital ICs.
Martin W. Dvorak (S’97) was born in Ontario, Canada in 1973. He received
the B.Sc. degree in engineering physics from Queen’s University, Kingston, ON,
in 1995, and the M.App.Sc. degree in engineering science from Simon Fraser
University, Burnaby, BC, Canada, in 1997, where he is currently pursuing the
Ph.D. degree in engineering science. His dissertation involves the fabrication
and characterization of ultra high-speed InP/GaAsSb/InP double heterojunction
bipolar transistors (DHBTs).
He is now with Agilent Technologies, Santa Rosa, CA.
P. Yeo, photograph and biography not available at the time of publication.
X. G. Xu, photograph and biography not available at the time of publication.
Simon P. Watkins (S’83–M’96) received the B.Sc. degree from Queen’s University, Kingston, ON, Canada, in 1980, and the Ph.D. in physics from Simon
Fraser University (SFU), Burnaby, BC, Canada, in 1986.
From 1986 to 1991, he was with American Cyanamid Company, Stamford
CT, where he worked with the team that developed alkyl group V precursors for
MOVPE growth that are now widely used in the III–V semiconductor industry.
In 1992, he joined the Physics Department, SFU, where he installed a major
facility for MOVPE growth of III–V compounds. His research spans a variety
of materials-related topics. Recent highlights include the first observation of
excitonic luminescence in InAs, phosphorus passivation of GaAs, growth and
characterization of ultrathin quantum wells, and studies of the electrical and
optical properties of GaAsSb/InP heterostructures.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 9, SEPTEMBER 2000
A 3-V Monolithic SiGe HBT Power Amplifier
for Dual-Mode (CDMA/AMPS) Cellular Handset
Applications
Pei-Der Tseng, Liyang Zhang, Guang-Bo Gao, Senior Member, IEEE, and M. Frank Chang, Fellow, IEEE
Abstract—A dual-mode (CDMA/AMPS) power amplifier has
been successfully implemented by using a monolithic SiGe/Si heterojunction bipolar transistor (HBT) foundry process for cellular
handset (824–849 MHz) applications. The designed two-stage
power amplifier satisfies both CDMA and AMPS requirements in
3 V, the power
output power, linearity, and efficiency. At
44.1 dBc
amplifier shows an excellent linearity (first ACPR
and second ACPR
57.1 dBc) up to 28 dBm of output power
for CDMA applications. Under the same bias condition, the
power amplifier also meets AMPS handset requirements in
output power (up to 31 dBm) and linearity (with second and
third harmonic to fundamental ratios lower than 37 dBc and
55 dBc, respectively). At the maximum output power level, the
worst power-added efficiencies (PAEs) are measured to be 36%
for CDMA and 49% for AMPS operations. The power amplifier
also tolerates severe output mismatch (VSWR 12 : 1) up to
4 V, with spurs measured to be
22 dBc in CDMA
outputs at two specific tuning angles, but with no spur in AMPS
outputs at any tuning angle.
=
=
Index Terms—Dual-mode cellular handset, monolithic integration, power amplifier, SiGe HBT.
I. INTRODUCTION
F
OR THE past several years, AlGaAs/GaAs heterojunction
bipolar transistor (HBT) power amplifiers have dominated
the CDMA handset transmitter market due to their excellent linearity and power-added efficiency (PAE). However,
GaAs-based integrated circuits are relatively expensive and
must be thinned for optimum performance in power amplification. Compared with AlGaAs/GaAs HBTs, SiGe/Si HBTs are
more attractive primarily due to their high substrate thermal
conductivity (150 W/m- C), comparable device performance
30 GHz and
50 GHz), lower emitter/base turn-on
(
voltage ( 0.75 V), and substantially lower production cost.
Unfortunately, SiGe/Si HBTs have their own disadvantages:
the substrate is very conductive, adding significant parasitics
to both active and passive components of the power amplifier.
SiGe HBTs also have relatively low breakdown voltages
5 V;
14.5 V) and low Early voltage ( 140 V)
(
versus 1000 V in GaAs HBTs. These characteristics are
Manuscript received November 30, 1999; revised December 20, 1999. This
work was supported by Grants from the U.S. Defense Advanced Research
Project Agency (DARPA) and ARMY MURI programs.
The authors are with the Department of Electrical Engineering, University of
California, Los Angeles, CA 90095-1594 USA.
Publisher Item Identifier S 0018-9200(00)05926-6.
detrimental to the gain, linearity, and dynamic range of the
power amplifier.
Recently, efforts have been made in making SiGe/Si HBT
power amplifiers for DECT and GSM handset transmission applications [1]–[4]. However, the output power of the DECT is
relatively low (24 dBm) and the linearity requirement of the
GSM is far less restrictive than that of the CDMA. To further
demonstrate the linearity and PAE of the SiGe HBT power amplifier at a significant power level, we have designed and characterized a monolithic SiGe/Si HBT power amplifier for dual
mode (CDMA/AMPS) cellular handset applications.
The power amplifier design specifications are:
1) Maximum output power: 28 dBm for CDMA and
31 dBm for AMPS;
44.1 dBc and
2) Linearity for CDMA: first ACPR
57.1 dBc with offset frequencies set at
second ACPR
885 kHz and 1980 kHz, respectively. The detailed measurement specifications are described in [5];
3) Linearity for AMPS: with second and third harmonic to
30 dBc at any output power level;
fundamental ratios
4) Power-Added Efficiency (PAE): 35% for CDMA and
45% for AMPS measured at the peak output power
level.
II. CIRCUIT DESIGN
We use a two-stage amplifier configuration to fulfill the
dual-mode design goals. A simplified schematic of the designed
power amplifier is shown in Fig. 1, which comprises driver
and power amplification stages, input, interstage and output
matching networks, and bias circuits for the driver and power
stages, respectively. To satisfy the output power requirement,
total emitter areas of the driver and power HBTs are chosen to
be 480 m and 3360 m , respectively. Each HBT unit cell
has an emitter size of 20 m .
For power HBTs at extremes of voltage and current, a
thermal–electrical feedback mechanism may constrict the
emitter current to localized hot spots and eventually lead to
second breakdown (or “thermal runaway”) and catastrophic
failure [6]. Emitter and base ballasting resistors are often used
to counter this regenerative effect and force uniform current
and temperature distributions across large-size transistors.
In our design, only base ballasting resistors are used [7].
Emitter-ballasting resistors are excluded for directly reducing
the output signal swing at the collector node. The minimum
base ballasting resistance required to reverse the onset of
0018–9200/00$10.00 © 2000 IEEE
TSENG et al.: POWER AMPLIFIER FOR DUAL-MODE CELLULAR HANDSET APPLICATIONS
1339
Fig. 1. Simplified schematic of a cellular handset power amplifier. On-chip components are surrounded by the dashed line.
thermal runaway can be calculated according to the dependence of collector current on the junction temperature [8], as
follows:
(1)
where
collector current;
base–emitter dc bias voltage;
junction temperature of the device;
transistor emitter resistance;
transistor base resistance;
external base ballasting resistance;
reverse saturation current of the emitter–base
junction;
common base current gain;
;
energy gap of the SiGe base material.
With low Germanium content (average 4%) in the base, the
can be approximated by that of
temperature dependence of
pure silicon [9],
(2)
and the temperature dependence of the HBT current gain can
be represented by
(3)
K and
from [10]. The threshold
where
for the onset of thermal runaway is
(4)
as a function
Fig. 2 shows the collector current density
, calculated based on (1)–(4) with varof base–emitter bias
ious base ballasting resistances. It is obvious from Fig. 2 that
Fig. 2. Calculated collect current density versus base–emitter bias voltage for
power HBTs constrained by various base ballasting resistances at T
358 K.
=
the base ballasting resistance must exceed 120 per unit cell
to reach a thermal stable operation of the power HBT at the
358 K) required for celhighest ambient temperature (
lular handset operation. To be conservative, we have chosen the
base resistance to be 170 per unit cell. Since it is significantly
higher than the intrinsic base resistance (12 per unit cell) of
the HBT, the base ballasting resistance also provides a relatively
high and stable input impedance for the second-stage amplifier
to be easily matched to the output of the first-stage amplifier.
The interstage matching network in our design contains a
coupling capacitor C1 and an RF chock made of an off-chip
and the
transmission line (RFC1), which links between the
collector of the first-stage amplifier. The RFC1 ( 150 mil long)
is chosen to minimize the gain variation over the frequency
band and the capacitor C1 ( 30 pF) is used to cut off the lowfrequency gain and eliminate amplifier oscillation. The input
matching of the first-stage amplifier is achieved by using an
on-chip LC network. The inductor (about 5 nH) has a of 4
at 0.9 GHz; on-chip capacitors which are made of MOS devices
enjoy very high capacitance per area (1.5 fF/ m ) with a of
33 at 0.9 GHz.
To design a power amplifier with both high linearity and high
PAE, we use an RC feedback network to linearize the first stage
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 9, SEPTEMBER 2000
Fig. 3. Microphotograph of a fabricated CDMA/AMPS SiGe HBT power
amplifier.
and bias the second stage at a rather low quiescent point to trade
for high PAE. In the micromodule, two microwave transmission
lines, TRL1 and TRL2 (110 mil and 250 mil long, respectively),
are implemented on alumina substrate to transform low output
impedance of the second-stage power HBT (about 3 ) to the
standard 50- output. Harmonic tuning techniques are also employed to suppress the second and third harmonics at the output
by using shunt resonators made of microwave transmission lines
(TRL3 and TRL4) in series with shunt capacitors. For instance,
TRL3 (38 mil long) is designed to resonate with a serial capacitor C2 (10 pF) to reflect the second harmonic signal. Similarly,
TRL4 (8 mil long) is designed to resonate with the capacitor
C3 (5.6 pF) to reflect the third harmonic signal. Since primary
harmonic components are mostly eliminated from the amplifier
output, the linearity and efficiency of the power amplifier are
significantly enhanced.
Bias circuits for both driver and power stages are designed
with current mirrors to regulate their quiescent currents. Current mirror ratios are chosen for the delicate tradeoff between
the thermal stability and PAE of the power amplifier. Bias circuits with lower current mirror ratios are more effective in regulating the bias of large power HBTs, but at greater expense
of PAE. Bias circuits with excessively high current mirror ratios have the adverse effects. In addition, the specific value of
the current mirror ratio is also constrained by the detailed layout
considerations. A moderate current mirror ratio of 8 : 1 is chosen
to balance the demands in both PAE and the thermal stability of
the amplifier.
Based on our design, a fabricated SiGe/Si HBT power amplifier IC is shown in Fig. 3. The chip is very compact (2.0
1.0 mm ) in size and can be easily housed in a micromodule,
as shown in Fig. 4. Emitter bonding pads are enlarged to incorporate more bonding wires to minimize the potential feedback inductance. Through-substrate via-holes are also avoided
for achieving an easy manufacturing. With input and interstage
matching networks and bias circuits built on-chip, the amplifier
leaves very few extra components (mainly the output matching
stage and RF chokes) to the micromodule for handset transmitter insertion.
Extensive simulations are conducted by using both time and
frequency domain simulators to optimize the power amplifier
performance. HP-Advanced Design System (ADS) is used
for circuit simulations; Gummel–Poon model is employed
Fig. 4.
Fabricated SiGe HBT power amplifier micromodule.
Fig. 5. Gain and PAE versus CDMA power amplifier output power as a
function of operating frequency.
Fig. 6. First and second ACPRs versus CDMA power amplifier output power
as a function of operating frequency.
for large-signal device simulations. Comparisons between
simulated and measured results are presented in Section IV.
III. CIRCUIT PERFORMANCE MEASUREMENT
We have characterized the power amplifier for both CDMA
and AMPS applications. Figs. 5 and 6 show the gain, PAE (%)
TSENG et al.: POWER AMPLIFIER FOR DUAL-MODE CELLULAR HANDSET APPLICATIONS
Fig. 7. Gain and PAE of versus AMPS power amplifier output power as a
function of operating frequency.
Fig. 9.
1341
Input return loss as a function of operating frequency.
(a)
Fig. 8. Second and third harmonics versus AMPS mode output power as a
function of operating frequency.
and the linearity (represented by first and second ACPRs) versus
the output power over the frequency band (824–849 MHz). For
CDMA operation, the amplifier satisfies linearity requirements
3 V with first ACPR better than 44.1 dBc and second
at
ACPR better than 57.1 dBc with output power up to 28 dBm.
The amplifier gain varies between 22–23 dB with PAEs of
36%–37% at 28 dBm output power.
Fig. 7 shows the gain and PAE (%) versus the output power for
AMPS operation. The amplifier satisfies the maximum output
3 V with 21 dB gain
power requirement of 31 dBm at
and 49%–51% PAE. As shown in Fig. 8, the amplifier shows
very low second and third harmonics, measured to be lower than
37 dBc and 55 dBc, respectively. The input return loss is
always measured below 12 dB at any input level in Fig. 9.
The power amplifier even meets dual-mode linearity speci2.7 V over the operating frequency band. At
fications at
this collector-supply voltage, the PAE slightly decreases to 33%
for CDMA and 48% for AMPS operation. The maximum input
return loss slightly increases to 10 dB. These results are carefully compared with that of simulations in Section IV.
An infrared scanning camera is used to characterize the
thermal property of the power amplifier IC. A dome-shaped
temperature profile is evenly distributed across the HBT power
(b)
Fig. 10. (a) Infrared image of a SiGe HBT power amplifier under 1 W output
power operation (the ambient temperature is set at 40 C). (b) Temperature
distribution of a multicell power HBT as a function of cell location.
stage as shown in Fig. 10. At 1 W output power, the maximum
C above the ambient.
chip temperature is measured to be
The peak temperature of individual SiGe HBT cells varies only
C from the center to the edge of the power HBT.
within
The outstanding thermal characteristics of SiGe power HBTs
may be attributed to the excellent thermal conductivity of the
silicon substrate and the use of base ballasting resistors in
power transistor design.
The ruggedness of SiGe power amplifiers is tested by
deliberately mismatching the output port. Power amplifiers
are first adjusted to their maximum output levels for both
CDMA and AMPS operations. We then replace the 50- load
by connecting the output port to a load tuner. By tuning
the output load impedance, we can test the power-amplifier
robustness under severe mismatch conditions. Under a high
standing-wave ratio of VSWR 12 : 1, we find that SiGe
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 9, SEPTEMBER 2000
Fig. 12.
No spur observed at any angle in AMPS output (at 31 dBm).
Fig. 13. Comparison between the simulated and measured first and second
2.7 V for CDMA operation at 840 MHz.
ACPRs versus output power at
V =
<0
Fig. 11. (a) Low spurs (
22 dBc) appeared at only two specific tuning
angles in CDMA output (at 28 dBm). (b) No spur appeared at the rest of tuning
angles in CDMA output (at 28 dBm)
power amplifiers survive well at all tuning angles up to
4.0 V, but die instantly as
4.5 V. The worst spurs
observed in CDMA outputs are about 22 dB below the
output signal level, at two specific tuning angles [Fig. 11(a)].
However, no spur is observed at the rest of tuning angles in
CDMA output [Fig. 11(b)]. There is also no spur observed in
AMPS output at any tuning angle (Fig. 12), even without a
spur-suppression circuit configuration.
IV. DISCUSSION
Fig. 13 compares simulated and measured results of first
2.7 V.
and second ACPRs versus the output power at
Two simulators are used for ACPR evaluation. One is HP-ADS
based on the envelope modulation analysis and the other is a
time-domain ACPR-calculator developed by the authors based
on a bandpass nonlinearity algorithm proposed by Chen and
coworkers [11]. Based on this algorithm, large-signal -parameters of the power HBT are calculated by using a SPICE model
provided by the foundry vendor. AM–AM and AM–PM disin magnitude
tortions, obtained directly from variations of
and phase, are multiplied into the complex CDMA input waveform (generated by a Rohde and Schwarz WinIQSIM software)
to produce the final power amplifier output. As shown in Fig.
13, simulated ACPRs agree well with measured ones within 5
dB in the most critical output power region (around 28 dBm).
The small discrepancy in simulation is caused by assigning
fixed large-signal -parameters to a nonlinear device, which
in reality vary according to operating frequency, power, and
external circuit configurations for harmonic terminations. The
power amplifier is also not a memoryless system as assumed
in [11]. Nevertheless, the time-domain ACPR calculator has
made a faster and reasonably accurate prediction of the amplifier linearity, and consequently has led to a more efficient
power-amplifier design.
Fig. 14 illustrates both simulated and measured gain and
2.7 V for CDMA
PAE of the HBT power amplifier at
and AMPS operations. The gain and PAE are simulated by
TSENG et al.: POWER AMPLIFIER FOR DUAL-MODE CELLULAR HANDSET APPLICATIONS
Fig. 14. Comparison between the simulated and measured amplifier gain and
2.7 V for CDMA and AMPS operations at
PAE versus output power at V
840 MHz.
=
HP-ADS according to envelope modulation and harmonic
balance analyses. The measured transducer gain is 1.5 dB lower
than the simulated. The measured PAE is at most 5% lower
than that of simulation. The discrepancies in gain and PAE may
be attributed to imperfect circuit modeling and matchings of
HBTs at high frequencies.
We have been conservative in selecting power amplifier
architecture and components to warrant the first-time design
success, which inevitably sacrifices the HBT power-amplifier
performance. With more experience in thermal management
and using better device modeling, we may further improve
the power-amplifier performance at lower collector-supply
voltages ( 2.7 V).
V. CONCLUSION
We have successfully designed and characterized a 3-V
monolithic dual-mode (CDMA/AMPS) power amplifier IC on
silicon substrate based on a standard SiGe/Si HBT foundry
technology. The dual mode power amplifier meets all linearity
and output power requirements down to 2.7 V with an outstanding performance that is comparable to that of GaAs HBTs.
We are in the process to further optimize the power amplifier
performance at lower collector-supply voltages ( 2.7 V) by
using more accurate large signal device modeling at high
frequencies.
ACKNOWLEDGMENT
The authors are very grateful for IBM’s excellent SiGe
foundry support and the contract supports from US DARPA
and Army MURI programs.
REFERENCES
[1] A. Schuppen, S. Gerlach, H. Dietrich, D. Wandrei, U. Seiler, and U.
Konig, “1-W SiGe power HBTs for mobile communication,” IEEE Microwave and Guided Wave Lett., vol. 6, pp. 341–343, Sept. 1996.
1343
[2] J. N. Burghartz, J.-O. Plouchart, K. A. Jenkins, C. S. Webster, and
M. Soyuer, “SiGe power HBTs for low-voltage high-performance RF
applications,” IEEE Electron Device Lett., vol. 19, pp. 103–105, Apr.
1998.
[3] D. Harame, L. Larson, M. Case, S. Kovacic, S. Voinigescu, T. Tewksbury, D. Nguyen-Ngoc, K. Stein, J. Cressler, S.-J. Jeng, J. Malinowski,
R. Groves, E. Eld, D. Sunderland, D. Rensch, M. Gilbert, K. Schonenberg, D. Ahlgren, S. Rosenbaum, J. Glenn, and B. Meyerson,
“SiGe HBT technology: Device and application issues,” IEDM, pp.
731–734, 1995.
[4] F. Huin, C. Duvanaud, D. Masliah, J. M. Paillot, H. Mokrani, S. Gerlach,
and K. Worner, “A low voltage integrated SiGe power amplifier for mobile applications,” in IMAPS ’98, Wireless Communications Conf., Session MP7, Part II.
[5] “CDMA/AMPS Power Amplifier RI 23 124U Application Notes,”
Conexant Systems, Newport Beach, CA, 1998.
[6] R. M. Scarlett, W. Schockley, and R. H. Haitz, “Thermal instabilities and
hot spot in junction transistors,” in Physics of Failure in Electronics, M.
F. Goldberg and J. Vaccaro, Eds. Baltimore, MD: Spartan, 1963, pp.
194–203.
[7] W. Liu, A. Khatibzadeh, J. Sweder, and H. F. Chau, “The use of base
ballasting to prevent the collapse of current gain in AlGaAs/GaAs heterojuntion bipolar transistors,” IEEE Trans. Electron Devices, vol. 43,
pp. 245–251, Feb. 1996.
[8] R. P. Arnold and D. S. Zoroglu, “A quantitative study of emitter ballasting,” IEEE Trans. Electron Devices, vol. 21, pp. 385–391, July 1974.
[9] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York, NY:
Wiley, 1981, ch. 1.
[10] SiGe5HP device engineering release notes for SiGe HBT models, IBM,
1998.
[11] S.-W. Chen, W. Panton, and R. Gilmore, “Effects of nonlinear distortion
on CDMA communication system,” IEEE Trans. Microwave Theory
Tech., vol. 44, pp. 2743–2750, Dec. 1996.
Pei-Der Tseng received the B.S. degrees from the
Departments of Physics and Mathematics, National
Tsing Hua University, Hsinchu, Taiwan, R.O.C., and
the M.S. degree from the Institute of Electronics,
National Chiao Tung University, Hsinchu. He is
currently working toward the Ph.D. degree at the
Electrical Engineering Department, University of
California, Los Angeles.
His research interests include power amplifier
design, MEMS switched antenna design, monolithic
microwave ICs, and integrated optics.
Liyang Zhang received the B.S. degree in 1985 in
information and control engineering and the M.S.
and the Ph.D. degrees in electromagnetic theory
and microwave techniques in 1988 and 1992, respectively, from Xi’an Jiaotong University, Xi’an,
R.O.C.
From 1992 to 1994, he worked as a Postdoctor in
Xidian University, Xi’an. He joined the Institute of
Electronics, Chinese Academy of Science, Beijing,
R.O.C., as an Associate Research Professor in 1994
and became a Research Professor in 1997. He is
currently a Postdoctor at the University of California, Los Angeles.
He has worked on field theory and microwave devices and circuits. Recently,
he has focused on 900-MHz and 1.9-GHz monolithic microwave integrated circuit design for communication applications and CMOS digital integrated circuit
design for wireless interconnect applications.
1344
Guang-bo Gao (SM’86) graduated from the
Department of Radio and Electronics Engineering,
Tsinghua University, Beijing, R.O.C., in 1965. He
received the Ph.D. degree from the Department
of Electrical and Electronics Engineering, Hosie
University, Tokyo, Japan.
He is currently a Senior Staff Engineer of the
Power Integrated Circuit Division, International
Rectifier, El Segundo, CA. From 1997 to 1998,
Dr. Gao was a Staff Engineer of the Reliability
Engineering and Technology Assessment Department, SGS-Thomson Microelectronics, Phoenix, AZ, where he published
the 0.35-m CMOS technology reliability qualification report. He worked
at Zenith Electrical Corporation, Glenview, IL, as a Senior Project Engineer
of failure analysis and reliability engineering from 1994 to 1997, where he
published the 150 FA reports. From 1988 to 1994 he was a Visiting Research
Professor and Principal Research Engineer in the Coordinated Science
Laboratory, University of Illinois, Urbana-Champaign. He was the Principal
Investigator of the National Science Foundation project on GaAs Power HBTs.
From 1980 to 1988, he was a Professor and the Director of Reliability Physics
Laboratories at Beijing Polytechnic University, Beijing. He has authored
or co-authored more than 100 technical papers, a comprehensive graduate
textbook Reliability Physics of Semiconductor Devices in 1987, and over 200
FA reports.
Dr. Gao was awarded the title of Distinguished National Scientist of China
in 1986, and received the National Invention Prizes from the Science and Technology Committee of China in 1983 and 1984. He received the Science and
Technology Prizes ten times from the Beijing Science and Technology Committee and the Ministry of Electronic Industry from 1979 to 1988, and the Best
Paper Awards from the Beijing and Chinese Institute of Electronics in 1980,
1986, 1987, and 1989 in recognition of his distinguished contributions to power
transistors and semiconductor device reliability.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 9, SEPTEMBER 2000
M. Frank Chang (F’96) received the B.S. in physics
from National Taiwan University, Taipei, Taiwan,
R.O.C., in 1972, the M.S. degree in material science
from National Tsing Hua University in 1974, and the
Ph.D. degree in electrical engineering from National
Chiao Tung University in 1979.
He is now a Professor at the Electrical Engineering
Department, University of California, Los Angeles
(UCLA). Before joining UCLA, he was the Assistant Director of the Electronic Devices Laboratory
and the Department Manager of the High Speed Materials and Devices from 1983 to 1997 at the Rockwell Science Center, Thousand Oaks, CA. During his career, his research work has been mostly in the
development of high-speed semiconductor (GaAs, InP, and SiGe) and MEMS
devices for digital, analog, microwave and optoelectronic integrated circuit applications. He has authored or co-authored over 150 technical papers and eight
book chapters, edited one book and held more than 14 U.S. patents.
Dr. Chang was honored with Rockwell’s Leonardo Da Vinci (Engineer of the
Year) Award in 1992, the Chinese Computer Association’s Outstanding Academic Achievement Award in 1994, and National Chiao-Tung University’s Outstanding Alumnus Award in 1997. Currently, he is a Co-Editor of the IEEE
TRANSACTIONS ON ELECTRON DEVICES (in compound semiconductor devices).
He served as a Guest Editor for the Special Issue on GaAs Integrated Circuits
of IEEE JOURNAL OF SOLID-STATE CIRCUITS in 1991 and 1992. He was named
an IEEE Fellow in 1996 for his pioneering work in HBT processing technology
for manufacturing HBT integrated circuits.
394
IEEE JOURNAL OF QUANTUM ELECTRONICS, VOL. 40, NO. 4, APRIL 2004
Current-Induced Light Modulation Using Quantum
Wells in the Collector of Heterojunction
Bipolar Transistors
Nachum Shamir, Dan Ritter, and David Gershoni
Abstract—We incorporated InGaAs quantum wells within the
collector of InP-based heterojunction bipolar transistors to form
novel light-modulating devices. We studied the properties of these
devices as light modulators by direct current injection. The devices
were characterized using differential photocurrent and transmission spectroscopies. Our results demonstrate the feasibility of light
modulation based on current rather than electric field modulation.
Maximum modulation is achieved when the accumulated carriers
quench the excitonic absorption resonance.
Index Terms—Electroabsorption, heterojunction bipolar
transistors (HBTs), optical modulation, optical spectroscopy,
quantum-well (QW) devices.
I. INTRODUCTION
M
ULTIPLE-QUANTUM-WELL (MQW) light modulators based on electric field modulation or the quantum
confined Stark effect (QCSE) are widely used and well understood [1], [2]. A different approach for light modulation
based on charge displacement is known as the barrier reservoir
and QW electron transfer (BRAQWET) structure. The latter
concept is based on absorption modulations by field-induced
accumulation and removal of carriers from the barriers to
the QWs and back [3]–[6]. Both types of modulators, though
different in concept, are voltage-driven and hence require
driver circuits capable of providing relatively high voltage
at high speed. In this study, we demonstrate an alternative
approach, in which the absorption is modulated and controlled
by the collector current of a heterojunction bipolar transistor
(HBT). The integrated transistor-modulator is operated in the
common base configuration, in which high-frequency current
modulation can be achieved. The advantage of the proposed
device is in the combined use of voltage and electric current.
Small voltage changes at the collector significantly affect the
carrier confinement and can be used for rapid depletion of the
wells. We believe that by optimizing the collector structure and
operating conditions one could speed up the device and obtain
useful operation frequencies at lower voltages compared to
standard modulation devices.
Manuscript received November 11, 2003. This work was supported by the
Consortium for Broadband Communication administered by the Chief Scientist
of the Israeli Ministry of Commerce and Industry.
N. Shamir and D. Ritter are with the Department of Electrical Engineering,
Technion—Israel Institute of Technology, Haifa 32000, Israel.
D. Gershoni is with the Department of Physics, Technion—Israel Institute of
Technology, Haifa 32000, Israel.
Digital Object Identifier 10.1109/JQE.2004.825116
Fig. 1.
Schematic description of the MQW HBT structure.
We used photocurrent and transmission spectroscopy to study
the feasibility of this novel concept. Our study conclusively
demonstrates that this concept works, and we suggest possible
ways for improving the modulation efficiency.
II. DEVICE STRUCTURE AND EXPERIMENTAL SETUP
In Fig. 1, we show the structure of the HBT-modulator
device. The device layers were grown by a compact metalorganic molecular beam epitaxy (MOMBE) system [7], on a
(100)-oriented substrate, with Be and Sn as P and N type
dopants, respectively. The lattice-matched InGaAs QW width
m.
was designed for effective light modulation at
In order to minimize light absorption in the transistor base
m layer
a quaternary In Ga As P
composition was used. The redistribution of beryllium in the
InP–InGaAsP HBTs limited the maximum doping level in
cm [8]. Large area (emitter size
the base to about
m) test devices were fabricated by conventional wet
etching. Pt–Ti–Pt–Au contacts were deposited by e-beam
evaporation and defined by a lift-off technique.
The band diagrams of the base collector layers as obtained by numerical solutions of the Poisson equations for
the three types of devices that we studied are shown in
Fig. 2. Devices and are single heterojunction transistors,
is a double heterojunction device with an
whereas device
In Ga As P
m grading layer. The
grading layer reduced the turn on voltage of the transistor to
allow low-voltage operation. Device C is similar to A with
the addition of thin InP barriers adjacent to each QW in order
0018-9197/04$20.00 © 2004 IEEE
SHAMIR et al.: CURRENT-INDUCED LIGHT MODULATION USING QWS IN THE COLLECTOR OF HBTS
395
signal superimposed on the dc voltage. We identified the true
current-induced modulations by comparison between the two
independent measurements.
The light- and heavy-hole excitonic absorption resonances
were clearly observed by photocurrent spectroscopy in all the
devices even at room temperature (Fig. 4). This indicates relatively sharp interfaces and low background doping. Under moderate reverse bias, the heavy-hole exciton resonance shifts toward lower energies as expected from the QCSE [1], [2]. For yet
higher bias, depending on the device, the resonance broadens
and eventually disappears. We note that the quenching of the
heavy-hole resonance in device A occurs at lower reverse bias
than that in devices B and C. This is probably due to weaker
confinement of the electronic wave function by the quaternary
barriers. In the following, we therefore discuss only measurements performed on devices B and C, which performed much
better than device A.
III. CURRENT-INDUCED ABSORPTION MODULATION
SPECTROSCOPY
Fig. 2. Base collector band diagrams, obtained by a numerical solution of
the Poisson equation, for devices (a) A, (b) B , and (c) C . Device A has
a homogeneous base collector junction. Device B has a graded composite
collector, and device C has a homogeneous base collector junction and thin
InP barriers to enhance the electron tapping and confinement.
to enhance the electron trapping efficiency. The background
doping level of the collector layers was about
cm .
We characterized the various devices using photocurrent and
transmission spectroscopy methods. The experimental setups
are schematically described in Fig. 3. For photocurrent measurements, the base collector junction was reversely biased in
an open emitter configuration, a mechanical chopper modulated
the incident light, and the photocurrent part was separated from
the total base collector junction current by a lock-in amplifier
[Fig. 3(a)].
For transmission modulation measurements, we backside-illuminated the devices through the InP substrate. The
transmitted light was reflected by the front metal contacts, thus
doubling the absorption of light in the modulator. The reflected
light was directed onto our Germanium detector by a beam
splitter [Fig. 3(b)]. For these measurements, the transistors
were operated in the common base mode. The modulations
in the intensity of the reflected light induced by the collector
current and voltage changes were measured using a standard
lock-in technique.
Current changes cause parasitic voltage changes, due to the
resistance of the base layer. In order to separate the current-induced absorption from that induced by voltage changes, we also
measured the reflected light modulation under direct modulation of the base–collector junction voltage using a 400-mV ac
The current-induced modulation spectra of devices and
are presented in Fig. 5 where they are also compared with the
voltage-induced modulation spectra. The detector phase was set
to produce positive modulation signals when the absorption increase correlated to the current or voltage increase. The current induced signal is clearly visible in the spectra of device
[Fig. 5(a)] at low reverse bias voltage of the base-collector junction. The signal decreases for higher reverse bias levels, probably due to the depletion of carriers from the wells and reduction
of the electron confinement efficiency.
The structural design of device C results in better carrier collection efficiency. This is clearly evident from the much lower
A
A/cm that are required
collector currents of
for observing current-induced modulations similar to these ob50 A/cm . These spectra are
served for device B at 1 mA
presented in Fig. 5(b), where the current-induced HH1 and LH1
excitonic resonances are observed at low bias. At higher bias
levels, these current-induced peaks are reduced due to the lower
density of carriers in the wells. The additional spectral features
in Fig. 5(a) are due to the HH2 and LH2 excitonic resonances
associated with the marginally bounded E2 level. We believe
that these spectral features in Fig. 5(b) are associated with the
E2 continuum miniband [9]–[11].
It has been previously demonstrated that optical interference
alters the phase of the photoreflection signals [12]. We assumed
that in our measurements the phase was not altered due to the
use of direct electrical modulation. To increase our confidence,
we repeated the voltage modulation measurements focusing the
light on the inactive collector area, below the base contact. In the
second measurement, the light was reflected by the base contact,
forming an optical path that did not include the emitter layers.
In the two measurements, we obtained similar voltage modulation signals. In addition, we measured several devices, located
on remote locations in the sample. In all, we received similar
modulation signals and did not observe any influence of the optical path through the sapphire holder, glue, and hand-polished
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IEEE JOURNAL OF QUANTUM ELECTRONICS, VOL. 40, NO. 4, APRIL 2004
Fig. 3. Schematic description of the experimental setup (a) for photocurrent spectroscopy and (b) for current and voltage induced transmission spectroscopy. In
the first mode, the light is modulated and the differential photocurrent is detected by the lock-in amplifier. In the second mode, the collector current or voltage are
modulated and the detector and lock-in amplifier measure the differential transmission.
substrate. Interference effects observed in wide-spectral-range
photocurrent measurements (not presented) indicated that the
optical paths were different for each device.
IV. DISCUSSION
The current-induced absorption modulation spectra are better
understood by comparison to the photocurrent spectra. We first
discuss the absorption modulation spectrum obtained by modulation of the base collector voltage keeping the emitter open,
i.e., with no current injection into the collector. This spectrum is
shown in Fig. 6 together with the photocurrent spectrum, both
measured for device C at 77 K. Two plots are presented, the first
at zero dc bias [Fig. 6(a)], and the second [Fig. 6(b)] at a reverse
bias of 2 V. In both cases, the voltage modulation amplitude was
400 mV. A marked difference between the two absorption modulation spectra can be seen: the zero bias spectrum is negative at
the absorption edge, while the 2-V bias curve is positive at the
absorption edge. Understanding this observation is crucial for
the understanding of the current-induced effects, as explained
below. While at zero bias, there is a residual density of carriers
in the QWs, due to background doping and thermal activation;
at reverse bias, the QWs are fully depleted. Thus, at zero bias,
the voltage modulation spectrum results from modulation of the
residual carrier density. These carriers quench and broaden the
excitonic absorption resonance, screen the built-in field and induce bandgap-narrowing effects [3], [13]. The trapped carrier
concentration is reduced when the reverse bias increases. The
negative signal at the band edge [region (1) in Fig. 6(a)] and the
positive peak [region (2)] at the wavelength of the heavy-hole
exciton resonance indicate a blue shift of the absorption edge
due to the field-induced carrier depletion with the voltage increase.
The QWs are completely depleted with the reverse bias increase. In Fig. 6(b), we compare photocurrent and voltage mod. At this bias, carrier-inulation spectra measured at
duced excitonic resonance screening are eliminated and sharp
excitonic absorption resonances are clearly observed in the photocurrent spectrum. Now, reverse bias results in the electric field
increase within the QWs and an associated red shift of the absorption edge due to the QCSE. As a result, a positive signal
is observed at the low-energy edge of the exciton resonance (1)
and a negative signal is observed at the high-energy edge (2).
In Fig. 6(c), we compare between voltage modulation spectra
as measured for various reverse bias levels of device (similar results were obtained for device , not shown). As clearly
observed in Fig. 6(c), at low voltages the modulation spectrum
is dominated by carrier-induced effects. At these voltages, the
spectra are negative below the band edge and positive at the
excitonic resonances due to carrier-induced bandgap reduction
and exciton quenching. At higher voltages, the spectra are dominated by the QCSE.
Based on the voltage modulation signals interpretation, we
can now explain the current induced results. The sharp negative
signal observed in Fig. 5(b) at reverse bias of 1 V is due to the
quenching of the excitonic absorption resonance as a result of
carrier accumulation. In this case, the effects of voltage and current modulation are opposite since higher voltage depletes the
wells while higher current increases the carrier concentration in
the wells. The current modulation signals in Fig. 5(a) are more
difficult to explain due to the large parasitic voltage modulations. Devices and have the same base and emitter structure
SHAMIR et al.: CURRENT-INDUCED LIGHT MODULATION USING QWS IN THE COLLECTOR OF HBTS
397
Fig. 5. Comparison of the current- and voltage-induced absorption modulation
spectra measured at 77 K for devices (a) B and (b) C . The amplitudes of
the current modulation were 1 mA ( 50 A/cm ) and 20 A( 1 A/cm )
correspondingly. The voltage modulation amplitude was 400 mV for both
devices.
Fig. 4. Room-temperature photocurrent spectra measured at various bias
levels. (a) The applied voltage quenched the excitonic absorption resonance
in device A. Due to stronger confinement in devices (b) B and (c) C , the
excitonic absorption resonance was observed at a wide reverse bias range.
and therefore similar current gain and lateral base layer resistance. The higher current used for measuring device causes
parasitic voltage modulation, which is 50 times larger than that
in the measurements of device . Decoupling of the current and
voltage effects cannot be achieved by simple curve subtraction
since the effective base collector voltage varies laterally across
the device. Yet, the large signals that are observed for low voltages [Fig. 5(a)] and their reduction with the reverse dc bias increase indicate the strong influence of carrier accumulation on
the absorption spectrum.
With this qualitative understanding, we try to more quantitatively estimate the effects of carrier injection on the absorption
spectrum of the HBT modulators. The magnitude of the currentinduced absorption modulation in Fig. 5(b) was evaluated by
multiplying the voltage-induced absorption changes, extracted
from photocurrent spectra, by the ratio of current and voltage
modulation signal magnitudes. We found that a collector current
A
A/cm induced a relative absorption modulation
of
of 15%. Higher collector currents yielded similar magnitudes,
indicating effective saturation of the carrier density within the
QWs.
We estimated the density of electrons required to generate this
theory-based absorption calculaeffect using eight-band
tions [14]–[16]. Our calculations indicate that saturation sheet
cm electrons trapped in each QW is likely
density of
to produce the measured 15% absorption modulation.
We finally comment on the applicability of our approach for
practical devices. Absorption modulation of 15% not is large
enough for practical applications; moreover, this result was ob-
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IEEE JOURNAL OF QUANTUM ELECTRONICS, VOL. 40, NO. 4, APRIL 2004
V. CONCLUSION
We studied the feasibility of light modulation by current
injection. This was achieved by incorporating QW structures
within the collectors of HBTs. Photocurrent and current-induced modulation spectroscopies were applied to measure
the absorption modulation by the collector current. Current
induced absorption modulation of 15% was obtained at 77 K.
These results demonstrate the feasibility of light modulators,
in which current injection, rather than electric field variation,
controls the absorption spectrum.
ACKNOWLEDGMENT
The authors would like to thank D. Schoenman for packaging
the samples, S. Cohen for technical support, and D. Regelman
for assistance in the numerical calculations.
REFERENCES
Fig. 6. Photocurrent and voltage modulation spectra measured at 77 K
= 0, (b) V
= 2 V , and (c) 400-mV voltage
for device C at (a) V
modulation spectra for various reverse biases. At low voltages, carrier-induced
effects determine the absorption modulation characteristics. At high voltages,
field-induced effects are dominant.
tained at a cryogenic temperature of 77 K. Further optimization
is clearly needed for practical room-temperature operation.
The measured room-temperature current-induced modulation signals were too weak to analyze. Since excitonic
absorption resonances are clearly observed at room temperature (photocurrent measurements in Fig. 4), we associated
the weak signals with insufficient carrier accumulation. One
way to enhance both trapping and confinement efficiency is
by using higher barriers such as strained GaInP layers [17].
InGaAs wells can be used to form a strain-compensated lattice.
The device efficiency could be further improved by using a
waveguide configuration in which small changes in absorption
and refractive index are sufficient for effective light modulation.
[1] D. A. B. Miller, “Quantum well electroabsorptive devices: physics and
applications,” in Proc. 34th Scottish Universities Summer School in
Physics, 1988, pp. 71–93.
[2] S. Schmitt-Rink, D. S. Chemla, and D. A. B. Miller, “Linear and non
linear optical properties of semiconductor quantum wells,” Adv. Phys.,
vol. 38, pp. 89–188, 1989.
[3] M. Wegener, T. Y. Chang, I. Bar-Joseph, J. M. Kuo, and D. S. Chemla,
“Electroabsorption and refraction by electron transfer in asymmetric
modulation doped multiple quantum well structures,” Appl. Phys. Lett.,
vol. 55, pp. 583–585, 1989.
[4] M. Wegener, J. E. Zucker, T. Y. Chang, N. J. Sauer, K. L. Jones, and D. S.
Chemla, “Absorption and refraction spectroscopy of a tunable electron
density quantum well and reservoir structure,” Phys. Rev. B, vol. 41, pp.
3097–3104, 1990.
[5] J. E. Zucker, T. Y. Chang, M. Wegener, N. J. Sauer, K. L. Jones, and D.
S. Chemla, “Large refractive index changes in tunable-electron-density
InGaAs/InAlAs quantum wells,” IEEE Photon. Technol. Lett., vol. 2, pp.
29–31, Jan. 1990.
[6] J. E. Zucker, K. L. Jones, M. Wegener, T. Y. Chang, N. J. Sauer, M. D.
Divino, and D. S. Chemla, “Multi gigahertz bandwidth intensity modulators using tunable electron density multiple quantum well waveguides,”
Appl. Phys. Lett., vol. 59, pp. 201–203, 1991.
[7] R. A. Hamm, D. Ritter, and H. Temkin, “Compact metalorganic molecular beam epitaxy growth system,” J. Vac. Sci. Technol. A, vol. 12, pp.
2790–2794, 1994.
[8] N. Shamir, D. Ritter, and C. Cytermann, “Beryllium doped InP/InGaAsP
heterojunction bipolar transistors,” Solid State Electron., vol. 42, pp.
2039–2045, 1998.
[9] S. Fafard, E. Fortin, and A. P. Roth, “Oscillatory behavior of the conAs/GaAs quantum wells due to capping-bartinuum states in In Ga
rier layers of finite size,” Phys. Rev. B, vol. 45, pp. 13 769–13 772, 1992.
, “Effects of an electric field on the continuum energy levels in
[10]
As/GaAs quantum wells terminated with thin cap layers,”
In Ga
Phys. Rev. B, vol. 47, pp. 10 588–10 595, 1993.
[11] Y. H. Chen, C. H. Chan, and G. J. Jan, “Investigation of GaAs/AlGaAs
multiple quantum well waveguides involving unconfined energy states,”
J. Vac. Sci. Technol. B, vol. 16, pp. 570–574, 1998.
[12] X. L. Zheng, D. Heiman, B. Lax, and F. A. Chambers, “Reflectance line
shapes from GaAs/GaAlAs quantum well structures,” Appl. Phys. Lett.,
vol. 52, pp. 287–289, 1988.
[13] P. C. Klipstein and N. Apsley, “A theory for the electroreflectance
spectra of quantum well structures,” J. Phys. C: Solid State Phys., vol.
19, pp. 6461–6478, 1986.
[14] G. A. Baraff and D. Gershoni, “Eigenfunction expansion method
for solving the quantum wire problem,” Phys. Rev. B, vol. 43, pp.
4011–4022, 1991.
[15] D. Gershoni, C. H. Henry, and G. A. Baraff, “Calculating the optical
properties of multidimensional heterostructures: application to the modeling of quaternary quantum well lasers,” IEEE J. Quantum Electron.,
vol. 29, pp. 2433–2450, 1993.
[16] M. E. Pistol and D. Gershoni, “Modeling of electroabsorption in semiconductor quantum structures within the eight band theory,” Phys. Rev.
B, vol. 50, pp. 738–745, 1994.
[17] G. M. Cohen and D. Ritter, “Microwave performance of
P/Ga
In
As resonant tunnelling diodes,” ElecGa In
tron. Lett., vol. 34, pp. 1267–1268, 1998.
SHAMIR et al.: CURRENT-INDUCED LIGHT MODULATION USING QWS IN THE COLLECTOR OF HBTS
Nachum Shamir received the B.Sc. degree in electrical engineering from the Technion, Israel Institute
of Technology, Haifa, in 1988, the M.Sc. degree in
electrical engineering from Tel Aviv University, Tel
Aviv, Israel, in 1994, and the Ph.D. degree in electrical engineering from the Technion in 1999.
He served as an Adjunct Lecturer with the
Technion Electrical Engineering faculty from 1998
to 2000. He joined the Mobile Platforms Group,
Intel Israel, Haifa, in 1999. His current research and
development areas are presilicon power estimation,
analysis, and validation and post-silicon power and thermal characterization.
Dan Ritter received the B.Sc, M.Sc., and Ph.D. degrees in electrical engineering from the Technion, Israel Institute of Technology, Haifa, in 1981, 1984,
and 1989, respectively. He then carried out post-doctoral research during three years at AT&T Bell Laboratories, Murray Hill, NJ.
In 1992, he joined the Technion Electrical
Engineering Department, where he is currently an
Associate Professor. His main research interest is
physics and the modeling of indium phosphide-based
devices. His group has been using the metalorganic
molecular beam epitaxy method to grow the epitaxial layers. The focus of his
current activity is heterojunction bipolar transistors.
399
David Gershoni was born in Israel in 1953. He received the D.Sc. degree from the Technion, Israel Institute of Technology, Haifa, in 1986.
After receiving the D.Sc degree, he joined AT&T
Bell Laboratories, Murray Hill, NJ, first as a postdoctorate and later as a Member of the Technical Staff.
He joined the Department of Physics, Technion, in
1991. He has published more than 100 papers in international journals and has organized and lectured at
major international conferences and workshops.
Dr. Gershoni was a recipient of the Fullbright Fellowship and the Wolf Prize.
370
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 16, NO. 3, AUGUST 2003
Highly Uniform InAlAs–InGaAs HEMT Technology
for High-Speed Optical Communication System ICs
Naoki Hara, Member, IEEE, Kozo Makiyama, Tsuyoshi Takahashi, Ken Sawada, Tomoyuki Arai, Toshihiro Ohki,
Mizuhisa Nihei, Toshihide Suzuki, Yasuhiro Nakasha, and Masahiro Nishi
Abstract—The authors have developed a highly uniform,
InP-based high-electron-mobility transistor (HEMT) technology
for high-speed optical communication system integrated circuits
(ICs). Special attention was paid to obtaining a high yield and
uniformity without degrading the high-frequency characteristics
of these HEMTs. An InP etch-stopper layer was employed to
control the gate recess etching. The authors successfully fabricated
InAlAs–InGaAs HEMTs with a cutoff frequency of 175 GHz
after interconnection, which is sufficiently high for application in
40-Gb/s optical communication ICs. The standard deviation of the
threshold voltage was only 13 mV across a 3-in wafer. They also
developed a fabrication process for a Y-shaped gate to maintain
high uniformity, enabling us to integrate more than a thousand
transistors with a 0.1- m-class gate length. With this technology,
ICs with over 1000 transistors were successfully fabricated and
operated at over 40 Gb/s. Furthermore, the authors fabricated a
2 : 1 multiplexer that had more than 200 transistors and reached
an operating speed of 90 Gb/s. They have thus concluded that their
InAlAs–InGaAs HEMT technology can be applied to fabricate
high-speed ICs for optical communication systems.
Index Terms—High-speed IC, InAlAs–InGaAs HEMT,
InP-based HEMT, optical communication IC, uniformity,
Y-shaped gate.
I. INTRODUCTION
HE DEVELOPMENT of optical communication systems,
such as those using time-division multiplexing (TDM)
and wavelength-division multiplexing (WDM), is being driven
by the rapidly increasing demand for transmission capacity.
This demand cannot be met without developing high-speed
integrated circuit (IC) technologies to provide data rates of
at least 40 Gb/s. Several types of digital and analog ICs have
been demonstrated for this purpose [1]–[26]. Devices used
for these ICs are the InP high-electron-mobility transistor
(HEMT) [1]–[9], the InP heterojunction bipolar transistor
(HBT) [10]–[18], and the SiGe HBT [19]–[26]. Of these
devices, the InP HEMT is the most promising because it is the
fastest. In fact, a cutoff frequency of over 500 GHz has been
obtained with an InP HEMT [27].
A device fabrication technology, which enables us to integrate
InP HEMTs with a short gate length, is necessary for IC fabrication. It is difficult, however, to obtain a device yield of over 99%
for 0.1- m class InP HEMTs by the conventional T-shaped gate
TABLE I
EPITAXIAL LAYER STRUCTURE
process [28]. We then developed a Y-shaped gate technology to
improve a yield by reducing an aspect ratio of gate opening. Uniformity of the transistors is also required to fabricate high-speed
ICs [29]. Therefore, we have developed InAlAs–InGaAs HEMT
technology while giving special attention to the uniformity of
the threshold voltage. An InP etch-stopper layer was employed
to control the threshold voltage. In this paper, we report uniform
InP-based HEMT technology with a high yield suitable for use
in 40-Gb/s ICs.
T
Manuscript received October 15, 2002; revised February 20, 2003.
N. Hara, K. Makiyama, T. Takahashi, K. Sawada, T. Arai, T. Ohki, M. Nihei,
T. Suzuki, and Y. Nakasha are with Fujitsu Laboratories Ltd., Kanagawa 2430197, Japan (e-mail: hara.naoki@jp.fujitsu.com).
M. Nishi is with Fujitsu Quantum Devices Ltd., Nakakomagun, Yamanashi
409-3883, Japan.
Digital Object Identifier 10.1109/TSM.2003.815629
II. FABRICATION
The critical requirements for InP HEMT technology are as
follows: a device yield of greater than 99.9% and a variation
of the threshold voltage within 50 mV, which corresponds a
standard deviation of less than 17 mV. Fabrication technology,
which meets to the requirements, is described in this section.
The epitaxial wafers we used to fabricate InAlAs–InGaAs
HEMs were grown by metalorganic vapor-phase epitaxy
(MOVPE) on 3-in semi-insulating InP substrates. The typical
layer structure, listed in Table I, consisted of the following
layers: a 200-nm undoped InAlAs buffer layer, a 25-nm
undoped InGaAs channel layer, a 3-nm undoped InAlAs
spacer layer, a 7-nm Si-doped InAlAs carrier-supply layer,
an 8-nm undoped InAlAs barrier layer, a 6-nm undoped InP
etch-stopper layer, and a 50-nm Si-doped InGaAs cap layer.
Each layer was lattice matched to the InP substrate. We inserted
the InP etch-stopper layer between the InAlAs barrier layer
and the InGaAs cap layer to improve the uniformity of device
characteristics such as the threshold voltage.
A cross section of an InAlAs–InGaAs HEMT is shown in
Fig. 1. Nonalloyed ohmic contacts consisting of Mo–Ti–Pt–Au
[30] were formed on the heavily doped InGaAs layer. The
contact resistance was 0.05 mm. We formed the gate recess
0894-6507/03$17.00 © 2003 IEEE
HARA et al.: HIGHLY UNIFORM InAlAs–InGaAs HEMT TECHNOLOGY FOR HIGH-SPEED OPTICAL COMMUNICATION
371
TABLE II
GATE OPENING SIZE BEFORE AND AFTER THERMAL TREATMENT
Fig. 1 Cross-sectional schematic of an InP-based HEMT.
Fig. 3 Current-voltage characteristics of an HEMT using the T-shaped gate
with a gate length of 0.13 m. Gate-to-source voltage was varied from 0.7 to
0 V in 0.1-V steps.
0
Fig. 2
Cross sections of HEMTs with (a) T-shaped gate and (b) Y-shaped gate.
by using electron-beam lithography and selective wet chemical
etching. We used citric-acid-based etchant [31]. A selectivity
for the etching of InGaAs on InP was greater than 100, which
is high enough to fabricate ICs. The InP surface in the recess
region was covered with a thin SiN dielectric film by using a
plasma-enhanced chemical-vapor-deposition (CVD) system.
This made the surface stable enough to prevent carrier depletion
when the device was subjected to high temperatures during
thermal processes.
Electron-beam lithography was used to form the gate electrode. It consisted of Ti–Pt–Au and was evaporated onto the
InP layer and then lifted off. The typical gate length was 0.13
m. We formed two types of gates: a conventional T-shaped
gate [28] and an advanced Y-shaped gate. The T-shaped gate is
easier to make, but for a 0.1- m-class gate length, it is mechanically weaker due to the high aspect ratio of the gate opening. As
shown in Fig. 2(a), the fine gate and over-gate of the T-shaped
gate were not connected well. This situation may result in a lack
of over-gate during the successive interconnection processes.
This problem is especially serious for integrating a relatively
large number of HEMTs. In fact, a device yield larger than
99.9% is required to fabricate ICs with a thousand transistors.
Actually, a device yield of 0.13- m T-shaped gate HEMT is
about 99%, which is insufficient for IC fabrication.
Therefore, we developed the Y-shaped gate to integrate
more than 1000 transistors. The gate opening was formed by
electron-beam lithography, with the same process used for
the T-shaped gate. We then rounded the edge of the resist
by thermal treatment to reduce the aspect ratio. By carefully
optimizing the process conditions for this treatment (we chose
140 C for 5 min), it was possible to form a Y-shaped gate
while controlling the size of the gate opening. As the final
Fig. 4 Current gain of an HEMT using the T-shaped gate with a gate length
of 0.13 m.
process step, the gate metal was evaporated and lifted off. A
cross section of a Y-shaped gate is shown in Fig. 2(b). There
was no crack in the gate metal, unlike the T-shaped case. To
check the uniformity of the gate opening size, we formed a
0.10- m opening and measured its length before and after the
thermal treatment. The averages and standard deviations across
a 3-in wafer are summarized in Table II. As shown by these
results, the thermal treatment did not degrade the uniformity of
the gate opening.
After fabricating HEMTs with both types of gates, we employed double-layer or triple-layer Au interconnections, with
benzocyclobutene (BCB) as an interlayer dielectric film.
III. DEVICE CHARACTERISTICS
A. DC and RF Characteristics
The current-voltage characteristics of an HEMT with the
T-shaped gate are shown in Fig. 3. Even at a drain-to-source
voltage of 2 V, a good pinchoff characteristic was obtained.
The threshold voltage and transconductance were 0.633 V
372
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 16, NO. 3, AUGUST 2003
TABLE III
UNIFORMITY OF THRESHOLD VOLTAGE ACROSS 3-IN WAFER
Fig. 5
Histogram of threshold voltages for HEMTs across a 3-in wafer.
Fig. 8 Performance summary for various ICs based on our HEMT technology.
Relationship between the integration level and the maximum operating speed is
shown.
Fig. 6 Histogram of level-shift voltages across a 3-in wafer.
Fig. 7 Histogram of offset voltages in differential amplifiers.
Fig. 9 Chip micrograph of a 4 : 1 MUX [32].
and 917 mS/mm, respectively. The frequency dependence of
the current gain is shown in Fig. 4. The cutoff frequency was
175 GHz. The HEMT with the Y-shaped gate had similar
characteristics. The threshold voltage, transconductance, and
cutoff frequency were 0.521 V, 953 mS/mm, and 175 GHz,
respectively. These values are sufficiently high for application
in 40-Gb/s ICs.
B. Uniformity
Variation between transistors is also an important factor in IC
performance [29]. Fig. 5 shows a histogram of threshold voltages for HEMTs across a 3-in wafer. A standard deviation of
13 mV was obtained. This result indicates that the gate-recess
etching was controlled well by employing the InP etch-stopper
layer. This also means that the thicknesses and doping concentrations of the epitaxial layers were uniform across the wafer.
The gate Schottky contacts of the HEMTs were examined for
their capability as level-shift diodes for IC application. Thus, the
gate characteristics of the HEMTs were also important, because
uniformity in the level-shift bias is necessary for IC operation so
that each HEMT can receive the appropriate bias for high-speed
operation. Fig. 6 shows a histogram of the level-shift voltage,
which we defined as the voltage at a current of 50 mA/mm. The
small standard deviation of 5 mV indicates that the Schottky
diodes consisting of the gate metal were suitable for use in ICs.
We fabricated several kinds of 40-Gb/s optical communication circuits [8], [9] and found that, in a high-gain differential
amplifier, it is important that the threshold voltages of each differential pair of FETs are the same. This type of amplifier is
commonly used in digital circuits, such as multiplexer (MUX)
or demultiplexer (DEMUX) circuits based on source-coupled
HARA et al.: HIGHLY UNIFORM InAlAs–InGaAs HEMT TECHNOLOGY FOR HIGH-SPEED OPTICAL COMMUNICATION
Fig. 10
373
Input and output eye diagrams of a 4 : 1 MUX measured at 43 Gb/s [32].
field effect transistor (FET) logic (SCFL). We, therefore, investigated the difference in threshold voltage by comparing offset
voltages among differential amplifiers. Fig. 7 shows a histogram
of the offset voltages in differential amplifiers based on our
HEMT technology. Even though these data were gathered by
using several wafers from different lots, the small standard deviation of 6.2 mV indicates the InAlAs–InGaAs HEMTs reported
in this paper are suitable for use in ICs based on SCFL.
The uniformity of HEMTs with the Y-shaped gate was also
measured. As shown in Table III, the standard deviation was almost the same as for the T-shaped gate HEMTs. This means that
the thermal treatment used to fabricate the Y-shaped gate did not
degrade the uniformity of the device characteristics. Therefore,
the Y-shaped gate design can be applied for IC fabrication.
of the threshold voltage was only 13 mV across a 3-in wafer.
This superior uniformity resulted from employing an InP etchstopper layer and using high-uniformity epitaxial wafers. We
also developed a fabrication process for a Y-shaped gate, which
did not degrade the uniformity, enabling us to integrate more
than a thousand transistors with a 0.1- m-class gate length.
With this technology, ICs with over 1000 transistors were successfully fabricated and operated at over 40 Gb/s. Furthermore,
MUX that had more than 200 transistors
we fabricated a
and reached an operating speed of 90 Gb/s. We have thus concluded that the InAlAs–InGaAs HEMT technology reported in
this paper can be applied to fabricate ICs for high-speed optical
communication systems.
ACKNOWLEDGMENT
C. IC performances
We next fabricated various ICs with the InP-based HEMT
technology described above. Metal-insulator-metal capacitors
made from SiN film and NiCr resistors were also included in
these ICs. Fig. 8 illustrates the performance results for the various digital ICs [8], [32]–[34]. ICs with more than 1000 transistors were successfully fabricated by using the Y-shaped gate
technology and operated at over 40 Gb/s [32], [34]. Fig. 9 shows
MUX [32]. The chip integrates 1355
a chip micrograph of a
transistors, 790 resistors, and 190 capacitors. The wave forms
of the input and output data at 43 Gb/s are shown in Fig. 10
[32]. Almost half of the ICs across a 3-in wafer operated at 43
Gb/s, which means that a device yield of over 99.9% has been
MUX with more than 200 tranachieved. Furthermore, a
sistors with the Y-shaped gate reached an operating speed of
90 Gb/s [33]. We have thus concluded that the InAlAs–InGaAs
HEMT technology reported here is suitable for fabricating ICs
for high-speed optical communication systems.
IV. SUMMARY
We have developed an InP-based HEMT technology for highspeed optical communication system ICs. We successfully fabricated InAlAs–InGaAs HEMTs with a cutoff frequency of 175
GHz after interconnection, which is high enough for application to 40-Gb/s optical communications. The standard deviation
The authors would like to thank T. Hirose, S. Yamaura, and H.
Kano for their fruitful discussions. They are also grateful to Y.
Yamaguchi, Y. Maeba, Y. Suzuki, and their colleagues for technical assistance and to Dr. M. Takikawa for his encouragement.
REFERENCES
[1] T. Otsuji, M. Yoneyama, Y. Imai, T. Enoki, and Y. Umeda, “64 Gbit/s
multiplexer IC using InAlAs/InGaAs/InP HEMT,” Electron. Lett., vol.
33, no. 17, pp. 1488–1489, 1997.
[2] T. Otsuji, Y. Imai, E. Sano, S. Kimura, S. Yamaguchi, M. Yoneyama,
T. Enoki, and Y. Umeda, “40 Gb/s IC’s for future lightwave communications systems,” IEEE J. Solid-State Circuits, vol. 32, pp. 1363–1370,
Sept. 1997.
[3] M. Yoneyama, A. Sano, K. Hagimoto, T. Otsuji, K. Murata, Y. Imai,
S. Yamaguchi, T. Enoki, and E. Sano, “Optical repeater circuit design
based on InAlAs/InGaAs HEMT digital IC technology,” IEEE Trans.
Microwave Theory Tech., vol. 45, pp. 2274–2282, Dec. 1997.
[4] T. Otsuji, K. Murata, T. Enoki, and Y. Umeda, “An 80 Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs,” IEEE J. Solid-State Circuits, vol. 33, pp. 1321–1327, Sept. 1998.
[5] K. Murata, T. Otsuji, and Y. Yamane, “45 Gbit/s decision IC using
InAlAs/InGaAs/InP HEMTs,” Electron. Lett., vol. 35, no. 16, pp.
1379–1380, 1999.
[6] K. Murata, T. Otsuji, E. Sano, S. Kimura, and Y. Yamane, “70-Gbit/s
multiplexer and 50-Gbit/s decision IC modules using InAlAs/InGaAs/InP HEMTs,” IEICE Trans. Electron., vol. E83-C, no. 7, pp.
1166–1169, 2000.
[7] K. Sano, K. Murata, and Y. Yamane, “50-Gbit/s demultiplexer IC
module using InAlAs/InGaAs/InP HEMTs,” IEICE Trans. Electron.,
vol. E83-C, no. 11, pp. 1788–1790, 2000.
374
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 16, NO. 3, AUGUST 2003
[8] T. Suzuki, H. Kano, Y. Nakasha, T. Takahashi, K. Imanishi, H. Ohnishi,
and Y. Watanabe, “40-Gbit/s D-type flip-flop and multiplexer circuits
using InP HEMT,” in IEEE MTT-S 2001 Int. Microwave Symp. Dig.,
2001, pp. 595–598.
[9] H. Shigematsu, M. Sato, T. Suzuki, T. Takahashi, K. Imanishi, N.
Hara, H. Ohnishi, and Y. Watanabe, “A 49-GHz preamplifier with a
transimpedance gain of 52 dB
using InP HEMTs,” IEEE J. Solid-State
Circuits, vol. 36, pp. 1309–1313, Sept. 2001.
[10] M. Mokhtari, T. Swahn, R. H. Walden, W. E. Stanchina, M. Kardos, T.
Juhola, G. Schuppener, H. Tenhunen, and T. Lewin, “InP-HBT chip-set
for 40-Gb/s fiber optical communication systems operational at 3 V,”
IEEE J. Solid-State Circuits, vol. 32, pp. 1371–1383, Sept. 1997.
[11] J. P. Mattia, R. Pullela, G. Georgieu, Y. Baeyens, H. S. Tsai, Y. K.
Chen, C. Dorschky, T. W. Von Mohrenfels, M. Reinhold, C. Groepper,
M. Sokolich, L. Nguyen, and W. Stanchina, “High-speed multiplexer:
A 50Gb/s 4:1 MUX in InP HBT technology,” in Tech. Dig. 1999 IEEE
GaAs IC Symp., 1999, pp. 189–192.
[12] E. Sano, H. Nakajima, N. Watanabe, S. Yamahata, and Y. Ishii, “40
Gbit/s 1:4 demultiplexer IC using InP-based heterojunction bipolar transistors,” Electron. Lett., vol. 35, no. 24, pp. 2116–2117, 1999.
[13] J. P. Mattia, R. Pullela, Y. Baeyens, Y.-K. Chen, H.-S. Tsai, G. Georgiou,
T. W. von Mohrenfels, M. Reinhold, C. Gropper, C. Dorschky, and C.
Schulien, “A 1:4 demultiplexer for 40 Gb/s fiber-optic applications,” in
IEEE 2000 Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2000, pp.
64–65.
[14] J. Mullrich, H. Thurner, E. Mullner, J. F. Jensen, W. E. Stanchina, M.
Kardos, and H.-M. Rein, “High-gain transimpedance amplifier in InPbased HBT technology for the receiver in 40-Gb/s optical-fiber TDM
links,” IEEE J. Solid-State Circuits, vol. 35, pp. 1260–1265, Sept. 2000.
[15] P. Andre, S. Blayac, P. Berdaguer, J.-L. Benchimol, J. Godin, N. Kauffmann, A. Konczykowska, A.-E. Kasbari, and M. Riet, “InGaAs/InP
DHBT technology and design methodology for over 40 Gb/s optical
communication circuits,” IEEE J. Solid-State Circuits, vol. 36, pp.
1321–1327, Sept. 2001.
[16] K. Ishii, K. Murata, M. Ida, K. Kurishima, T. Enoki, T. Shibata, and
E. Sano, “Very-high-speed selector IC using InP/InGaAs heterojunction
bipolar transistors,” Electron. Lett., vol. 38, no. 10, pp. 480–481, 2002.
[17] G. Georgiou, Y. Baeyens, Y.-K. Chen, A. H. Gnauck, C. Gropper, P.
Paschke, R. Pullela, M. Reinhold, C. Dorschky, J. P. Mattia, T. W.
von Mohrenfels, and C. Schulien, “Clock and data recovery IC for 40
Gb/s fiber-optic receiver,” IEEE J. Solid-State Circuits, vol. 37, pp.
1120–1125, Sept. 2002.
[18] Y. Baeyens, G. Georgiou, J. S. Weiner, A. Leven, V. Houtsma, P.
Paschke, Q. Lee, R. F. Kopf, Y. Yang, L. Chua, C. Chen, C. T. Liu, and
Y.-K. Chen, “InP D-HBT IC’s for 40-Gb/s and higher bitrate lightwave
tranceivers,” IEEE J. Solid-State Circuits, vol. 37, pp. 1152–1159, Sept.
2002.
[19] M. Moller, H.-M. Rein, A. Felder, and T. F. Meister, “60 Gbit/s timedivision multiplexer in SiGe-bipolar technology with special regard to
mounting and measuring technique,” Electron. Lett., vol. 33, no. 8, pp.
679–680, 1997.
[20] A. Felder, M. Moller, M. Wurzer, M. Rest, T. F. Meister, and H.-M.
Rein, “60 Gbit/s regenerating demultiplexer in SiGe bipolar technology,” Electron. Lett., vol. 33, no. 23, pp. 1984–1986, 1997.
[21] T. Masuda, K. Ohhata, F. Arakawa, N. Shiramizu, E. Ohue, K. Oda,
R. Hayami, M. Tanabe, H. Shimamoto, M. Kondo, T. Harada, and K.
Washio, “45GHz transimpedance 32dB limiting amplifier and 40Gb/s
1:4 highly-sensitivity demultiplexer with decision circuit using SiGe
HBT’s for 40Gb/s optical receivers,” in IEEE 2000 Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2000, pp. 60–61.
[22] M. Reinhold, C. Dorschky, R. Pullela, E. Rose, P. Mayer, P. Paschke, Y.
Baeyens, J. P. Mattia, and F. Kunz, “A fully-integrated 40 Gb/s clock
and data recoverly / 1:4DEMUX IC in SiGe technology,” in IEEE 2001
Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2001, pp. 84–85.
[23] T. Masuda, K. Ohhata, N. Shiramizu, E. Ohue, K. Oda, R. Hayami, H.
Shimamoto, M. Kondo, T. Harada, and K. Washio, “40 Gb/s 4:1 multiplexer and 1:4 demultiplexer IC module using SiGe HBTs,” in IEEE
MTT-S 2001 Int. Microwave Symp. Dig., 2001, pp. 1697–1700.
[24] K. Ohhata, F. Arakawa, T. Masuda, N. Shiramizu, and K. Washio,
“40-Gb/s analog IC chipset for optical receivers—AGC amplifier,
full-wave rectifier and decision circuit—Implemented using self-aligned
SiGe HBTs,” in IEEE MTT-S 2001 Int. Microwave Symp. Dig., 2001,
pp. 1701–1704.
[25] M. Meghelli, A. Rylyakov, and L. Shan, “50GB/s SiGe BiCMOS 4:1
multiplexer and 1:4 demultiplexer for serial-communication systems,”
in IEEE 2002 Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002,
pp. 260–261.
[26] G. Freeman, M. Meghelli, Y. Kwark, S. Zier, A. Rylyakov, M. A. Sorna,
T. Tanji, O. M. Schreiber, K. Walter, J.-S. Rieh, B. Jagannathan, A.
Joseph, and S. Subbanna, “40-Gb/s circuits built from a 120-GHz fT
SiGe technology,” IEEE J. Solid-State Circuits, vol. 37, pp. 1106–1114,
Sept. 2002.
[27] Y. Yamashita, A. Endoh, K. Shinohara, K. Hikosaka, T. Matsui, S.
Hiyamizu, and T. Mimura, “Pseudomorphic In
Al
As/In
Ga
As HEMT’s with an ultrahigh f of 562 GHz,” IEEE Electron
Device Lett., vol. 23, pp. 573–575, Oct. 2002.
[28] T. Takahashi, M. Nihei, K. Makiyama, M. Nishi, T. Suzuki, and N. Hara,
“Stable and uniform InAlAs/InGaAs HEMT IC’s for 40-Gbit/s optical
communication systems,” in Proc. 2001 Indium Phosphide and Related
Materials Conf., 2001, pp. 614–617.
[29] T. Maeda and M. Fujii, “Analytical expression for operating speed of
GaAs SCFL D-type flip-flop,” Solid-State Electron., vol. 41, no. 11, pp.
1687–1691, 1997.
[30] K. Onda, A. Fujihara, E. Mizuki, Y. Hori, H. Miyamoto, N. Samoto, and
M. Kuzuhara, “Highly reliable InAlAs/InGaAs heterojunction FET’s
fabricated using completely Molybdenum-based electrode technology
(COMET),” in IEEE MTT-S 1994 Int. Microwave Symp. Dig., 1994, pp.
261–264.
[31] M. Tong, K. Nummila, A. Ketterson, I. Adesida, C. Caneau, and R. Bhat,
“InAlAs/InGaAs/InP MODFET’s with uniform threshold voltage obtained by selective wet gate recess,” IEEE Electron Device Lett., vol.
13, pp. 525–527, Oct. 1992.
[32] Y. Nakasha, T. Suzuki, H. Kano, A. Ohya, K. Sawada, K. Makiyama,
T. Takahashi, M. Nishi, T. Hirose, M. Takikawa, and Y. Watanabe,
“A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology,” IEEE J. Solid-State Circuits, vol. 37, pp. 1703–1709, Dec.
2002.
[33] T. Suzuki, Y. Nakasha, T. Takahashi, K. Makiyama, K. Imanishi, T.
Hirose, and Y. Watanabe, “A 90Gb/s 2:1 multiplexer IC in InP-based
HEMT technology,” in IEEE 2002 Int. Solid-State Circuits Conf. Dig.
Tech. Papers, 2002, pp. 192–193.
[34] H. Kano, T. Suzuki, S. Yamaura, Y. Nakasha, K. Sawada, T. Takahashi,
K. Makiyama, T. Hirose, and Y. Watanabe, “A 50-Gbit/s 1:4 demultiplexer IC in InP-based HEMT technology,” in IEEE 2002 MTT-S Int.
Microwave Symp. Dig., vol. 1, 2002, pp. 75–78.
Naoki Hara (M’99) was born in Tokyo, Japan, in
1963. He received the B.E., M.E., and Ph.D. degrees
from the University of Tokyo, Tokyo, Japan in 1985,
1987, 1990, respectively.
In 1990, he joined Fujitsu Laboratories Ltd.,
Kanagawa, Japan, where he has been engaged in
the research and development of HEMTs and other
heterostructure devices. Currently, he is also with the
Nanoelectronics Collaborative Research Center, the
Institute of Industrial Science, University of Tokyo.
Dr. Hara is a member of the Institute of Electronics,
Information and Communication Engineers of Japan, the Japan Society of Applied Physics, and the Institute of Electrical Engineers of Japan.
Kozo Makiyama was born in Yamaguchi, Japan, on
August 21, 1962. He received the B.E. and M.E. degrees in electrical engineering from the Osaka Institute of Technology, Osaka, Japan, in 1986 and 1988,
respectively.
In 1988, he joined the Compound Semiconductor
Laboratory of Fujitsu Laboratories, Ltd., Atsugi,
Japan, where he has been engaged in research and
development of HEMT device technologies.
Mr. Makiyama is a member of the Japan Society
of Applied Physics.
HARA et al.: HIGHLY UNIFORM InAlAs–InGaAs HEMT TECHNOLOGY FOR HIGH-SPEED OPTICAL COMMUNICATION
Tsuyoshi Takahashi was born in Tochigi, Japan, in
1963. He received the B.E. and M.E. degrees from
the University of Tsukuba, Ibaraki, Japan in 1985 and
1987, respectively.
In 1987, he joined the Fujitsu Laboratories Ltd.,
Kanagawa, Japan, where he has been engaged in
research on fabrication technology for InP-based
HEMTs and InGaP-emitter HBTs.
Mr. Takahashi is a member of the Japan Society of
Applied Physics, the Institute of Electronics, Information and Communication Engineers of Japan.
375
Mizuhisa Nihei was born in Fukushima, Japan on
July 16, 1966.
He received the B.E. and M.E. degrees from Tohoku University, Sendai, Japan, in 1990 and 1992, respectively. Since 1992 he has worked at Fujitsu Laboratories Ltd., Atsugi, Japan, where he has been engaged in the developments of HEMT LSIs. He is currently involved with the developments of carbon nanotubes for its electronic application.
Mr. Nihei is a member of the Japan Society of Applied Physics.
Toshihide Suzuki was born in Okayama, Japan,
in 1969. He received the B.S. and M.S. degrees
in electronic engineering from Osaka University,
Osaka, Japan, in 1991 and 1993, respectively.
In 1993, he joined Fujitsu Laboratories Ltd.,
Kanagawa, Japan. There he has been engaged in
research and design of high-speed digital ICs using
GaAs-HBTs and InP-based HEMTs.
Mr. Suzuki is a member of the Institute of Electronics, Information and Communication Engineers
of Japan.
Ken Sawada was born in Osaka, Japan, on
November 11, 1973. He received the B.E. and M.E.
degrees in electronic science and engineering from
Kyoto University, Kyoto, Japan, in 1996 and 1998,
respectively.
In 1998, he joined Fujitsu Laboratories Ltd.,
Kanagawa, Japan. Since then, he has studied and
developed InP-based HEMT devices and their
fabrication techniques.
Mr. Sawada is a member of the Japan Society of
Applied Physics.
Yasuhiro Nakasha was born in Aichi, Japan, in
1964. He received the B.E. and M.E. degrees in
electrical engineering from Nagoya University,
Nagoya, Japan, in 1987 and 1989, respectively.
In 1989, he joined Fujitsu Laboratories Ltd.,
Kanagawa, Japan, where he is engaged in research
and development on high-speed ICs using compound semiconductor heterostructure devices for
communication systems.
Mr. Nakasha is a member of the Institute of Electronics, Information and Communication Engineers
Tomoyuki Arai was born in Kobe, Japan, on July 31,
1974. He received the B.E. and M.E. degree in materials science and engineering from Kyoto University,
Kyoto, Japan, in 1998 and 2000, respectively.
In 2000, he joined Fujitsu Laboratories Ltd.,
Kanagawa, Japan, where he has been engaged in
the research and development of InP-based HEMTs
devices.
Mr. Arai is a member of the Japan Society of Applied Physics.
of Japan.
Toshihiro Ohki was born in Chiba, Japan, on August
7, 1976. He received the B.E. and M.E. degrees from
Waseda University, Tokyo, Japan, in 1999 and 2001,
respectively.
Since 2001, he was been with Fujitsu Laboratories
Ltd., Atsugi, Japan, where he has been engaged in the
research and development of RTDs and HEMTs for
high speed ICs.
Mr. Ohki is a member of the Japan Society of Applied Physics.
Masahiro Nishi was born in Kanagawa, Japan in
1966.
In 1985, he joined Fujitsu Laboratories Ltd., Kanagawa, Japan. In 1999, he was transferred to Fujitsu
Quantum Devices Ltd, Yamanashi, Japan. Since then,
he has been engaged in the development of process
technologies for compound semiconductor ICs.
2212
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 10, OCTOBER 2004
Continuously Tunable Long-Wavelength
MEMS-VCSEL With Over 40-nm Tuning Range
F. Riemenschneider, M. Maute, H. Halbritter, G. Boehm, M.-C. Amann, and P. Meissner
Abstract—This letter presents for the first time an electrically
pumped tunable vertical-cavity surface-emitting laser (VCSEL)
with a record-breaking tuning range of 40 nm at long wavelengths.
The VCSEL is based on a two-chip concept. The laser peak can
be tuned continuously and without mode-hopping in a wavelength
range above 1.55 m due to a microelectromechanical movable mirror membrane. The VCSEL is single mode all over the
tuning range with a 32-dB sidemode suppression ratio. The laser
emits a maximum output power of 100 W in continuous-wave
operation at room temperature. Dynamic measurements of the
tuning characteristics show that the 3-dB cutoff frequency for an
electrothermal wavelength modulation is about 500 Hz and the
1 -time constant of the step response is about 1 ms.
Index Terms—Microelectromechanical systems (MEMS), tunable lasers, vertical-cavity surface-emitting laser (VCSEL).
Fig. 1. Schematic cross section of the two-chip MEMS-VCSEL.
I. INTRODUCTION
T
UNABLE long-wavelength lasers enable a large number
of applications in various areas such as in flexible intelligent optical networks (wavelength-division-multiplexing
systems), trace gas sensing, sensor applications involving
fiber Bragg gratings, process control, or medical diagnostics.
Tunable vertical-cavity surface-emitting lasers (VCSELs) are
very attractive devices as they offer several advantages compared to other types of tunable lasers, e.g., a continuous and
mode-hop-free wavelength tuning. VCSELs using microelectromechanical systems (MEMS-VCSELs) to vary the resonator
length are key-components for applications which need a fast
tuning capability and a wide continuous tuning range that
can be easily controlled. Several monolithic approaches of
MEMS-VCSELs have been presented in [1]–[3]. Among them,
optically pumped devices show the largest tuning range and
highest output power [2]. Devices employing electrostatic actuation offer the fastest tuning capability. In [4], we have reported
for the first time on an electrically pumped MEMS-VCSEL with
a tuning range of approximately 30 nm. This letter presents now
an electrothermally tunable 1.55- m MEMS-VCSEL based
on a two-chip concept with a record-breaking tuning range of
more than 40 nm. This is, to our knowledge, the widest tuning
range ever published for electrically pumped VCSELs. In
Manuscript received April 28, 2004; revised June 7, 2004. This work was
supported by the German BMBF Project (Contract 01BP271).
F. Riemenschneider, H. Halbritter, and P. Meissner are with Two-Chip
Photonics AG, and also with the Institut für Hochfrequenztechnik, Technische
Universität Darmstadt, D-64283 Darmstadt, Germany (e-mail: Riemenschneider@Two-Chip-Photonics.com;
F_Riemenschneider@hf.tu-darmstadt.de; halbritter@hf.tu-darmstadt.de; meissner@hf.tu-darmstadt.de).
M. Maute, G. Boehm, and M.-C. Amann are with the Walter Schottky Institut, Technische Universität München, D-85748 Garching, Germany (e-mail:
markus.maute@wsi.tum.de; boehm@wsi.tum.de; mcamann@wsi.tum.de).
Digital Object Identifier 10.1109/LPT.2004.833885
addition, we investigate the temporal tuning capabilities of such
an electrothermally actuated MEMS-device. By measuring
the frequency response and the step response, it is possible to
evaluate the VCSEL’s tuning speed.
II. TWO-CHIP MEMS-VCSEL DESIGN
The wavelength tuning of this MEMS-VCSEL is based on an
increase of the cavity length that shifts the laser peak to longer
wavelengths. Simply speaking, the fixed epitaxial top mirror of a
nontunable VCSEL [5] has been replaced by a movable mirror
membrane. This mirror membrane is fabricated on a separate
chip which avoids the need of making disadvantageous compromises for neither the micromechanics nor the VCSEL amplifier. Both chips are mounted together in a final assembly step.
A Si-made submount supports the mounting of the two chips
that have different dimensions (Fig. 1). Due to a strong concave membrane curvature and a well-elaborated technique, the
alignment of the two chips during assembly is uncritical [6].
The mirror membrane consists of a GaAs–AlGaAs—distributed
Bragg reflector (DBR) with 24.5 pairs of partly doped quarter
wavelength layers. The last pairs of the DBR remain undoped in
order to obtain a high resistance between membrane and the top
n-contact. A gradual intrinsic stress across the DBR achieved
by Indium inclusion forces the membrane to a concave bending
(radius of curvature: 5.5 mm), resulting in an initial deflection
of 6.5 m after substrate removal. This initial deflection represents the initial air gap of the VCSEL (see Fig. 2). Via-hole
contacts through the substrate facilitate the electrical connection
to the membrane for electrothermal actuation as the membrane
chip is mounted upside-down. By injecting a small heating current through the doped membrane material the flexible suspension beams warm up and slightly expand, the clamped mem-
1041-1135/04$20.00 © 2004 IEEE
RIEMENSCHNEIDER et al.: CONTINUOUSLY TUNABLE LONG-WAVELENGTH MEMS-VCSEL WITH OVER 40-nm TUNING RANGE
2213
Fig. 3. Typical PI and voltage–current characteristics for the MEMS-VCSEL
with 20-m BTJ. Here, the laser wavelength at maximum output power was at
1572 nm and the corresponding spectrum is shown in Fig. 4.
Fig. 2. Photograph of the tunable MEMS-VCSEL. Inset left: two–dimensional
profile measurement. Inset right: profile measurement along dotted line.
brane deflects and the VCSEL resonator increases. The membrane diameter is 190 m and the length of each suspension
beam measures 170 m. Further information on the membrane
fabrication is reported in [7]. The main elements of the active
part are the AlGaInAs-based active region with five compressively strained quantum wells, a lateral structured buried tunnel
m underneath, and a dijunction (BTJ) of diameter
electric–gold mirror acting as the VCSEL’s bottom mirror. Outside of the BTJ, a reverse biased pn-junction efficiently confines
the pump current in the active region. The gold mirror in comdielectric DBR (2.5 pairs)
bination with a thin
leads to a high reflectivity and to a low thermal resistance for the
heat transport out of the active region. Together with the curved
mirror membrane a stable plan-concave microcavity is formed.
Additional information of the VCSEL fabrication can be found
in [4] and [5].
III. STATIC DEVICE CHARACTERIZATION
The MEMS-VCSEL is always single mode. The maximum
continuous wave output power at room temperature is around
100 W and the threshold current is only 10.5 mA (Fig. 3). The
estimated corresponding threshold current density is as low as
2.5 kA/cm assuming a carrier diffusion of 1.5 m. The comparatively low output power can be explained with the very high
reflectivity of the top mirror. Taking into account the air gap,
simulations show that the active region sees a reflectivity as high
as 99.95%. By optimizing this value, we expect to considerably
increase the VCSEL output power.
The spectrum of the single-mode MEMS-VCSEL is shown
in Fig. 4. When the laser wavelength is tuned, the power of the
laser peak at different wavelength is given by the envelop trace
in Fig. 4. The VCSEL wavelength is tunable over a range of
more than 40 nm. Even if the sidemode suppression ratio over
the complete tuning range is more than 32 dB, the presence of
higher order peaks still indicates a mismatch between cavity
Fig. 4. Typical spectrum of the laser. The envelope shows the maximum output
power during tuning of the laser peak. The laser output is single mode over more
than 40 nm.
length, membrane curvature, and BTJ diameter. Usually nontunable VCSELs with BTJ diameters larger than 5 m are multimode. Therefore, single-mode operation of the MEMS-VCSEL
with a BTJ diameter of 20 m is remarkable and can be attributed to the long cavity length and the top mirror’s curvature.
The dissipated electrical power that is converted into heat inside
the membrane’s suspension beams is proportional to the square
of the tuning current. The relation between resonance wavelength of the cavity and tuning current has been measured and is
depicted in Fig. 5. Simulations of the laser wavelength as a function of membrane deflection using the one-dimensional transfer
matrix method are in excellent agreement with the experiment,
indicating that the membrane deflection is exactly proportional
to the square of the tuning current.
IV. DYNAMIC TUNABILITY CHARACTERIZATION
To be able to estimate the tuning speed, the frequency response and the step response have been recorded. For both measurements, the pump current remained constant above threshold.
To obtain the frequency response, the MEMS tuning current has
been modulated with a variable frequency and with four different amplitudes at two different bias points (the 16-mA operating bias leads to the same laser wavelength as the 8-mA bias
,
because the mirror membrane is deflected additionally by
compared to the 8-mA deflection). Fig. 6 shows the amplitude
2214
Fig. 5. Simulation and measurement of membrane deflection, respectively,
resonance wavelength of cavity versus square of tuning current.
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 10, OCTOBER 2004
Fig. 7. Step response of the MEMS-VCSEL showing the temporal behavior
of the laser wavelength as the tuning current is changed rapidly from 6 to 8 mA,
respectively, from 6 to 12 mA.
V. CONCLUSION
Fig. 6. Frequency response of the MEMS-VCSEL showing the amplitude
decrease of the wavelength shift for increasing tuning current modulation
frequencies. The tuning current has been modulated around two different
operating bias points.
of the corresponding wavelength modulation. The 3-dB cutoff
frequency is around 500 MHz for both bias points and almost
independent of the modulation amplitude. To obtain the step response, the tuning current has been modulated with a rectangular signal of sufficient low frequency. The temporal wavelength shift of the VCSEL has been recorded using an optical
Fabry–Pérot filter with a periodic transmission characteristic
(periodicity: free-spectral range of 50 GHz 0.4 nm) followed
by a receiver connected to an oscilloscope. The moving laser
peak scans the well-known filter characteristic which is temporarily visualized on the oscilloscope. Two different amplitudes have been investigated leading to a wavelength jump of
8 and 29 nm (Fig. 7). The membrane shows a typical first-order
-time constant of around 1 ms.
exponential behavior with a
This value is almost identical for both wavelength shifts and
for a rising as well as for a falling edge of the applied current step. Therefore, also a 40-nm jump will show a similar behavior. As expected, electrothermal actuation of the membrane
is slower compared to electrostatic actuation but fast enough
for many applications. However, the presented electrothermally
tuned VCSEL is insensitive against tuning current noise and
other effects, which might affect electrostatic devices in terms
of wavelength stability.
We have presented a tunable long-wavelength MEMSVCSEL with a continuous and mode-hop-free tuning range of
more than 40 nm which is the highest value ever published
for electrically pumped VCSELs. The device is based on a
two-chip approach enabling a separate optimization of the
micromechanical part and the VCSEL amplifier. This concept
allows a single-mode laser operation even for a very large current aperture of 20 m, which is extraordinary. This is attributed
to the relatively long VCSEL resonator and the top mirror’s
bending. Therefore, it can be expected that the VCSEL output
power can be increased considerably by a further optimization
of the top mirror reflectivity and the resonator geometry. The
tuning of the VCSEL is realized by electrothermal actuation.
Investigations of the wavelength tunability have shown that the
frequency response is almost independent of the operating bias
and the modulation amplitude. The 3-dB cutoff frequency is
-time constant of the step
typically around 500 Hz while the
response is typically about 1 ms.
REFERENCES
[1] D. Sun, W. Fan, P. Kner, J. Boucart, T. Kageyama, D. Zhang, R. Pathak,
R. F. Nabiev, and W. Yuen, “Long wavelength-tunable VCSELs with
optimized MEMS bridge tuning structure,” IEEE Photon. Technol. Lett.,
vol. 16, pp. 714–716, Mar. 2004.
[2] D. Vakhshoori, P. Tayebati, C.-C. Lu, M. Azimi, P. Wang, J.-H. Zhou,
and E. Canoglu, “2 mW CW single-mode operation of a tunable 1550 nm
vertical cavity surface emitting laser with 50 nm tuning range,” Electron.
Lett., vol. 35, pp. 900–901, 1999.
[3] C. Chang-Hasnain, “Tunable VCSEL,” IEEE J. Select. Topics Quantum
Electron., vol. 6, pp. 978–987, Nov. 2000.
[4] M. Maute, F. Riemenschneider, G. Boehm, H. Halbritter, M. Ortsiefer, P.
Meissner, and M.-C. Amann, “Micro-mechanically tunable long wavelength VCSEL with a buried tunnel junction,” Electron. Lett., vol. 40,
pp. 430–431, Apr. 2004.
[5] M. Ortsiefer, R. Shau, G. Boehm, F. Koehler, and M.-C. Amann,
“Low-threshold index-guided 1.5 m long-wavelength vertical-cavity
surface-emitting laser with high efficiency,” Appl. Phys. Lett., vol. 76,
pp. 2179–2181, 2000.
[6] F. Riemenschneider, I. Sagnes, G. Böhm, H. Halbritter, M. Maute, C.
Symonds, M.-C. Amann, and P. Meissner, “A new concept for tunable
long wavelength VCSEL,” Opt. Commun., vol. 222/1-6, pp. 341–350,
July 2003.
[7] F. Riemenschneider, M. Aziz, H. Halbritter, I. Sagnes, and P. Meissner,
“Low-cost electrothermally tunable optical microcavities based on
GaAs,” IEEE Photon. Technol. Lett., vol. 14, pp. 1566–1568, Nov.
2002.
APPLIED PHYSICS LETTERS
VOLUME 85, NUMBER 20
15 NOVEMBER 2004
Optimization of ridge height for the fabrication of high performance
InGaAsN ridge waveguide lasers with pulsed anodic oxidation
C. Y. Liu,a) Y. Qu, and Shu Yuan
School of Materials Engineering, Nanyang Technological University, Singapore, 639798, Singapore
S. F. Yoon
School of Electrical and Electronic Engineering, Nanyang Technological University,
Singapore, 639798, Singapore
(Received 18 November 2003; accepted 5 October 2004)
The dependence of the ridge height on the performance of the ridge waveguide (RWG) lasers has
been systematically studied. It was found that the optimum ridge height corresponds to an etching
depth where all the p-doped layers above the active region were removed. InGaAsN
triple-quantum-well RWG lasers with optimized ridge height were fabricated with pulsed anodic
oxidation. The lowest threshold current density 共Jth兲 of 711 A / cm2 was obtained from a 10
⫻ 1300 ␮m2 InGaAsN RWG laser. The corresponding transparency current density 共Jtr兲 of the
fabricated InGaAsN RWG lasers was 438 A / cm2 (equivalent to 146 A / cm2 per well). © 2004
American Institute of Physics. [DOI: 10.1063/1.1824180]
Recently, the growth of InGaAsN quantum well (QW)
active region on GaAs substrate has been studied extensively
to realize light emitters at 1.3 ␮m regime for telecommunication applications.1–8 High performance broad area
InGaAsN QW lasers have been fabricated from wafers
grown by using both molecular beam epitaxy (MBE)1–5 and
metalorganic chemical vapor deposition (MOCVD).6–8 Li et
al.2 have reported that the lowest threshold current density
共Jth兲 of the MBE grown InGaAsN QW lasers is 546 A / cm2
at wavelength of 1317 nm. For the MOCVD-grown
InGaAsN lasers, Tansu et al.8 have reported that the lowest
Jth is in the range of 210– 270 A / cm2. On the other hand,
nearly all the reports on the Jth of InGaAsN QW ridge waveguide (RWG) lasers have shown much higher value than that
of the broad area lasers.3–5 Optimization of the ridge height
is of crucial importance in achieving the lowest possible Jth
of an RWG laser.9,10
Pulsed anodic oxidation (PAO) has been proposed to
produce high quality native oxide on compound semiconductors for laser diode fabrication.11–13 We have recently shown
a significant reduction of Jth in AlGaInP/ GaInP lasers by
using PAO in the laser fabrication.13
In this letter, we report the fabrication of high performance strain-compensated InGaAsN triple quantum well
(TQW) RWG lasers in the 1.3 ␮m regime by using PAO
method with an optimized ridge height. Since the growth of
InGaAs/ GaAs laser structure is much more mature, and furthermore, its structure is similar to InGaAsN laser structure
except their active regions. Thus, we first optimized the ridge
height on InGaAs/ GaAs 980 nm, lasers in terms of Jth and
external quantum efficiency 共␩d兲. Then, the TQW InGaAsN
RWG lasers were fabricated with PAO based on the results
obtained from the fabricated InGaAs/ GaAs lasers.
InGaAsN/ TQW laser structures are listed in Table I
grown by MOCVD. Following the standard photolithograa)
Author to whom correspondence should be addressed; present address:
S1-B2C-20, Clean Room, School of Electrical and Electronic Engineering,
Nanyang Technological University, Singapore, 639798, Singapore; electronic mail: liucy@ntu.edu.sg
phy process, wet chemical etching at RT was carried out with
H3PO4 / H2O2 / H2O (1:1:5) as the etchant to form the ridge.
InGaAs/ GaAs samples with identical size 共7 ⫻ 7 mm2兲 from
the same 2 in. wafer were etched with various time, resulting
in the different etch depths of 0.39, 0.80, 1.23, 1.55, and
1.77 ␮m (below the active region). The etching depth was
measured with an Alpha-step stylus profiler. With photoresist
still on top of the ridge, oxide film with a thickness of
200± 5 nm was formed by means of PAO.12,13 Laser output
power versus injection current 共P – I兲 characteristics of the
InGaAs/ GaAs lasers with different ridge height were measured at RT under cw operation. After optimizing the ridge
height using InGaAs/ GaAs laser structure, we fabricated
InGaAsN RWG lasers based on the obtained information.
Figure 1 shows typical P – I characteristics of three
1100 ␮m long InGaAs/ GaAs 980 nm lasers with ridge
heights 共h兲 of 0.39, 1.23, and 1.77 ␮m, respectively, under
cw operation at RT. The corresponding Jth 共␩d兲 were found to
be 136 (57.8%), 94 (88.5%), and 116 A / cm2 (77.5%), reTABLE I. Strain-compensated InGaAsN/ TQW laser structure.
Layer
GaAs
Al0–0.5GaAs
Al0.5Ga0.5As
Al0–0.5GaAs
GaAs
GaAs0.82P
In0.35Ga0.65As0.85N0.015
Thickness (nm)
Doping 共cm−3兲
200
100
900
200
35
12
C, 1.4⫻ 1019
C, 5.0⫻ 1017
C, 5.0⫻ 1017
Undoped
Undoped
Undoped
Quantum well region
6.4/ 7 / 8
/GaAs/ GaAs0.82P
GaAs0.82P
GaAs
Al0.5–0GaAs
Al0.5Ga0.5As
Al0.0.5GaAs
GaAs
共100兲 GaAs substrate
12
35
200
900
100
200
a.u.
3 period
Undoped
Undoped
Undoped
Si, 6.0⫻ 1017
Si, 5.0⫻ 1017
Si, 1.0⫻ 1018
Si, 1.0⫻ 1018
0003-6951/2004/85(20)/4594/3/$22.00
4594
© 2004 American Institute of Physics
Downloaded 19 Nov 2004 to 132.210.92.112. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
Liu et al.
Appl. Phys. Lett., Vol. 85, No. 20, 15 November 2004
4595
FIG. 1. Light output power 共P兲 vs injection current 共I兲 characteristics of
InGaAs/ GaAs lasers with different ridge height 共h兲 of 0.39, 1.23, and
1.77 ␮m, respectively. The cavity length 共L兲 for all the lasers is 1100 ␮m,
with contact ridge width 共w兲 of 50 ␮m.
spectively. The laser with h of 1.23 ␮m has shown both the
lowest Jth and the highest ␩d. It is clearly seen that the value
of h plays an important role in the device performance. From
the relationship between the reciprocal of ␩d and the cavity
length L for 50 ␮m stripe width InGaAs/ GaAs lasers, an
internal optical loss ␣i of 3.54 cm−1 and average internal
quantum efficiency ␩i of 95.94% were obtained for the
InGaAs/ GaAs laser structure used in this work.
Figure 2(a) plots ln共Jth兲 against the inverse of cavity
length 共l / L兲 of the InGaAs/ GaAs lasers with different values
of h. It is observed that the laser with an h = 1.23 ␮m showed
the lowest Jth for all the cavity lengths. This is consistent
with the finding given in Fig. 1. The transparency current
density 共Jtr兲 of the lasers can be deduced from Fig. 2(a) using
the following equation:14
冉 冊
ln Jth = ln
eJtr
␩i
+
␣i Lopt
− 1,
+
⌫g0
L
共1兲
where ␣i is the internal optical loss, ␩i is the internal quantum efficiency, ⌫ is the optical confinement factor, and g0 is
the material gain. The optimum cavity length is defined as
Lopt = 共1 / 2⌫g0兲ln共1 / R1R2兲. R1共=0.32兲 and R2共=0.32兲 are the
optical power reflection coefficients at the two cleaved facets.
Figure 2(b) shows the estimated value of Jtr as a function
of h. It is shown that the lowest Jtr 共61.2 A / cm2兲 is obtained
from the laser with h of 1.23 ␮m, which corresponds to an
etching depth where all the p-doped layers above the active
region were removed (i.e., p-type contact layer, p-type upper
cladding layer). This value of Jtr (i.e., 61.2 A / cm2) is not too
far from the theoretically calculated Jtr (i.e., 43 A / cm2) for
InGaAs/ GaAs lasers emitting at 980 nm.10 Lasers with the
other values of h such as h = 0.39 ␮m (etching off the P+GaAs contact layer), h = 0.80 ␮m (etching stopped in the upper cladding layer), h = 1.55 ␮m (right above the quantum
well), h = 1.77 ␮m (extended below the active region)
showed noticeably higher magnitude of Jtr. This is because if
lasers with shallower ridges, the injected carriers spread out
laterally and the effective carrier density in the active regions
was lower, thus a higher Jtr was required. However, if lasers
FIG. 2. (a) Logarithm of threshold current density, ln共Jth兲, vs inverse cavity
length 共1 / L兲 for InGaAs/ GaAs lasers of different ridge height 共h兲 of 0.39,
1.23, and 1.77 ␮m, respectively, with contact ridge width 共w兲 of 50 ␮m. For
each height, the laser cavity length 共L兲 ranged from 500 to 1300 ␮m. (b)
Transparency current density 共Jtr兲 of InGaAs/ GaAs lasers with different
ridge height 共h兲 of 0.39, 0.80, 1.23, 1.55, and 1.77 ␮m, respectively.
with too high ridges (i.e., h ⬎ 1.23 ␮m), the sidewall area of
the ridge will be large and resulting in a heavy carrier loss
due to interface recombination. In addition, when the active
region is exposed to air, the light will be confined laterally in
the region defined by the high ridge, light scattering at the
side wall of the active region might also cause losses to the
laser field, contributing to the increase of Jtr. Our studies of
InGaAs 980 nm lasers have indicated that the optimal ridge
height can be obtained if the p-doped layers above the active
are completely removed (i.e., including the top contact layer
and p-doped cladding layer).
Using the similar approach for the design of the ridge
height of the InGaAs/ GaAs 980 nm lasers, InGaAsN RWG
lasers with ridge height of ⬃1.2 ␮m were also fabricated
with PAO. Figure 3 shows the P – I characteristics of a
4 ␮m ⫻ 1260 ␮m TQW InGaAsN RWG laser (without facet
coating and intentional heatsink) under RT and cw operation.
The inset shows the emission spectrum at 1.2895 ␮m with
an inject current of 150 mA.
Figure 4(a) shows the relationship between the reciprocal of ␩d and the cavity length L from a batch of unbonded
as-cleaved InGaAsN lasers with a contact ridge width of
Downloaded 19 Nov 2004 to 132.210.92.112. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
4596
Liu et al.
Appl. Phys. Lett., Vol. 85, No. 20, 15 November 2004
FIG. 3. Light output power 共P兲 vs injection current 共I兲 characteristics for a
4 ␮m ⫻ 1260 ␮m InGaAsN laser diode with 1.23 ␮m ridge height 共h兲; the
inset shows the emission spectra of the same laser with the injection current
of 150 mA.
10 ␮m. The internal quantum efficiency ␩i and internal optical loss coefficient ␣i were determined to be 92% and
12.5 cm−1, respectively. Figure 4(b) shows a plot of ln共Jth兲 vs
1 / L from the same batch InGaAsN lasers presented in Fig.
4(a). Using Eq. (1), a Jtr of 438 A / cm2 was obtained
(equivalent to 146 A / cm2 per well). The lowest Jth in this
work was obtained from a 10 ␮m InGaAsN laser with a
cavity length of 1300 ␮m, which was 711 A / cm2. Riechert
et al.3 reported pulsed operation of InGaAsN RWG laser
emitting at 1.29 ␮m with a Jth of 1.71 kA/ cm2; Borchert et
al.4 reported cw, RT operation of InGaAsN RWG laser in the
1.29 ␮m with a Jth of 1.5 kA/ cm2; recently, Fischer et al.5
reported cw operation of InGaAsN RWG laser in the 1.3 ␮m
with a Jth of 875 A / cm2. These indicated that our InGaAsN
RWG lasers emitting at 1.29– 1.30 ␮m regime have the lowest value of Jth when compared with the literatures. The high
performance of our InGaAsN RWG lasers is attributed to the
proper selection of ridge height to achieve minimum scattering and absorption losses. Furthermore, since the native oxide in the PAO process was formed by consuming a part of
the semiconductor material, better passivation of the sidewalls after wet etching can be expected.
In conclusion, we have systematically studied the influence of ridge height on the performance of RWG lasers. It is
found that the optimum ridge height can be obtained by removing all the p-doped layers of the RWG. The lowest Jth
and Jtr as well as the highest ␩d can be obtained from lasers
under this optimal condition. High performance InGaAsN
TQW RWG lasers were fabricated with PAO using the optimum ridge height. The lowest Jth was 711 A / cm2 obtained
from a 10 ␮m ⫻ 1300 ␮m InGaAsN RWG laser, with a Jtr of
438 A / cm2 (equivalent to 146 A / cm2 per well) for the
InGaAsN RWG laser. PAO has also presented itself again as
a cost-effective, reliable method in the fabrication of high
performance RWG lasers.
The authors thank S. F. Yu, W. J. Fan, S. M. Wang, and
S. Z. Wang for comments on the manuscript and helpful
discussions. They also thank J. Ma, F. Boey, G. Chen, K.
Pita, and S. C. Tjin for their support of the work.
FIG. 4. (a) Inverse external quantum efficiency 共1 / ␩d兲 as a function of
InGaAsN TQW RWG laser cavity length 共L兲, with contact ridge width 共w兲
of 10 ␮m, ridge height 共h兲 of 1.23 ␮m. The internal quantum efficiency 共␩i兲
and internal optical loss 共␣i兲 were determined to be 92% and 12.5 cm−1,
respectively. (b) Logarithm of threshold current density, ln共Jth兲, as a function
of InGaAsN TQW RWG laser inverse cavity length 共1 / L兲. The transparency
threshold current density 共Jtr兲 was determined to be 438 A / cm2 (equivalent
to 146 A / cm2 per well).
1
M. Kondow, K. Uomi, A. Niwa, T. Kitatani, S. Watahiki, and Y. Yazawa,
Jpn. J. Appl. Phys., Part 1 35, 1273 (1996).
2
W. Li, T. Jouhti, C. S. Peng, J. Konttinen, P. Laukkanen, E.-M. Pavelescu,
M. Dumitrescu, and M. Pessa, Appl. Phys. Lett. 79, 3386 (2001).
3
H. Riechert, A. Y. Egorov, D. Livshits, B. Borchert, and S. Illek, Nanotechnology 11, 201 (2000).
4
B. Borchert, A. Y. Egorov, S. Illek, and H. Riechert, IEEE Photonics
Technol. Lett. 12, 597 (2000).
5
M. Fischer, D. Gollub, M. Reinhardt, and M. Kamp, J. Cryst. Growth 251,
353 (2003).
6
N. Tansu, N. J. Kirsch, and L. J. Mawst, Appl. Phys. Lett. 81, 2523
(2002).
7
N. Tansu, A. Quandt, M. Kanskar, and L. J. Mawst, Appl. Phys. Lett. 83,
18 (2003).
8
N. Tansu, J.-Y. Yeh, and L. J. Mawst, Appl. Phys. Lett. 83, 2512 (2003).
9
C. P. Chao, S. Y. Hu, K-K. Law, B. Young, J. L. Merz, and A. C. Gossard,
J. Appl. Phys. 69, 7892 (1991).
10
S. Y. Hu, D. B. Young, A. C. Gossard, and L. A. Coldren, IEEE J. Quantum Electron. 30, 2245 (1994).
11
M. J. Grove, D. A. Hudson, P. S. Zory, R. J. Dalby, C. M. Harding, and A.
Rosenberg, J. Appl. Phys. 76, 587 (1994).
12
S. Yuan, C. Y. Liu, and F. Zhao, J. Appl. Phys. 93, 9823 (2003).
13
C. Y. Liu, S. Yuan, J. R. Dong, S. J. Chua, M. C. Y. Chan, and S. Z. Wang,
J. Appl. Phys. 94, 2962 (2003).
14
S. L. Chuang, Physics of Optoelectronic Devices (Wiley, New York,
1995).
Downloaded 19 Nov 2004 to 132.210.92.112. Redistribution subject to AIP license or copyright, see http://apl.aip.org/apl/copyright.jsp
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 11, NOVEMBER 2004
2541
A Novel Two-Color Photodetector Based on an
InAlAs–InGaAs HEMT Layer Structure
M. Marso, M. Wolter, and P. Kordos̆
Abstract—The spectral responsivity of an InAlAs–InGaAs
metal–semiconductor–metal diode above a two-dimensional electron gas (2DEG) is investigated as a function of the applied bias.
At low voltages, only the InAlAs layer above the 2DEG contributes
to the photocurrent, while the InGaAs channel layer is activated at
higher bias. This results in a voltage-dependent spectral response
of the photodetector. The ratio of the responsivities at 1300 and
850 nm changes from 0.03- at 1-V to 0.44- at 1.6-V bias. This
property makes the device a candidate suitable to detect and
to separate optical information originated both from the GaAs
(850 nm) and in the InGaAs (1300, 1550 nm)-based optoelectronic
technology.
Index Terms—Infrared detectors, metal–semiconductor–metal
(MSM) devices, MODFETs, photodetectors, spectroscopy.
Fig. 1. Layer system and schematic diagram of an MSM-2DEG diode
integrated with an HEMT.
I. INTRODUCTION
C
OLOR IMAGE processing is usually performed with
color-filter-coated photodetectors [1]. To overcome the
splitting of one color pixel into several chromatic subpixels,
different photodetector designs to detect the color information
in one single device have been proposed. One concept uses a
stack of p-n or p-i-n photodiodes, where the spectral sensitivity
of the individual junctions is realized by the wavelengthdependent absorption coefficient of -Si : H alloys [2] or by
the different penetration depths of red, green, and blue light
in crystalline silicon [3]. By another approach, the spectral
sensitivity of two-terminal devices depends on the applied bias
voltage, as was demonstrated with GaAs-based multiquantum
well infrared photodetectors [4]. In this work, we investigate
the voltage-dependence of the spectral responsivity of a metal–
semiconductor–metal diode above a two-dimensional electron
gas (MSM-2DEG).
II. DEVICE CONCEPT
The MSM-2DEG has been investigated extensively for use
as varactor diode and as photodetector [5]–[8]. It consists of
two Schottky contacts above a high-electron mobility transistor
(HEMT) layer system, simplifying integration in HEMT circuits
(Fig. 1) [9]. The 2DEG with its high sheet carrier concentration
(typically in the order of 10 cm for InAlAs–InGaAs based
structures) acts as an equipotential plane that forces the electric
field and the depletion layer of the reverse biased Schottky contact in the region between surface and 2DEG, provided that the
Manuscript received May 7, 2004; revised June 25, 2004.
The authors are with the Institute of Thin Films and Interfaces and CNI,
Center of Nanoelectronic Systems for Information Technology, Research Centre
Jülich, 52425 Jülich, Germany (e-mail: m.marso@fz-juelich.de).
Digital Object Identifier 10.1109/LPT.2004.834909
Fig. 2. Extension of the depletion zone for (A) low and (B) high bias voltage.
The electrode on the right is reverse-biased.
bias voltage is not too high [Fig. 2(A)]. When the applied bias
becomes sufficiently high to totally deplete the 2DEG channel
below the contact then the depletion region penetrates the region below the channel [Fig. 2(B)]. This causes a dramatic decrease of the device capacitance that can be used for varactor
applications [5]. When the device is used as photodetector, then
only the carriers generated in the depletion region contribute to
the photocurrent. In former publications, only the high-voltage
regime was used for photodetector applications. An InAlAs–
InGaAs-based MSM-2DEG photodetector was published with
a bandwidth of 20 GHz by excitation with 1.3- m wavelength
light [9]. For use as a two-color detector, we take advantage of
the voltage-dependent penetration depth of the depletion region
to control the spectral dependence of the photodetector responsivity by the applied voltage. In contrast to a conventional MSM
without 2DEG, the penetration of the depletion region into the
InGaAs layer is very abrupt and can be controlled by the carrier
concentration in the channel.
1041-1135/04$20.00 © 2004 IEEE
2542
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 11, NOVEMBER 2004
Fig. 3. Scanning electron microscope picture of an MSM-2DEG photodetector
with airbridges to contact the electrodes. Device area is 10 10 m .
2
III. DEVICE FABRICATION
The HEMT layer sequence is grown by molecular beam
epitaxy on a semi-insulating InP substrate. It consists of a
200-nm-thick InAlAs buffer layer, a 100-nm-thick InGaAs absorption layer, an 8-nm-thick strained In Ga As channel
Si delta
layer, a 5-nm-thick InAlAs spacer, 3 10 cm
doping, a 40-nm-thick InAlAs barrier layer, and a 10-nm-thick
n -doped InGaAs cap layer. All layers except the channel are
lattice-matched to InP. Room-temperature Hall measurements
and
yield a 2DEG carrier concentration of 1.8 10 cm
a mobility of 7400 cm /Vs. The devices are prepared within
the standard HEMT fabrication process (for details see [10]).
The Schottky contacts are defined by e-beam lithography. They
consist of an opaque Ti–Au layer system with finger width
and spacing of 300 and 600 nm, respectively. The InGaAs cap
layer is removed before metallization by succinic acid. Mesa
etching is performed as last step after contact pad formation.
The contact metallization at the edges of the mesa is only
1.5 m wide to obtain underetching during mesa formation.
This technique avoids a shortcut of the contacts to the InGaAs
absorption layer at the mesa edges (Fig. 3).
IV. MEASUREMENT RESULTS
All measurements are performed on a photodetector with
50 50 m active area. The device is at first characterized
by electrical dc and capacitance–voltage measurements with
an AGILENT 4155B semiconductor parameter analyzer and an
AGILENT 4294A impedance analyzer. The abrupt decrease of
the capacitance at 1.1 V identifies the transition voltage where
the 2DEG below the reverse biased electrode is completely
emptied and where the depletion layer starts to penetrate the
InGaAs absorption layer. The dark current is 1 A at 3-V
bias voltage. For optoelectronic measurements, a setup is used
where the light from a Xenon arc lamp is directed through a
grating monochromator. The monochromatic light is focused
by a lens to the device under test. The measurement accuracy
is improved by a lock-in amplifier including a chopper in the
light beam. The power of the incident light is in the range of
1–3 W, depending on wavelength. Because the active device
area is smaller than the focused light spot, the measured responsivity is calibrated at 850- and 1310-nm wavelength with
Fig. 4. Spectral responsivity for an applied bias below (1 V) and above (1.6 V)
the transition voltage (1.1 V).
an HP 8153A lighwave multimeter, using a glass fiber with
9- m core diameter. The light that misses the active device
area affects the measurement to less than 1% in the whole
wavelength range, as determined by measurement of reference
samples with similar contact pads as the photodetector, but
without mesa or Schottky contacts. Fig. 4 shows the spectral
responsivity for two different bias voltages. At 1 V, the depletion region is stopped at the DEG channel. The electric
field is limited to the InAlAs barrier layer with a bandgap of
1.43 eV [11] that corresponds to a wavelength of 867 nm. The
responsivity drops from 12 mA/W below 800 nm to less than
0.2 mA/W above 900-nm wavelength because the photocurrent
is mainly created in the depletion region. The increase of the
bias voltage to 1.6 V (above the transition voltage of 1.1 V)
extends the depletion layer into the InGaAs absorption layer.
The responsivity is extended to the wavelength range up to
1700 nm that is the limit for lattice-matched InGaAs with a
bandgap of 0.73 eV. This result demonstrates the property of
the InAlAs–InGaAs-based MSM-2DEG photodetector that the
responsivity can be switched ON and OFF in the wavelength
range between 900 and 1700 nm by changing the bias voltage,
while the responsivity below 900 nm only changes its value.
In general, the device provides two linear independent spectral
responses by measuring at two different bias voltages (one
below and one above the transition voltage). This allows the
separation of the incident light in two different colors, e.g., the
determination of the intensities of two incident light beams
with 850- and 1300-nm wavelength, respectively.
Fig. 5 depicts the responsivity as a function of the bias voltage
for two selected wavelengths. The 850-nm wavelength light that
excites both InAlAs and InGaAs creates a photocurrent already
at very low bias voltages, while the 1300-nm light activates the
photodetector not until 1.1 V, when the depletion region starts to
of
penetrate the InGaAs absorption layer. The ratio
the responsivities at 1300 and 850 nm is below 0.03 at low voltages. It begins to increase above 1.1 V and reaches a maximum
value of 0.44 at 1.6 V. For larger bias voltages, the responsivity
at 850 nm increases faster than the value for 1300 nm, resulting
MARSO et al.: NOVEL TWO-COLOR PHOTODETECTOR BASED ON AN InAlAs–InGaAs HEMT LAYER STRUCTURE
2543
ACKNOWLEDGMENT
The authors thank A. Förster for MBE growth of the samples.
REFERENCES
Fig. 5. Voltage-dependence of the responsivity at 850 and 1300 nm (right
scale) and of the responsivity ratio (left scale).
in a reduction of the reponsivity ratio. This behavior is due to the
penetration of the depletion region into the InAlAs buffer layer.
V. CONCLUSION
We present a planar photodetector that requires only HEMT
layer structure and fabrication technology. The spectral responsivity is tunable by the bias voltage making the device
applicable as two-color photodetector. A detector fabricated in
the InAlAs–InGaAs material system detects and discriminates
light originated by GaAs (800–860 nm) and by InP (1300,
1550 nm) based optoelectronic technology. The responsivity of
the presented device can be improved by increasing the thickness of the InGaAs absorption layer and by using transparent
Schottky electrodes [12]. In fact, MSM-2DEG diodes that
were optimized as high frequency photodetectors at 1300-nm
wavelength have shown responsivities up to 0.61 A/W [13].
An alternative method to increase the responsivity is to design
the device as edge-coupled photodetector [14]. The extension
of the device structure by a third layer with a further spectral
responsivity, also separated by a conductive channel, allows the
fabrication of a three-color device.
[1] K. Engelhardt and P. Seitz, “Optimum color filters for CCD digital cameras,” Appl. Opt., vol. 32, pp. 3015–3023, 1993.
[2] D. Knipp, P. G. Herzog, and H. Stiebig, “Stacked amorphous silicon
color sensors,” IEEE Trans. Electron Devices, vol. 49, pp. 170–176, Jan.
2002.
[3] P. Gwynne, “Tricolor sensors create a sharper image,” IEEE Spectr., vol.
39, pp. 23–24, May 2002.
[4] A. Majumdar, K. K. Choi, J. L. Reno, L. P. Rokhinson, and D. C. Tsui,
“Two-color quantum-well infrared photodetector with large tunable
peaks,” Appl. Phys. Lett., vol. 80, pp. 707–709, 2002.
[5] M. Marso, M. Horstmann, H. Hardtdegen, P. Kordos̆, and H. Lüth, “Electrical behavior of the InP/InGaAs based MSM-2DEG diode,” Solid-State
Electron., vol. 41, pp. 25–31, 1997.
[6] M. Marso, M. Horstmann, K. Schimpf, J. Muttersbach, H. Hardtdegen, G. Jacob, and P. Kordos̆, “High bandwidth InP/InGaAs based
MSM-2DEG diodes for optoelectronic application,” in Proc. 9th Int.
Conf. Indium Phosphide and Related Materials, Hyannis, MA, 1997,
pp. 494–497.
[7] M. Marso, M. Wolter, P. Javorka, A. Fox, and P. Kordos̆, “AlGaN/GaN
varactor diode for integration in HEMT circuits,” Electron. Lett., vol. 37,
pp. 1476–1478, 2001.
[8] M. Marso, J. Bernát, M. Wolter, P. Javorka, A. Fox, and P. Kordos̆,
“MSM diodes based on an AlGaN/GaN HEMT layer structure for
varactor and photodiode application,” in Proc. 4th Int. Conf. Advanced
Semiconductor Devices and Microsystems, 2002, ISBN 0-7803-7276-X,
pp. 295–298.
[9] U. Hodel, A. Orzati, M. Marso, O. Homan, A. Fox, A. v.d. Hart, A.
Förster, P. Kordos̆, and H. Lüth, “A novel InAlAs/InGaAs layer structure
for monolithically integrated photoreceiver,” in Proc. 2000 Int. Conf.
Indium Phosphide and Related Materials, Williamsburg, VA, 2000, pp.
466–469.
[10] M. Marso, P. Gersdorf, A. Fox, A. Förster, U. Hodel, R. Lambertini,
and P. Kordos̆, “An InAlAs-InGaAs OPFET with responsivity above 200
A/W at 1.3 m wavelength,” IEEE Photon. Technol. Lett., vol. 11, pp.
117–119, Jan. 1999.
[11] S. Nojima and K. Watika, “Optimization of quantum well materials and
structures for excitonic electroabsorption effects,” Appl. Phys. Lett, vol.
53, pp. 1958–1960, 1988.
[12] W. A. Wohlmuth, J.-W. Seo, P. Fay, C. Caneau, and I. Adesida, “A
high-speed ITO-InAlAs-InGaAs Schottky-barrier photodetector,” IEEE
Photon. Technol. Lett., vol. 9, pp. 1388–1390, Oct. 1997.
[13] M. Horstmann, M. Marso, J. Muttersbach, K. Schimpf, and P. Kordos̆,
“Responsivity enhancement of InGaAs based MSM photodetectors
using 2DEG layer sequence and semitransparent electrodes,” Electron.
Lett., vol. 32, pp. 1613–1614, 1996.
[14] K. Kato, “Ultrawide-band/high-frequency photodetectors,” IEEE Trans.
Microwave Theory Tech., vol. 47, pp. 1265–1281, July 1999.
1342
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 15, NO. 10, OCTOBER 2003
Improvement of Near-Ultraviolet InGaN–GaN
Light-Emitting Diodes With an AlGaN
Electron-Blocking Layer Grown at Low Temperature
Ru-Chin Tu, Chun-Ju Tun, Shyi-Ming Pan, Chang-Cheng Chuo, J. K. Sheu, Ching-En Tsai, Te-Chung Wang,
and Gou-Chung Chi
Abstract—The 400-nm near-ultraviolet InGaN–GaN multiple
quantum well light-emitting diodes (LEDs) with Mg-doped AlGaN
electron-blocking (EB) layers of various configurations and grown
under various conditions, were grown on sapphire substrates by
metal–organic vapor phase epitaxy system. LEDs with AlGaN EB
layers grown at low temperature (LT) were found more effectively
to prevent electron overflow than conventional LEDs with an
AlGaN one grown at high temperature (HT). The electroluminescent intensity of LEDs with an LT-grown AlGaN layer was
nearly three times greater than that of LEDs with an HT-grown
AlGaN. Additionally, the LEDs with an LT-grown AlGaN layer in
H2 ambient were found to increase the leakage current by three
orders of magnitude and reduce the efficiency of emission.
Index Terms—AlGaN, electron-blocking (EB) layer, GaN,
InGaN, light-emitting diodes (LEDs), low temperature (LT).
I. INTRODUCTION
T
HE RECENT commercialization of blue–green
light-emitting diodes (LEDs) and laser diodes (LDs)
has led to much interest in Group III nitride compound semiconductor materials [1]. Although blue–green LEDs are already
commercially available, fabricating highly efficient ultraviolet
(UV) LEDs remains difficult. [2]–[4] GaN-based UV emitters
are attracting attention as pump sources in the development
of white LEDs, and much research is presently focused on
maximizing the efficiency of visible and UV GaN emitters. A
thin AlGaN cap is generally placed above the multiple quantum
wells (MQWs) of InGaN-based LEDs and LDs to prevent
electron overflow from the active region, and to protect the
InGaN active region from the subsequent high-temperature
growth of p-type layers. [1], [5] Although an Mg-doped AlGaN
layer is generally grown above the active region of the LED
at high temperatures (HTs) of the p-type GaN contacting
layers, to serve as an electron-blocking (EB) layer, it does not
protect the MQWs from the HT growth of the p-type GaN
contacting layers. Instead, the Mg-doped AlGaN CB layer
grown at low temperatures (LT) directly above the final InGaN
well of the InGaN QWs will perform both functions [5]. This
work demonstrates that the growth at LT of Mg-doped AlGaN
Manuscript received May 6, 2003; revised June 25, 2003. This work was supported by the Ministry of Economic Affairs of the Republic of China.
R.-C. Tu, S.-M. Pan, C.-C. Chuo, C.-E. Tsai, and T.-C. Wang are with the
Opto-Electronics and System Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C. (e-mail: RuChinTU@itri.org.tw).
C.-J. Tun, J. K. Sheu, and G.-C. Chi are with the Institute of Optical Science,
National Central University, Chung-Li 32054, Taiwan, R.O.C.
Digital Object Identifier 10.1109/LPT.2003.818240
directly on the final InGaN well layer can increase the emission
efficiency and reduce the leakage current of near-UV LEDs.
II. EXPERIMENTS
In this study, five InGaN–GaN MQWs near-UV LED
structures were grown on c-face sapphire substrates by
metal–organic vapor phase epitaxy (MOVPE) [6]–[10]. A
30-nm-thick low-temperature GaN nucleation layer was first
grown at 550 . The reactor temperature was then increased
to 1050 C to grow a 4- m-thick underlying Si-doped GaN
layer. Thereafter, the temperature was gradually decreased to
850 C to grow the In Ga N–GaN MQW active region in
N ambiance, including five pairs of 2.5-nm-thick undoped
In Ga N well layers and 7.5-nm-thick Si-doped GaN barrier layers. Notably, in conventional LED sample 9F, the final
undoped GaN barrier was grown to a thickness of 5.0 nm at the
same temperature as previous MQW layers; the temperature of
the substrate was then increased to 1050 C to grow the 30-nm
Mg-doped Al Ga N EB layer in H ambient at HT, and
then to grow the topmost 0.2- m-thick Mg-doped GaN layer as
a contact layer. Additionally, four additional LED samples (7B,
7D, 7F, and 8B) with LT-grown Mg-doped Al Ga N EB
layers grown under various conditions, were grown to investigate the effect of the LT-grown Mg-doped AlGaN EB layer
directly on the final InGaN well layer. Fig. 1(a) and (b) shows
the schematic LEDs device structures with corresponding
band diagram of the InGaN–GaN MQW active region with
the LT-grown Mg-doped AlGaN EB layer on the last InGaN
quantum well and HT-grown Mg-doped AlGaN EB layer on
the last GaN barrier, respectively. Table I lists detailed growth
conditions and the placement of the Mg-doped AlGaN EB
layer above the active region. The LEDs (300 300 m) were
fabricated using photolithographic patterning, dry etching, and
deposition of Ni–Au and Ti–Al as p- and n-type Ohmic contacts, respectively. The current–voltage ( – ) characteristics
were measured at room temperature (RT) using an HP4156
semiconductor parameter analyzer. RT electroluminescence
(EL) and the luminous intensity of these fabricated LEDs were
measured as functions of forward injection current between 0
and 250 mA.
III. RESULTS AND DISCUSSION
The temperature and ambient atmosphere of growth of
LT-AlGaN differ from those of the growth of conventional
HT-AlGaN EB layers, and so the Mg-doping efficiencies in
1041-1135/03$17.00 © 2003 IEEE
TU et al.: IMPROVEMENT OF NEAR-UV InGaN–GaN LEDs WITH AN AlGaN EB LAYER GROWN AT LT
Fig. 1. Schematic band diagram of the InGaN–GaN MQW active region with
(a) the Mg-doped AlGaN EB layer on the last InGaN quantum well and (b) on
the last GaN barrier.
1343
Fig. 2. RT EL spectra of LEDs 7B (160 mA), 7D (20 mA), and 7F (20 mA).
The inset plots the relative output luminous intensity as a function of injection
current between 10 and 250 mA for three LEDs.
TABLE I
DETAILED GROWTH CONDITIONS AND THE PLACEMENT OF THE Mg-DOPED
AlGaN EB LAYER ABOVE THE ACTIVE REGION
AlGaN can also differ in these two cases. In the first three
samples, 7B, 7D, and 7F, as listed in Table I, near-UV LED
structures that contain Mg-doped LT-AlGaN EB layers grown
with various Cp Mg flow rates, were grown to investigate the
Mg-doping efficiency of the LT-AlGaN in N ambiance. Fig. 2
shows the EL spectra of LEDs 7B (160 mA), 7D (20 mA),
and 7F (20 mA) at RT. The peak wavelength of three LEDs
is around 400 nm. Obviously, the EL intensity of LED 7B is
much smaller than the intensities of LEDs 7D and 7F. Notably,
the EL intensity of LED 7D is approximately double that of
LED 7F at 20 mA. The inset in Fig. 2 presents the relative
output luminous intensity as a function of injection current
between 0 and 250 mA for three LEDs. Notably, although
the luminous intensity of LED 7B begins to increase after an
80-mA injection current is applied, that of LED 7D increases
more than that of 7F at an injection current of up to 250 mA.
Fig. 3 compares the forward – characteristics of the three
V) exceeds
LEDs. The forward voltage of LED 7B (
V). Consequently,
that of both LEDs 7D and 7F (
the much lower output luminous intensity of LED 7B could
be attributed to the larger forward voltage and the poorer
current spreading of the LT-grown Mg-doped AlGaN layer on
the active layer with lower Cp Mg flow rates. Additionally,
the smaller output luminous intensity of LED 7F (with more
Cp Mg) than that of 7D (with less Cp Mg) could be attributed
to the fact that too many Mg impurities diffused into final
InGaN well layer during the ramping of the temperature to
the growth of the HT-GaN contacting layer. In addition, too
many Mg impurities in LT-AlGaN EB layer could also lead
Fig. 3. Forward I –V characteristics of three LEDs. The forward voltage of
LED 7B (V = 3:63 V) exceeds that of both LEDs 7D and 7F (V = 3:25 V).
to the auto-compensation and/or structural degradation in the
LED 7F. After the Cp Mg doping efficiency of the LT-grown
Mg-doped AlGaN layer was optimized, the optimal Cp Mg
flow rate used to grow the AlGaN layer at LT was found to be
almost the same as that used to grow the layer grown at HT.
Hereafter, a Cp Mg flow rate of 150 nmole/s was adopted, as
for sample 7D.
The temperature, pressure, and ambient atmosphere of the
growth of the InGaN–GaN MQWs active layer at LT differed
significantly from the p-type GaN grown at HT, so several
growth conditions could be adopted to grow the Mg-doping
AlGaN layer. Here, the effects of growing AlGaN EB layers
in H and N ambiance at LT were investigated. Fig. 4 shows
the RT EL spectra of LEDs 7D (20 mA), 8B (60 mA), and
9F (20 mA). The peak wavelength of three LEDs is around
400 nm. Clearly, the EL intensity of LED 8B is much smaller
than those of LEDs 7D and 9F. Notably, the EL intensity of
LED 7D is approximately three times of magnitude higher
than that of LED 9F at 20 mA. The inset in Fig. 4 presents the
relative output luminous intensity as a function of injection
current between 0 and 250 mA for three LEDs. Notably, the
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IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 15, NO. 10, OCTOBER 2003
IV. CONCLUSION
An LT-grown Mg-doped AlGaN EB layer has been adopted
to improve the emission efficiency of the 400-nm near-UV
InGaN–GaN MQWs LEDs grown on c-face sapphire substrates
by MOVPE. The LT-grown Mg-doped AlGaN EB layer is
optimized, and the optimal Cp Mg flow rate used for growing
the AlGaN layer at LT was almost the same as that used to
grow the layer at HT. The EL intensity of LEDs with LT-grown
Mg-doped AlGaN layers was nearly three times larger than
that of LEDs with HT-grown AlGaN. Moreover, an Mg-doped
AlGaN layer in N ambient grown at LT is found to be better
than that grown in the H ambient due to the prevention
of dissociation and etching of the final InGaN well layer.
Meanwhile, the leakage current is reduced by three orders of
magnitude, and the emission efficiency is enhanced.
Fig. 4. RT EL spectra of LEDs 7D (20 mA), 8B (60 mA), and 9F (20 mA).
The inset plots the relative output luminous intensity as a function of injection
current between 10 and 250 mA for three LEDs.
ACKNOWLEDGMENT
The authors would like to thank the Shipley Company for the
support of high-purity metal–organic sources on this work.
REFERENCES
Fig. 5. Reverse I –V characteristics of three LEDs. The leakage currents of
LEDs 7D, 8B, and 9F at a reverse bias of 5 V were approximately 6 nA, 3.75 A,
and 50 nA, respectively.
luminous intensity of LED 8B begins to increase after a 40- mA
injection current is applied, but that of LED 7D increases more
than that of 9F until an injection current of 250 mA is applied.
Consequently, replacing an HT-grown AlGaN EB layer with
an LT-grown AlGaN one will prevent electron overflow from
the active region and enhance the efficiency of LEDs. Fig. 5
compares the reverse – characteristics of three LEDs.
The leakage currents of LEDs 7D, 8B, and 9F at a reverse
bias of 5 V were approximately 6 nA, 3.75 A, and 50 nA,
respectively. LED 8B has a dramatically higher leakage current
because it has a worse interface between the final InGaN well
layer and the Mg-doped AlGaN layer. The exposure of the final
InGaN well layer in the H ambient can cause the dissociation
and etching [11], [12] of the final InGaN well layer degrades
the p-n junction of LED devices and facilitates current leakage.
Consequently, the luminous intensity of LED 8B was much
lower than those of LED 7D and LED 9F.
[1] S. Nakamura and G. Fasol, The Blue Laser Diode, Berlin, Germany:
Springer-Verlag, 1997.
[2] S. J. Chang, C. H. Kuo, Y. K. Su, L. W. Wu, J. K. Sheu, T. C. Wen,
W. C. Lai, J. F. Chen, and J. M. Tsai, “400-nm InGaN-GaN and InGaNAlGaN multiquantum well light-emitting diodes,” IEEE J. Select. Topics
Quantum Electron., vol. 8, pp. 744–748, July/Aug. 2002.
[3] T. Nishida, H. Saito, and N. Kobayashi, “Efficient and high power
AlGaN-based ultraviolet light-emitting diode grown on bulk GaN,”
Appl. Phys. Lett., vol. 79, pp. 711–712, 2001.
[4] Y. B. Lee, T. Wang, Y. H. Liu, J. P. Ao, Y. Izumi, Y. Lacroix, H. D. Li,
J. Bai, Y. Naoi, and S. Sakai, “High-performance 348 nm AlGaN/GaNbased ultraviolet-light-emitting diode with a SiN buffer layer,” Jpn. J.
Appl. Phys., vol. 41, pp. 4450–4453, 2002.
[5] M. Hansen, J. Piprek, P. M. Pattison, J. S. Speck, S. Nakamura, and S.
P. DenBaars, “Higher efficiency InGaN laser diodes with an improved
quantum well capping configuration,” Appl. Phys. Lett., vol. 81, pp.
4275–4277, 2002.
[6] R.-C. Tu, C.-J. Tun, J. K. Sheu, W.-H. Kuo, T.-C. Wang, C.-E. Tsai, J.-T.
Hsu, J. Chi, and G.-C. Chi, “Improvement of InGaN–GaN laser diodes
Ga
N–GaN short-period superlattice tunby using a Si-doped In
neling contact layer,” IEEE Electron Device Lett., vol. 24, pp. 206–208,
Apr. 2003.
[7] S.-M. Pan, R.-C. Tu, Y.-M. Fan, R.-C. Yeh, and J.-T. Hsu, “Improvement
of InGaN–GaN light emitting diodes with surface-textured indium-tinoxide transparent ohmic contacts,” IEEE Photon. Technol. Lett., vol. 15,
pp. 649–651, May 2003.
[8]
, “Enhanced output power of InGaN–GaN light-emitting diodes
with high-transparency nickel-oxide/indium-tin-oxide ohmic contacts,”
IEEE Photon. Technol. Lett., vol. 15, pp. 646–648, May 2003.
[9] J. K. Sheu, G. C. Chi, and M. J. Jou, “Low-operation voltage
of InGaN–GaN light-emitting diodes by using a Mg-doped
Al
Ga
N–GaN superlattice,” IEEE Electron Device Lett.,
vol. 22, pp. 160–162, Apr. 2001.
[10] J. K. Sheu, J. M. Tsai, S. C. Shei, W. C. Lai, T. C. Wen, C. H. Kou, Y. K.
Su, S. J. Chang, and G. C. Chi, “Low-operation voltage of InGaN-GaN
light-emitting diodes with Si-doped In Ga N–GaN short-period superlattice tunneling contact layer,” IEEE Electron Device Lett., vol. 22,
pp. 460–462, Oct. 2001.
[11] A. V. Sakharov, W. V. Lundin, I. L. Krestnikov, D. A. Bedarev, A. F.
Tsatsul’nikov, A. S. Usikov, Z. I. Alferov, N. N. Ledentsov, A. Hoffmann, and D. Bimberg, “Influence of growth interruptions and gas ambient on optical and structural properties of InGaN/GaN multiplayer
structures,” in Proc. Int. Workshop Nitride Semiconductors IPAP Conf.
Series 1, 2000, pp. 241–243.
[12] E. L. Piner, M. K. Behbehani, N. A. El-Masry, F. G. McIntosh, J. C.
Roberts, K. S. Boutros, and S. M. Bedair, “Effect of hydrogen on the
indium incorporation in InGaN epitaxial films,” Appl. Phys. Lett., vol.
70, pp. 461–463, 1997.
1930
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 8, AUGUST 2004
Fabrication of 1.55-m Si-Based Resonant Cavity
Enhanced Photodetectors Using Sol-Gel Bonding
R. W. Mao, C. B. Li, Y. H. Zuo, B. W. Cheng, X. G. Teng, L. P. Luo, J. Z. Yu, and Q. M. Wang
Abstract—In this work, a novel bonding method using silicate
gel as the bonding medium was developed to fabricate an InGaAs
narrow-band response resonant cavity enhanced photodetector on
a silicon substrate. The bonding was performed at a low temperature of 350 C without any special treatment on bonding surfaces
and a Si-based narrow-band response InGaAs photodetector was
successfully fabricated, with a quantum efficiency of 34.4% at the
resonance wavelength of 1.54 m, and a full-width at half-maximum of about 27 nm. The photodetector has a linear photoresponse up to 4-mW optical power under 1.5 V or higher reverse
bias. The low temperature wafer bonding process demonstrates a
great potential in device fabrication.
Index Terms—Bonding medium, direct bonding, photodetector,
resonant cavity enhanced (RCE).
I. INTRODUCTION
T
HE INCREASING demand for bandwidth of telecommunication has greatly promoted the development of optical
fiber communications. One of the promising technologies
is wavelength-division multiplexing (WDM). Since the early
1960s, single-channel communication has not been able to meet
the explodingly increasing demands of information; resonant
cavity enhanced (RCE) photodectors, with the ability of wavelength selectivity, have become a promising candidate, and have
attracted much attention due to their potential of circumventing
the tradeoff between bandwidth and responsivity [1]–[2].
A lot of work about the design and optimization of RCE photodetectors has been conducted [3]–[7]. However, how to fabricate long wavelength RCE photodetectors with high reflectivity distributed Bragg reflectors (DBR) and high absorption
layers is still a problem, and how to fabricate Si-based high
quantum efficiency RCE photodectors operating at 1.55 m for
fiber-optic communication is even more difficult [8]. In general, the methods of fabricating RCE photodetectors operating
at 1.55 m can be divided into three groups: InP-based, GaAsbased, and Si-based. 1) In the InP-based case, InGaAsP–InP is
used for the reflector and InGaAs for the active layer. For mature InP-based epitaxy technology, it is easy to grow a lattice
constant matched InGaAs layer with a peak absorption wavelength at about 1.55 m; however, more than 30 pairs of InP–InGaAsP are needed to form a DBR with a reflectivity higher
Manuscript received February 10, 2004; revised April 7, 2004. This work was
supported by the Major State Basic Research Program (G2000036603), by the
National Natural Science Foundation of China (90104003 and 60336010), and
by the National High Technology Research and Development Program of China
(2002AA312010).
The authors are with the Institute of Semiconductors, Chinese Academy of
Sciences, Beijing 100083, China (e-mail: maorongwei@red.semi.ac.cn).
Digital Object Identifier 10.1109/LPT.2004.831049
than 99%, due to the small refractive index difference between
them [9]. To grow such a thick high quality mirror is expensive for industrial manufacturing. Although other technologies
such as air-gap DBR have been used to improve the reflectivity
of mirrors [10], the fabrication process is somewhat too complicated. 2) The GaAs-based case uses the reflector of GaAs–AlAs
and the active layer of GaInNAs. The refractive index difference between GaAs–AlAs material is much larger than that of
InP–InGaAsP; however, it is difficult to grow a high-quality
GaInNAs layer on a GaAs substrate with the peak absorption
wavelength at about 1.55 m currently, due to their large lattice
constant mismatch between them [11]. 3) In the Si-based case,
GeSi is used as the active layer material and SiO –Si is used
as the reflector material. Three pairs of SiO –Si can achieve a
high reflectivity of more than 99%, due to the large refractive
index difference between them, but the indirect bandgap property of GeSi limits the quantum efficiency at 1.55 m. Resonant
cavity structure was used to improve the quantum efficiency of
long wavelength GeSi photodector [12]. To combine the advantage of mature epitaxy technology of InP-based InGaAsP,
and the larger refractive index difference between SiO –Si to
fabricate Si-based RCE photodetectors, direct wafer bonding
technology has been developed [13]. In order to achieve high
bonding quality, special treatment such as chemical–mechanical
polishing and wet etching are required to ensure flat, clean, and
oxide-free surfaces of the wafers to be bonded together. Bonding
medium such as Au, AuGeNiCr was also used for alleviating the
bonding requirement [14]. However, it is difficult to deposit a
flat metal layer on an epitaxy layer; moreover, metal used as the
bonding medium would absorb most incident long wavelength
light, which makes it impossible to be integrated with other optic
components vertically. Based on our patent technologies, in this
work, a novel bonding method using silicate gel as the bonding
medium was developed to fabricate InGaAs narrow-band response RCE photodetectors on a silicon substrate. The bonding
was performed at a low temperature of 350 C without any special treatment of bonding surfaces. Silicate gel was prepared by
the acid catalyzed hydrolysis of tetraethylorthosilicate [15], and
converted into glass after annealing, which was transparent for
long wavelength light. It makes it possible to integrate photodetectors with other optic components vertically.
II. EXPERIMENT AND RESULTS
The epitaxial structure of the RCE p-i-n photodiode was
designed using the transfer-matrix-method-based simulations.
A schematic diagram of the device is shown in Fig. 1. A
double-heterostructure epitaxy layer was grown on an (100)
InP substrate by metal-organic chemical vapor deposition
1041-1135/04$20.00 © 2004 IEEE
MAO et al.: FABRICATION OF 1.55- m Si-BASED RCE PHOTODETECTORS USING Sol-Gel BONDING
1931
Fig. 1. Schematic diagram of the InGaAs RCE photodetector.
Fig. 2.
with a 200-nm-thick absorption layer of In Ga As and
Ga
As P
910-nm total thick spacer layers of In
(
m), the upper and the lower spacer layer being 310
and 600 nm thick, respectively. The as-grown wafer, cut into a
typical size of 0.8 1 cm , was then coated with a 300-nm-thick
SiO layer grown by plasma-enhanced chemical vapor deposition (PECVD) at 340 C. A 3.5-period SiO –Si bottom DBR
with its calculated reflectivity of about 99% was deposited on
a silicon substrate by e-beam evaporation. Prebonding surface
cleaning, including solvent cleaning, deionized water rinsing,
and standard RCA1, was performed on both wafers. The wafers
were then blow-dried in N , and coated with silicate gel, after
which the wafers were immediately brought together. The
bonded InP–Si pair was annealed at 65 C for 9 h and then
at 350 C for 4 h in a low vacuum under uniaxial pressure
to increase the bonding strength. After annealing, the silicate
gel was converted into glass, which was proved to have little
absorption at the operation wavelengths by our experiments.
The thickness of the glass was about 1.6 m. After bonding, the
chemical
InP substrate was removed by HCl : H PO
etching solution with the epitaxy layer fully transfered onto the
silicon substrate. The bonding strength was strong enough to
endure the following processes, including ultrasonic cleaning.
Standard photolithography and chemical etching were used to
define the photodetector mesa. A 400-nm-thick SiO , deposited
by PECVD at 340 C, was used for passivating layer. Finally,
a 2.5-period SiO –Si top DBR with its calculated reflectivity
of about 80% was deposited on the top device by PECVD to
complete the RCE photodector structure.
The dark current of the RCE photodetector was measured
by an HP 4140B amperemeter. The dark current density is
16.7 A/cm at 5 V reverse bias.
Fig. 2 shows the experimental photocurrent spectral response
of the Si-based InGaAs RCE photodetector. A monochrometer
with 1-nm resolution was used to select the excitation wavelength from a chopped tungsten light source. The signal was
measured by a lock-in amplifier. The spectral response was
measured under zero reverse bias. The resonance wavelength is
about 1.54 m, with the quantum efficiency of 34.4%. From the
figure, a four-fold improvement on the quantum efficiency of
the RCE photodetector due to the resonant cavity enhancement
was observed. The responsivities of the photodetector under
various reverse biases were also measured by using a tunable
laser (Agilent 8163A) at room temperature with the optical
input power up to 4 mW, which was the maximum power that
Measured photocurrent response of the sample under zero reverse bias.
Fig. 3. Photocurrent of the photodetector versus optical input power under
various reverse biases.
could be obtained from the laser. Fig. 3 shows the photocurrent
response versus input optical power at the resonance wavelength of 1541 nm. The saturation current increases with the
reverse bias. Under 1.5 V or higher reverse bias, the photodetector has a linear photoresponse up to 4-mW optical power.
This saturation was mainly due to the electric field screening
caused by photogenerated carriers [16], [17]. In order to obtain
a higher saturation current, a lower bandgap offset, graded
heterojunction, or a novel structure such as velocity-matched
traveling-wave structure can be adopted.
Compared with the simulation result of about 20 nm, a
larger full-width at half-maximum (FWHM) of about 27 nm
may be caused by mirror undulation and unflatness of bonding
surfaces. The smaller refractive index of 2.7 of the silicon
grown by low temperature PECVD also contributes to FWHM
widened. Assuming an internal quantum efficiency of 100%,
the external quantum efficiency for the RCE photodetectors
can be expressed as shown in (1) at the top of the next page
are the power reflectivity of top and bottom
[7], where
mirrors, respectively, and is the total thickness of absorption
layers. is the cavity length from the top mirror to the bottom
are the phase shifts at the mirrors. Since the
mirror.
propagation constant
(where is the vacuum
is the effective refractive index) has a
wavelength and
wavelength dependence, is a periodic function of the inverse
of wavelength.
Due to their Fabry–Pérot cavity configurations, RCE photodectors have intrinsic wavelength selectivity, which may be
of the
useful in some WDM applications. The FWHM
1932
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 8, AUGUST 2004
(1)
According to this letter, the fabrication process of Si-based
InGaAs narrow-band response RCE photodetectors can be
performed more simply and easily to thereby contribute to
improved quality, cost-effective fabrication, and increased
yields of the semiconductor devices.
REFERENCES
Fig. 4. Simulated quantum efficiency of an optimized Si-based RCE InGaAs
photodetector.
spectral response, measuring the wavelength selectivity of photodetectors, can be expressed as [7]
(2)
where
is the effective cavity length.
In order to decrease the FWHM of photodetectors, the thickness of absorption layer should be reduced and the reflectivity
of mirrors must be increased. Fig. 4 shows the simulated the
quantum efficiency of the optimized RCE photodetector calculated by the transfer matrix method, in which the thickness of
absorption layer is decreased to 45 nm. The improved structure
of the RCE p-i-n photodetector is as follows: an active layer is
sandwiched by two mirrors, a top mirror of 2.5-period SiO –Si
and a bottom mirror of 5-period SiO –Si, and the active layer
As, a 930-nm-thick upper
comprises a 45-nm-thick In Ga
spacer layer and an 1085-nm-thick lower spacer layer. A narrower FWHM of about 4.5 nm can be obtained. In theoretical
calculation, an even narrower FWHM of about 0.8 nm can be
obtained, if the thickness of the InGaAs absorption layer is decreased to about 12 nm, with a 3.5-period top DBR being used.
Of course, the fabrication difficulty will increase.
III. CONCLUSION
This work has developed a novel method to fabricate
Si-based high quantum efficiency RCE photodetectors, employing bonding technology at a low temperature of 350 C
without any special treatment on bonding surfaces, and a
Si-based narrow-band response InGaAs photodetector was
successfully fabricated, with a quantum efficiency of 34.4%
at the resonance wavelength of 1.54 m, and an FWHM of
about 27 nm. Under 1.5 V or higher reverse bias, it has a
linear photoresponse up to 4-mW optical power. In theoretical
calculation, with the thickness of absorption layers decreased
to 45 nm, a narrower FWHM of about 4.5 nm can be obtained.
[1] M. S. Ünlü and S. Strite, “Resonant cavity enhanced photonic devices,”
J. Appl. Phys., vol. 78, pp. 607–639, 1995.
[2] M. S. Ünlü, G. Ulu, and M. Gökkavas, “Resonant cavity enhanced
photodetectors,” in Photodetectors and Fiber Optics, H. S. Nalwa,
Ed. NewYork: Academic, 2001, pp. 97–201.
[3] E. Özbay, Ï. Kimukin, N. Biyikli, O. Aytür, M. Gökkavas, G. Ulu, M. S.
Ünlü, R. P. Mirin, K. A. Bertness, and D. H. Christensen, “High-speed
>90% quantum-efficiency p-i-n photodiodes with a resonance wavelength adjustable in the 795–835 nm range,” Appl. Phys. Lett., vol. 74,
no. 8, pp. 1072–1074, 1999.
[4] D. S. Goluboviæ, P. S. Matavulj, and J. B. Radunoviæ, “Resonant cavityenhanced schottky photodiode-modeling and analysis,” Semicond. Sci.
Technol., vol. 15, pp. 950–956, 2000.
[5] D. M. Gvozdiæ, P. L. Nikoliæ, and J. B. Radunoviæ, “Optimization of a
resonant cavity enhanced MSM photodetector,” Semicond. Sci. Technol.,
vol. 15, pp. 630–637, 2000.
[6] M. Gökkavas, B. M. Onat, E. Özbay, E. P. Ata, J. Xu, E. Towe, and
M. S. Ünlü, “Design and optimization of high-speed resonant cavity enhanced schottky photodiodes,” IEEE J. Quantum Electron., vol. 35, pp.
208–214, Feb. 1999.
[7] K. Kishino, M. S. Ünlü, J. Chyi, J. Reed, L. Arsenault, and H. Morkoc,
“Resonant cavity-enhanced (RCE) photodetectors,” IEEE J. Quantum
Electron., vol. 27, pp. 2025–2034, Aug. 1991.
[8] M. K. Emsley, O. Dosunmu, and M. S. Ünlü, “High-speed resonant-cavity-enhanced silicon photodetectors on reflecting silicon-on-insulator substrates,” IEEE Photon. Technol. Lett., vol. 14, pp. 519–521,
Apr. 2002.
[9] A. G. Dentai, R. Kuchibhotla, and J. C. Campbell, “High quantum efficiency, long wavelength InP/InGaAs microcavity photodiode,” Electron.
Lett., vol. 27, no. 23, pp. 2125–2127, 1991.
[10] H. Huang, Y. Q. Huang, X. Y. Wang, Q. Wang, and X. M. Ren, “Long
wavelength resonant cavity photodetector based on InP/Air-gap Bragg
reflectors,” IEEE Photon. Technol. Lett., vol. 16, pp. 245–247, Jan. 2004.
[11] J. S. Harris Jr., “Tunable long-wavelength vertical-cavity lasers: The
engine of next generation optical networks,” IEEE J. Select. Topics
Quantum Electron., vol. 6, pp. 1145–1160, Nov./Dec. 2000.
[12] C. Li, Q. Q. Yang, H. J. Wang, J. Z. Yu, Q. M. Wang, Y. K. Li, J.
M. Zhou, H. Huang, and X. M. Ren, “Back-incident SiGe/Si multiple
quantum-well resonant-cavity-enhanced photodetectors for 1.3-m operation,” IEEE Photon. Technol. Lett., vol. 12, pp. 1373–1375, Oct. 2000.
[13] A. Salvador, F. Huang, B. Sverdlov, A. E. Botchkarev, and H. Morkoc,
“InP-InGaAs resonant cavity enhanced photodetector and light emitting
diode with external mirrors on Si,” Electron. Lett., vol. 30, no. 18, pp.
1527–1529, 1994.
[14] H. C. Lin, W. H. Wang, K. C. Hsieh, and K. Y. Cheng, “Fabrication of
1.55 m VCSELs on Si using metallic bonding,” Electron. Lett., vol. 38,
no. 11, pp. 516–517, 2002.
[15] C. J. Brinker, K. D. Keefer, D. W. Schaefer, and C. S. Ashley, “Sol-gel
transition in simple silicates,” J. Non-Cryst. Solids, vol. 48, pp. 47–64,
1982.
[16] L. Y. Lin, M. C. Wu, T. Itoh, T. A. Vang, R. E. Muller, D. L. Sivco, and
A. Y. Cho, “High-power high-speed photodetectors—Design, analysis,
and experimental demonstration,” IEEE Trans. Microwave Theory Tech.,
vol. 45, pp. 1320–1331, Aug. 1997.
[17] Y. L. Huang and C. K. Sun, “Nonlinear saturation behaviors of highspeed p-i-n photodetectors,” J. Lightwave Technol., vol. 18, pp. 203–212,
Feb. 2000.
RÖSEL et al.: ENHANCED TUNING EFFICIENCY IN TUNABLE LASER DIODES USING TYPE-II SUPERLATTICES
739
TABLE III
DETAILS OF THE TYPE-I CHEMICAL BEAM EPITAXY GROWN LAYER STRUCTURE
Fig. 3. Measured differential carrier lifetime and current density as a function
of the nominal current density for the type-II diode (squares) and type-I diode
(triangles). Lines are drawn as visual aid.
Fig. 2. Measured and fitted impedance of the type-II diode at I = 1 mA.
Lines are experimental data and points represent a fit using Z (!) according to
(2). The inset shows the equivalent circuit.
III. RESULTS
To investigate the recombination properties, differential carrier lifetimes were derived from impedance measurements in
combination with a small-signal equivalent circuit modeling. To
carry out the impedance measurements, p-i-n diodes with diameters ranging from 15 to 80 m were fabricated. Thereby, mesas
were wet-chemical etched through the entire epitaxial layer sequence preventing an out-diffusion of the carriers. After passivation of the diodes with an advanced electronic resin ensuring
a low contact capacitance of below 150 fF, the diodes exhibit
low series resistances analyzed by dc voltage–current measurements.
The impedance of the type-II diodes was measured in a frequency range between 100 kHz and 1 GHz using a 50- analyzer. Fig. 2 represents a typical measurement of the impedance
of the type-II diode at 1 mA of bias current and with a device diameter of 80 m. To extract the differential carrier lifetime, the
small-signal equivalent circuit of a p-i-n diode was used, which
and capaciconsists of a parallel combination of resistance
tance
. In addition, a parallel combination of resistance
and capacitance
were included in series because of a heterobarrier resistance between the intrinsic AlGaAsSb layer and
the p-doped AlInAs cladding layer. The impedance of the circuit can be written as
Fig. 4. Simulation of the refractive index change induced by the electrons via
the free-carrier plasma effect as a function of the nominal current density for the
type-II diode and type-I diode.
(2)
(4)
where
is the characteristic time equal to the differential carrier lifetime [6]. Since our device consists of only
one quantum well for the electrons and holes, transport dynamics have not to be taken into account. In Fig. 2, the modeled
ns,
impedance of the type-II diode is shown and yields
, and
,
pF at 1 mA of bias
current and with a diode diameter of 80 m.
Fig. 3 shows the differential carrier lifetime and the carrier
density of the type-II and type-I diode as a function of the nom-
whereby is the photon emission wavelength,
is the refracis the effective electron mass. The refractive
tive index, and
index values at 1.55- m wavelength and the important effective
masses are given in Table II. The effective masses of AlGaInAs
and AlGaAsSb were evaluated by linear interpolation between
the parameters of AlInAs–GaInAs and AlAsSb–GaAsSb, respectively.
In Fig. 4, the refractive index change is calculated for the
type-II and type-I diode. It is clearly seen that type-II super-
inal current density. Integrating the differential carrier lifetime
over the bias current the carrier density is obtained by
(3)
For low current densities, the carrier lifetime of the type-II
diode is over a magnitude larger compared to the type-I diode.
As a result of the larger lifetime, the carrier density in the type-II
diode shows an enhanced increase as a function of the current.
Finally, the type-II diode yields an enhanced carrier density by
more than a factor of two in the high current regime. Regarding
the lifetime at high currents, it is obvious that the lifetime of
the type-II diode decreases stronger with increasing current as
a consequence of the higher carrier density.
IV. SIMULATION
The following calculation is based on the refractive index
via the free-carrier plasma effect [8]. In this case,
change
the electrons mainly show a large contribution by
740
IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 16, NO. 3, MARCH 2004
lattices can offer the same index change as a type-I structure at
a reduced current consumption of almost a factor of ten. Beside
the improved carrier density-current function, the enhanced carrier lifetime leads to a reduction of the internal achievable tuning
speed. However, for the case of a voltage-controlled injection,
the time response of a tuning region depends no longer on the
carrier lifetime, but on the value of the series resistance of the
external bias network [1].
For comparison of the effective index change and, thus, the
tuning range, the confinement factor of the two structures has
to be taken into account. Assuming a waveguide formed by a
),
300-nm-thick tuning layer and two cladding layers (
the type-I structure yields a confinement factor of around 54%,
whereas, due to the smaller refractive index, the confinement
factor of the type-II superlattices is not as high, but still around
47%. Therefore, an improvement of the tuning range by nearly
a factor of two can be expected at a given current. The thickness
of the type-II diode can be variably chosen by the number of
periods of type-II quantum wells.
V. CONCLUSION
A type-II diode consisting of AlGaAsSb–AlGaInAs latticematched to InP has been developed which is ideally suited for
the use as a tuning region in tunable laser diodes. Since the recombination in type-II heterostructure can be reduced by more
than one order of magnitude due to the spatial separation of electrons and holes, the tuning efficiency as well as the tuning range
can significantly be improved. Furthermore, heating of the laser
is effectively suppressed so the deteroriation of the laser performance (output power reduction, red shift) during tuning can
be avoided. Experimentally, we found that the carrier density
in the AlGaAsSb–AlGaInAs type-II superlattice has been en-
hanced by a factor of two as compared to the commonly used
type-I heterostructure tuning diodes.
ACKNOWLEDGMENT
The authors would like to thank G. Böhm, C. Lin, R. Todt,
J. Grottenthaler, and L. Mora for their assistance.
REFERENCES
[1] M.-C. Amann and J. Buus, Tunable Laser Diodes. Norwood, MA:
Artech House, 1998, pp. 1–5 and 94–95.
[2] J.-P. Weber, “Optimization of the carrier-induced effective index change
in InGaAsP waveguides-application to tunable bragg filters,” IEEE J.
Quantum Electron., vol. 30, pp. 1801–1815, Aug. 1994.
[3] M.-C. Amann and S. Illek, “Tunable laser diodes utilizing transverse
tuning scheme,” J. Lightwave Technol., vol. 11, pp. 1168–1182, July
1992.
[4] S. Neber and M.-C. Amann, “Tunable laser diodes with type II superlattices in the tuning region,” Semicond. Sci. Technol., vol. 13, pp. 801–805,
Mar. 1998.
[5] J. B. Khurgin, I. Vurgraftman, J. R. Meyer, S. Xu, and J. U. Kang,
“Reduced crosstalk semiconductor optical amplifiers based on type-II
quantum wells,” IEEE Photon. Technol. Lett., vol. 14, pp. 278–280, Mar.
2002.
[6] G. E. Shtengel, D. A. Ackerman, P. A. Morton, E. J. Flynn, and M.
S. Hybertsen, “Impedance-corrected carrier lifetime measurements in
semiconductor lasers,” Appl. Phys. Lett., vol. 67, no. 11, pp. 1506–1508,
Sept. 1995.
[7] G. Rösel, F. Köhler, R. Meyer, and M.-C. Amann, “Optimization of
type-II heterostructures for the tuning region in tunable laser diodes,”
Semicond. Sci. Technol., vol. 18, pp. 325–329, Feb. 2003.
[8] B. R. Bennett, R. A. Soref, and J. A. Del Alamo, “Carrier-induced
change in refractive index of InP, GaAs, and InGaAsP,” IEEE J.
Quantum Electron., vol. 26, pp. 113–122, Jan. 1990.
[9] S. Nojima and H. Asahi, “Refractive index of InGaAs/InAlAs multiquantum-well layers grown by molecular-beam epitaxy,” J. Appl. Phys.,
vol. 63, no. 2, pp. 479–483, Jan. 1988.
[10] M. Guden and J. Piprek, “Material parameters of quaternary III-V semiconductors for multilayer mirrors at 1.55 m wavelength,” Modeling
Simul. Mater. Sci. Eng., vol. 4, pp. 349–357, 1996.
[11] I. Vurgraftman and J. R. Meyer, “Band parameters for III-V compound
semiconductors and their alloys,” J. Appl. Phys., vol. 89, no. 11, pp.
5815–5875, June 2001.