test and inspection
Successful ICT Boundary Scan Implementation
Eight steps to getting the best possible test coverage.
IEEE 1149.1 for boundary scan adoption has seen a
extra system and manpower costs, not to mention
an additional process.
There are other minor reasons, such as local support, especially for the majority of high-volume manufacturing sites in Asia. Availability of expert support
from the benchtop boundary scan vendors in Asia
has not come far compared with that offered by ICT
vendors. This is understandable, since ICT has been
around for more than 30 years in electronics manufacturing, fostering a more robust support model.
These are just a few reasons why most assemblers
prefer ICT for boundary scan test for volume products. Besides, ICT offers coverage for most of the PCB
defect spectrum (opens, shorts), analog components
value measurements, as well as powered test, which
includes voltage measurements, clock measurements,
digital test and in-system programming capabilities.
Table 1 compares boundary scan test coverage of a
typical benchtop boundary scan setup with an ICT
offering boundary native scan capabilities.
Although native boundary scan on ICT is the preferred solution during volume manufacturing testing,
avoidable implementation issues can affect stability
of the test.
Boundary scan tests, like any other digital test
during ICT testing, are susceptible to noise, which
affects stability. As such, the following best practices
should be considered:
1. Assign critical attributes to JTAG pins (TDO,
TDI, TMS, TCK and TRST) to ensure the shortest wire possible (Figure 1). To ensure signal
quality and fidelity, consider assigning critical
attributes to the JTAG pins during test development to ensure the fixture
has the shortest wire possible
Table 1. PC Boundary Scan and ICT Boundary Scan Feature Comparison
(as short as 1") from the ICT
Boundary Scan TestBenchtop Boundary Scan
ICT
system’s digital card pins to
IC code
Yes
Yes
the test probe. The shorter
the wire on those JTAG pins,
Infrastructure
Yes
Yes
the less the possibility of an
Interconnect (1149.1/1149.6)
Yes
Yes
adjacent wire crosstalk.
steady climb in use for the past five years. In particular, it has gained popularity with NPI test engineers
working with high node count printed circuit boards
for telecom network servers/switches and PC servers.
There are several ways to implement boundary scan
test on PCBs, the two most common being:
■■ Native boundary scan on in-circuit test
systems. (Note: Native boundary on ICT is an
integrated solution where the boundary scan test
will be developed and executed within the same
ICT interface. No additional third-party hardware
or software is needed.)
■■ Standalone benchtop boundary scan. Standalone benchtop boundary scan is preferred during
prototype/NPI, as it enables PCB testing without
building an ICT fixture. However, it has not been
adopted for high-volume manufacturing, where
the majority of manufacturers use the native
boundary scan on ICT. Here’s why:
■■ Cost. A basic benchtop boundary scan setup is
about $10,000 to $20,000. Additional licenses
for development, debug and runtime features will
increase the cost of the benchtop boundary scan
solution up to two to three times the basic cost.
Compared to the cost of using native boundary
scan on ICT solution, the latter is practically free,
as most EMS providers and ODMs would already
have boundary scan licenses enabled on their existing ICT systems, which include development and
debug features.
■■ Separate station. Running an extra station after
ICT doesn’t appeal to most assemblers, as it means
Jun Balangue is
technical marketing
engineer at Agilent
Buswire
Yes
Yes
Technologies
1149. shorted capacitor
No
Yes
(agilent.com);
Powered short
No
Yes*
Connect test No
Yes *
DDR (memory test)
Yes
Yes (Silicon Nail)
Cluster test (non-BScan digital test)
Yes
Yes (Silicon Nail)
NOR flash, flash SPI, I2C programming
Yes
Yes +
CPLD programming
Yes
Yes
Powered vectorless test (Cover Extend) No
Yes
jun_balangue@
agilent.com.
*Using ICT digital resources +Direct Flash programming or using 3rd party programming solution
50
PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY
Figure 1. Short wire ICT
fixture.
september 2010
test and inspection
2. Proper
fixture ground plane implementation. The main
objective of using a ground plane on the ICT fixture is to
reduce ground loop created by the distance between the ICT
system ground and the PCB ground via fixture wiring. Unfortunately, few understand proper ground plane implementation, which can make or break the ICT digital or boundary
scan test (Figure 2). The objective of having a proper ground
plane is to help ensure the PCB ground is as short as possible
to the ICT system’s digital ground during digital test, to minimize ground loop, as well as ensure that the signal wire stays
closer to the ground to minimize crosstalk. Figure 3 is an
example of a badly implemented ICT fixture ground plane,
which is worse than not having a ground plane.
3. Twisted-pair wiring on JTAG pins (TDO, TDI, TMS, TCK
and TRST). Aside from short wiring, another strategy to
ensure signal integrity and minimizing noise is implementing twisted-pair wiring on JTAG pins. Twisted-pair impedance of approximately 100 Ω matches the low output
impedance of the digital driver of the ICT system, which
will result in a better drive signal integrity.
4. Removing physical test probes. For nodes that have only
boundary scan devices connected to them (100% boundary
scan nodes), removing these probes could ensure the signal
integrity on those nodes stays clean. However, use a conservative approach in removing test probes on boundary scan
nodes, as it will mean losing test coverage if there are nonboundary scan devices or analog components connected to it.
5. Dual-stage fixture. Most of the designs of high node count
assemblies have resorted to a dual-stage fixturing solution
where during the first stage, all the test probes are in contact while executing unpowered and powered in ICT (Figure 4). At the second stage, executed after all first stage
tests have been passed, the fixture probe plate will move up
either mechanically or via a pneumatic cylinder to disengage most of the normal test probes, with only a few long
travel test probes remaining in contact. The test probes in
contact during this second stage are power, ground, JTAG
pins (TDI, TDO, TCK, TMS and TRST), as well as compliance and disabling pins (Figure 5). With the dual-stage
fixture strategy, most noise coupled through the fixture
wires is eliminated, resulting in a stable boundary scan test.
6. Power cycling or reset sequence. Adding a power
cycling or reset sequence procedure to the test plan ensures
the boundary scan devices in chains are in the proper state
Figure 2. Ground plane
implementation on an ICT
fixture. Ground plane wire
should be as short as possible and avoid going through
above the signal wires.
september 2010
Figure 3. Wrong ground
plane implementation on
ICT fixture. The black wire
represents long ground wire,
which in this case is on top of
all the blue signal wires that
create a ground loop.
for testing. During boundary scan, the core logic of the
devices in the chain is disconnected from the rest of the
board, which probably would affect other devices operating in normal mode. Other devices exchanging data with
boundary scan devices will consider the devices inoperable.
Note that when the board comes out of boundary scan
mode, all the boundary scan devices go into BYPASS, and
the core logic is reconnected to the I/O pins, but the board
and the boundary scan devices do not necessarily pick up
where they left off. To get the board back to normal operating mode, the board reset procedure must be run, or board
power must be cycled. This can be done by adding a reset
sequence or power cycling procedure to the test plan.
For multiple chains, interactions between chains can be a
problem. For problems with connect tests or disabling difficulties, try adding a power cycling or reset sequence to the test.
7. Disabling upstream device, oscillator, switching voltage regulator. When a digital or boundary scan device
is being tested, its surrounding devices can affect the way
the device operates. This, in turn, can affect the test for
that device, resulting in an unstable boundary scan test.
To some extent, the effect that other devices have on the
inputs to the device under test is minimized in the test system by overdriving. However, this is not always completely
effective and cannot be used with high-speed signals. Disabling the upstream devices ensures that there is no other
signal interference while executing boundary scan test.
Disabling on-board oscillator and switching voltage regulators ensure that noise coupled through fixture wiring is
minimized, which will result in a stable boundary scan test.
8. Maintaining JTAG pins signal during boundary scan
test and disable state. Most PCBA with good boundary
scan design for test implementation will take care of the pullup/down resistor of the JTAG pins to ensure stability of the
boundary scan test. If these DfT factors have not been included on the board, implementing them on the fixture will help.
The TCK (test clock) should be treated like any clock pin,
although it has nothing to do with the on-board clock function. The TCK should be terminated with a 68 Ω resistor in
series with a 100 pF capacitor to ground.
Maintaining stable TMS (test mode select) signals, either
during boundary scan test or the disable state, is very important. During boundary scan test, the test generated by ICT will
ensure that TMS will maintain its level according to the state
diagram. However, during boundary scan test, disabled TMS
should maintain a signal level to remain in the reset state. A
pull-up resistor will help to ensure that TMS remains high.
(continued on p. 60)
Figure 4. First stage – fixture
during ICT.
Figure 5. Second stage –
fixture during boundary scan
test.
PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY
51
Ad Index
To learn about the advertisers in this issue, go to pcdandf.com or circuitsassembly.com and select “Current Issue” to access the digital edition. This will provide
you with direct links to the websites of each advertiser in this index.
Company
Page No.
Bare Board Group, www.bareboard.com. . . . . . . . . . . . . . . . . . 60, 63
Koh Young, www.kohyoung.com. . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BEST Inc., www.solder.net. . . . . . . . . . . . . . . . . . . . . . . . . . . . insert
Leica Microsystems, www.leica-microsystems.com/bigpicture . . . 53
Sierra Circuits, www.protoexpress.com/betterDFM. . . . . . . . . . insert
Cookson Electronics, www.alphasolderpaste.com. . . . . . . . . . . . . 31
Mentor, www.mentor.com/go/pads-eval. . . . . . . . . . . . . . . . . Cover 4
Sierra Circuits, www.protoexpress.com/webpcb. . . . . . . . . . . . insert
CST, www.cst.com/emc; www.cst.com/emc. . . . . . . . . . . . . . . . . . 19
Miller-Stephenson Chemical, www.miller-stephenson.com . . . . . . 63
SMTA International, www.smta.org/smtai . . . . . . . . . . . . . . . . . . . 40
Custom Design Services. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MIRTEC, www.mirtecusa.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Speedline, www.speedlinetech.com/mpm . . . . . . . . . . . . . . . . . . . 29
DEK, www.dek.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
National Instruments, www.ni.com/multisim. . . . . . . . . . . . . . . . . . 4
Streamline Circuits, www.streamlinecircuits.com. . . . . . . . . . . . . 25
Design 2 Part, www.cst.com/pcb; www.cst.com/emc. . . . . . . . . . . 43
Numerical Innovations, www.numericalinnovations.com. . . . . . . . 61
Superior Processing, www.superior-processing.com . . . . . . . . . . . 61
Digi-Key Corp., www.digikey.com. . . . . . . . . . . . . . . . . . . . . . Cover 2
Online Electronics, www.pcb4less.com . . . . . . . . . . . . . . . . . . . . . 62
Valor Computerized Systems, www.valor.com. . . . . . . . . . . . . . . . 33
Dow Electric Materials, www.dow.com. . . . . . . . . . . . . . . . . . . . . . 13
Overnite Protos, www.pcborder.com. . . . . . . . . . . . . . . . . . . . . . . . 62
Virtual PCB, www.virtualpcb.com. . . . . . . . . . . . . . . . . . . . . . . . . . 34
DownStream Technologies, www.pcbshows.com/webinars. . . . . . . . 5
PCB Fab Express, www.pcbfabexpress.com. . . . . . . . . . . . . . . . . . 61
DownStream Technologies, www.downstreamtech.com. .Cover 3, 15
PCB West, www.pcbwest.com. . . . . . . . . . . . . . . . . . . . insert, 48, 49
eFabPCB, www.efabpcb.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PICA, www.picasales.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EMS Directory, www.circuitsassembly.com/dems. . . . . . . . . . . . . . 63
ResinLab, www.resinlab.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Eremex, www.eremex.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rogers, www.rogerscorp.com/acm. . . . . . . . . . . . . . . . . . . . . . . . . 11
Europlacer, www.europlacer.com. . . . . . . . . . . . . . . . . . . . . . . . . . 37
Production Solutions, www.production-solutions.com. . . . . . . . . . 57
EzPCB, www.ezpcb.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Rogers, www.rogerscorp.com/acm. . . . . . . . . . . . . . . . . . . . . . . . . 29
Fine Circuits, www.finecircuits.com. . . . . . . . . . . . . . . . . . . . . . . . 62
Samtec, www.samtec.com/edgerate . . . . . . . . . . . . . . . . . . . . . . . . 7
Imagineering Inc., www.PCBnet.com. . . . . . . . . . . . . . . . . . . . . 1, 61
Seika Machinery, www.seikausa.com. . . . . . . . . . . . . . . . . . . . 30, 39
Test and Inspection, continued from p. 51
TRST pins, boundary scan will enter
the TEST-LOGIC-RESET mode when
TMS is held high for at least five rising
edges of TCK. The TRST signal should
include a pull-down resistor when possible to reduce the chance the signal
floats when it is not being driven by
the ICT driver.
The success of boundary scan test
implementation on ICT lies not only with
the tools used, but also the project team’s
support of the strategy from design
and test engineering up to production.
With a new set of boundary scan-related
IEEE standards (P1687, P1581, 1149.7,
1149.8.1) expected soon, boundary scan
will get a further boost in the board
testing environment. CA
TRST (test rest) is an optional
JTAG pin designed to let the boundary
scan test get into the TEST-LOGICRESET mode regardless of the state
of TMS or TCK. Whenever TRST gets
asserted alternatively in the absence of
Bibliography
1.
2.
3.
60
PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY
IEEE, 1149.1-2001, “Standard Test
Access Port and Boundary-Scan Architecture.” June 2001.
SMTA, SMTA/TMAG Testability
Guidelines TP-101D, 2008.
Kenneth P. Parker, Boundary Scan
Handbook, 3d edition, 2003.
SEA Awards, http://www.circuitsassembly.com/cms/sea-award. .47
The advertising index is published as an additional service. The publisher
does not assume any liability for errors or omissions.
Advertising Sales
North America/Europe/Asia (except Korea):
UP Media Group, Inc.
PO Box 470, Canton, GA 30169
Circuits Assembly Sales Manager:
Krista Fabian, 302-519-4064, kfabian@upmediagroup.com
Printed Circuit Design & Fab Sales Manager:
Frances Stewart, 678-817-1286, fstewart@upmediagroup.com
Korea Sales: Young Media, 82 2 756 4819, ymedia@ymedia.co.kr
Selective Soldering, continued from p. 45
Have uniform control of the “freeboard” of solder above the nozzles.
However, selective soldering nozzles,
particularly smaller-diameter nozzles,
are notorious for gradually losing the
height of the solder freeboard over time
due to the buildup of contamination
inside the nozzle. Real-time measurement of the solder height that will automatically adjust pump speed in order
to maintain a pre-set desired height is
valuable here. That’s a critical part of
the process. If solder height diminishes
and you aren’t aware of it, soon you’re
not soldering at all, or at least not getting the desired quality.
Selection, shape, design and function
of selective soldering nozzles are a
critical focal point of successful soldering. Know your nozzles! Understand
their features, how they affect and
control the solder wave, and what their
vulnerabilities may be to the specific
alloy used. CA
september 2010
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