CE- Amplifier
Experiment -415
S
CE AMPLIFIER
Jeethendra Kumar P K
KamalJeeth Instrumentation & Service Unit, No-610, Tata Nagar, Bengaluru-560092,INDIA
Email: labexperiments@kamaljeeth.net
Abstract
Using a BC107 silicon transistor, frequency response of a common emitter (CE)
amplifier is studied in the frequency range 100Hz-3MHz and gain-bandwidth
product, mid-band gain, input and output impedances are determined and
compared with the corresponding theoretical values.
Introduction
Design and construction of CE amplifier is one of the classic experiments in physics.
Single transistor voltage amplification from milli-volt to volt level was employed in the
early transistor radio circuits, which are now replaced by integrated circuits. Hence
these circuits are the fundamental building blocks of integrated circuits. CE amplifier
provides a fundamental circuit design exercise in physics.
CE amplifier design
+12V
R1, 75K
RC, 3K
VC
Co,1µF
Cin, 1µF
VB
VE
Vo
Vin
R2,
33K
RE, 3K
CE,
10µF
Figure-1: CE amplifier circuit
To start with the design of a transistor amplifier circuit involves selection of an
appropriate transistor and noting down its h-parameters from the data manual. The
manufacturer typically provides the minimum and maximum values of the hparameters for a certain value of the collector current. The h-parameters of the BC107
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CE- Amplifier
transistor are tabulated in Table-1, taken from the previous experiment in this issue of
LE. Generally the transistors are graded by the manufacturer depending on their DC
gain, βdc (hFE). We have used a BC107B transistor for which the parameters are listed in
Table-1.
Figure-1 shows a CE amplifier circuit with voltage divider bias. The CE amplifier
design starts with fixing a Q-point (setting VCE, IC) at the middle of the dc load line.
Once we choose the Q-point the voltage gain is determined. A small ac signal is coupled
to the input using a coupling capacitor. The ac input signal produce fluctuations in the
quiescent current and the Q-point move up-down on the dc load line as shown in
Figure-2 producing fluctuations or amplifications in the collector current. Hence a small
change in the base current (∆IB = ib) is capable of producing large change in the collector
current (∆IC = iC), hence producing amplification. The Q-point will move to position A
during positive half cycle of the input sine wave and move to position C during the
negative half of input sine wave, thus producing sinusoidal fluctuations in the collector
current.
Table-1: h-parameters and DC current gain of a BC107B transistor
Parameters
BC107B
β dc (hFE)
110*
hfe
125
hie (KΩ)
7.5
*These are the minimum values measured at 2mA, VCE=5V
I
C sat
A
IB=30uA
I
C
Q
IB=20uA
C
V
CE
IB=10uA
V
CC
Figure-2: DC load line and Q-point
Coupling capacitor
Ac signals are generally coupled through a coupling capacitor in discrete form of
amplifier circuits. However, in the integrated form, capacitor above 100pF is difficult to
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CE- Amplifier
fabricate hence direct coupling is preferred. The size of the coupling capacitor will
depend on the lowest frequency of amplifier operation. A firm coupling is the one
whose reactance at the lowest frequency of operation is 1/10 of total series resistance.
This 1:10 ratio is followed in coupling ac signal to the CE amplifier.
A coupling capacitor is always associated with a resistance. The input impedance (Zin)
of the CE amplifier in Figure-1 is in series with the input coupling capacitor CC. The
input impedance is combination of resistances RB= R1//R2 and h ie of the transistor used
in the circuit. The value RB large (at least 10 times) in compared to h ie, hence hie is the
resistance in series with input coupling capacitor. Hence input coupling capacitor is
selected such that its impedance
XCC ≤ 0.1hie
For the BC107B transistor used in this experiment
XCC ≤ 0.1x7.5K =750Ω
ଵ
750 = ଶ̟୤େ
ౙ
At lowest frequency of operation, say 100Hz CC is
CC = 2.12µF
A 1µF capacitor is used as input coupling capacitor.
Similarly the output coupling capacitor is decided by the series resistance R C =3K
XCC ≤ 0.1x3K =300Ω
This gives 0.5µF at 100Hz. We have selected 1µF.
By-pass capacitor
Capacitor CE connected in parallel to RE is used to filter or by-pass the ac signal from
the emitter there by keeping emitter at ac ground. This capacitance is in series with hie
of the transistor as shown in the input circuit in Figure-3. The three larger resistances
(RB, h ie and RE) can be neglected in comparison with Rs, the resistance of ac source or
the function generator. Hence the smallest time constant in the input circuit is CERs,
which will decide the lower cut-off frequency of the CE-amplifier.
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CE- Amplifier
Rs
50
7.5K
hie
3K
RE
RB
22.9K
10uF
CE
Figure-3: Input equivalent circuit of the CE amplifier
The value CE can be selected using same 1:10 thumb rule as
XCE =
ଵ
ଶ̟୤ୖు
≤ 0.1RE =300Ω
This gives CE = 5.3µF we have used 10µF. With selection the lower cut-off frequency
becomes
fL =
ଵ
ଶ̟୶ହ଴୶ଵ଴୶ଵ଴షల
= 318Hz
Firm voltage divider bias
A CE amplifier circuit shown in Figure-1 is biased (energized) with firm voltage divider
bias circuit [1]. Figure-4 shows the equivalent circuit for the voltage divider bias.
R
R
TH
I
VT H
C
Vcc
V BE
B
I
R
E
E
Figure-4: Equivalent circuit of firm voltage divider
Applying Kirchhoff’s voltage law to the input loop we can write
VTH = IBRTH+VBE+IER E
Substituting for IB =IE/βdc , the emitter current
IE = ୖ
୚౐ౄ ି୚ాు
ుାୖ౐ౄ /β ౚౙ
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CE- Amplifier
A firm voltage divider is the one that satisfy the condition
RTH ≤ 0.1βdc RE
This 10:1 ratio must be satisfied for the minimum value of βdc. The manufacture will
provide the minimum and maximum value in data sheet. For the transistor BC107B
βdcmin is 110.
The value of R2 is always smaller than R1 hence the smaller value should be selected
such that
R2 ≤ 0.1βdcmin RE = 0.1x3Kx110= 33KΩ
We have taken R2 as 33K and hence R1 is calculated using voltage divider formula
V୆ =
R1=
Rଶ
V
R ଶ + Rଵ େେ
ୖమ ሺ୚ిిష ୚ా ሻ
୚ా
=
ଷଷ୏ሺଵଶିଷ.଺ሻ
ଷ.଺
=77K
We have selected R 1=75KΩ
Setting the Q-point
The Q-point is set at the center of dc load line by selecting VCE = 0.5VCC. This selection
ensures a rock-solid Q-point. Taking VCC =12V, VCE = 6V, which appears across the
collector emitter terminal of the transistor. The remaining 6 volts is dropped equally
across the collector resistance RC and Emitter resistance RE. Since CE amplifier is voltage
amplifier we shall take IC =1mA as small Quiescent current. Hence
IE =1mA, Voltage across RE =3V
୚ు
୍ు
= R ୉ = 3KΩ
Since equal voltage dropped across RE, and IC≈ IE
୚ి
୍ి
= R େ = 3KΩ
The voltage gain is fixed when choose the collector current and collector resistor R C
AV =
ୖి
୰′౛
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CE- Amplifier
Where RC is the collector resistor and ‫ݎ‬௘′ is ac emitter resistance. The value of which
depend on the quiescent current
rୣ′ =
ଶହ
୍ి
Ohms
Where IC is quiescent current in milli-amphere
Once we decide the Q-point the gain is fixed
In our design IC =1mA hence
rୣ′ =
AV =
ଶହ
ଵ
= 25 Ohms
ଷ଴଴଴
ଶହ
= 120
Band width of CE Amplifier
As frequency is varied, the reactive impedance of various capacitors rolls of the voltage
gain. The coupling capacitors (Cin, Co) are effective in the low frequency region and the
shunt capacitor (CE and inter junction capacitance of the transistor) are active in the
high frequency region. The three capacitance in the CE amplifier circuit, that provide
three cut off frequencies namely fin, fout and fE.
The cut off frequency fin, is the result of input impedance of the function generator (RS)
along with CE rolls of the gain at lower frequencies. Out of the two time constants in the
CE amplifier circuit namely, RSCE, hie CE, whichever is smaller will be considered as the
lower cut-off frequency.
The upper cut-off frequency (f2) will depend entirely on the inter-junction capacitance
of the transistor. Hence band width
BW = f2-f1
Where
f1 is lower cut off frequency and
f2 is upper cut of frequency
Gain bandwidth product GBW is given by
GBW = Av (f2-f1)
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CE- Amplifier
This product is constant for given transistor amplifier.
Apparatus used
Transistor amplifier Expt set-up model TRA-201, KamalJeeth make consisting of 12 Volt
power supply, wide band ac volt meter (0-2V, 200 KHz), Function generator 3MHz,
Digital storage oscilloscope (DSO). The complete experimental set-up is shown in
Figure-5.
Figure-5: Hybrid parameter experimental set-up
Experimental procedure
Experiment consists of three parts
Part-1: Construction of CE amplifier and Verification Q-point
Part-2: Frequency response
Part-3: Determination of input and output resistances
Part-1: Construction of CE amplifier and Verification Q-point
1. The CE amplifier circuit is rigged using BC107B transistor as shown in Figure-1
and supply voltage (12V) is connected circuit. Using a multi meter (20V range)
the voltages at the three terminals of the transistor is measured.
VB = 3.02V, VC = 9.01V, VE = 3.59V
ଵ
These voltages are as per our design and VCE = 5.99V= ( Vୡୡ) ensures that the Qଶ
point is at the center of dc load line. The quiescent current ICQ
The emitter current IE is calculated
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CE- Amplifier
ICQ = IE =
௏ಶ
ோಶ
ଷ.଴ଶ
=
ଷ௄
=1mA
Hence Q-point (VCE, IC) = (5.99V, 1mA)
Ac emitter resistance rୣ′ =25/IC =25/1 =25 Ω
Ac voltage gain of the amplifier is
AV = RC/rୣ′ = 3000/25 =120
The input resistance of the function generator measured using a multi-meter
with function generator switched off
RS =50 Ω
The input resistance (h ie) of the CE amplifier is much greater than 50Ω. Hence the
lower cut-off frequency is given by
ଵ
fL = f1 = ଶ̟େ
ు ୖ౏
ଵ
= ଶగ௫ହ଴௫ଵ଴షల = 318Hz
Part-2: Frequency response
2. The function generator is connected to input of CE amplifier and sine input is
selected and its frequency is set to 100Hz and amplitude is set to 50mV (this is
the minimum input from the function generator) and output is noted and gain is
calculated and presented in Table-2.
At 100Hz, Vin = 50mV, VO = 1.1V
Voltage gain =
௏ೀ
௏೔೙
=
ଵଵ଴଴
ହ଴
= 22
3. Trial is repeated by varying frequency in suitable steps up to maximum of
3MHz. At each frequency, the input and output is noted from the CRO and gain
is calculated and presented in Table-2.
4. A graph is drawn taking frequency on log on X-axis and gain on Y-axis as shown
in Figure-6. From the frequency response curve, mid band gain AM (100) and
lower and upper cut-off frequencies at gain (0.707x AM) are noted.
Table-2: Gain at different frequencies
Frequency
Output (V)
Gain
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CE- Amplifier
(KHz)
CRO
WBM
CRO
WBM
0.1
1.1
0.33
22
18
0.2
2.0
0.65
40
37
0.4
3.4
1.09
68
61
0.6
4.0
1.37
80
78
0.8
4.4
1.54
88
87
1
4.8
1.63
96
92
2
5.0
1.80
100
102
3
5.0
1.84
100
104
4
5.0
1.86
100
105
10
5.0
1.86
100
105
20
5.0
1.86
100
105
30
5.0
1.86
100
105
40
5.0
1.86
100
105
50
5.0
1.86
100
105
60
5.0
1.86
100
105
70
4.9
1.86
98
105
100
4.8
1.81
96
102
200
4.3
1.50
86
85
300
3.7
1.13
74
64
400
2.8
56
500
2.4
48
600
2.1
42
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CE- Amplifier
800
1.6
32
1000
1.3
26
1500
1.0
20
2000
0.8
16
2500
0.6
12
3000
0.5
10
50mV PP input with CRO, 17.6mV with WBM
f1 = fL = 400 Hz = 0.4 KHz
f2 = 300 KHz
BW = 300 KHz-0.4 KHz ≈ 300 KHz
GBW =100x300K =30MHz
Voltage gain
CRO
0.1
Wide band meter
120
110
100
90
80
70
60
50
40
30
20
10
0
1
10
100
1000
10000
Frequrncy (KHz)
Figure-6: Frequency variation
5. The experiment is repeated using the wideband meters provided in the set-up.
The readings obtained are tabulated in Table-2. And Figure-6 shows the
frequency response. Both CRO and the wide band meters almost same readings.
However after 300 KHz the wide band meter does not show reading.
Part-3: Determination of input and output resistances
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CE- Amplifier
6. To measure the input impedance of the CE amplifier a decade resistor box is
connected in series with the function generator as shown in Figure-7.
Cc
Cc
DRB
CE-amplifier
Output to
wide band
meter
Figure-7: Circuit connection to determine input resistance
7. The resistance in the DRB is set 0Ω, and frequency is set to 10 KHz (Mid band).
The output is noted
Vo =1.88V
The resistance in the DRB is slowly increased until the output is reduced to half
(0.94V). The resistance in box is noted. This is input impedance of the CE
amplifier
Zin = 7.5KΩ
This value tally with the h ie (7.5KΩ) of the BC107B transistor used.
8. To determine output impedance, the resistance box is first adjusted to maximum
value, before shunting to the CE amplifier circuit as shown in Figure-8.The
output is monitored on CRO
9. With f=10KHz, input 50mV output is noted
V0 =1.88V
The resistance in the box is decreased until the output becomes half (0.94V). The
resistance in the box is noted. This is the output impedance of the CE amplifier
Zout =3KΩ =RC
This exactly equal to RC, which the theatrical value of output impedance.
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CE- Amplifier
Cc
DRB
Cc
CE-amplifier
Output to
wide band
meter
Figure-8: Circuit connections to determine output resistance
Results
The results obtained are summarized in Table-3.
Table-3: Experimental results
Parameters
Experimental
105
Voltage gain
Theoretical
120
Lower cut-off
frequency
318Hz
400Hz
Upper cutoff
frequency
-
300KHz
GBW
30MHz
References
[1]
A P Malvino, Electronic Principles, 3rd Edition, 1984, Page-172.
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