LABORATORY MANUAL
ELECTRONIC CIRCUITS AND PULSE CIRCUITS
LABORATORY
II B.Tech – II Semester
Department of
Electronics & Communication Engineering
MLR Institute of Technology, Dundigal, Hyderabad
SIMULATION USING MULTISIM
&
TESTING THE HARDWARE
LABORATORY
EXPERIMENT NO. – 1
COMMON EMITTER AMPLIFIER
Pre lab:
1.
2.
3.
4.
Study the operation and working principle of CE amplifier.
Identify all the formulae will need in this Experiment.
Learn the procedure of using Multisim tool (Schematic & Circuit File).
In this experiment you will use “decibels”, or dB. This is a dimensionless ratio, in
logarithmic form.
The formula is XdB = 20log10(|X|), where X is any dimensionless ratio. For example, X
might be the gain A of an amplifier. If the gain A of an amplifier is 100, you can also
say that the amplifier has a gain of 40 dB. Note that negative values correspond to a
ratio of less than unity, for example an amplifier with a gain of 0.01 has a gain of
40 dB. You can compute a voltage ratio by taking the exponent of 10, for example the
voltage ratio corresponding to a gain of 15 dB is 10 (15/20) = 5.623.
Calculate the following:
Objective:
1.
2.
3.
4.
5.
a. The gain in dB of an amplifier with a gain of 10,000.
b. The gain in dB of an amplifier with a gain of 0.1.
c. The voltage ratio that corresponds to – 3 dB.
To simulate the Common Emitter amplifier using Multisim and study the transient
and frequency response.
Obtain the frequency response characteristics of CE amplifier by hardware
implementation.
To determine the phase relationship between the input and output voltages by
performing the transient analysis.
To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies
and bandwidth of CE amplifier by performing the AC analysis.
Determine the effects of input signal frequency on capacitor coupled common
emitter amplifiers
Software Tool:
Multisim
Requirements:
1. Regulated power supply(0-30V)
2. 1 MHz Function generator
3. 20 MHz Dual Channel CRO
4. Transistor (BC 107 or 2N2222)
5. Resistors
6. Capacitors
7. Bread Board
8. Connecting wires
Circuit Diagram:
-
1 No.
1 No.
1 No.
1 No.
as per circuit
as per circuit
1 No.
XSC1
R7
100kΩ
G
R1
2.2kΩ
A
B
T
C2
V1
12 V
R2
2.2kΩ
XFG1
C1
Q1
BC107BP
1µF
1µF
C4
R6
10kΩ
R5
100µF
1kΩ
5%
Theory:
The practical circuit of CE amplifier is shown in the figure. It consists of different circuit
components. The functions of these components are as follows:
1.
Biasing Circuit: The resistances R1, R2 and RE form the voltage divider biasing
circuit for the CE amplifier. It sets the proper operating point for the CE amplifier.
2.
Input capacitor C1: This capacitor couples the signal to the transistor. It blocks any
dc component present in the signal and passes only ac signal for amplification. Because of
this, biasing conditions are maintained constant.
3.
Emitter Bypass Capacitor CE: An emitter bypass capacitor CE is connected in
parallel with the emitter resistance, RE to provide a low reactance path to the amplified ac
signal. If it is not inserted, the amplified ac signal passing through RE will cause a voltage
drop across it. This will reduce the output voltage, reducing the gain of the amplifier.
4.
Output Coupling Capacitor C2: The coupling capacitor C2 couples the output of the
amplifier to the load or to the next stage of the amplifier. It blocks dc and passes only ac
part of the amplified signal.
Operation:
When positive half of the signal is applied, the voltage between base and emitter (V be)
is increased because it is already positive with respect to ground. So forward bias is increased
i.e., the base current is increased. Due to transistor action, the collector current IC is
increased  times. When this current flows through R Cthe drop IC RC increases considerably.
As a consequence of this, the voltage between collector and emitter (V ce) decreases. In this
way, amplified voltage appears across RC). Therefore the positive going input signal appears
as a negative going output signal i.e., there is a phase shift of 180° between the input and
output.
Procedure:
Frequency response characteristics:
1.
2.
3.
Connect the circuit on the bread board as shown in fig
Set Vin = 20mV at 1 KHz.
Keeping the input voltage constant at this value, vary the frequency from 50Hz
to 1 MHz in convenient steps and measure the V out at each frequency
VO
 VO 
.
, AV ( dB )  20 log 
Vin
 Vin 
4.
Find the voltage gain, AV 
5.
6.
Plot AV VS frequency on a semi-log sheet.
Expected Graphs:
Frequency Response
Observations:
Frequency response Characteristics:
S.No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input
voltage,
Vin(mV)
Input
frequency
Output
voltage,
VO(V)
Gain,
AV 
VO
Vin
Gain in dB,
V 
AV ( dB )  20 log  O 
 Vin 
Observations/Gra
Transient Response:
Frequency Response
Inference:
1. From the transient analysis the phase relationship between input and output voltage
signals is ___________ degrees.
2. From the frequency response curve the following results are calculated
S. No.
Parameter
1
Max. Absolute Gain
2
Max. Gain in dB
3
3dB Gain
4
Lower Cutoff Frequency
5
Upper Cutoff Frequency
6
Bandwidth
Value
Review Questions:
1. Why the CE amplifier provides a phase reversal?
2. In the dc equivalent circuit of an amplifier, how are capacitors treated?
3. What is the effect of bypass capacitor on frequency response?
4. Define lower and upper cutoff frequencies for an amplifier.
5. State the reason for fall in gain at low and high frequencies.
6. What is meant by unity gain frequency?
7. Define Bel and Decibel.
8. What do we represent gain in decibels?
9. Why do you plot the frequency response curve on a semi-log paper?
EXPERIMENT NO. – 2
COMMON SOURCE AMPLIFIER
Pre lab:
1.
Study the operation and working principle of CS amplifier.
2.
Identify all the formulae will need in this experiment.
3.
Study the procedure of using Multisim (Schematic & Circuit File).
4.
In this lab you will use “decibels”, or dB. This is a dimensionless ratio, in logarithmic
form.
The formula is XdB = 20log10(|X|), where X is any dimensionless ratio. For example, X might be
the gain A of an amplifier. If the gain A of an amplifier is 100, you can also say that the amplifier
has a gain of 40 dB. Note that negative values correspond to a ratio of less than unity, for example
an amplifier with a gain of 0.01 has a gain of -40 dB. You can compute a voltage ratio by taking
the exponent of 10, for example the voltage ratio corresponding to a gain of 15 dB is 10 (15/20) =
5.623.
Calculate the following:
a. The gain in dB of an amplifier with a gain of 10,000.
b. The gain in dB of an amplifier with a gain of 0.1.
c. The voltage ratio that corresponds to – 3 dB.
Objective:
1. To simulate the Common Source amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of CS amplifier by hardware implementation.
3. To determine the phase relationship between the input and output voltages by performing
the transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of CS amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on Common Source amplifiers
Software Tool: Multisim
Requirements:
Regulated power supply
(0-30V)
1. 1 MHz Function generator
2. 20 MHz Dual Channel CRO
3. FET (BFW 10)
4. Resistors
5. Capacitors
6. Bread Board
7. Connecting wires
Circuit Diagram:
-
1 No.
1 No.
1 No.
1 No.
as per Circuit
as per Circuit
1 No.
XSC1
G
R3
6.8kΩ
A
B
T
C2
V1
12 V
Q1
R4
C1
8.2kΩ
10µF
XFG 1
10µF
BFW11
R1
1MΩ
5%
R2
2.2kΩ
C3
10µF
RT
Theory:
In Common Source Amplifier Circuit Source terminal is common to both the input and output
terminals. In this Circuit input is applied between Gate and Source and the output is taken from
Drain and the source JFET amplifiers provide an excellent voltage gain with the added advantage
of high input impedance and other characteristics JFETs are often preferred over BJTs for certain
types of applications. The CS amplifier of JFET is analogous to CE amplifier of BJT.
Procedure:
Frequency response characteristics:
1. Connect the circuit on the bread board as shown in fig
2. Set Vin = 100mV
3. Keeping the input voltage constant at this value, vary the frequency from 100Hz to 1
MHz in convenient steps and measure the Vout at each frequency.
VO
 VO 
4. Find the voltage gain, AV  V , AV ( dB )  20 log   .
in
 Vin 
5. Plot AV VS frequency on a semi-log sheet.
Expected Graphs:
Observations / Graphs:
Transient Response:
Frequency Response
Inference:
1. From the transient analysis the phase relationship between input and output voltage signals
is ___________ degrees.
2. From the frequency response curve the following results are calculated:
S. No.
Parameter
1
Max. Absolute Gain
2
Max. Gain in dB
3
3dB Gain
4
Lower Cutoff Frequency
5
Upper Cutoff Frequency
6
Bandwidth
Value
Review Questions:
1. What is Miller effect on common source amplifier?
2. What is the purpose of source resistor and gate resistor?
3. What is swamping resistor
4. What is the purpose of swamping resistor in common source amplifier
5. FET is a liner or non-linear device. And justify your answer
6. What is square law and give an example for a square law device
7. What is pinch off voltage?
EXPERIMENT NO. – 3
TWO STAGE RC COUPLED AMPLIFIER
Pre lab:
1.
2.
3.
4.
5.
Study the purpose of multistage amplifiers.
Learn the different types of coupling methods.
Study the effect of cascading on Bandwidth.
Identify all the formulae you will need in this experiment.
Learn the procedure of using Multisim tool (Schematic & Circuit File).
Objective:
1. To simulate the Two Stage RC Coupled Amplifier in multisim and study the transient
and frequency response.
2. To determine the phase relationship between the input and output voltages by
performing the transient analysis.
3. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of Two Stage RC Coupled Amplifier by performing the AC analysis.
4. To determine the effect of cascading on gain and bandwidth.
Software Tool: Multisim
Requirements:
1.
2.
3.
4.
5.
6.
7.
8.
Regulated power supply (0-30V)
1 MHz Function generator
20 MHz Dual channel CRO
Transistor (BC 107 or 2N2222)
Resistors
Capacitors
Bread Board
Connecting wires
-
1 No.
1 No.
1 No.
1 No.
2 No.
as per circuit
as per circuit
Circuit Diagram:
VCC
12 V
RC1
10kΩ
R3
47kΩ
R1
47kΩ
RC2
10kΩ
C2
C3
Q2
Rs
Q1
C1
1µF
1µF
2N2222A
1kΩ
Vin
0.1mVpk
1kHz
0°
1µF
R2
5kΩ
R4
5kΩ
2N2222A
RE1
2kΩ
CE1
10µF
RE2
2kΩ
RL
10kΩ
CE2
10µF
Theory:
An amplifier is the basic building block of most electronic systems. Just as one brick
does not make a house, a single-stage amplifier is not sufficient to build a practical electronic
system. The gain of the single stage is not sufficient for practical applications. The voltage
level of a signal can be raised to the desired level if we use more than one stage. When a
number of amplifier stages are used in succession (one after the other) it is called a
multistage amplifier or a cascade amplifier. Much higher gains can be obtained from the
multi-stage amplifiers.
In a multi-stage amplifier, the output of one stage makes the input of the next stage.
We must use a suitable coupling network between two stages so that a minimum loss of
voltage occurs when the signal passes through this network to the next stage. Also, the dc
voltage at the output of one stage should not be permitted to go to the input of the next. If it
does, the biasing conditions of the next stage are disturbed.
Figure shows how to couple two stages of amplifiers using RC coupling scheme. This is
the most widely used method. In this scheme, the signal developed across the collector
resistor RC (R2)of the first stage is coupled to the base of the second stage through the
capacitor CC.(C2) The coupling capacitor blocks the dc voltage of the first stage from reaching
the base of the second stage. In this way, the dc biasing of the next stage is not interfered
with. For this reason, the capacitor CC (C2)is also called a blocking capacitor.
As the number of stages increases, the gain increases and the bandwidth decreases.
RC coupling scheme finds applications in almost all audio small-signal amplifiers used in
record players, tape recorders, public-address systems, radio receivers, television receivers,
etc.
Procedure:
Frequency response characteristics:
1. Connect the circuit on the bread board as shown in fig
2. Set Vin = 10mVp
3. Keeping the input voltage constant at this value, vary the frequency from dc to 1
MHz in convenient steps and measure the V out at each frequency.
4. Find the voltage gain, AV 
VO
 VO 
.
, AV ( dB )  20 log 
Vin
 Vin 
5. Plot AV VS frequency on a semi-log sheet.
Observations/Graphs:
Transient Response:
ii) Frequency Response:
Inference:
1.
From the transient analysis, it is observed that,____________________________.
2.
From the frequency response curve the following results are calculated:
S. No.
3.
Parameter
1
Max. Gain in dB
2
3dB Gain
3
Lower Cutoff Frequency
4
Upper Cutoff Frequency
5
Bandwidth
Value
From the AC response, it is observed that, ________________________________.
Review Questions:
1.
Why do you need more than one stage of amplifiers in practical circuits?
2. What is the effect of cascading on gain and bandwidth?
3. What happens to the 3dB frequencies if the number of stages of amplifiers increases?
4. Why we use a logarithmic scale to denote voltage or power gains, instead of using the
simpler linear scale?
5. What is loading effect in multistage amplifiers?
EXPERIMENT NO. – 4 A
CURRENT SHUNT FEEDBACK AMPLIFIER
Pre lab:
1.
2.
3.
4.
5.
Study the concept of feedback in amplifiers.
Study the characteristics of current shunt feedback amplifier.
Study the characteristics of Voltage Series feedback amplifier.
Identify all the formulae will need in this experiment.
Analyze the circuit using Multisim
Objective:
1. To simulate the Current Shunt Feedback Amplifier in Multisim and study the transient
and frequency response.
2. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of Current Shunt Feedback Amplifier by performing the AC analysis.
3. To determine the effect of feedback on gain and bandwidth and compare with Multisim
results.
Requirements:
1.
2.
3.
4.
5.
6.
7.
Transistor – 2n2222(2)
Resistors – as per circuit diagram
Capacitors – as per circuit diagram
RPS – 0-30V.
CRO.
Breadboard.
Connecting wires and Probes.
Software Tool:
Multisim
Circuit Diagram:
XSC1
V1
10 V 47kΩ
R1
R6
10kΩ
R3
47kΩ
Ext Trig
+
R8
10kΩ
_
C3
C2
R9
Q1 1µF
C1
Q2
BC107BP
500Ω
B
A
+
_
+
_
1µF
BC107BP
1µF
XFG1
R2
4.7kΩ
C4
R10
1µF
R7
2.2kΩ
4.7kΩ
R4
4.7kΩ
R5
2.2kΩ
Theory:
Feedback plays a very important role in electronic circuits and the basic parameters,
such as input impedance, output impedance, current and voltage gain and bandwidth, may be
altered considerably by the use of feedback for a given amplifier.
A portion of the output signal is taken from the output of the amplifier and is combined
with the normal input signal and thereby the feedback is accomplished.
There are two types of feedback. They are i) Positive feedback and ii) Negative
feedback. Negative feedback helps to increase the bandwidth, decrease gain, distortion, and
noise, modify input and output resistances as desired.
A current shunt feedback amplifier circuit is illustrated in the figure. It is called a
series-derived, shunt-fed feedback. The shunt connection at the input reduces the input
resistance and the series connection at the output increases the output resistance. This is a
true current amplifier.
Procedure:
1.
2.
3.
4.
5.
6.
Connect the circuit as per the circuit diagram.
Apply the input signal.
Vary the frequency conveniently and note down the output voltage.
Plot the curve between gain and resonant frequency.
Calculate the gain.
Calculate the resonant frequency and compare it with the theoretical value.
Observations/Graphs:
i) Transient Response:
ii) Frequency Response:
Inference:
1. From the frequency response curve the following results are calculated:
S. No.
1
2
3
Parameter
Max. Gain in dB
3dB Gain
Lower Cutoff Frequency
Value
5
2.
Bandwidth
From the AC response, it is observed that, _____________________________.
Review Questions:
1. State the merits and demerits of negative feedback in amplifiers.
2. If the bypass capacitor CE in an RC coupled amplifier becomes accidentally open
circuited, what happens to the gain of the amplifier? Explain.
3. When will a negative feedback amplifier circuit be unstable?
4. What is the parameter which does not change with feedback?
5. What type of feedback has been used in an emitter follower circuit?
EXPERIMENT NO. – 4 B
VOLTAGE SERIES FEED BACK AMPLIFIER
Pre lab:
1.
2.
3.
4.
Study the concept of feedback in amplifiers.
Study the characteristics of Voltage Series feedback amplifier.
Identify all the formulae will need in this experiment.
Analyze the circuit using Multisim
Objective:
1. To simulate the Current Shunt Feedback Amplifier in Multisim and study the transient and
frequency response.
2. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of Current Shunt Feedback Amplifier by performing the AC analysis.
3. To determine the effect of feedback on gain and bandwidth and compare with Multisim
results.
REQUIREMENTS:
Transistor BC 107
Breadboard
Regulated Power Supply (0-30V, 1A)
Function Generator
CRO (20 MHz, dual trace)
Resistors
Capacitors
Bread Board Trainer Kit
Connecting wires
CIRCUIT DIAGRAM:
XSC1
V1
12 V
R1
33kΩ
R4
2.2kΩ
Ex t Trig
+
_
B
A
+
_
+
_
Q1
C1
10µF
BC107BP
XFG1
R2
3.3kΩ
R3
1kΩ
C3
10µF
C2
100µF
R5
1kΩ
THEORY:
When any increase in the output signal results into the input in such a way as to cause
the decrease in the output signal, the amplifier is said to have negative feedback.
The advantages of providing negative feedback are that the transfer gain of the amplifier with
parameters of the other active devices used in the circuit. The most advantage of the negative
feedback is that by proper use of this , there is significant improvement in the frequency response
and in the linearity of the operation of the amplifier. This disadvantage of the negative feedback is
that the voltage gain is decreased.
In Voltage-Series feedback , the input impedance of the amplifier is decreased and the output
impedance is increased. Noise and distortions are reduced considerably.
PROCEDURE:
1. Connections are made as per circuit diagram.
2. Keep the input voltage constant at 20mV peak-peak and 1kHz frequency. For different values
of load resistance, note down the output voltage and calculate the gain by using the
expression
Av = 20log(V0 / Vi ) dB
3 Add the emitter bypass capacitor and repeat STEP 2.And observe the effect of Feedback on the
gain of the amplifier
4. For plotting the frequency the input voltage is kept constant at 20mV peak-peak and the
frequency is varied from 100Hz to 1MHz.
5. Note down the value of output voltage for each frequency. All the readings are tabulated and
the voltage gain in dB is calculated by using expression Av = 20log(V0 / Vi ) dB
6.
A graph is drawn by taking frequency on X-axis and gain on Y-axis on semi log graph sheet
7. The Bandwidth of the amplifier is calculated from the graph using the expression Bandwidth
B.W = f2 – f1.
Where f1 is lower cut off frequency of CE amplifier
f 2 is upper cut off frequency of CE amplifier
The gain-bandwidth product of the amplifier is calculated by using the expression
Gain-Bandwidth Product = 3-dB mid band gain X Bandwidth.
OBSERVATIONS:
Voltage Gain:
S.NO
Output
Voltage Output
Voltage Gain(dB) with Gain(dB)
(Vo)with feedback (Vo)
feedback
without
without feedback
feedback
Frequency Response: Vi = 20mV
S.NO
Frequency (Hz)
Output Voltage (Vo)
MODEL WAVEFORMS:
Gain A = Vo- Gain in dB
/Vi
20log(Vo/Vi)
PRECAUTIONS:
1. While taking the observations for the frequency response, the input voltage must be
maintained constant at 20mV.
2. The frequency should be slowly increased in steps.
3. The three terminals of the transistor should be carefully identified.
4. All the connections should be correct.
Review Questions:
1. What is the Difference between voltage and current amplifiers
2. What is meant by feed back in an electronic circuits
3. What are different types of feed backs
EXPERIMENT NO. – 5
RC PHASE SHIFT OSCILLATOR USING TRANSISTORS
Pre lab:
1.
2.
3.
4.
Study the concept of positive feedback.
Study the operation and working principle of RC phase shift oscillator.
Identify all the formulae you will need in this Lab.
Analyze the circuit using Multisim
Objective:
1. To simulate the RC Phase Shift oscillator using Multisim and study the transient
response.
2. To determine the frequency of oscillation and compare its value with the Multisim
values
Requirements:
1.
2.
3.
4.
5.
6.
7.
Transistor – 2N2222 or BC 107
Resistors
Capacitors
RPS – 0-30V.
20 MHz Dual Channel CRO.
Breadboard.
Connecting wires and Probes.
Software Tool: Multisim
Circuit Diagram:
X S C1
G
R6
47kΩ
5%
R5
4.7kΩ
A
B
T
C5
C1470µF
C2
Q1
100nF
BC107BP
100nF
R4
4.7kΩ
V1
C3
100nF
R7
4.7kΩ
12 V
R1
4.7kΩ
R3
560Ω
C4
470µF
R2
1kΩ
Theory:
Any circuit which is used to generate an ac voltage without an ac input signal is called an
oscillator. Positive feedback is used in oscillators. Based on the type of components used, the
In the RC phase shift oscillator the required phase shift of 180° in the feedback loop from
output to input is obtained by using R and C components. Figure shows the circuit of RC phase
shift oscillator using cascaded connection of high pass filter. Here, a common emitter amplifier is
followed by three sections of RC phase shift network, the output of the last section being returned
to the input.
 1 
The phase shift, φ, given by each RC section is φ = tan -1  CR  . If R is made zero, then φ
will become 90°. But making R=0 is impracticable because if R is zero, then the voltage across it
will become zero. Therefore, in practice the value of R is adjusted such that φ becomes 60°. If the
values of R and C are so chosen that, for the given frequency f r, the phase shift of each RC section
is 60°. Thus such a RC ladder network produces a total phase shift of 180° between its input and
output voltages for the given frequency. Therefore, at the specific frequency f r, the total phase shift
from the base of the transistor around the circuit and back to the base will be exactly 360° or 0°,
the thereby satisfying Barkhausen condition for oscillation. The frequency of oscillation is given
by
fr =
1
2RC (6  4 K )
At this frequency, it is found that the feedback factor of the network is || = 1/29. In order that |A|
shall not be less than unity, it is required that the amplifier gain |A| must be more than 29 for
oscillator operation.
Procedure:
1. Connect the circuit on the bread board as per the circuit diagram.
2. Connect the CRO and observe the waveform.
3. Calculate the resonant frequency and compare it with the theoretical value.
4. Repeat for another set of RC values.
Observations/Graphs:
Transient Response:
Inference:
The theoretical and practical calculation of the frequency of oscillation of RC phase shift
oscillator is calculated as follows:
Theoretical
Calculations
Practical
Calculations
R = 10k
C = 0.01u
T= ________ms
fr =
1
2RC 6  4k
f= 1/T= __________Hz
Where k = Rc/R = 0.18
fr = ________Hz
Review Questions:
1. What is Barkhausen criterion?
2. What is the maximum phase shift provided by the single RC network?
3. What is the condition of phase shift oscillator to produce sustained oscillations?
4. Where does the starting voltage for an oscillator?
5. Why are RC oscillators preferred for the generation of low frequencies?
6. If the percentage feedback for sustained oscillations in an oscillator is 5%, what is the
required gain of amplifier?
7. Find the percentage feedback to produce sustained oscillators if amplifier gain is 60.
8. An RC phase shift oscillator circuit has 3 identical RC networks with R=100Ω, C=10μF.
Find the frequency of oscillation.
EXPERIMENT NO. – 6
CLASS A POWER AMPLIFIER (Transformer Less)
Pre lab:
1.
2.
3.
4.
Study the difference between voltage and power amplifiers.
Study the operation and working principle of Class A power amplifier.
Identify all the formulas you will need in this Lab.
Learn the procedural steps using Multisim tool (Schematic & Circuit File).
Objective:
1. To simulate the Class A power amplifier in Multisim and study the transient response.
2. To determine the Collector efficiency of Class A power amplifier.
3. To obtain the output characteristics and frequency response of Class A power
amplifier.
Software Tool: Multisim
Requirements:
1.
2.
3.
4.
5.
6.
7.
8.
Transistors – 2n2222 (NPN) or SL100 (NPN), 2n2907A (PNP) or SK100 (PNP).
Resistor
Capacitor
Inductor
RPS –(0-30V)
Dual Channel CRO.
Breadboard.
Connecting wires and Probes
Circuit Diagram:
XSC1
G
XMM2
C1
V1
4V
R1
R2
1.8kΩ
5%
8.2Ω
5%
10µF
B
T
Q1
BD137
XFG1
A
R3
1.8kΩ
5%
Theory:
Class A power amplifier is one in which the output current flows during the entire cycle
(360°) of input signal. Thus the operating point is selected in such a way that the transistor
operates only over the linear region of its load line. So this amplifier can amplify input signals
of small amplitude. The theoretical efficiency of transformer coupled or inductively coupled
class A power amplifier is 50%.
Practically it is in the range of 30 – 35%. The formula for calculating collector efficiency is
% 
PAC
100 , where PAC and PDC values are calculated as follows:
PDC
Using RMS values:
PDC =
VCC
 IDC
PAC = Vrms  Irms
Using Peak values:
PDC =
VCC
 IDC
PAC = Vrms  Irms =
V
I 
Vm I m 
Vrms  m , I rms  m 

2 
2
2
Vm 2
I m 2 RL
or
PAC =
2 RL
2
Using Peak to Peak values:
PDC =
VCC
 IDC
PAC = Vrms  Irms =
PAC =
Vpp 2
8RL
or
V pp
I pp 
V pp I pp 
Vm
I

, I rms  m 
Vrms 

8
2 2 2
2 2 2

I pp 2 RL
8
PROCEDURE:
1. Connect the circuit diagram as shown in the fig. above
2. Set Vs = 0 at 1 KHz.
3. Increase Vs till undistorted waveform is seen on the CRO.
4. Measure the input voltage Vs.
5. Vary the frequency from dc to 1MHz in convenient steps and measure the V O at every
frequency for constant input.
6. Find the voltage gain, AV =
 VO
VO
, AV(dB) = 20 log 
VS
 VS

 .

7. Plot AV Vs Frequency using Semi-log paper.
8. Repeat the above steps from 4 to 6 for different values of load resistance.
OBSERVATIONS/GRAPHS:
I) TRANSIENT RESPONSE:
II) FREQUENCY RESPONSE:
CALCULATIONS:
PDC =
PAC =
VCC
Vpp 2
 IDC
I pp 2 RL
or
8RL
8
P
%  AC 100
PDC
Theoretical Efficiency = ___________________.
Practical Efficiency =___________________.
INFERENCE:
1. From transient it is observed that the Class A power amplifier conducts for
____________ angle.
2. The collector efficiency of class A power amplifier is ______________.
Review Questions:
1. What are the types of power amplifiers differentiate each of them
EXPERIMENT NO. – 7
CLASS B COMPLEMENTARY SYMMETRY POWER AMPLIFIER
PRELAB:
1. Study the operation and working principle of Class B power amplifier.
2. Identify all the formulas you will need in this Lab.
3. Study the procedure of using Multisim (Schematic & Circuit File).
OBJECTIVE:
1. To simulate the Class B Complementary Symmetry power amplifier in Multisim and
study the transient response.
2. To eliminate the cross-over distortion using modified circuitry.
SOFTWARE TOOL:
Multisim
Requirements:
Transistors
Resistors
Capacitors
RPS (0-30V)
1 MHz Function Generator
20MHz Dual Channel CRO
CIRCUIT DIAGRAM:
V2
12 V
XSC1
Q1
Ext Trig
+
_
BD137
+
XFG1
B
A
_
+
_
Q2
1kΩ
R1
BD138
V1
12 V
THEORY:
Fig. Class B Complementary Symmetry Power Amplifier
The use of both the input and output transformers in an ordinary push-pull amplifier
circuit is eliminated using a circuit called complementary-symmetry push-pull amplifier circuit.
This uses a pair of transistors having complementary symmetry, that is, one transistor is PNP
and the other is NPN. Note that the complementary symmetry circuit requires two power
supplies, since each transistor must be biased suitably.
The transistors Q1 and Q2 are operated in class-B. That is, the bias is adjusted such
that the operating point corresponds to the cut-off points. Hence, with no signal input, both
transistors are cut-off and no collector current flows. The signal applied at the input goes to
the base of both the transistors. Since the transistors are of opposite type, they conduct in
opposite half-cycles of the input. For example, during the positive half-cycle of the input
signal, the PNP transistor Q1 is reverse biased and does not conduct. The NPN transistor Q2,
on the other hand, is forward-biased and conducts. This results in a half-cycle of output
voltage across the load resistor. The other half-cycle of output across the load is provided by
the conduction of transistor Q1 (the transistor Q2 remains cut-off) during the negative halfcycle of the input. Since the collector current from each transistor flows through the load
during the alternate half-cycles of the input signal, no centre-tapped output transformer is
required.
The two transistors – though of opposite type – must be matched. If there is an
imbalance in the characteristics of the two transistors, even harmonics will no longer be
cancelled. This would result in considerable distortion. Increasing availability of
complementary transistors is making the use of class-B transformer coupled stages obsolete.
All modern power amplifier circuits are transformer less and use complementary transistors.
PROCEDURE :
1. Connect the circuit diagram as shown in the fig. above
2. Set Vs = 0 at 1 KHz.
3. Increase Vs till undistorted waveform is seen on the CRO.
4. Measure the input voltage Vs.
5. Vary the frequency from dc to 1MHz in convenient steps and measure the V O at every
frequency for constant input.
6. Find the voltage gain, AV =
 VO
VO
, AV(dB) = 20 log 
VS
 VS

 .

7. Plot AV Vs Frequency using Semi-log paper.
8. Repeat the above steps from 4 to 6 for different values of load resistance.
OBSERVATIONS/GRAPHS:
INFERENCE:
1. From transient response of Class B complementary symmetry power amplifier, it is
observed that _____________________________________________________.
2. Using modified circuitry of Class B complementary symmetry power amplifier
_______________________________________________.
Review Questions:
1. Differentiate voltage and power amplifiers
2.
Explain impedance matching provided by transformer
3. How can you reduce cross over distortion
4. What is maximum theoretical frequency
5. Is the amplifier working in class A or B
s
EXPERIMENT NO. – 8
COMMON BASE AMPLIFIER
Pre lab:
1.
2.
3.
4.
Study the operation and working principle of CB amplifier.
Identify all the formulae you will need in this Lab.
Study the procedure of using Multisim tool (Schematic & Circuit File).
In this lab you will use “decibels”, or dB. This is a dimensionless ratio, in logarithmic
form.
The formula is XdB = 20log10(|X|), where X is any dimensionless ratio. For example, X
might be the gain A of an amplifier. If the gain A of an amplifier is 100, you can also
say that the amplifier has a gain of 40 dB. Note that negative values correspond to a
ratio of less than unity, for example an amplifier with a gain of 0.01 has a gain of
40 dB. You can compute a voltage ratio by taking the exponent of 10, for example the
voltage ratio corresponding to a gain of 15 dB is 10 (15/20) = 5.623.
Calculate the following:
a. The gain in dB of an amplifier with a gain of 10,000.
b. The gain in dB of an amplifier with a gain of 0.1.
c. The voltage ratio that corresponds to – 3 dB.
Objective:
1. To simulate the Common Base amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of CB amplifier by hardware
implementation.
3. To determine the phase relationship between the input and output voltages by
performing the transient analysis.
4. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies
and bandwidth of CB amplifier by performing the AC analysis.
5. Determine the effects of input signal frequency on common Base. amplifiers
Software Tool:

Multisim.
Requirements:
1.
2.
3.
4.
5.
6.
7.
8.
Regulated power supply
Function generator
CRO
Transistor (BC 107 or 2N2222)
Resistors
Capacitors
Bread Board
Connecting wires
Circuit Diagram:
-
1 No.
1 No.
1 No.
1 No.
1 No.
2 Nos.
1 No.
XSC1
Q1
BC107BP
C1
C2
Ext Trig
+
_
10µF
10µF
+
XFG1
R1
20kΩ
B
A
_
+
_
R2
20kΩ
R3
1kΩ
V1
20 V
PART – I
V2
20 V
EXPERIMENT Theory:
In Common Base Amplifier Circuit Base terminal is common to both the input and output
terminals.
In this Circuit input is applied between
collector and the base.
emitter and base and the output is taken from
As we know, the emitter current is greater than any other current in the transistor, being the
sum of base and collector currents .i.e IE= IB+ IC In the CE and CC amplifier configurations,
the signal source was connected to the base lead of the transistor, thus handling the least
current possible.
Because the input current exceeds all other currents in the circuit, including the output
current, the current gain of this amplifier is actually less than 1 (notice how Rload is connected
to the collector, thus carrying slightly less current than the signal source). In other words, it
attenuates current rather than amplifying it. With common-emitter and common-collector
amplifier configurations, the transistor parameter most closely associated with gain was β. In
the common-base circuit, we follow another basic transistor parameter: the ratio between
collector current and emitter current, which is a fraction always less than 1. This fractional
value for any transistor is called the alpha ratio, or α ratio.( α= IC/IE)
Since it obviously can't boost signal current, it only seems reasonable to expect it to boost
signal voltage.
Theory:
The positive going Pulse of input Source increases the emitter voltage. As the base voltage is
Constant , the forward bias of emitter base junction reduces. This reduces I B, reducing IC and
hence the drop across RC Since VO=VCC - IC RC ,the reduction in IC results in an increase in VO.
Therefore , we can Say that positive going input produces positive going output and similarly
negative going input produces negative going output and there is no phase shift between
input and output in a common base Amplifier.
Procedure:
Frequency response characteristics:
1. Connect the circuit on the bread board as shown in fig
2. Set Vin = 0 at 1 KHz.
3. Increase Vin till undistorted waveform is seen on the CRO.
4. Measure the input voltage Vin.
5. Keeping the input voltage constant at this value, vary the frequency from dc to 1
MHz in convenient steps and measure the V out at each frequency.
6. Find the voltage gain, AV 
VO
 VO 
.
, AV ( dB )  20 log 
Vin
 Vin 
7. Plot AV VS frequency on a semi-log sheet.
8. Expected Graphs:
Observations:
Frequency response Characteristics:
S.No.
Input
voltage,
Vin(mV)
Input
frequency
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Observations / Graphs:
Transient Response:
Output
voltage,
VO(V)
Gain,
AV 
VO
Vin
Gain in dB,
V 
AV ( dB )  20 log  O 
 Vin 
Frequency Response:
Inference:
1. From the transient analysis the phase relationship between input and output voltage
signals is ___________ degrees.
2. From the frequency response curve the following results are calculated:
S. No.
Parameter
1
Max. Absolute Gain
2
Max. Gain in dB
3
3dB Gain
4
Lower Cutoff Frequency
5
Upper Cutoff Frequency
Value
6
Bandwidth
Review Questions:
1. Suppose the source resistance of VIN is 50Ω. Will the CB amplifier perform well in
amplifying the signal from vin? Why?
2. Why the CB amplifier is commonly used as a current buffer?
3. What type of capacitors in RC Coupled amplifier
4. The main features of large signal amplifier circuit?
5. The principle advantages of BJTs over MOSFETs
EXPERIMENT NO. – 9
CLASS C POWER AMPLIFIER
PRELAB:
1. Study the operation and working principle of Class C power amplifier.
2. Identify all the formulas you will need in this Lab.
3. Study the procedure of using Multisim (Schematic & Circuit File).
OBJECTIVE:
1. To simulate the Class C power amplifier in Multisim and study the transient response.
2. To observe the output and frequency response of class C power amplifier.
SOFTWARE TOOL:
Multisim
APPARATUS:
1.
2.
3.
4.
5.
6.
7.
Transistors – BD137 or SL 100
Resistor
Capacitor
Inductor – 2.5mH
Dual Channel RPS – 0-30V
20 MHz CRO
Breadboard.
8. Connecting wires and Probes
CIRCUIT DIAGRAM:
V3
12 V
L1
10mH
XSC1
C2
1µF
Ext Trig
+
Q1
C1
_
B
A
BD137
+
_
+
_
1µF
XFG1
R1
20.0kΩ
V1
12 V
THEORY:
Class-C amplifiers conduct less than 50% of the input signal and the distortion at the output
is high, but high efficiencies (up to 90%) are possible. Some applications (for example,
megaphones) can tolerate the distortion. The usual application for class-C amplifiers is in RF
transmitters operating at a single fixed carrier frequency, where the distortion is controlled by
a tuned load on the amplifier. The input signal is used to switch the active device causing
pulses of current to flow through a tuned circuit forming part of the load.
The tuned circuit resonates at one frequency, the fixed carrier frequency, and so the
unwanted frequencies are suppressed, and the wanted full signal (sine wave) will be extracted
by the tuned load. The signal bandwidth of the amplifier is limited by the Q-factor of the
tuned circuit but this is not a serious limitation. Any residual harmonics can be removed using
a further filter.
In practical class-C amplifiers a tuned load is invariably used. In one common arrangement
the resistor shown in the circuit above is replaced with a parallel-tuned circuit consisting of an
inductor and capacitor in parallel, whose components are chosen to resonate the frequency of
the input signal. Power can be coupled to a load by transformer action with a secondary coil
wound on the inductor. The average voltage at the drain is then equal to the supply voltage,
and the signal voltage appearing across the tuned circuit varies from near zero to near twice
the supply voltage during the rf cycle. The input circuit is biased so that the active element
(e.g. transistor) conducts for only a fraction of the rf cycle, usually one third (120 degrees) or
less.
The active element conducts only while the drain voltage is passing through its minimum. By
this means, power dissipation in the active device is minimized, and efficiency increased.
Ideally, the active element would pass only an instantaneous current pulse while the voltage
across it is zero: it then dissipates no power and 100% efficiency is achieved. However
practical devices have a limit to the peak current they can pass, and the pulse must therefore
be widened, to around 120 degrees, to obtain a reasonable amount of power, and the
efficiency is then 60-70%.
PROCEDURE :
1. Connect the circuit diagram as shown in the fig. above
2. Set Vs = 0 at 1 KHz.
3. Increase Vs till undistorted waveform is seen on the CRO.
4. Measure the input voltage Vs.
5. Vary the frequency from dc to 1MHz in convenient steps and measure the V O at every
frequency for constant input.
6. Find the voltage gain, AV =
 VO
VO
, AV(dB) = 20 log 
VS
 VS

 .

7. Plot AV Vs Frequency using Semi-log paper.
8. Repeat the above steps from 4 to 6 for different values of load resistance.
OBSERVATIONS/GRAPHS:
I. TRANSIENT RESPONSE:
INFERENCE:
1. From transient response of Class B complementary symmetry power amplifier, it is
observed that _____________________________________________________.
Review Questions:
1. What is the difference between ac dc load line
2. How do you locate the Q point
3. What is the example for the output swing in a power amplifier
EXPERIMENT NO. – 10
SINGLE TUNED VOLTAGE AMPLIFIER
Sampling Circuit
Pre lab:
1. Study the concept of Resonance and Parallel Tuned Circuit.
2. Study the operation of Single Tuned Voltage Amplifiers.
3. Analyze the circuit using Multisim
Objective:
1. To measure the resonant frequency of a single tuned voltage amplifier.
2. To measure the gain at resonant frequency.
Apparatus:
1.
2.
3.
4.
5.
6.
7.
8.
Transistor
Resistors
Capacitors
Inductor
RPS – 0-30V.
20 MHz dual Channel CRO.
Breadboard.
Connecting wires and Probes.
Circuit Diagram:
XSC1
G
A
R7
100kΩ
10nF
C3 L1
2.2mH
B
C2
T
XSA1
IN T
V1
12 V
R2
C1
1kΩ
10µF
XFG1
Q1
BC107BP
10µF
C4
R6
10kΩ
R5
1kΩ
5%
100µF
Theory:
A tuned amplifier uses one or more parallel tuned LC circuit as the load impedance.
Tuned amplifiers are used for amplifying electrical signals consisting of either a single radio
frequency (>30KHz) or a narrow band of frequencies in the RF (radio frequency) region.
Tuned amplifiers are properly referred to as radio frequency (RF) amplifiers.
The resonant frequency of tuned amplifier is given by
fr =
1
2 LC
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Apply maximum undistorted input signal.
3. Vary the frequency conveniently and note down the output voltage.
4. Calculate the gain at resonant frequency.
5. Plot the curve between gain and resonant frequency.
6. Calculate the resonant frequency and compare it with the theoretical value.
Expected Waveforms/Graphs:
Theoretical Calculations:
fr =
1
2 LC
=
1
3
2 10 10 100 109
= 5.03 KHz
Practical Calculations:
Observations:
S. No.
Input
Input Voltage,
Output Voltage,
Absolute
Gain in
1
Frequency (Hz)
Vin (mV)
Vout (V)
Gain
dB
2
3
4
5
6
7
8
9
10
Inference:
The resonant frequency of single tuned voltage amplifier is ______________________.
The maximum gain at resonant frequency is _______________________.
Review Questions:
1. What is tuned amplifier?
2. Discuss the quality (Q) factor of a tuned amplifier, the factors that affect its value, and
its relationship to amplifier bandwidth.
3. How does tuned amplifier acts as a filter?
4. What is stagger tuning?
5. What is neutralization?
EXPERIMENT NO. – 11
COLPITT’S OSCILLATOR & HARTLEY OSCILLATOR
Pre lab:
1. Study the operation and working principle of Colpitt’s Oscillator
2. Study the procedure conducting the experiment in the lab.
Objective:
To determine the frequency of oscillations of Colpitt’s Oscillator
Requirements:
1. Transistor
2. Resistors
3. Capacitors
4. Inductor
5. RPS-0- 30V
6. Dual Channel CRO
7. Bread board
8. Connecting wires and probes.
Software Tool:
Multisim
Circuit Diagram:
XSC1
Ext Trig
+
_
B
A
R7
100kΩ
R1
2.2kΩ
V1
12 V
C1
Q1
BC107BP
10µF
+
_
+
_
C2
10µF
C4
100µF
C5
R6
10kΩ
R5
330Ω
10µF
C6
10µF
L1
10mH
Theory:
The Colpitt’s Oscillator circuit is given above. The feedback network consisting of
capacitors C1, C4 and an inductor L1 determines the frequency of the oscillator. The
frequency of Colpitt’s oscillator is given by 1/2∏ √[(C1+C4)/L1C1C4].
The condition for sustained oscillations is h fe = C2/C1.
Procedure:
1.
2.
3.
4.
Connect the circuit on the bread board as shown in the figure.
Connect the CRO at the output terminals of the circuit.
Note down the amplitude and frequency of the output voltage.
This will give the frequency of the oscillations of the Colpitt’s Oscillator.
Observations/Graphs:
i) Expected Graph:
Inference:
Frequency of the given Colpitt’s oscillator is determined both practically, theoretically and
using Multisim.
Review Questions:
1. What is the condition for sustained oscillations in Colpitt’s Oscillator?
2. In Colpitt’s Oscillator which elements provide required dc bias to the transistor and
which determine the frequency of the output signal?
3. What are the applications of Colpitt’s oscillator?
4. What are the differences between Colpitt’s and Hartley Oscillator?
5. How the oscillations are produced in Colpitt’s Oscillator?
EXPERIMENT NO. – 11
HARTLEY OSCILLATOR
Pre lab:
1. Study the operation and working principle of Hartley Oscillator
2. Study the procedure conducting the experiment in the lab.
Objective:
To determine the frequency of oscillations of Hartley Oscillator
Requirements:
1. Transistor BC107
2. Resistors 300, 8K, 10K, 100K
3. Capacitors 10u (4).
4. Inductors 2m, 100m
5. RPS -12V
6. CRO
7. Breadboard
8. Connecting Wires and probes
Software Tool:
Multisim
Circuit Diagram:
XSC1
Ext Trig
+
_
B
A
R7
100kΩ
R1
2.2kΩ
V1
12 V
C1
Q1
BC107BP
10µF
+
_
+
_
C2
10µF
C4
100µF
R6
10kΩ
R5
330Ω
L1
L2
10mH
10mH
C3
10µF
Theory:
The Hartley Oscillator circuit is given above. The feedback network consisting of
inductors L1, L2 and a capacitor C determines the frequency of the oscillator. The frequency
of Hartley oscillator is given by 1/2∏ √[(L1+L2)C].
The condition for sustained oscillations is h fe = L1/L2.
Procedure:
1. Connect the circuit on the bread board as shown in the figure
2. Connect the CRO at the output terminals of the circuit.
3. Note down the amplitude and frequency of the output voltage.
4. This will give the frequency of the oscillations of the Hartley Oscillator.
Observations/Graphs:
i) Expected Graph:
Inference:
Frequency of the given Harltey oscillator is determined both practically, theoretically and
using Multisim.
Review Questions:
1. What is the condition for sustained oscillations in Hartley Oscillator?
2. In Hartley’s Oscillator which elements provide required dc bias to the transistor and
which determine the frequency of the output signal?
3. What are the applications of Colpitt’s oscillator?
4. What is piezo electric effect?
5. Draw the ac equivalent circuit of a crystal oscillator? What is the most frequently used
material in crystal oscillator?
EXPERIMENT NO. – 12
DARLINGTON PAIR AMPLIFIER
Pre lab:
1.
Study the operation and working principle of Darlington pair Amplifier
2.
Identify all the formulae you will need in this Lab.
3.
Study the procedure of using Multisim (Schematic & Circuit File).
4.
In this lab you will use “decibels”, or dB. This is a dimensionless ratio, in
logarithmic
form.
The formula is XdB = 20log10(|X|), where X is any dimensionless ratio. For example, X
might be the gain A of an amplifier. If the gain A of an amplifier is 100, you can also
saythat the amplifier has a gain of 40 dB. Note that negative values correspond to a ratio
of
less than unity, for example an amplifier with a gain of 0.01 has a gain of
-40 dB.
You can compute a voltage ratio by taking the exponent of 10, for example the voltage
ratio corresponding to a gain of 15 dB is 10 (15/20) = 5.623.
Calculate the following:
a. The gain in dB of an amplifier with a gain of 10,000.
b. The gain in dB of an amplifier with a gain of 0.1.
c. The voltage ratio that corresponds to – 3 dB.
Objective:
1. To simulate the Darlington Pair amplifier in Multisim and study the transient and
frequency response.
2. Obtain the frequency response characteristics of Darlington pair amplifier by hardware
implementation.
3. To determine the maximum gain, 3dB gain, lower and upper cutoff frequencies and
bandwidth of Darlington pair Amplifier by performing the AC analysis.
Software Tool: Multisim
Requirements:
1. Regulated power supply
-
1 No.
2. Function generator
-
1 No.
3. CRO
-
1 No.
4. Transistor (BC 107 or 2N3904)
-
2 No.
5. Resistors
as per circuit
6. Capacitors (1 µF)
-
3 No.
7. Bread Board
-
1 No.
8. Connecting wires
Circuit Diagram:
XSC1
R1
1kΩ
Ext Trig
+
Q1
C1
_
B
A
+
1µF
_
+
_
BC107BP
Q2
V1
12 V
XFG1
R2
1kΩ
BC107BP
R3
100Ω
T
heory:
The Darlington transistor (often called a Darlington pair) is a compound structure
consisting of two bipolar transistors (either integrated or separated devices) connected in
such a way that the current amplified by the first transistor is amplified further by the second
one. This configuration gives a much higher current gain than each transistor taken
separately and, in the case of integrated devices, can take less space than two individual
transistors because they can use a shared collector. Integrated Darlington pairs come
packaged singly in transistor-like packages or as an array of devices (usually eight) in an
integrated Circuit.
The Darlington pair transistor circuit configuration can be very useful in electronics
circuit design. Although it has speed limitations, the Darlington Pair is nevertheless very
useful in many areas where high levels of current gain are required, particularly for emitter
follower style applications.
Procedure:
Frequency response characteristics:
1. Connect the circuit on the bread board as shown in fig
2. Set Vin= 0 at 1 KHz.
3. Increase Vin till undistorted waveform is seen on the CRO.
4. Measure the input voltage Vin.
5. Keeping the input voltage constant at this value, vary the frequency from dc to 1
MHz in convenient steps and measure the V out at each frequency.
6. Find the voltage gain, AV 
VO
 VO 
.
, AV ( dB )  20 log 
Vin
 Vin 
7. Plot AV VS frequency on a semi-log sheet.
Observations / Graphs:
Frequency Response
Inference:
1. From the transient analysis the phase relationship between input and output voltage
signals is ___________ degrees.
2. From the frequency response curve the following results are calculated:
S. No.
Parameter
1
Max. Absolute Gain
2
Max. Gain in dB
3
3dB Gain
Value
4
Lower Cutoff Frequency
5
Upper Cutoff Frequency
6
Bandwidth
Review Questions:
1. Is Darlington pair transistor used in power amplifiers? Justify Your answer?
2. What is the input impedance of Darlington pair amplifier?
3. Compare common emitter amplifier with Darlington amplifier
4. Why do we need pre regulators
5. What is other name of a pre regulator circuit?
Part-II
Experiment No:1
LINEAR WAVE SHAPING
AIM :
a) To study the response of RC Low pass circuit and to determine
rise time for a square wave input for different time constants.
i) RC>>T
ii) RC = T
iii) RC<<T
b) To study the response of RC High pass circuit and to determine
percentage tilt for a square input for different time constants.
i) RC>>T
ii) RC = T
iii) RC<<T.
Components Required :
9. Resistors - 10k, 100 k, 1M
10. Capacitor - 0.01F
Apparatus Required :
1. Bread Board.
2. CRO
3. Function Generator.
4. Connecting Wires.
THEORY:
LINEAR WAVE SHAPING
The process of where by the form of a non-sinusoidal signal is altered by
transmission through a linear network is called “LINEAR WAVE SHAPING”.
a) RC Low Pass Circuit :
R
Vi
C
V0
Figure 1: RC Low Pass Circuit.
The circuit passes low frequencies readily but attenuates high frequencies because the
reactance of the capacitor decreases with increasing frequency. At very high frequencies the
capacitor acts as a virtual short circuit and the output falls to zero. This circuit also works as
integrating circuit. A circuit in which the output voltage is proportional to the integral of the
input voltage is known as integrating circuit. The condition for integrating circuit is RC value
must be much greater than the time period of the input wave (RC>>T)
Let Vi = alternating input voltage. i =
resulting current
Applying Kirchoff’s Voltage Law to RC low pass circuit (fig.1).
1T
V  iR 
i.dt
i

C o
Multiplying throughout by C, we get
T
CVi  iRC  i.dt
o
T
As RC >> T, the term i.dt may be neglected
o

CVi  iRC
Integrating with respect to T on both sides, we get
T
T
 CVi .dt  RC i.dt
0
0
1

C
T
i.dt 
RC
0
1

1
t

V i.dt
0
T
V0 
C 0 i.dt
1 t
V

0
Vi .dt
RC

0
The output voltage is proportional to the integral of the input voltage.
EXPECTED GRAPH:
Vi
t
(0.9)V0
(0.1)V0
RC<T
t
tr
V0
RC>>T
t
b) RC High Pass Circuit.
C
Vi
R
V0
Figure: 2. RC High Pass Circuit.
The higher frequency components in the input signal appears at the output with less
attenuation than the lower frequency components because the reactance of the capacitor
decreases with increase in frequency. This circuit works as a differential circuit. A circuit in
which the output voltage is proportional to the derivative of the input voltage is known as
differential circuit. The condition for differential circuit is RC value must be much smaller then
the time period of the input wave (RC<<T).
Applying Kirchoff’s Voltage Law to RC high pass circuit (fig.2)
V
iR .
i
1
T
C o
i.dt 
Divide throughout by R
Vi

1
T
i.dt  i .
RC o
R
As RC << T, the above equation is modified as
V
i

1
T
i.dt
RC o
R
Differentiating above equation with respect to T.
1 d V  1
.i
i
R dt
RC
RC
dV
i  iR
dt
V0  iR
V
Therefore
0
 RC d Vi .
dt
V0 
d
dt
Vi
EXPECTED GRAPHS:
Vi
t
V1
V1
t
V RC=T
RC<<T
t
DESIGN:
1.
2.
3.
4.
5.
6.
7.
Choose T = 1msec.
Select C = 0.01 F.
For RC = T; select R.
For RC >> T; select R.
For RC << T; select R.
If RC << T, the High pass circuit works as a differentiator.
If RC >> T, the Low pass circuit works as an integrator.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
Connect the circuit as shown in the figure1 &2.
Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
Apply a square wave signal of frequency 1KHz at the input.
(T = 1
msec.)
Observe the output waveform of the circuit for different time constants.
Calculate the rise time for low pass filter and tilt for high pass filter and compare
with the theoretical values.
For low pass filter select rise time (tr) = 2.2 RC (theoretical). The rise time is
defined as the time taken by the output voltage to rise from 0.1 to 0.9 of its final
value.
% tilt = ( T/2RC )  100 ( theoretical)
% tilt = [ ( V1 – V1 ) / ( V / 2 ) ]  100 ( practical)
RESULT:
1. Rise time for lowpass filter when RC <<T
Theoretical =
Practical =
2. % tilt for highpass filter when RC = T.
Theoretical =
Practical =
Response of RC Low pass circuit is observed and rise time
calculated. Response of RC High pass circuit is observed and
percentage tilt is calculated.
Experiment No:2
NON LINEAR WAVE SHAPING - CLIPPERS
AIM : To study the clipping circuits for the following reference voltages and to
verify the responses.
Components Required:
1. Resistors - 1K
2. IN4007 Diode – 2No.
Apparatus Required :
1. Bread board.
2. Function generator
3. CRO
4. Power supply 0-30V
5. Connecting wires.
THEORY:
The non-linear semiconductor diode in combination with resistor can function as clipper
circuit. Energy storage circuit components are not required in the basic process of clipping.
These circuits will select part of an arbitrary waveform which lies above or below some
particular reference voltage level and that selected part of the waveform is used for transmission.
So they are referred as voltage limiters, current limiters, amplitude selectors or slicers.
There are three different types of clipping circuits.
1) Positive Clipping circuit.
2) Negative Clipping.
3) Positive and Negative Clipping ( slicer ).
In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negative
portion of sinusoidal signal is obtained in the output of reference voltage is added, instead of
complete positive cycle that portion of the positive cycle which is above the reference voltage
value is clipped.
In negative clipping circuit instead of positive portion of sinusoidal signal, negative
portion is clipped.
In slicer both positive and negative portions of the sinusoidal signal are clipped.
1K
I. Positive Clipping
Vi
IN 4007
Figure:1
V0
Vi
V0
V
t
t
Figure: 2(a). Input waveform
Figure: 2(b)Output waveform.
Vi is a input sinusoidal signal as shown in the figure 2(a) . For positive portion of the
sinusoidal the diode IN4007 gets forward biased. The output voltages in the voltage across the
diode under forward biased which is cut-in-voltage of the diode. Therefore the positive portion
above the cut-in-voltage is clipped or not observed in the output (V0) as shown in figure 2(b).
II. Positive Clipping with Positive Reference Voltage
1K
IN 4007
Vi
V0
VR
Figure:3.
V0
Vi
V R + V
t
Figure:4(a). Input waveform
t
Figure:4(b). Output waveform.
The input sinusoidal signal (Vi ) in figure 4(a) can make the diode to conduct when its
instantaneous value is greater than VR. Up to that voltage (VR) the diode is open circuited and the
output voltage is same as the input voltage. After that voltage (VR) the output voltage is VR plus
the cut-in-voltage (V ) of the diode as shown in figure 4(b).
III. Positive Clipping with Negative Reference Voltage
1K
IN 4007
Vi
V0
VR
Figure: 5.
V0
Vi
t
V -VR
t
Figure:6(a). Input waveform
Figure:6(b) Output waveform.
In this circuit the diode conducts the output voltage is same as input voltage. The diode
conducts at a voltage less by VR from cut-in-voltage called as V. For voltage less than V, the
diode is open circuited and output is same as input voltage.
IV Negative Clipping Circuit
1K
Vi
IN 4007
Figure:7.
V0
Vi
V0
t
t
-V
Figure:8 (a). Input waveform
Figure:8 (b). Output waveform.
For this portion of the input sinusoidal signal (Vi), the diode gets reverse biased and it is
open. Then the output voltage is same as input voltage. For the negative portion of the signal the
diode gets forward biased and the output voltage is the cut-in-voltage (-V ) of the diode. Then
the input sinusoidal variation is not seen in the output. Therefore the negative portion of the input
sinusoidal signal (Vi) is clipped in the output signal ( V0 ).
V. Negative Clipping with Negative Reference Voltage
1K
IN 4007
Vi
V0
VR
Figure:9
Vi
V0
t
t
-VR-V
Figure:10(a). Input waveform.
Figure:10(b) Output waveform.
In this circuit, the diode gets forward biased for the input sinusoidal voltage is less than
(–VR). For input voltage greater than (–VR), the diode is non-conducting and it is open. Then the
output voltage is same as input voltage.
VI. Negative Clipping with Positive Reference Voltage
1K
IN 4007
Vi
V0
VR
Figure:11.
Vi
V0
VR-V
t
t
Figure:12(a) Input waveform
Figure:12(b) Output waveform.
For input sinusoidal signal voltage less than VR, the diode is shorted and the output
voltage is fixed ar VR. For input sinusoidal voltage greater than VR the diode is reverse biased
and open circuited. Then the output voltage is same as input voltage.
VII. Slicer
1K
IN 4007
VR1
Figure:13.
IN 4007
VR2
V0
Vi
V+VR
t
t
V-VR
Figure:14(a). Input waveform
Figure14(b). Output waveform.
DESIGN:
1. For positive clipping at ‘V’ volts reference select V R = V.
2. For negative clipping at ‘V’ volts reference select V R = V.
3. For clipping at two independent levels at V1&V2 reference voltages
select VR1 = V1, VR2 = V2 and VR2 > VR1.
PROCEDURE:
1. Connect the circuit as shown in the figure 1.
2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a sine wave signal of frequency 1KHz at the input and observe the
output waveforms of the circuits.
4. Repeat the procedure for figure 3, 5, 7, 9, 11 and 13.
RESULT:
V =
Clipping circuits for different reference voltages are studied.
QUESTIONS:
1. What is a clipper? Describe (i) Positive clipper (ii) Biased clipper (iii)
Combination clipper.
2. Discuss the differences between shunt and series clipper.
NON LINEAR WAVE SHAPING – CLAMPERS
AIM : To get positive and negative clamping for sinusoidal and Square wave inputs.
Components Required:
1.
Resistors - 1k
2. IN4007 Diode
3. Capacitor -10F
Apparatus Required:
1.
2.
3.
4.
5.
Bread board
Function generator
CRO
Power supply 0-30V
Connecting Wires.
THEORY:
Clamping Circuit
“A clamping circuit is one that takes an input waveform and provides an output that is
a faithful replica of its shape but has one edge tightly clamped to the zero voltage reference
point”.
There are various types of Clamping circuits, which are mentioned below:
1. Positive Clamping Circuit.
2. Negative Clamping Circuit.
3. Positive Clamping with positive reference voltage.
4. Negative Clamping with positive reference voltage.
5. Positive Clamping with negative reference voltage.
6. Negative Clamping with negative reference voltage.
Negative Clamping Circuit
VA
+
+
C
D
Vi
V0
Figure:1
The input signal is a sinusoidal which begins at t=0. The capacitor C is charged at t = 0.
The waveform across the diode at various instant is studied.
During the first quarter cycle the input signal rises from zero to the maximum value Vm.
The diode being ideal, no forward voltage may appear across it. During this first quarter cycle
the capacitor voltage VA = Vi. The voltage across C rises sinusoidally, the capacitor is charged
through the series combination of the signal source and the diode. Throughout this first quarter
cycle the output V0 has remained zero. At the end of this quarter cycle there exists across the
capacitor a voltage VA = Vm.
After the first quarter cycle, the peak has been passed and the input signal begins to fall,
the voltage VA across the capacitor is no longer able to follow the input voltage. For in order to
do so, it would be required that the capacitor discharge, and because of the diode, such a
discharge is not possible. The capacitor remains charged to the voltage VA = Vm, and, after the
first quarter cycle the output is V0 = Vi – Vm. During succeeding cycles the positive excursion of
the signal just barely reaches zero. The diode need never again conduct, and the positive
extremity of the signal has been clamped to zero. The average value of the signal is –Vm.
Positive Clamping Circuit:
Vm
+
+
+
C
Vi
-
D
Figure:2
V0
-
It is also called as negative peak clamper, because this circuit clamps at the negative
peaks of a signal.
Let the input signal be Vi = Vm sint. When Vi goes negative, diode gets forward biased
and conducts. The capacitor charges to voltage Vm, with polarity as shown. Under steady state
condition, the positive clamping circuit is given as,
V0  Vi  (Vm )
V0  Vi Vm
Eq.1
During the negative half cycle of Vi, the diode conducts and C charges to –Vm volts, i.e.,
the negative peak value. The capacitor cannot discharge since the diode cannot conduct in the
reverse direction. Thus the capacitor acts as a battery of –Vm volts and the output voltage is given
by equation.1 above. It is seen for figure 2, that the negative peaks of the input signal are
clamped to zero level. Peak-to-peak amplitude of output voltage 2Vm, which is the same as that
of the input signal.
Negative Clamping with Positive Reference Voltage
C
D
Vi
V0
VR
Figure:2
Since VR is in series with the output of negative clamping circuit, now the average value of the
output becomes (-Vm + VR ).
Similarly, the average of
i) Negative clamping with negative reference voltage is (-Vm + VR ).
ii) Positive clamping is +Vm.
iii) Positive clamping with positive reference voltage is Vm + VR.
iv) Positive clamping with negative reference voltage is Vm - VR.
Clamping Circuit Theorem:
It states that for any input waveform the ratio of the areas under the output voltage curve
in forward direction to that in the reverse direction is equal to the ratio (Rf / R).
A R
f
 f.
Ar R
Where Af = area of the output wave in forward direction.
Ar = area of the output wave in reverse direction.
Rf and R are forward and reverse resistances of the diode.
I. Negative Clamping
10F
C
1K
Vi
D
IN 4007
R
V0
Figure:3
Vi
V0
Vm
t
t
-Vm
-2Vm
Figure:4 (a).Input waveform
Figure:4 (b) Output waveform.
II. Negative Clamping with Positive Reference Voltage.
10F
C
D
IN 4007
R
V0
Vi
1K
VR
Figure:5
Vi
V0
VR
t
t
Figure:6 (a).Input waveform
Figure:6 (b) Output waveform.
III. Negative Clamping with Negative Reference Voltage.
10F
C
D
IN 4007
R
V0
Vi
1K
VR
Figure:7
Vi
V0
t
t
-VR
Figure:8 (a).Input waveform
Figure:8 (b) Output waveform.
IV. Positive Clamping.
10F
C
D
Vi
1K
R
V0
IN 4007
figure:9
2Vm
Vi
V0
Vm
t
t
-Vm
Figure:10 (a).Input waveform
Figure:10 (b) Output waveform.
V. Positive Clamping with Negative Reference Voltage.
10F
C
D
IN 4007
R
V0
Vi
1K
VR
Figure: 11
Vi
-VR
V0
t
t
Figure:12 (a).Input waveform
Figure:12 (b) Output waveform.
VI. Positive Clamping with Positive reference Voltage.
10F
C
D
IN 4007
R
V0
Vi
1K
VR
Figure: 13
Vi
V0
VR
t
Figure:14 (a).Input waveform
t
Figure:14 (b) Output waveform.
PROCEDURE:
1. Connect the circuit as shown in the figure 3.
2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a sine wave and square wave signal of frequency 1kHz at the input and
observe the output waveforms of the circuits in CRO.
4. Repeat the above procedure for the different circuit diagram as shown inf figure 5, 7,
9, 11 and 13.
RESULT: The clamping voltages for positive and negative clamping circuits are noted.
QUESTIONS:
1. Explain the operation of a clamping circuit for a square wave input.
2. Differentiate the clippers with clampers.
3. Give the applications of clampers.
Experiment No:3
TRANSISTOR AS A SWITCH
Aim:
Design Transistor to act as a Switch and verify the operation. Choose V CC = 10V, ICmax
= 10 mA, hfe = 50, VCESat = 0.2, Vin = 4Vp-p, VBESat = 0.7 V
Apparatus:
1.
2.
3.
4.
5.
6.
7.
Transistor (BC 107).
Breadboard.
CRO.
Resistors (1K,6.8K).
DC power supply.
Function Generator.
Connecting patch cards.
Theory:
When the I/P voltage Vi is negative or zero, transistor is cut-off and no current flows
through Rc hence V0  VCC when I/P Voltage Vi jumps to positive voltage, transistor will be
driven into saturation. Then
V0 = Vcc – ICRC  VCESat
Design procedure:
V
CC
V
I
CESat
When Q is ON, RC =
C max
= (10-0.2) / 10 mA
= 1K
IB ICmax / hfe
 10mA / 50
IB 0.2 mA
Tokeep
transistorremainin
Ibmin = 0.2mA
ON,IBshouldbegreaterthan
Vin = IBRB + VBE Sat
(VBE sat for Si 0.7& Ge is
0.2) 2V = 0.2 mA RB + 0.7V
RB = 6.5 K (choose practical values as 6.8K)
Circuit diagram:
Procedure:
1. Connect the circuit as shown in figure.
2. Apply the Square wave 4 Vp-p frequency of 1 KHz
3. Observe the waveforms at Collector and Base and plot it.
Precautions:
1. When you are measuring O/P waveform at collector and base, keep the CRO in DC
mode.
2. When you are measuring VBE Sat, VCE Sat keep volts/div switch at either 0.2 or 0.5
position.
3. When you are applying the square wave see that there is no DC voltage in that. This
can be checked by CRO in either AC or DC mode, there should not be any
jumps/distortion in waveform on the screen.
Expected waveforms:
Result:
Transistor as a switch has been designed and O/P waveforms are observed.
Questions:
1.
2.
3.
4.
5.
6.
Differentiate between Diode and Transistor as a switch?
Mention typical values of VBE Sat, VCE Sat for both Si, Ge Transistors?
Define ON time, OFF time of the transistor?
In which regions Transistor acts as a switch?
Explain phenomenon of “ latching “ in a Transistor switch?
Define Rise time & fall time ?
Experiment No:4
BISTABLE MULTIVIBRATOR
AIM:
To design a fixed bias Bistable Multivibrator and to measure the stable state
voltages and after triggering.
COMPONENTS REQUIRED:
1. Resistors
2. Capacitors.
3. Transistors 2N2369 – 2
APPARATUS:
1. Bread board
2. Power supply 0-30V
3. CRO
4. Connecting wires
THEORY:
A bistable multivibrator has two stable output states. It can remain indefinitely in any
one of the two stable states, and it can be induced to make an abrupt transition to the other stable
state by means of suitable external excitation. It would remain indefinitely in this stable state,
until it is again induced to switch into the original stable state by external triggering.
Bistable multivibrators are also termed as ‘Binary’s or Flip-flops’. A binary is sometimes
referred to as ‘Eccles-Jordan Circuit’.
+VCC
I1
I2
RC1
RC2
R1
R1
C
D
A
B
Q2
Q1
R2
R2
-VBB
Figure 1
Principle of Operation of bistable multivibrator.
Consider the circuit as shown in the figure.1. The transistor Q1 and Q2 are n-p-n
transistors. They are coupled to each other as shown in figure 1. It is evident that the output of
each transistor is coupled to the input of the other transistor. Since the transistors are identical,
there quiescent currents would be the same, unless the loop gain is greater than unity. When I1
increases slightly, the voltage drop across the collector resistance RC1 increases. Since VCC is
fixed, the voltage of point C decreases. This has the effect of decreasing the base current of Q2.
This, in turn, decreases the collector current of Q2 viz. I2 decreases, the voltage drop I2RC2
decreases. Hence the voltage of point D increases.
Due to increase of VD, the base current of Q1 increases. This increases the collector
current of Q1 viz I1. Thus I1 further increases. I1RC1 drop further increases, VC further decreases,
the base current of Q2 further decreases, with the result that I2 further decreases. Thus it can
easily seen that if the collector current I1 increases even marginally, I2 would go on
progressively decreasing and as a result, I1 would progressively increase. Eventually I2 would
become practically zero, cutting off the transistor Q2, at the same time transistor Q1 would
conduct heavily with the result that it would be driven into saturation. Thus Q2 becomes OFF
and Q1 becomes ON. It can similarly be shown that if I2 increases even marginally similar
sequence of operation would result and ultimately Q2 would be ON and Q1 OFF. Thus when Q1
is ON, Q2 is OFF and when Q1 is OFF Q2 is ON.
CIRCUIT DIAGRAM:
VCC 12V
RC1
2.2K
RC2
2.2K
R1 15K
R1 15K
2N2369
2N2369
Q1
2
1
0
0
K
100K
R2
R
Q2
-VBB = -1.5V
Figure: 2
PROCEDURE:
1.
2.
3.
4.
Connect the circuit as shown in figure 2.
Observe the waveforms at VBE1, VBE2, VCE1, VCE2
Observe which transistor is in ON state and which transistor is in OFF state.
Apply –ve triggering at the base of the ON transistor and observe the voltages
VC1, VC2, VB1, and VB2.
5. Apply + ve triggering at the base of the OFF transistor and observe the
Voltages VC1, VC2, VB1, VB2.
Voltage
Voltage
EXPECTED WAVEFORMS:
VC1
VC2
VC1
VC2
0
t
0
t
After Triggering
Before Triggering
RESULT:
VBE1
VBE2
VCE1
VCE2
Stable state Voltages
QUESTIONS:
1. What is Multivibrator? Explain the principle on which it works? Why is it called
a binary?
2. Explain the role of commutating capacitors in a Bistable Multivibrator?
3. Give the Application of a Binary.
Experiment No:5
ASTABLE MULTIVIBRATOR
AIM : a) To design and test performance of an Astable Multivibrator to
generate clock pulse for a given frequency.
COMPONENTS REQUIRED:
1. Resistors
2. Capacitors 0.1 f - 2
3. Transistors 2N2369 – 2
APPARATUS :
1.
2.
3.
4.
CRO
Power supply 0-30V
Bread board
Connecting wires
THEORY:
An Astable multivibrator has two quasi-stable states, and it keeps on switching between
these two states, by itself, No external triggering signal is needed. The astable multivibrator
cannot remain indefinitely in any of these two states. The two amplifiers of an astable
multivibrator are regeneratively cross-coupled by capacitor.
Principle:
A collector-coupled astable multivibrator using n-p-n transistor in figure 1. The working
of an astable multivibrator can be studied with respect to the figure1.
VCC 12V
RC1
R2
R1
RC2
C
D
C2
2N2369
C1
Q1
Q2
A
2N2369
B
Figure:1
Let it be assumed that the multivibrator is already in action and is oscillating i.e.,
switching between the two states. Let it be further assumed that at the instant considered, Q2 is
ON and Q1 is OFF.
i) Since Q2 is ON, capacitor C2 charges through resistor RC1. The voltage across C2 is VCC.
ii) Capacitor C1discharges through resistor R1, the voltage across C1 when it is about to start
discharging is VCC.(Capacitor C1 gets charged to VCC when Q1 is ON).
As capacitor C1 discharges more and more, the potential of point A becomes more and
more positive (or less and less negative), and eventually V A becomes equal to V, the cut in
voltage of Q1. For VA > V, transistor Q1 starts conducting. When Q1 is ON Q2 becomes OFF.
Similar operations repeat when Q1 becomes ON and Q2 becomes OFF.
Thus with Q1 ON and Q2 OFF, capacitor C1 charges through resistor RC2 and capacitor
C2 discharges through resistor R2. As capacitor C2 discharges more and more , it is seen that the
potential of point B becomes less and less negative (or more and more positive), and eventually
VB becomes equal to V, the cut in voltage of Q2. when VB > V, transistor Q2 starts conducting.
When Q2 becomes On, Q 1 becomes OFF.
It is thus seen that the circuit keeps on switching continuously between the two quasistable states and once in operation, no external triggering is needed. Square wave voltage are
generated at the collector terminals of Q1 and Q2 i.e., at points C and D.
DESIGN:
IC max = 5 mA ; VCC = 12 V; VCE (SAT) = 0.2V
RC = (VCC - VCE(SAT)) / IC MAX
Let C = 0.1 f and R= 10K
T = 0.69 (R1C1+R2C2) = 0.69(2RC) Q ( R1=R2 ; C1=C2)
=TON+TOFF
PROCEDURE:
1. Connect the circuit as shown in figure 1.
2. Observe the waveforms at VBE1, VBE2, VCE1, VCE2 and find frequency.
3. Vary C from 0.01 to 0.001F and measure the frequency at each step.
4. Keep the DC- AC control of the Oscilloscope in DC mode.
EXPECTED WAVEFORMS:
Q1 OFF, Q2 ON
Q1 OFF, Q2 ON
VCC
Q1 ON, Q2 OFF
Q1 ON, Q2 OFF
VC1
VCE (SAT)
t
VCC
VC2
VCE (SAT)
t
V
VB1
t
VB2
V
t
I.R C
Figure 2
RESULT:
TON =
TOFF =
T(TON + TOFF) =
Astable multivibrator is designed and its performance is tested.
QUESTIONS:
1. What is a switching circuit?
2. Justify that the Astable Multivibrator is a two stage RC coupled Amplifier using
negative feedback. How does it generate square wave.
3. What is the difference between a switching transistor and an ordinary transistor?
4. What is the effect of slew rate on the working of an Op-amp Multivibrator?
Experiment No:6
MONOSTABLE MULTIVIBRATOR
AIM : a) To design and test performance of a monostable multivibrator to generate clock pulse
for a given frequency. And obtain the waveforms.
Components Required:
1. Resistors
2. Capacitors.
3. Transistors 2N2369 – 2
Apparatus Required:
1. CRO
2. Power supply 0-30V
3. Bread board
4. Connecting wires
CIRCUIT DIAGRAM:
VCC 12V
RC1
RC2
R=10K
R1
C=0.1F
2N2369 Q1
Q2 2N2369
R2
-VBB -1.5V
Figure 1
THEORY :
‘A monostable multivibrator has only one stable state, the other state being quasistable. Normally the multivibrator is in the stable state, and when an external triggering pulse is
applied, it switches from the stable to the quasi-stable state. It remains in the quasi-stable state
fro a short duration, but automatically reverts i.e. switches back to its original stable state,
without any triggering pulse’.
Principle of operation
A collector-coupled Monostable multivibrator of the two transistors Q1 and Q2, Q1 is
normally OFF and Q2 is Normally ON. Resistor R1 and R2 are connected to the normally OFF
transistor, and the capacitor C is connected to the normally ON transistor.
It is seen from the circuit of the monostable multivibrator that, under normal conditions,
the supply voltage VCC provides enough base drive to the transistor Q 2 through resistor R, with
the result that Q2 goes into saturation. With Q2 ON, Q1 goes OFF, as already studied in the
context of binary operation.
With Q2 ON and Q1 OFF, the capacitor finds a charging path. The voltage across the
capacitor is VCC with polarity. It is obvious that in the stable state of the multivibrator, Q 2 is ON
and Q1 is OFF.
If the negative triggering pulse is applied to the collector of Q 1, it is transmitted to the
base of Q2 through the capacitor, and hence makes the base of Q2 negative. Immediately Q2 goes
OFF and Q1 becomes ON. However, this is only a quasi-stable state as is obvious form the
following observation.
With Q1 ON and Q2 OFF, the capacitor C finds a discharging path. As the capacitor
discharges, it is seen that the potential at the base of the transistor Q 2 becomes less and less
negative, and after a time, we have VB = V, the cut-in-voltage of Q2.
As soon as VB crosses the level of V, Q2 starts conducting and gets saturated.
When Q2 becomes ON, Q 1 becomes OFF. Thus the original stable state of the multivibrator is
restored.
[ In quasi-stable state: Q1 is ON and Q2 is OFF]
The interval during which the quasi-stable state of the multivibrator persists i.e., Q2
remains OFF is dependent upon the rate at which the capacitor C discharges. This duration of the
quasi-stable state is termed as delay time or pulse width or gate time. It is denoted as T. The
wave forms of the voltage at base of the transistor Q2 and C (Collector of Q1)
DESIGN:
V CE = 5.56v, V CC = 6v, V CE(sat) = 0.3v, V BE(sat) , = 0.7v, I C = 6mA,V F = -0.3v
V R V
R
Rc = (VCC–VCE(sat))/IC.
V

CE
V R
CC
V
1
R1  RC
 BE
R
(sat )
C
R1  R C
VF 
BB
1
R R
1
2

CE ( sat )
2
RR
1
2
Find the values of R1 and R2
PROCEDURE:
1. Connect the circuit as shown in figure.
2. With the help of a triggering circuit and using the condition T (trig)
> T(Quasi) a pulse waveform is generated.
3. The output of the triggering circuit is connected to the base of the off
transistor.
4. The Off transistor goes into ON state.
5. Observe the waveforms at VBE1, VBE2, VCE1, VCE2
6. Keep the DC- AC control of the Oscilloscope in DC mode.
EXPECTED WAVEFORMS:
Q2 OFF, Q1 ON
VC2
VCC
Q1 OFF, Q2 ON
VCE (SAT)
Q2 ON, Q1 OFF
t
V
VB2
t
I.R C
VCC
VC1
VCE (SAT)
t
VB1
V
t
Figure 2
RESULT:
TON =
TOFF =
Total T (TON + TOFF) =
Monostable multivibrator is designed and studied.
QUESTIONS:
1. Explain the operation of collector coupled Monostable Multivibrator?
2. Derive the expression for the gate width of a transistor Monostable Multivibrator?
3. Give the application of a Monostable Multivibrator.
Experiment No:7
SCHMITT TRIGGER
AIM:
To design and analyze Schmitt trigger and to observe the waveforms.
COMPONENTS REQUIRED:
1. Resistors
2. Transistors 2N2369 – 2
3.
APPARATUS:
1. Bread board
2. Power supply 0-30V
3. Signal generator
4. CRO
5. Connecting Wires.
CIRCUIT DIAGRAM:
VCC = 12V
RC1
RC2
R1
RB
Q2 2N2369
Q1 2N2369
Vi
+
Signal
Generator
V0
RE
R2
-
Figure:1
THEORY:
The most important application of Schmitt Trigger circuit are amplitude comparator and
squaring circuit are amplitude comparator and squaring circuit. The circuit is used to obtain a
square waveform from any arbitrary input waveform. The loop gain is to be less than unity.
If Q2 is conducting there will be voltage drop across RZ which will elevate the emitter of
Q1. Consequently if V is small enough in voltage, Q1 will be cut-off with Q1 conducting, the
circuit amplifies and since the gain is positive, the output to rise, V2 continues to fall and Z2
continues to rise. Therefore a value of V will be reached where Q2 is turned OFF. At the point
the output no longer responds to the input.
Here the input signal is arbitrary except that it has large enough excursion to carry input
beyond the limits of hysteresis range, VH = (V1 – V2).
The output is a square wave whose amplitude is independent of the amplitude of the
input waveform.
DESIGN:
IC2 = 5mA
(Rc2 + RE) = VCC /
IC2 U.T.P = VE2 = 5V
VE2 = (RE VCC) /
(Rc2+RE) I2 = 0.1IC2
L.T.P = VE1 = 3V
R2 = ER2i / I2 = VE1 / I2 = L.T.P /
I2 Rc1 = {(REVCC) / VE1} –RE
IB2 = IC2 / hfe(min)
(VCC - VE2) / (R1+RL1))) =
(VE2/R2)+IB2 RB = (hfeRE) / 10
Find R1, R2, RE, Rc1and Rc2 from the above equations
PROCEDURE:
1. Connect the circuit as shown in figure 1 with designed values.
2. Apply VCC of 12V and an input frequency of 1KHz with an amplitude more than the
designed UTP.
3. Now note down the output wave forms
4. Observe that the output comes to ON state when input exceeds UTP and it comes to OFF
state when input comes below LTP
5. Observe the waveforms at VC1, VC2, VB2 and VE and plot graphs.
6. Keep the DC- AC control of the Oscilloscope in DC mode.
MODEL GRAPHS:
UTP
Input sin wave
VMAX>UTP
VC2
VC1
VB2
RESULT:
Schmitt Trigger circuit is designed and studied.
QUESTIONS:
1. Explain how a Schmitt trigger acts as a comparator?
2. Derive its expressions for UTP & LTP.
LTP
Schmitt Trigger
output
Experiment No:8
UJT RELAXATION OSCILLATOR
Aim:
a.To observe the sweep time of the relaxation oscillator,to compare frequency of
oscillator theoretically and practically
b.To calculate the slope error,transmission error and displacement error
Equipment and components required:
1.UJT
2.Resistors
3.Capacitor
4. Regulated power supply
5. C.R.O.
6. Connecting wires
2N2646-1No
1K, 2.2K,100 K
0.1uf
Theory:
The Unijunction transistor(UJT) has two doped regions with three external leads.It has
one emitter and two bases.The emitter is heavily doped having many holes.The n-region is
lightly doped.For this reason,the resistance between the bases is relatively high,typically 5KΩ to
10KΩ when the emitter is open.This is called Inter base Resistance RBB
UJT relaxation oscillator come under non sinusoidal oscillator.It is a example of non
feedback type of oscillator.A relaxation circuit term is employed to any circuit in which timing
intervals are determined by exponentially charging and discharging .A charged capacitor
functions like a stiff spring.A discharging capacitor is analogous to a relaxing spring.
Circuit diagram:
5V
1KΩ
100nf
Procedure:
2.2KΩ
1.Connect the circuit as shown in the circuit
diagram. 2.Observe the sweep time
3.Calculate sweep time and restoration time.
4.Calculate and compare the frequencies of oscillations theoretically and practically.
Model Waveforms:
Result: Required waveform is obtained and slope error, transmission error and displacement
error are also calculated.
Experiment No:9
BOOTSTRAP SWEEP CIRCUIT
Aim:To design a Bootstrap sweep circuit and to generate a linear ramp generator.
Equipment and components required:
1.Transistor
2.Resistors
3.Capacitor
4. Diode
5. BNC adapters
6.Regulated power supply
7.C.R.O.
8.Function generator
9. Connecting wires
BC547-2 No’s
100K-1 No,10K-2 No’s
10Kpf-2 No’s,0.1uf-1 No
1N4007-1 No
Theory:
The basic principle involved in the bootstrap circuit is the generator voltage is assumed
to be equal to the Vc so far the amplifier input voltage Vi is equal to Vo i.e.,(Vo=Vi) and output
will be linear if the amplifier gain is unity.So in this way,the voltage V rises by its own
bootstraps,hence we get the linear bootstrap sweep.
Circuit diagram:
Procedure:
Department of ECE
Electronic Circuits and Pulse Circuits Laboratory
1. Connect the circuit diagram as shown in above figure.
2. Apply Vcc = 15v, Vp-p = 10v,10KHz frequency.
3. Apply pulse to the base of Q1 and observe the output waveform.
4. Vary the pulse width of input pulse and observe the output.
Model Waveforms:
Result: Output waveform of ramp is obtained and sweep speed is calculated.
MLR Institute of Technology, Dundigal, Hyderabad
92